diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2019-07-19 15:38:04 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:05:09 +0800 |
| commit | 0a0add4eb99143fe22b247a4c5a84ed42e9be30f (patch) | |
| tree | c7c09b0e22953e2ac9b5466b75776a59bdf3a11b /arch/arm64/boot/dts/freescale/imx8qm.dtsi | |
| parent | 7d99868f45780570d600e58469ff613787e9c4e4 (diff) | |
arm64: dts: imx8qm: convert to new clock binding
convert to new clock binding
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm.dtsi | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index e8c3cb723818..05050037ecdb 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -69,7 +69,7 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; - clocks = <&clk IMX_A53_CLK>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; @@ -80,7 +80,7 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; - clocks = <&clk IMX_A53_CLK>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; @@ -91,7 +91,7 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; - clocks = <&clk IMX_A53_CLK>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; @@ -102,7 +102,7 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; - clocks = <&clk IMX_A53_CLK>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; @@ -197,6 +197,12 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ }; + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "clk_dummy"; + }; + xtal32k: clock-xtal32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -227,7 +233,7 @@ clk: clock-controller { compatible = "fsl,imx8qm-clk", "fsl,scu-clk"; - #clock-cells = <1>; + #clock-cells = <2>; clocks = <&xtal32k &xtal24m>; clock-names = "xtal_32KHz", "xtal_24Mhz"; }; |