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authorDong Aisheng <aisheng.dong@nxp.com>2019-07-20 19:09:10 +0800
committerDong Aisheng <aisheng.dong@nxp.com>2019-11-25 16:05:11 +0800
commit654bbac86c689e438cd1f6dc0b4db3993fb34d5e (patch)
tree646f39f32971792899cae85ec2e94f1630b1065b /arch/arm64/boot/dts/freescale/imx8qm.dtsi
parent85b32baaba94a89c6905c999fa08d1971bc14390 (diff)
arm64: dts: imx8qm: include second level SoC dtsi
Include the required second level SoC dtsi. Also move PD node before scu clk node. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qm.dtsi14
1 files changed, 9 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 05050037ecdb..937dd6d19d53 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -231,6 +231,11 @@
&lsio_mu1 1 3
&lsio_mu1 3 3>;
+ pd: imx8qx-pd {
+ compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
+ #power-domain-cells = <1>;
+ };
+
clk: clock-controller {
compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
#clock-cells = <2>;
@@ -256,11 +261,6 @@
};
};
- pd: imx8qx-pd {
- compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
- #power-domain-cells = <1>;
- };
-
rtc: rtc {
compatible = "fsl,imx8qm-sc-rtc";
};
@@ -378,3 +378,7 @@
#include "imx8-ss-hsio.dtsi"
#include "imx8-ss-img.dtsi"
};
+
+#include "imx8qm-ss-dma.dtsi"
+#include "imx8qm-ss-conn.dtsi"
+#include "imx8qm-ss-lsio.dtsi"