diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2019-10-31 17:34:50 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:08:59 +0800 |
| commit | f677bffe25e2c2aef16ec0b7e9dc78b54a0ae279 (patch) | |
| tree | 70e0f8b1743fda2cc51c966fbec9c8c3b22eb402 /arch/arm64/boot/dts/freescale/imx8qm.dtsi | |
| parent | 4960791f494fbde399fa7b2523cf7a2a86de2572 (diff) | |
arm64: dts: imx8qm: Add A72 cluster cpufreq support
Add A72 cluster OPP table to support cpufreq.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qm.dtsi')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8qm.dtsi | 36 |
1 files changed, 35 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index ab5abb64b446..bccee593eefa 100755 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -126,8 +126,10 @@ device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x0 0x100>; + clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; next-level-cache = <&A72_L2>; + operating-points-v2 = <&a72_opp_table>; #cooling-cells = <2>; }; @@ -135,8 +137,10 @@ device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x0 0x101>; + clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; next-level-cache = <&A72_L2>; + operating-points-v2 = <&a72_opp_table>; #cooling-cells = <2>; }; @@ -149,7 +153,7 @@ }; }; - a53_opp_table: opp-table { + a53_opp_table: a53-opp-table { compatible = "operating-points-v2"; opp-shared; @@ -179,6 +183,36 @@ }; }; + a72_opp_table: a72-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + }; + + opp-1596000000 { + opp-hz = /bits/ 64 <1596000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + gic: interrupt-controller@51a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ |