arm64: dts: imx8qxp: enable enet2 port for MEK board

Enable enet2 port for MEK board.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
[ Aisheng: fix small conflicts during upgrade ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

1 files changed, 57 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi
new file mode 100644
index 000000000000..dd363d61efb8
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-enet2-tja1100.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&fec1 {
+	status = "disabled";
+};
+
+&fec2 {
+	pinctrl-0 = <&pinctrl_fec2_rmii>;
+	clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
+		 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
+		 <&conn_lpcg IMX_CONN_LPCG_ENET1_RGMII_TXC_CLK>,
+		 <&conn_lpcg IMX_CONN_LPCG_ENET1_RMII_REF_50MHZ_CLK>,
+		 <&conn_lpcg IMX_CONN_LPCG_ENET1_TXC_SAMPLING_CLK>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy2>;
+	/delete-property/ phy-supply;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy2: ethernet-phy@5 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <5>;
+			tja110x,refclk_in;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl_fec2_rmii: fec2rmiigrp {
+		fsl,pins = <
+			IMX8QXP_ENET0_MDC_CONN_ENET1_MDC		0x06000020
+			IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO		0x06000020
+			IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT	0x06000020
+			IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x06000020
+			IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x06000020
+			IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER	0x06000020
+			IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL	0x06000020
+			IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x06000020
+			IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x06000020
+			IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL	0x06000020
+		>;
+	};
+};