ARM64: dts: imx8qxp: enable dsp function

enable dsp function

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
[ Aisheng: fix conflict due to upstreamed MU13 ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

1 files changed, 125 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsp.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsp.dts
new file mode 100644
index 000000000000..859fbb63c544
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dsp.dts
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright NXP 2018
+
+#include "imx8qxp-mek.dts"
+
+/ {
+	sound-cs42888 {
+		status = "disabled";
+	};
+
+	sound-wm8960 {
+		status = "disabled";
+	};
+
+	dspaudio: dspaudio {
+		compatible = "fsl,dsp-audio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_esai0>;
+		status = "okay";
+	};
+
+	sound-dsp {
+		compatible = "fsl,imx-dsp-audio";
+		model = "dsp-audio";
+		cpu-dai = <&dspaudio>;
+		audio-codec = <&cs42888>;
+		audio-platform = <&adma_dsp>;
+	};
+};
+
+&edma0 {
+	compatible = "fsl,imx8qm-edma";
+	reg = <0x59280000 0x10000>, /* spdif0 rx */
+		<0x59290000 0x10000>, /* spdif0 tx */
+		<0x592c0000 0x10000>, /* sai0 rx */
+		<0x592d0000 0x10000>, /* sai0 tx */
+		<0x592e0000 0x10000>, /* sai1 rx */
+		<0x592f0000 0x10000>, /* sai1 tx */
+		<0x59350000 0x10000>,
+		<0x59370000 0x10000>;
+	#dma-cells = <3>;
+	shared-interrupt;
+	dma-channels = <8>;
+	interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
+			<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
+			<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
+			<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */
+			"edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */
+			"edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */
+			"edma0-chan21-tx",		/* gpt5 */
+			"edma0-chan23-rx";		/* gpt7 */
+	status = "okay";
+};
+
+&adma_dsp {
+	compatible = "fsl,imx8qxp-dsp";
+	reserved-region = <&dsp_reserved>;
+	reg = <0x596e8000 0x88000>;
+	clocks = <&adma_lpcg IMX_ADMA_LPCG_ESAI_0_IPG_CLK>,
+		<&adma_lpcg IMX_ADMA_LPCG_ESAI_0_EXTAL_CLK>,
+		<&adma_lpcg IMX_ADMA_LPCG_ASRC_0_IPG_CLK>,
+		<&clk IMX_CLK_DUMMY>,
+		<&adma_lpcg IMX_ADMA_LPCG_AUD_PLL_DIV_CLK0_CLK>,
+		<&adma_lpcg IMX_ADMA_LPCG_AUD_PLL_DIV_CLK1_CLK>,
+		<&adma_acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
+		<&adma_acm IMX_ADMA_ACM_AUD_CLK1_SEL>;
+	clock-names = "esai_ipg", "esai_mclk", "asrc_ipg", "asrc_mem",
+			"asrck_0", "asrck_1", "asrck_2", "asrck_3";
+	assigned-clocks = <&adma_acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
+			<&clk IMX_ADMA_AUD_PLL0>,
+			<&clk IMX_ADMA_AUD_PLL_DIV_CLK0_CLK>,
+			<&clk IMX_ADMA_AUD_REC_CLK0_CLK>,
+			<&adma_lpcg IMX_ADMA_LPCG_ESAI_0_EXTAL_CLK>;
+	assigned-clock-parents = <&adma_lpcg IMX_ADMA_LPCG_AUD_PLL_DIV_CLK0_CLK>;
+	assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>;
+	fsl,dsp-firmware = "imx/dsp/hifi4.bin";
+	power-domains = <&pd IMX_SC_R_MU_13A>,
+			<&pd IMX_SC_R_MU_13B>,
+			<&pd IMX_SC_R_IRQSTR_DSP>,
+			<&pd IMX_SC_R_DSP>,
+			<&pd IMX_SC_R_DSP_RAM>,
+			<&pd IMX_SC_R_ESAI_0>,
+			<&pd IMX_SC_R_DMA_0_CH6>,
+			<&pd IMX_SC_R_DMA_0_CH7>,
+			<&pd IMX_SC_R_AUDIO_CLK_0>,
+			<&pd IMX_SC_R_AUDIO_CLK_1>,
+			<&pd IMX_SC_R_AUDIO_PLL_0>,
+			<&pd IMX_SC_R_AUDIO_PLL_1>,
+			<&pd IMX_SC_R_ASRC_0>,
+			<&pd IMX_SC_R_DMA_0_CH0>,
+			<&pd IMX_SC_R_DMA_0_CH1>,
+			<&pd IMX_SC_R_DMA_0_CH2>,
+			<&pd IMX_SC_R_DMA_0_CH3>,
+			<&pd IMX_SC_R_DMA_0_CH4>,
+			<&pd IMX_SC_R_DMA_0_CH5>;
+};
+
+&adma_esai0 {
+	status = "disabled";
+};
+
+&adma_asrc0 {
+	status = "disabled";
+};
+
+&adma_sai1 {
+	status = "disabled";
+};
+
+&wm8960 {
+	status = "disabled";
+};
+
+&cs42888 {
+	assigned-clocks = <&clk IMX_ADMA_AUD_PLL0>,
+			<&clk IMX_ADMA_AUD_PLL_DIV_CLK0_CLK>,
+			<&clk IMX_ADMA_AUD_REC_CLK0_CLK>,
+			<&adma_lpcg IMX_ADMA_LPCG_MCLKOUT0>;
+	assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
+};