diff options
| author | Han Xu <han.xu@nxp.com> | 2019-06-05 22:52:29 -0500 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:04:32 +0800 |
| commit | 37f783cdf805bf94d0e9b8529cee6ab086543898 (patch) | |
| tree | 4e779365a628044b72bffb4d1bd98692b485dae4 /arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | |
| parent | f5fc8e4f9a1ab797c832f9976e1de094cd2a8bd5 (diff) | |
MLK-21960-4: arm64: dts: enable fspi in imx8qxp dts
enable fspi in imx8qxp DT file
Signed-off-by: Han Xu <han.xu@nxp.com>
[ Aisheng: sort in reg address and fix conflict ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qxp-mek.dts')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 8a8169325564..212f51d360f8 100755 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -460,6 +460,22 @@ }; }; +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &adma_i2c1 { #address-cells = <1>; #size-cells = <0>; @@ -788,6 +804,27 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + pinctrl_ioexp_rst: ioexp_rst_grp { fsl,pins = < IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 |