arm64: imx8-ss-dc0.dtsi: Improve DC0 subsystem device tree

This patch improves DC0 subsystem device tree to clearly reflect it is
the first DC subsystem instance embedded in a SoC. So, some renaming
happens in imx8-ss-dc.dtsi, and finally imx8-ss-dc.dtsi is renamed to be
imx8-ss-dc0.dtsi.

Also, extract the i.MX8qxp specific compatible string, display clocks,
display ports and display-subsystem from imx8-ss-dc0.dtsi and put them
in SoC specific imx8qxp-ss-dc.dtsi.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

1 files changed, 51 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi
new file mode 100644
index 000000000000..98530941c91d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2019 NXP
+ */
+
+&dpu1 {
+	compatible = "fsl,imx8qxp-dpu";
+	clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>,
+		 <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>,
+		 <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>,
+		 <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>;
+	clock-names = "pll0", "pll1", "disp0", "disp1";
+
+	dpu_disp0: port@0 {
+		reg = <0>;
+
+		dpu_disp0_ldb1_ch0: endpoint@0 {
+			remote-endpoint = <&ldb1_ch0>;
+		};
+
+		dpu_disp0_ldb1_ch1: endpoint@1 {
+			remote-endpoint = <&ldb1_ch1>;
+		};
+
+		dpu_disp0_mipi_dsi: endpoint@2 {
+		};
+	};
+
+	dpu_disp1: port@1 {
+		reg = <1>;
+
+		dpu_disp1_ldb2_ch0: endpoint@0 {
+			remote-endpoint = <&ldb2_ch0>;
+		};
+
+		dpu_disp1_ldb2_ch1: endpoint@1 {
+			remote-endpoint = <&ldb2_ch1>;
+		};
+
+		dpu_disp1_mipi_dsi: endpoint@2 {
+		};
+	};
+};
+
+/ {
+	display-subsystem {
+		compatible = "fsl,imx-display-subsystem";
+		ports = <&dpu_disp0>, <&dpu_disp1>;
+	};
+};