diff options
| author | Aisheng Dong <aisheng.dong@nxp.com> | 2019-12-06 11:42:30 +0000 |
|---|---|---|
| committer | Robert Chiras <robert.chiras@nxp.com> | 2019-12-10 11:38:00 +0200 |
| commit | 01b8b7a56fcdacbae7ee09c25a2de27cbdc67556 (patch) | |
| tree | 94193c39a646274884ad1f32b9db6f4ed2aafd43 /arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi | |
| parent | a6a3a9cd11ae8b5f997a4fe004bd163e5f6f8eff (diff) | |
arm64: dts: mipi-lvds: fix mipi rx/tx clocks
By default, the MIPI RX and TX clocks are parented to the BYPASS clock,
but it seems that this doesn't work on QXP. Since these clocks can also
be parented to MIPI_PLL and MIPI_PLL_DIV2, use the MIPI_PLL_DIV2 with a
fixed rate of 432M and parent the RX and TX clocks to it.
This works on both QM and QXP.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi index b1d7b9c5ac82..e6ccbdbb3f43 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi @@ -18,6 +18,13 @@ clock-output-names = "mipi_ipg_clk"; }; + mipi_pll_div2_clk: clock-mipi-div2-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <432000000>; + clock-output-names = "mipi_pll_div2_clk"; + }; + mipi0_lis_lpcg: clock-controller@56223000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x56223000 0x4>; @@ -223,9 +230,13 @@ "phy_ref", "tx_esc", "rx_esc"; - assigned-clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>, + assigned-clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>, <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>; - assigned-clock-rates = <18000000>, <72000000>; + assigned-clock-parents = <&mipi_pll_div2_clk>, + <&mipi_pll_div2_clk>, + <&mipi_pll_div2_clk>; + assigned-clock-rates = <0>, <18000000>, <72000000>; interrupts = <16>; interrupt-parent = <&irqsteer_mipi_lvds0>; power-domains = <&pd IMX_SC_R_MIPI_0>; @@ -385,9 +396,13 @@ "phy_ref", "tx_esc", "rx_esc"; - assigned-clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>, + assigned-clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>, <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>; - assigned-clock-rates = <18000000>, <72000000>; + assigned-clock-parents = <&mipi_pll_div2_clk>, + <&mipi_pll_div2_clk>, + <&mipi_pll_div2_clk>; + assigned-clock-rates = <0>, <18000000>, <72000000>; interrupts = <16>; interrupt-parent = <&irqsteer_mipi_lvds1>; power-domains = <&pd IMX_SC_R_MIPI_1>; |