diff options
| author | Liu Ying <victor.liu@nxp.com> | 2019-11-14 16:02:11 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:10:05 +0800 |
| commit | 2ff0f55f2f399e3eaec860776b926c998f8bf366 (patch) | |
| tree | 95ca7807b469c3cef0338cc7bddf35f90741a9ef /arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi | |
| parent | bcb66a5be4a619e531cb016c1093e582274d257f (diff) | |
arm64: imx8qxp-ss-lvds.dtsi: Add mipi0/1_pwm_lpcg clocks support
This patch adds mipi0/1_pwm_lpcg clocks support for
i.MX8QXP MIPI DSI/LVDS subsystem device tree.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi index ea1ab05a864b..f75d2584e000 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi @@ -28,6 +28,20 @@ power-domains = <&pd IMX_SC_R_MIPI_0>; }; + mipi0_pwm_lpcg: clock-controller@5622300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5622300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>, + <&mipi_ipg_clk>; + bit-offset = <0 16 4>; + clock-output-names = "mipi0_pwm_lpcg_clk", + "mipi0_pwm_lpcg_ipg_clk", + "mipi0_pwm_lpcg_32k_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>; + }; + mipi0_i2c0_lpcg: clock-controller@56223010 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x56223010 0x4>; @@ -50,6 +64,20 @@ power-domains = <&pd IMX_SC_R_MIPI_1>; }; + mipi1_pwm_lpcg: clock-controller@5624300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5624300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>, + <&mipi_ipg_clk>; + bit-offset = <0 16 4>; + clock-output-names = "mipi1_pwm_lpcg_clk", + "mipi1_pwm_lpcg_ipg_clk", + "mipi1_pwm_lpcg_32k_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; + }; + mipi1_i2c0_lpcg: clock-controller@56243010 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x56243010 0x4>; |