diff options
| author | Robert Chiras <robert.chiras@nxp.com> | 2019-11-27 17:48:59 +0200 |
|---|---|---|
| committer | Robert Chiras <robert.chiras@nxp.com> | 2019-11-28 17:22:30 +0200 |
| commit | 48df7dc20ced7686e950a8a0eabaa5f69ff2eed7 (patch) | |
| tree | 0b1badea95d34652dc365217a7335a0982259d0d /arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi | |
| parent | 60b1ead90c75eb2cfb1fae6f07bc6ca4abb6f357 (diff) | |
arm64: dts: imx8qxp: Add mipi dsi nodes
Add dts file for mipi dsi nodes and the corresponding endpoints.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi | 113 |
1 files changed, 111 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi index d3d4719c5f68..af6338e30c4e 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi @@ -186,7 +186,7 @@ i2c0_mipi_lvds0: i2c@56226000 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x56226000 0x4000>; + reg = <0x56226000 0x1000>; interrupts = <8>; interrupt-parent = <&irqsteer_mipi_lvds0>; clocks = <&mipi0_i2c0_lpcg 0>, @@ -198,6 +198,60 @@ status = "disabled"; }; + mipi0_dphy: dphy@56228300 { + compatible = "fsl,imx8qm-mipi-dphy"; + reg = <0x56228300 0x100>; + clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + status = "disabled"; + }; + + mipi0_dsi_host: dsi_host@56228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qx-nwl-dsi"; + reg = <0x56228000 0x300>; + clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>; + clock-names = "pixel", + "bypass", + "phy_ref", + "tx_esc", + "rx_esc"; + assigned-clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>; + assigned-clock-rates = <18000000>, <72000000>; + interrupts = <16>; + interrupt-parent = <&irqsteer_mipi_lvds0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + phys = <&mipi0_dphy>; + phy-names = "dphy"; + csr = <&lvds_region1>; + use-disp-ss; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + mipi0_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpu_disp0_mipi_dsi>; + }; + }; + }; + }; + irqsteer_mipi_lvds1: irqsteer@56240000 { compatible = "fsl,imx-irqsteer"; reg = <0x56240000 0x1000>; @@ -294,7 +348,7 @@ i2c0_mipi_lvds1: i2c@56246000 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x56246000 0x4000>; + reg = <0x56246000 0x1000>; interrupts = <8>; interrupt-parent = <&irqsteer_mipi_lvds1>; clocks = <&mipi1_i2c0_lpcg 0>, @@ -305,5 +359,60 @@ power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; status = "disabled"; }; + + mipi1_dphy: dphy@56248300 { + compatible = "fsl,imx8qx-mipi-dphy"; + reg = <0x56248300 0x100>; + clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + status = "disabled"; + }; + + mipi1_dsi_host: dsi_host@56248000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qx-nwl-dsi"; + reg = <0x56248000 0x300>; + clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>; + clock-names = "pixel", + "bypass", + "phy_ref", + "tx_esc", + "rx_esc"; + assigned-clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>; + assigned-clock-rates = <18000000>, <72000000>; + interrupts = <16>; + interrupt-parent = <&irqsteer_mipi_lvds1>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + phys = <&mipi1_dphy>; + phy-names = "dphy"; + csr = <&lvds_region2>; + use-disp-ss; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + mipi1_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpu_disp1_mipi_dsi>; + }; + }; + }; + }; + }; }; |