diff options
| author | Liu Ying <victor.liu@nxp.com> | 2020-03-27 16:24:42 +0800 |
|---|---|---|
| committer | Liu Ying <victor.liu@nxp.com> | 2020-04-10 15:23:57 +0800 |
| commit | e15cfc057d95ea52669cd8c46cee12ea20b38a35 (patch) | |
| tree | f66e10777fa0ffea7015db524a9273f1d841af41 /arch/arm64/boot/dts/freescale/imx8x-mek.dtsi | |
| parent | 64b07f682ba45f0fda3b716afe673c9b5a72bc19 (diff) | |
LF-1189-11 arm64: dts: imx8qxp-mek: Add LCDIF pinctrl
This patch adds all pinctrl settings for LCDIF to send
out parallel display signals to externel display device.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8x-mek.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8x-mek.dtsi | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi index 9b2ed9e87e07..732639cf9271 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi @@ -1459,4 +1459,31 @@ >; }; + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x00000060 + IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x00000060 + IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x00000060 + IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x00000060 + IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x00000060 + IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x00000060 + IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x00000060 + IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x00000060 + IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x00000060 + IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x00000060 + IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x00000060 + IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x00000060 + IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x00000060 + IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x00000060 + IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x00000060 + IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x00000060 + IMX8QXP_UART1_RTS_B_ADMA_LCDIF_D16 0x00000060 + IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x00000060 + IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x00000060 + IMX8QXP_SPI3_CS1_ADMA_LCDIF_RESET 0x00000060 + IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x00000060 + IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x00000060 + IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x00000060 + >; + }; }; |