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| author | Mihaela Martinas <Mihaela.Martinas@freescale.com> | 2015-09-17 18:52:09 +0300 |
|---|---|---|
| committer | Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com> | 2019-11-29 11:42:56 +0200 |
| commit | 58b9c9e00e30deb2a8a2f379134432914a5f14cf (patch) | |
| tree | 12a69693fc984b1546be461a1f1804e96899ab35 /arch/arm64/boot/dts/freescale/s32v234-sbc.dts | |
| parent | 38395e17e73da43430fee47cb6ce7a582f618c69 (diff) | |
arm64: dts: s32v234-evb: Use macros for MSCR and config pairs
Make use of the new macros defined in s32v234-pinctrl.h. The MSCR
numbers will no longer be hardcoded either.
Signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com>
Signed-off-by: Catalin Udma <catalin-dan.udma@nxp.com>
Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/s32v234-sbc.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/s32v234-sbc.dts | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/arch/arm64/boot/dts/freescale/s32v234-sbc.dts b/arch/arm64/boot/dts/freescale/s32v234-sbc.dts index 7997556164ec..aba08280e2da 100644 --- a/arch/arm64/boot/dts/freescale/s32v234-sbc.dts +++ b/arch/arm64/boot/dts/freescale/s32v234-sbc.dts @@ -76,42 +76,42 @@ pinctrl_uart0: uart0grp { fsl,pins = < - 12 PAD_CTL_UART_TX - 11 PAD_CTL_UART_RX_MSCR - 712 PAD_CTL_UART_RX_IMCR + S32V234_PAD_PA12__UART0_TXD + S32V234_PAD_PA11__UART0_RXD_OUT + S32V234_PAD_PA11__UART0_RXD_IN >; }; pinctrl_uart1: uart1grp { fsl,pins = < - 14 PAD_CTL_UART_TX - 13 PAD_CTL_UART_RX_MSCR - 714 PAD_CTL_UART_RX_IMCR + S32V234_PAD_PA14__UART1_TXD + S32V234_PAD_PA13__UART1_RXD_OUT + S32V234_PAD_PA13__UART1_RXD_IN >; }; pinctrl_usdhc0: usdhc0grp { fsl,pins = < - 150 PAD_CTL_USDHC_CLK - 902 PAD_CTL_MUX_MODE_ALT3 - 151 PAD_CTL_USDHC_CMD - 901 PAD_CTL_MUX_MODE_ALT3 - 152 PAD_CTL_USDHC_DAT0_3 - 903 PAD_CTL_MUX_MODE_ALT3 - 153 PAD_CTL_USDHC_DAT0_3 - 904 PAD_CTL_MUX_MODE_ALT3 - 154 PAD_CTL_USDHC_DAT0_3 - 905 PAD_CTL_MUX_MODE_ALT3 - 155 PAD_CTL_USDHC_DAT0_3 - 906 PAD_CTL_MUX_MODE_ALT3 - 159 PAD_CTL_USDHC_DAT4_7 - 907 PAD_CTL_MUX_MODE_ALT3 - 160 PAD_CTL_USDHC_DAT4_7 - 908 PAD_CTL_MUX_MODE_ALT3 - 161 PAD_CTL_USDHC_DAT4_7 - 909 PAD_CTL_MUX_MODE_ALT3 - 162 PAD_CTL_USDHC_DAT4_7 - 910 PAD_CTL_MUX_MODE_ALT3 + S32V234_PAD_PK6__USDHC_CLK_OUT + S32V234_PAD_PK6__USDHC_CLK_IN + S32V234_PAD_PK7__USDHC_CMD_OUT + S32V234_PAD_PK7__USDHC_CMD_IN + S32V234_PAD_PK8__USDHC_DAT0_OUT + S32V234_PAD_PK8__USDHC_DAT0_IN + S32V234_PAD_PK9__USDHC_DAT1_OUT + S32V234_PAD_PK9__USDHC_DAT1_IN + S32V234_PAD_PK10__USDHC_DAT2_OUT + S32V234_PAD_PK10__USDHC_DAT2_IN + S32V234_PAD_PK11__USDHC_DAT3_OUT + S32V234_PAD_PK11__USDHC_DAT3_IN + S32V234_PAD_PK15__USDHC_DAT4_OUT + S32V234_PAD_PK15__USDHC_DAT4_IN + S32V234_PAD_PL0__USDHC_DAT5_OUT + S32V234_PAD_PL0__USDHC_DAT5_IN + S32V234_PAD_PL1__USDHC_DAT6_OUT + S32V234_PAD_PL1__USDHC_DAT6_IN + S32V234_PAD_PL2__USDHC_DAT7_OUT + S32V234_PAD_PL2__USDHC_DAT7_IN >; }; }; |