Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM 64-bit DT updates from Olof Johansson:
 "This is the first release where we split up the 64-bit contributions a
  bit more, and in particular we are having a separate DT branch for
  them.

  Contents:

   - New devices added to Broadcom NorthStar2
   - Misc fixes for Exynos7 boards
   - QCOM updates for MSM8916
   - Rockchip tweaks for rk3368 SoC and eval board
   - A series of fixes for APM X-Gene v1 and v2
   - Renesas R8A7795 CPU/PSCI additions
   - Marvell Berlin4CT PSCI, cpuidle, watchdog portions
   - Freescale LS1043a SoC and dev board support

  + some treewide or other misc changes"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (104 commits)
  dts/ls2080a: Update DTSI to add support of SP805 WDT
  Documentation: DT: Add entry for ARM SP805-WDT
  arm64: dts: X-Gene v2: I2C1 clock is always on
  arm64: dts: X-Gene v1: I2C0 clock is always on
  arm64: dts: Fix to use standard DT node names for X-Gene 1 and X-Gene 2 platforms
  arm64: dts: hikey: add label properties to UARTs
  arm64: dts: apq8016-sbc: add label properties for UART, I2C, and SPI
  arm64: dts: apq8016-sbc: enable UART0 on LS connector
  arm64: dts: juno: Add idle-states to device tree
  arm64: dts: Added syscon-reboot node for FSL's LS2080A SoC
  arm64: dts: add LS1043a-RDB board support
  arm64: dts: add Freescale LS1043a SoC support
  Documentation: DT: Add entry for Freescale LS1043a-RDB board
  arm64: dts: uniphier: add PH1-LD10 SoC/board support
  arm64: renesas: r8a7795: fix SATA clock assignment
  arm64: dts: salvator-x: Enable SATA controller
  arm64: dts: r8a7795: Add SATA controller node
  arm64: renesas: r8a7795: add internal delay for i2c IPs
  arm64: renesas: salvator-x: Add board part number to DT bindings
  arm64: dts: r8a7795: Add pmu device nodes
  ...

2 files changed, 45 insertions, 1 deletions

diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 9b1482a1d007..e427f04a9f45 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -102,6 +102,13 @@
 };
 
 &pio {
+	disp_pwm0_pins: disp_pwm0_pins {
+		pins1 {
+			pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
+			output-low;
+		};
+	};
+
 	mmc0_pins_default: mmc0default {
 		pins_cmd_dat {
 			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
@@ -200,6 +207,12 @@
 	};
 };
 
+&pwm0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&disp_pwm0_pins>;
+	status = "okay";
+};
+
 &pwrap {
 	pmic: mt6397 {
 		compatible = "mediatek,mt6397";
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 424a4939c1b4..ec135eae31f5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -96,7 +96,7 @@
 	};
 
 	psci {
-		compatible = "arm,psci";
+		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
 		method = "smc";
 		cpu_suspend   = <0x84000001>;
 		cpu_off	      = <0x84000002>;
@@ -248,6 +248,15 @@
 			reg = <0 0x10007000 0 0x100>;
 		};
 
+		timer: timer@10008000 {
+			compatible = "mediatek,mt8173-timer",
+				     "mediatek,mt6577-timer";
+			reg = <0 0x10008000 0 0x1000>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&infracfg CLK_INFRA_CLK_13M>,
+				 <&topckgen CLK_TOP_RTC_SEL>;
+		};
+
 		pwrap: pwrap@1000d000 {
 			compatible = "mediatek,mt8173-pwrap";
 			reg = <0 0x1000d000 0 0x1000>;
@@ -558,6 +567,28 @@
 			#clock-cells = <1>;
 		};
 
+		pwm0: pwm@1401e000 {
+			compatible = "mediatek,mt8173-disp-pwm",
+				     "mediatek,mt6595-disp-pwm";
+			reg = <0 0x1401e000 0 0x1000>;
+			#pwm-cells = <2>;
+			clocks = <&mmsys CLK_MM_DISP_PWM026M>,
+				 <&mmsys CLK_MM_DISP_PWM0MM>;
+			clock-names = "main", "mm";
+			status = "disabled";
+		};
+
+		pwm1: pwm@1401f000 {
+			compatible = "mediatek,mt8173-disp-pwm",
+				     "mediatek,mt6595-disp-pwm";
+			reg = <0 0x1401f000 0 0x1000>;
+			#pwm-cells = <2>;
+			clocks = <&mmsys CLK_MM_DISP_PWM126M>,
+				 <&mmsys CLK_MM_DISP_PWM1MM>;
+			clock-names = "main", "mm";
+			status = "disabled";
+		};
+
 		imgsys: clock-controller@15000000 {
 			compatible = "mediatek,mt8173-imgsys", "syscon";
 			reg = <0 0x15000000 0 0x1000>;