summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/xilinx
diff options
context:
space:
mode:
authorMichal Simek <michal.simek@xilinx.com>2016-08-09 15:13:02 +0200
committerMichal Simek <michal.simek@xilinx.com>2016-08-19 12:29:10 +0200
commit78b83b8cb34f610bc88abe5699426833664f4597 (patch)
tree3e7166a0a7ba44f67a4e5797ded153ffaab53055 /arch/arm64/boot/dts/xilinx
parent7393fd869119e39184fe519ed8b1e61346662032 (diff)
ARM64: zynqmp: Add PCIe node
Add PCIe node with prefetchable memory which goes beyond 4GB. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm64/boot/dts/xilinx')
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp.dtsi39
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index d24014765111..fbdd6ab98988 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -193,6 +193,45 @@
#size-cells = <0>;
};
+ pcie: pcie@fd0e0000 {
+ compatible = "xlnx,nwl-pcie-2.11";
+ status = "disabled";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ msi-controller;
+ device_type = "pci";
+ interrupt-parent = <&gic>;
+ interrupts = <0 118 4>,
+ <0 117 4>,
+ <0 116 4>,
+ <0 115 4>, /* MSI_1 [63...32] */
+ <0 114 4>; /* MSI_0 [31...0] */
+ interrupt-names = "misc", "dummy", "intx",
+ "msi1", "msi0";
+ msi-parent = <&pcie>;
+ reg = <0x0 0xfd0e0000 0x0 0x1000>,
+ <0x0 0xfd480000 0x0 0x1000>,
+ <0x80 0x00000000 0x0 0x1000000>;
+ reg-names = "breg", "pcireg", "cfg";
+ ranges = <0x02000000 0x00000000 0xe0000000 0x00000000
+ 0xe0000000 0x00000000 0x10000000
+ /* non-prefetchable memory */
+ 0x43000000 0x00000006 0x00000000 0x00000006
+ 0x00000000 0x00000002 0x00000000>;
+ /* prefetchable memory */
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
+ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
+ <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
+ <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
+ pcie_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
sata: ahci@fd0c0000 {
compatible = "ceva,ahci-1v84";
status = "disabled";