diff options
| author | Nitin Garg <nitin.garg@nxp.com> | 2019-12-04 19:03:59 -0600 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2019-12-11 13:58:36 +0800 |
| commit | 7ae82f64e9648cca0e3c9f59a678b80138d251e1 (patch) | |
| tree | fe3137eccf0bb05a5a74927dc0303381caef3e05 /arch/arm64/kvm | |
| parent | faee6309301eb0e0866e7e3a0df3f7747f38bbd5 (diff) | |
LF-363 arm64: kernel: TKT340553 Errata workaround update for i.MX8QM
As per latest i.MX8QM SOC Errata, TKT340553 workaround needs to be
updated to unconditionally downgrade TLB operations and instruction
cache maintenance.
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm64/kvm')
| -rw-r--r-- | arch/arm64/kvm/hyp/tlb.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index eb0efc5557f3..6a109156681c 100644 --- a/arch/arm64/kvm/hyp/tlb.c +++ b/arch/arm64/kvm/hyp/tlb.c @@ -16,6 +16,8 @@ struct tlb_inv_context { u64 sctlr; }; +extern bool TKT340553_SW_WORKAROUND; + static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm, struct tlb_inv_context *cxt) { @@ -126,8 +128,12 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) * Instead, we invalidate Stage-2 for this IPA, and the * whole of Stage-1. Weep... */ - ipa >>= 12; - __tlbi(ipas2e1is, ipa); + if (TKT340553_SW_WORKAROUND) { + __tlbi(vmalls12e1is); + } else { + ipa >>= 12; + __tlbi(ipas2e1is, ipa); + } /* * We have to ensure completion of the invalidation at Stage-2, |