diff options
| author | Zihao Yu <yuzihao@ict.ac.cn> | 2021-03-17 16:17:25 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-04-16 11:46:38 +0200 |
| commit | 2d71bffbe9a0f2b25d4ba03df21bddd5dbdfa9cc (patch) | |
| tree | 5223c77df0dcf06f126665a5905e902de7aac1d6 /arch/riscv | |
| parent | 90b71ae8e5cf8b868b6a4de55c3cdf878cedfee3 (diff) | |
riscv,entry: fix misaligned base for excp_vect_table
[ Upstream commit ac8d0b901f0033b783156ab2dc1a0e73ec42409b ]
In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
base of the table is not 8-byte aligned, loading an entry in the table
will raise a misaligned exception. Although such exception will be
handled by opensbi/bbl, this still causes performance degradation.
Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/kernel/entry.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 8ca479831142..9c87ae77ad5d 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -387,6 +387,7 @@ ENTRY(__switch_to) ENDPROC(__switch_to) .section ".rodata" + .align LGREG /* Exception vector table */ ENTRY(excp_vect_table) RISCV_PTR do_trap_insn_misaligned |