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authorDmitry Osipenko <digetx@gmail.com>2019-04-12 01:12:48 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2019-05-25 18:26:49 +0200
commit6f0d9b0b5ec1076be6c70878500a316ddcdb0a14 (patch)
tree5a2348f7cd525d480c4bc0bdb3a0fb6cef7134e2 /drivers/memory
parent17fe9003ffccd0f7b26f9935cc1d60d0bf2bdc12 (diff)
memory: tegra: Fix integer overflow on tick value calculation
commit b906c056b6023c390f18347169071193fda57dde upstream. Multiplying the Memory Controller clock rate by the tick count results in an integer overflow and in result the truncated tick value is being programmed into hardware, such that the GR3D memory client performance is reduced by two times. Cc: stable <stable@vger.kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/memory')
-rw-r--r--drivers/memory/tegra/mc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index 1d49a8dd4a37..7c040a3b45be 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -72,7 +72,7 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
u32 value;
/* compute the number of MC clock cycles per tick */
- tick = mc->tick * clk_get_rate(mc->clk);
+ tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);
do_div(tick, NSEC_PER_SEC);
value = readl(mc->regs + MC_EMEM_ARB_CFG);