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authorRichard Zhu <hongxing.zhu@nxp.com>2020-10-19 16:13:47 +0800
committerRichard Zhu <hongxing.zhu@nxp.com>2020-10-20 12:12:40 +0800
commit6e8f69523e69aef6187b96868143128f65eadc70 (patch)
tree516cf2356ef996dbf1b3d5377f29ff92a5af1ea3 /drivers/pci/controller/dwc/pci-imx6.c
parent98d2a8d1486bc990a96c92fe02d9c96968f4e257 (diff)
MLK-24901 PCI: imx: use ep mem windown to setup the alignment
EP has it's own memory windown alignment, use it to refine the EP/RC validation codes. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'drivers/pci/controller/dwc/pci-imx6.c')
-rw-r--r--drivers/pci/controller/dwc/pci-imx6.c21
1 files changed, 2 insertions, 19 deletions
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 099dacf62d0b..e60c95615ce6 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1914,29 +1914,11 @@ static int imx6_pcie_host_init(struct pcie_port *pp)
if (gpio_is_valid(imx6_pcie->dis_gpio))
gpio_set_value_cansleep(imx6_pcie->dis_gpio, 1);
-
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- /*
- * Configure the msi_data to 64Kbytes alignment, since
- * the 64Kbytes alignment are mandatory required by some
- * iMX PCIe inbound/outbound regions.
- */
- pp->msi_data = (u64)(pp->cfg1_base + pp->cfg1_size);
- if (pp->io)
- pp->msi_data += pp->io_size;
- if (pp->msi_data & (SZ_64K - 1))
- pp->msi_data = ALIGN(pp->msi_data, SZ_64K);
- /* Program the msi_data */
- dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO,
- lower_32_bits(pp->msi_data));
- dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI,
- upper_32_bits(pp->msi_data));
- }
-
dw_pcie_setup_rc(pp);
pci_imx_set_msi_en(pp);
if (imx6_pcie_establish_link(imx6_pcie))
return -ENODEV;
+ dw_pcie_msi_init(pp);
return 0;
}
@@ -2132,6 +2114,7 @@ static int __init imx_add_pcie_ep(struct imx6_pcie *imx6_pcie,
ep->phys_base = res->start;
ep->addr_size = resource_size(res);
+ ep->page_size = SZ_64K;
ret = dw_pcie_ep_init(ep);
if (ret) {