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authorRichard Zhu <hongxing.zhu@nxp.com>2020-10-22 15:26:10 +0800
committerRichard Zhu <hongxing.zhu@nxp.com>2020-10-26 11:39:30 +0800
commit801c87e9fd7f63a6c225c852e2ab0e635335f356 (patch)
treed92b5a6f76d5b65747fe50eb0bdb40fe6715605f /drivers/pci/controller/dwc/pci-imx6.c
parent06d81e69ddc3b37863fd343f8b6775f5402c5ecf (diff)
MLK-24910-2 PCI: imx: refine pcie driver
pci imx set the dbi_wr_en when re-configure the link gen Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'drivers/pci/controller/dwc/pci-imx6.c')
-rw-r--r--drivers/pci/controller/dwc/pci-imx6.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index db979ecfe4ac..b1c2e78d14ae 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1799,6 +1799,7 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
u32 tmp;
int ret;
+ dw_pcie_dbi_ro_wr_en(pci);
/*
* Force Gen1 operation when starting the link. In case the link is
* started in Gen2 mode, there is a possibility the devices on the
@@ -1870,11 +1871,13 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
dev_info(dev, "Link: Gen2 disabled\n");
}
+ dw_pcie_dbi_ro_wr_dis(pci);
tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
return 0;
err_reset_phy:
+ dw_pcie_dbi_ro_wr_dis(pci);
dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));