diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-03-06 11:14:27 +0800 |
|---|---|---|
| committer | Richard Zhu <hongxing.zhu@nxp.com> | 2020-03-06 15:25:10 +0800 |
| commit | 904c984a8d028f5f8649e636de5c4bc6b6198cf8 (patch) | |
| tree | e558e25cf4e74fdd969abc1f756dd38ce2c999e5 /drivers/pci/controller/dwc/pci-imx6.c | |
| parent | ef965379100fd7ca90372c8875fb98caab3aff9e (diff) | |
LF-1088 PCI: imx: pcie rc can't access ep's memory
RC can't access EP's DDR memory on i.MX8MQ/i.MX8MM platforms.
Rootcause: The BAR# of EP are not configured correct.
The BAR# offset is 1Mbytes on i.MX8MQ/i.MX8MM, but is 4Kbytes on
other i.MX platforms(e.x 6/7/8QM/8QXP/8MP).
Correct the BAR# access offset on i.MX8MQ/i.MX8MM to fix it.
Let DBI always be writeable in EP/RC validation system.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'drivers/pci/controller/dwc/pci-imx6.c')
| -rw-r--r-- | drivers/pci/controller/dwc/pci-imx6.c | 28 |
1 files changed, 19 insertions, 9 deletions
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index a74e77f06de5..a20015efdfde 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1777,6 +1777,8 @@ static void imx6_pcie_regions_setup(struct device *dev) struct dw_pcie *pci = imx6_pcie->pci; struct pcie_port *pp = &pci->pp; + dw_pcie_dbi_ro_wr_en(pci); + switch (imx6_pcie->drvdata->variant) { case IMX8QM: case IMX8QXP: @@ -1817,7 +1819,7 @@ static struct attribute_group imx6_pcie_attrgroup = { .attrs = imx6_pcie_ep_attrs, }; -static void imx6_pcie_setup_ep(struct dw_pcie *pci) +static void imx6_pcie_setup_ep(struct dw_pcie *pci, unsigned int bar_offset) { int ret; u32 val; @@ -1884,16 +1886,16 @@ static void imx6_pcie_setup_ep(struct dw_pcie *pci) /* 32bit none-prefetchable 8M bytes memory on bar0 */ writel(0x0, pci->dbi_base + PCI_BASE_ADDRESS_0); - writel(SZ_8M - 1, pci->dbi_base + (1 << 12) + writel(SZ_8M - 1, pci->dbi_base + bar_offset + PCI_BASE_ADDRESS_0); /* None used bar1 */ writel(0x0, pci->dbi_base + PCI_BASE_ADDRESS_1); - writel(0, pci->dbi_base + (1 << 12) + PCI_BASE_ADDRESS_1); + writel(0, pci->dbi_base + bar_offset + PCI_BASE_ADDRESS_1); /* 4K bytes IO on bar2 */ writel(0x1, pci->dbi_base + PCI_BASE_ADDRESS_2); - writel(SZ_4K - 1, pci->dbi_base + (1 << 12) + + writel(SZ_4K - 1, pci->dbi_base + bar_offset + PCI_BASE_ADDRESS_2); /* @@ -1902,7 +1904,7 @@ static void imx6_pcie_setup_ep(struct dw_pcie *pci) * is fixed to 256 bytes. */ writel(0x8, pci->dbi_base + PCI_BASE_ADDRESS_3); - writel(SZ_1M - 1, pci->dbi_base + (1 << 12) + writel(SZ_1M - 1, pci->dbi_base + bar_offset + PCI_BASE_ADDRESS_3); /* @@ -1910,9 +1912,9 @@ static void imx6_pcie_setup_ep(struct dw_pcie *pci) * FIXME BAR4,5 are not enabled yet */ writel(0xc, pci->dbi_base + PCI_BASE_ADDRESS_4); - writel(SZ_1M - 1, pci->dbi_base + (1 << 12) + writel(SZ_1M - 1, pci->dbi_base + bar_offset + PCI_BASE_ADDRESS_4); - writel(0, pci->dbi_base + (1 << 12) + PCI_BASE_ADDRESS_5); + writel(0, pci->dbi_base + bar_offset + PCI_BASE_ADDRESS_5); } static irqreturn_t imx6_pcie_dma_isr(int irq, void *param) @@ -2555,11 +2557,19 @@ static int imx6_pcie_probe(struct platform_device *pdev) } dw_pcie_dbi_ro_wr_en(pci); - imx6_pcie_setup_ep(pci); + switch (imx6_pcie->drvdata->variant) { + case IMX8MQ: + case IMX8MM: + case IMX8MP: + imx6_pcie_setup_ep(pci, SZ_1M); + break; + default: + imx6_pcie_setup_ep(pci, SZ_4K); + break; + } pci_imx_set_msi_en(pp); platform_set_drvdata(pdev, imx6_pcie); imx6_pcie_regions_setup(dev); - dw_pcie_dbi_ro_wr_dis(pci); /* * iMX6SX PCIe has the stand-alone power domain. |