diff options
| author | Fancy Fang <chen.fang@nxp.com> | 2019-03-17 12:16:26 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 15:59:56 +0800 |
| commit | 2a0fed9fbbb0f5ff30758f43709e6378ff76c6ad (patch) | |
| tree | 93dc804d5a5e0ba39861eb5d5c763014aa468ed3 /include/drm | |
| parent | a087a95aa2ce963e64b8f36c267b011ebe8cd842 (diff) | |
MLK-21150-4 drm/bridge: sec-dsim: a general way to compute PLL PMS
A fixed PLL PMS setting for attached panel is obviously not
enough for any other mipi panel which needs a different PLL
output clock frequency, and besides, for the CEA-861 standard
display modes, the 'pll_pms' table also can not cover all the
modes requirements. So a general way is created to solve this
problem which can provide an optimum solution to output a PLL
bit clock to match the request frequency in a maximum degree
and also satisfy the input clock and intermediate clocks limit
according to the PLL specification.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Diffstat (limited to 'include/drm')
| -rw-r--r-- | include/drm/bridge/sec_mipi_dsim.h | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/include/drm/bridge/sec_mipi_dsim.h b/include/drm/bridge/sec_mipi_dsim.h index 2b125b26b675..2f9233563ee6 100644 --- a/include/drm/bridge/sec_mipi_dsim.h +++ b/include/drm/bridge/sec_mipi_dsim.h @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2019 NXP * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,6 +19,7 @@ #include <linux/bsearch.h> struct sec_mipi_dsim_dphy_timing; +struct sec_mipi_dsim_pll; struct sec_mipi_dsim_plat_data { uint32_t version; @@ -26,11 +27,28 @@ struct sec_mipi_dsim_plat_data { uint64_t max_data_rate; const struct sec_mipi_dsim_dphy_timing *dphy_timing; uint32_t num_dphy_timing; + const struct sec_mipi_dsim_pll *dphy_pll; int (*dphy_timing_cmp)(const void *key, const void *elt); enum drm_mode_status (*mode_valid)(struct drm_connector *connector, struct drm_display_mode *mode); }; +/* DPHY PLL structure */ +struct sec_mipi_dsim_range { + uint32_t min; + uint32_t max; +}; + +struct sec_mipi_dsim_pll { + struct sec_mipi_dsim_range p; + struct sec_mipi_dsim_range m; + struct sec_mipi_dsim_range s; + struct sec_mipi_dsim_range k; + struct sec_mipi_dsim_range fin; + struct sec_mipi_dsim_range fpref; + struct sec_mipi_dsim_range fvco; +}; + /* DPHY timings structure */ struct sec_mipi_dsim_dphy_timing { uint32_t bit_clk; /* MHz */ |