diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2019-12-24 18:19:33 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2019-12-26 10:28:09 +0800 |
| commit | a904ae5784cd879996288f6d20e142f58b00b83a (patch) | |
| tree | 25d206de535ce991fcf53eaec9ed4ce97da0f1cb /include/dt-bindings | |
| parent | 3f72ffaa34d2ddba4b71e4e1b408c597265bf0ab (diff) | |
MLK-23159-9 arm64: dts: freescale: Add i.MX8MP basic DT support
Add i.MX8MP SoC & board basic DT support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Ella Feng<ella.feng@nxp.com>
Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/reset/imx8mp-mediamix.h | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/imx8mp-mediamix.h b/include/dt-bindings/reset/imx8mp-mediamix.h new file mode 100644 index 000000000000..c63eab069887 --- /dev/null +++ b/include/dt-bindings/reset/imx8mp-mediamix.h @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#ifndef __IMX8MP_MEDIAMIX_H___ +#define __IMX8MP_MEDIAMIX_H___ + +/* MEDIAMIX soft reset */ +#define IMX8MP_MIPI_DSI_PCLK_RESET 0 +#define IMX8MP_MIPI_DSI_CLKREF_RESET 1 +#define IMX8MP_MIPI_CSI_PCLK_RESET 2 +#define IMX8MP_MIPI_CSI_ACLK_RESET 3 +#define IMX8MP_LCDIF_PIXEL_CLK_RESET 4 +#define IMX8MP_LCDIF_APB_CLK_RESET 5 +#define IMX8MP_ISI_PROC_CLK_RESET 6 +#define IMX8MP_ISI_APB_CLK_RESET 7 +#define IMX8MP_BUS_BLK_CLK_RESET 8 +#define IMX8MP_MIPI_CSI2_PCLK_RESET 9 +#define IMX8MP_MIPI_CSI2_ACLK_RESET 10 +#define IMX8MP_LCDIF2_PIXEL_CLK_RESET 11 +#define IMX8MP_LCDIF2_APB_CLK_RESET 12 +#define IMX8MP_ISP_CORE_CLK_RESET 13 +#define IMX8MP_ISP_AXI_CLK_RESET 14 +#define IMX8MP_ISP_AHB_CLK_RESET 15 +#define IMX8MP_DWE_CORE_CLK_RESET 16 +#define IMX8MP_DWE_AXI_CLK_RESET 17 +#define IMX8MP_DWE_AHB_CLK_RESET 18 +#define IMX8MP_MIPI_DSI2_CLKREF_RESET 19 +#define IMX8MP_LCDIF_AXI_CLK_RESET 20 +#define IMX8MP_LCDIF2_AXI_CLK_RESET 21 +#define IMX8MP_MEDIAMIX_SFT_RSTN_NUM 22 + +/* MEDIAMIX clock soft enable */ +#define IMX8MP_MIPI_DSI_PCLK_EN 0 +#define IMX8MP_MIPI_DSI_CLKREF_EN 1 +#define IMX8MP_MIPI_CSI_PCLK_EN 2 +#define IMX8MP_MIPI_CSI_ACLK_EN 3 +#define IMX8MP_LCDIF_PIXEL_CLK_EN 4 +#define IMX8MP_LCDIF_APB_CLK_EN 5 +#define IMX8MP_ISI_PROC_CLK_EN 6 +#define IMX8MP_ISI_APB_CLK_EN 7 +#define IMX8MP_BUS_BLK_CLK_EN 8 +#define IMX8MP_MIPI_CSI2_PCLK_EN 9 +#define IMX8MP_MIPI_CSI2_ACLK_EN 10 +#define IMX8MP_LCDIF2_PIXEL_CLK_EN 11 +#define IMX8MP_LCDIF2_APB_CLK_EN 12 +#define IMX8MP_ISP_CORE_CLK_EN 13 +#define IMX8MP_ISP_AXI_CLK_EN 14 +#define IMX8MP_ISP_AHB_CLK_EN 15 +#define IMX8MP_DWE_CORE_CLK_EN 16 +#define IMX8MP_DWE_AXI_CLK_EN 17 +#define IMX8MP_DWE_AHB_CLK_EN 18 +#define IMX8MP_MIPI_DSI2_CLKREF 19 +#define IMX8MP_LCDIF_AXI_CLK 20 +#define IMX8MP_LCDIF2_AXI_CLK 21 +#define IMX8MP_MEDIAMIX_CLK_EN_NUM 22 + +/* MIPI reset */ +#define IMX8MP_MIPI_S_RESET 0 +#define IMX8MP_MIPI_M_RESET 1 +#define IMX8MP_MIPI_S2_RESET 2 +#define IMX8MP_MIPI_M2_RESET 3 +#define IMX8MP_MIPI_RESET_NUM 4 + +#endif /* __IMX8MP_MEDIAMIX_H___ */ |