Merge remote-tracking branch 'origin/clock/s32' into clock/next

* origin/clock/s32: (9 commits)
  clk: s32v234: Enable FlexCAN clock
  clk: s32v234: Add definitions for CAN clocks
  clk: s32v234: Initial enet clk support
  clk: s32v234: Add dfs clk
  clk: Enable SDHC clock for S32V234
  ...

1 files changed, 65 insertions, 0 deletions

diff --git a/include/dt-bindings/clock/s32v234-clock.h b/include/dt-bindings/clock/s32v234-clock.h
new file mode 100644
index 000000000000..1ddfae5c1422
--- /dev/null
+++ b/include/dt-bindings/clock/s32v234-clock.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_S32V234_H
+#define __DT_BINDINGS_CLOCK_S32V234_H
+
+#define	S32V234_CLK_DUMMY			0
+#define	S32V234_CLK_FXOSC			1
+#define	S32V234_CLK_FIRC			2
+/* PERIPH PLL */
+#define	S32V234_CLK_PERIPHPLL_SRC_SEL		3
+#define	S32V234_CLK_PERIPHPLL_VCO		4
+#define	S32V234_CLK_PERIPHPLL_PHI0		5
+#define	S32V234_CLK_PERIPHPLL_PHI0_DIV3		6
+#define	S32V234_CLK_PERIPHPLL_PHI0_DIV5		7
+#define	S32V234_CLK_PERIPHPLL_PHI1		8
+/* LINFlexD Clock */
+#define	S32V234_CLK_LIN				9
+#define	S32V234_CLK_LIN_SEL			10
+#define	S32V234_CLK_LIN_IPG			11
+/* SDHC Clock */
+#define	S32V234_CLK_SDHC			12
+#define	S32V234_CLK_SDHC_SEL			13
+/* ENET PLL */
+#define	S32V234_CLK_ENETPLL_SRC_SEL		14
+#define	S32V234_CLK_ENETPLL_VCO			15
+#define	S32V234_CLK_ENETPLL_PHI0		16
+#define	S32V234_CLK_ENETPLL_PHI1		17
+#define	S32V234_CLK_ENETPLL_DFS0		18
+#define	S32V234_CLK_ENETPLL_DFS1		19
+#define	S32V234_CLK_ENETPLL_DFS2		20
+#define	S32V234_CLK_ENETPLL_DFS3		21
+/* System Clock */
+#define	S32V234_CLK_SYS_SEL			22
+#define	S32V234_CLK_SYS3			23
+#define	S32V234_CLK_SYS6			24
+#define	S32V234_CLK_SYS6_DIV2			25
+/* ENET Clock */
+#define	S32V234_CLK_ENET_TIME_DIV		26
+#define	S32V234_CLK_ENET_TIME_SEL		27
+#define	S32V234_CLK_ENET_DIV			28
+#define	S32V234_CLK_ENET_SEL			29
+
+#define	S32V234_CLK_ENET			30
+#define	S32V234_CLK_ENET_TIME			31
+
+/* ARM PLL */
+#define	S32V234_CLK_ARMPLL_SRC_SEL		32
+#define	S32V234_CLK_ARMPLL_VCO			33
+#define	S32V234_CLK_ARMPLL_PHI0			34
+#define	S32V234_CLK_ARMPLL_PHI1			35
+#define	S32V234_CLK_ARMPLL_DFS0			35
+#define	S32V234_CLK_ARMPLL_DFS1			36
+#define	S32V234_CLK_ARMPLL_DFS2			37
+
+/* CAN Clock */
+#define S32V234_CLK_CAN				38
+#define S32V234_CLK_CAN_SEL			39
+
+#define	S32V234_CLK_END				40
+
+#endif /* __DT_BINDINGS_CLOCK_S32V234_H */