diff options
| author | Joakim Zhang <qiangqing.zhang@nxp.com> | 2020-09-22 00:22:03 +0800 |
|---|---|---|
| committer | Joakim Zhang <qiangqing.zhang@nxp.com> | 2020-09-23 18:19:04 +0800 |
| commit | 40028973d39560bd09097bf015617ec1ade93eeb (patch) | |
| tree | c2fcdd150015a9ec20530db68659f414d5dc9d5c /tools | |
| parent | fcea4ac4b80e971c621742342a3864f1339f371b (diff) | |
MLK-24823 tools: perf: correct ddr bit width for i.MX8MN
The ddr bit width on i.MX8MN evk board is 16 bit, not 32 bit.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Diffstat (limited to 'tools')
| -rw-r--r-- | tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mn-ddr-uncore.json | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mn-ddr-uncore.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mn-ddr-uncore.json index 27d64e1cb76b..b7da56f7ce63 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mn-ddr-uncore.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mn-ddr-uncore.json @@ -3,7 +3,7 @@ "PublicDescription": "lpddr4 evk board bandwidth usage", "BriefDescription": "imx8mn: percentage of bandwidth usage for ddr0", "MetricName": "imx8mn-ddr0-bandwidth-usage-lpddr4", - "MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (800 * 1000000 * 4 * 4)", + "MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/) * 4 * 2 / duration_time) / (800 * 1000000 * 4 * 2)", "MetricGroup": "i.MX8MN_DDR_MON", "ScaleUnit": "1e2%", "SocName": "i.MX8MN" @@ -12,25 +12,25 @@ "PublicDescription": "ddr4 evk board bandwidth usage", "BriefDescription": "imx8mn: percentage of bandwidth usage for ddr0", "MetricName": "imx8mn-ddr0-bandwidth-usage-ddr4", - "MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (600 * 1000000 * 4 * 4)", + "MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/) * 4 * 2 / duration_time) / (600 * 1000000 * 4 * 2)", "MetricGroup": "i.MX8MN_DDR_MON", "ScaleUnit": "1e2%", "SocName": "i.MX8MN" }, { - "PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.", + "PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 2 bytes of each beat since DDR burst width is 16 bit.", "BriefDescription": "imx8mn: bytes of all masters read from ddr0", "MetricName": "imx8mn-ddr0-all-r", - "MetricExpr": "imx8_ddr0\\/read\\-cycles\\/ * 4 * 4", + "MetricExpr": "imx8_ddr0\\/read\\-cycles\\/ * 4 * 2", "MetricGroup": "i.MX8MN_DDR_MON", "SocName": "i.MX8MN" }, { - "PublicDescription": "Calculate bytes all masters write to DDR based on write-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.", + "PublicDescription": "Calculate bytes all masters write to DDR based on write-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 2 bytes of each beat since DDR burst width is 16 bit.", "BriefDescription": "imx8mn: bytes of all masters write to ddr0", "MetricName": "imx8mn-ddr0-all-w", - "MetricExpr": "imx8_ddr0\\/write\\-cycles\\/ * 4 * 4", + "MetricExpr": "imx8_ddr0\\/write\\-cycles\\/ * 4 * 2", "MetricGroup": "i.MX8MN_DDR_MON", "SocName": "i.MX8MN" } |