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| author | Joakim Zhang <qiangqing.zhang@nxp.com> | 2020-09-01 20:29:40 +0800 |
|---|---|---|
| committer | Joakim Zhang <qiangqing.zhang@nxp.com> | 2020-09-02 01:56:27 +0800 |
| commit | e80e6ddda63021eb44a3d7256911d7354337c444 (patch) | |
| tree | 6c6e861a960bc61d35e155d499a8b8e491e802f4 /tools | |
| parent | 1e43e235fb134e5a991854f0e1b724400028ea21 (diff) | |
MLK-24666-1 perf vendor: add JSON file for i.MX8MN DDR Perf
Add JSON file for i.MX8MN DDR Perf
Test Report:
---------------------------------------------------------------
root@imx8mnevk:~# ./perf list metric
List of pre-defined events (to be used in -e):
Metrics:
imx8mn-ddr0-all-r
[imx8mn: bytes of all masters read from ddr0]
imx8mn-ddr0-all-w
[imx8mn: bytes of all masters write to ddr0]
imx8mn-ddr0-bandwidth-usage-ddr4
[imx8mn: percentage of bandwidth usage for ddr0]
imx8mn-ddr0-bandwidth-usage-lpddr4
[imx8mn: percentage of bandwidth usage for ddr0]
------------------------------------------------------------------
root@imx8mnevk:~# ./perf stat -a -I 1000 -M imx8mn-ddr0-all-r,imx8mn-ddr0-all-w
1.000469875 108120 imx8_ddr0/read-cycles/ # 1729920.0 imx8mn-ddr0-all-r
1.000469875 28841 imx8_ddr0/write-cycles/ # 461456.0 imx8mn-ddr0-all-w
2.001191750 37396 imx8_ddr0/read-cycles/ # 598336.0 imx8mn-ddr0-all-r
2.001191750 6090 imx8_ddr0/write-cycles/ # 97440.0 imx8mn-ddr0-all-w
------------------------------------------------------------------
root@imx8mnevk:~# ./perf stat -a -I 1000 -M imx8mn-ddr0-bandwidth-usage-lpddr4 dd if=/dev/zero of=/dev/null bs=1M count=1000000
1.000762250 840456 imx8_ddr0/read-cycles/ # 48.9 % imx8mn-ddr0-bandwidth-usage-lpddr4
1.000762250 390024176 imx8_ddr0/write-cycles/
1.000762250 1000762250 ns duration_time
2.001982125 592944 imx8_ddr0/read-cycles/ # 48.5 % imx8mn-ddr0-bandwidth-usage-lpddr4
2.001982125 387366923 imx8_ddr0/write-cycles/
2.001982125 1001219875 ns duration_time
3.003123250 542650 imx8_ddr0/read-cycles/ # 48.4 % imx8mn-ddr0-bandwidth-usage-lpddr4
3.003123250 386631603 imx8_ddr0/write-cycles/
3.003123250 1001141125 ns duration_time
4.004289875 538522 imx8_ddr0/read-cycles/ # 48.4 % imx8mn-ddr0-bandwidth-usage-lpddr4
4.004289875 386577020 imx8_ddr0/write-cycles/
4.004289875 1001166625 ns duration_time
5.005546750 515596 imx8_ddr0/read-cycles/ # 48.4 % imx8mn-ddr0-bandwidth-usage-lpddr4
5.005546750 386800889 imx8_ddr0/write-cycles/
5.005546750 1001256875 ns duration_time
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Diffstat (limited to 'tools')
| -rw-r--r-- | tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mn-ddr-uncore.json | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mn-ddr-uncore.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mn-ddr-uncore.json new file mode 100644 index 000000000000..27d64e1cb76b --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/imx8mn-ddr-uncore.json @@ -0,0 +1,37 @@ +[ + { + "PublicDescription": "lpddr4 evk board bandwidth usage", + "BriefDescription": "imx8mn: percentage of bandwidth usage for ddr0", + "MetricName": "imx8mn-ddr0-bandwidth-usage-lpddr4", + "MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (800 * 1000000 * 4 * 4)", + "MetricGroup": "i.MX8MN_DDR_MON", + "ScaleUnit": "1e2%", + "SocName": "i.MX8MN" + }, + { + "PublicDescription": "ddr4 evk board bandwidth usage", + "BriefDescription": "imx8mn: percentage of bandwidth usage for ddr0", + "MetricName": "imx8mn-ddr0-bandwidth-usage-ddr4", + "MetricExpr": "(( imx8_ddr0\\/read\\-cycles\\/ + imx8_ddr0\\/write\\-cycles\\/) * 4 * 4 / duration_time) / (600 * 1000000 * 4 * 4)", + "MetricGroup": "i.MX8MN_DDR_MON", + "ScaleUnit": "1e2%", + "SocName": "i.MX8MN" + }, + + { + "PublicDescription": "Calculate bytes all masters read from DDR based on read-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.", + "BriefDescription": "imx8mn: bytes of all masters read from ddr0", + "MetricName": "imx8mn-ddr0-all-r", + "MetricExpr": "imx8_ddr0\\/read\\-cycles\\/ * 4 * 4", + "MetricGroup": "i.MX8MN_DDR_MON", + "SocName": "i.MX8MN" + }, + { + "PublicDescription": "Calculate bytes all masters write to DDR based on write-cycles event. DDR interface generates 2 up and 2 down edges in an internal clock cycle, can pass 4 beats of data. 4 bytes of each beat if DDR burst width is 32 bit.", + "BriefDescription": "imx8mn: bytes of all masters write to ddr0", + "MetricName": "imx8mn-ddr0-all-w", + "MetricExpr": "imx8_ddr0\\/write\\-cycles\\/ * 4 * 4", + "MetricGroup": "i.MX8MN_DDR_MON", + "SocName": "i.MX8MN" + } +] |