diff options
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-apalis.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-apalis.dtsi | 76 |
1 files changed, 72 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 05f07ea3e8c8..0b47aecf336a 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -61,6 +61,18 @@ status = "disabled"; }; + /* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */ + i2cddc: i2c@0 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_ddc>; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */ + &gpio2 30 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + status = "disabled"; + }; + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; regulator-name = "+V3.3"; @@ -138,6 +150,54 @@ spdif-out; status = "disabled"; }; + + vgabridge: bridge { + compatible = "dumb-vga-dac"; + #address-cells = <1>; + #size-cells = <0>; + de-active = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&vga_display_out>; + }; + }; + }; + }; + + vgadisplay: display@di0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu2_vdac>; + status = "disabled"; + + port@0 { + reg = <0>; + + vga_display_in: endpoint { + remote-endpoint = <&ipu2_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + vga_display_out: endpoint { + remote-endpoint = <&vga_bridge_in>; + }; + }; + }; + }; &audmux { @@ -373,6 +433,10 @@ status = "disabled"; }; +&ipu2_di0_disp0 { + remote-endpoint = <&vga_display_in>; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; @@ -482,10 +546,6 @@ }; &iomuxc { - /* pins used on module */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_moci>; - pinctrl_apalis_gpio1: gpio2io04grp { fsl,pins = < MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 @@ -636,6 +696,14 @@ >; }; + pinctrl_i2c_ddc: gpioi2cddcgrp { + fsl,pins = < + /* DDC bitbang */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 |