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Ensure that all the code in busfreq driver that is SMP dependent is
enclosed with CONFIG_SMP define, else the build breaks when CONFIG_SMP=n.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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command line
When nosmp is added to the command line, setup_max_cpus is set to 0
by the kernel. And this results in num_possible_cpus() returning 0 and the kernel
does not boot.
This patch ensures that at least one CPU's state is set to "possible" as part
of the boot process.
Cherry picked from 3.10.y kernel:
e94363b07a94bfe587a78330f7b9517f5cacb273
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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Remove unused symbol "done" in dma_pool_alloc_nonbufferable.
Signed-off-by: Peng Fushi <fushi.peng@freescale.com>
Signed-off-by: Li Jun <b47624@freescale.com>
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Since pool_alloc_page_nonbufferable already do list_add, so
dma_pool_alloc_nonbufferable cannot do it again, which will result
in page_list mess and kernel panic when destory pool of memory block
alloced by dma_pool_alloc_nonbufferable.
This patch also can fix MLK-9656.
Signed-off-by: Peng Fushi <fushi.peng@freescale.com>
Signed-off-by: Li Jun <b47624@freescale.com>
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Remove dead code.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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During suspend resume we only need to ensure that DDR is put self-refresh. There
is no need to set the CON_REQ bit as we are not re-calibrating the DDR.
Setting the CON_REQ bit requires that the SW needs to wait for the CON_ACK bit
to be set before proceeding further. And under certain circumstances the MMDC
does set the CON_ACK bit and the SW is waiting for ever until the watch dog resets
the system.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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procedure
Backport busfreq patch from 3.10.x kernel:
2d1f2b76919e13d8744cc8579316c002f832c675
The ddr frequency change code was responsible for some random kernel crashes.
This was due to the fact that L1 and L2 caches were not correctly flushed/synced
during the frequency change procedure.
This patch attempts to fix the issue by:
1. Ensure that every active core put into wfe flushes and disables its L1.
2. All cores (except the one executing the ddr freq change code) informs the SCU
that it going into a power down state after flushing and disabling its L1. It
also removes itself out the SMP cluster.
3. Variables shared across cores are stored in non-cacheable IRAM space.
4. SCU power status register is used to identify if all cores have reached a quiscent state
before the core running the ddr freq change code proceeds further.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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after boot.
Back ported from 3.10.x kernel:
516bf00a8ce530a269f6d2f1470f88e299584524
The self-bias circuit is used by the bandgap during startup.
Once the bandgap has stabilized, the self-bias circuit should be
disabled for best noise performance of analog blocks.
Also this bit should be disabled before the chip enters STOP mode or
when ever the regular bandgap is disabled.
This patch ensures that the self-bais bit is cleared before the bandgap
is disabled in low power code and during suspend/resumne.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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Backport from 3.10.x kernel.
Set the SCU CPU Power status register to reflect the correct status of
a CPU (active/inactive/not-present).
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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The DDR freq code had an incorrect workaround for ERR005778.
ERR005778 MMDC: DDR Controller’s measure unit may return an incorrect value
when operating below 100 MHz
Workarounds:
To workaround this issue, following steps should be performed by software:
1. Prior to reducing the DDR frequency (528 MHz), read the measure unit count bits
(MU_UNIT_DEL_NUM).
2. Bypass the automatic measure unit when below 100 MHz, by setting the measure unit bypass
enable bit (MU_BYP_EN).
3. Double the measure unit count value read in step 1 and program it in the measure unit bypass
bit (MU_BYP_VAL) of the MMDC PHY Measure Unit Register, for the reduced frequency
operation below 100 MHz.
Software should re-enable the measure unit when operating at the higher frequencies, by clearing
the measure unit bypass enable bit (MU_BYP_EN). This code should be executed out of Internal
RAM or a non-DDR based external memory.
This patch fixes the code to follow the workaround specified in the errata
document.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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for rx dma buffer"
Since we already use non-bufferable dma memory for all usb host dma memory
allocations which can cover all class drivers, so revert this commmit.
This reverts commit e314064d431d32a5a81da6681f57cdb3c20cad5b.
Signed-off-by: Li Jun <b47624@freescale.com>
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This patch changes usb host dma allocation to be non-bufferable to fix
data coherent issue.
Signed-off-by: Li Jun <b47624@freescale.com>
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memory mapping"
This reverts commit 321862cbad506707fe9d0ae4dcca24a865a5feea.
this patch is from Vivante without test, it causes X issue
Date: Sep 18, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit 7cc50eb75efb4c8d41e48577dc020a700ddb1039)
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The USB OTG controller may respond nothing to USB Host token,
if the RXFIFO overrun occurs due to busy system bus when the USB
OTG controller works in device mode, disable stream mode can work
around this issue.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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use dma_pool_alloc_nonbufferable for rx buf instead of dma_alloc_coherent
for usb host cdc-acm to fix data coherent issue.
Signed-off-by: Li Jun <b47624@freescale.com>
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output
In mono speaker configuration, the SPKOUT_ENA bit should be
WM8962_CLASS_D_CONTROL_1 register bit 6 instead of bit 7.
Signed-off-by: Peter Chan <B18700@freescale.com>
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configuration
In WM8962 mono speaker configuration, "add route SPKOUTL->Ext Spk"
error will occur when initializing the codec. This is because in
mono speaker configuration, there is no widget naming with "SPKOUTL".
Fix this error by using the correct name "SPKOUT" for mono speaker
configuration.
Signed-off-by: Peter Chan <B18700@freescale.com>
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The optimal resize ratio should be used if the downscaler is not needed. This
will fix a vertical line in the center for some scaling ratios.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
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When split mode deinterlacing is the ipu_calc_stripes_sizes() was failing due
to an unnecessary test. Added logic to use the maximal_stripe_width only if
the flag parameter has the bit 0 clear for not equal stripe sizes.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
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Added additional check to handle stripe limits differently for upscaling
and downscaling. Upscaling requires relaxed checking because input stripe
may fall slighty outside of the input window. Downscaling requires strict
limit checking.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
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Changed alignement for planar formats back to 16 pixels.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
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The downsizing ratio overflow check should cover every stripe
in the split mode. We need to do the overflow check correctly
by taking the width/height 8-pixel alignment requirement into
consideration since the alignment would be done when every
stripe is checked in it's own ipu task.
This patch takes a workaround for the issue which can be
reproduced by this unit test case:
==================================================================
mxc_v4l2_output.out -iw 1920 -ih 1080 -ow 200 -oh 200 -v 1
mxc_ipu mxc_ipu: ERR:create_split_child_task() ret:-22
mxc_ipu mxc_ipu: sp_task[0],no-0x12 fail state:-22, queue err:-22.
mxc_ipu mxc_ipu: ERR: [0xac73ea00] no-0x10,state 3: error
mxc_ipu mxc_ipu: ERR: no-0x10,ipu_queue_task err:-125
mxc_v4l2_output v4l2_out.35: display work fail ret = -125
mxc_ipu mxc_ipu: ERR:create_split_child_task() ret:-22
mxc_ipu mxc_ipu: sp_task[0],no-0x22 fail state:-22, queue err:-22.
mxc_ipu mxc_ipu: ERR: [0xac73ea00] no-0x20,state 3: error
mxc_ipu mxc_ipu: ERR: no-0x20,ipu_queue_task err:-125
mxc_v4l2_output v4l2_out.35: display work fail ret = -125
mxc_ipu mxc_ipu: ERR:create_split_child_task() ret:-22
mxc_ipu mxc_ipu: sp_task[0],no-0x32 fail state:-22, queue err:-22.
mxc_ipu mxc_ipu: ERR: [0xac63c400] no-0x30,state 3: error
mxc_ipu mxc_ipu: ERR: no-0x30,ipu_queue_task err:-125
mxc_v4l2_output v4l2_out.35: display work fail ret = -125
VIDIOC_QBUF failed -1
==================================================================
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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This patch fixes the following build warning by
initializing some local variables:
drivers/mxc/ipu3/ipu_calc_stripes_sizes.c: In function ‘ipu_calc_stripes_sizes’:
drivers/mxc/ipu3/ipu_calc_stripes_sizes.c:393:3: warning: ‘difwr’ may be used uninitialized in this function [-Wuninitialized]
drivers/mxc/ipu3/ipu_calc_stripes_sizes.c:393:3: warning: ‘onw’ may be used uninitialized in this function [-Wuninitialized]
drivers/mxc/ipu3/ipu_calc_stripes_sizes.c:393:3: warning: ‘inw’ may be used uninitialized in this function [-Wuninitialized]
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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In rotation cases, the width and height of IPUv3 IC scaling block's
output should align with the width and height of IPUv3 IC rotation
block. And, users only tell the IPUv3 device driver about the parameters
of scaling block's input and rotation block's output. So, we need to
swap the width and height of rotation block in cache before we do
downsize(a functionality of the scaling block) overflow check.
This patch fixes the issue which can be reproduced by this unit test case:
/unit_tests/mxc_v4l2_output.out -iw 128 -ih 128 -ow 176 -oh 10 -r 90
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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- Need to use different multiple and index parameters for vertical
and horizontal stripes
- Use correct multiple and index based upon pixel format
- Allow input crop and size to be larger than width by upto 16 pixels
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
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For downscaling, it is possible that downscaler output is greater
than 1024. Added a function, calc_split_resize_coeffs, based upon
_calc_resize_coeffs to calculate resizing and downscaling coefficients.
In ipu_ic.c, checks for the range of *_resize_ratio are no longer needed.
Non split cases will always have *_resize_ratio of zero.
In ipu_device, additional checks are needed to check for an error from
ipu_calc_stripes_sizes if calc_split_resize_coeffs fails.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
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This patch handles downsize ratio overflow error by doing
input cropping with 8 pixel step.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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IPUv3 IC task downsize scaling ratio cannot exceed or be
equal to 8:1. This patch makes the code return error code
if the ratio overflows.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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This patch improves IPU IC task scale check logic
so that we may return with error code if the calculation
for scale coefficients fails.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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change procedure
A missing end of comment inadvertently ensured that the DLL off
procedure was executed even when the DLL was already disabled (switching
from 24MHz to 50MHz and vice-versa).
This patch fixes the above issue. And also ensures that automatic entry into
self-refresh is enabled for both DLL ON and DLL OFF modes.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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separate GPU low memory killer and GPU reserve memory account query code,
so that we can separate control GPU low memory killer and android system
low memory killer to query the reserve memory account.
Signed-off-by: Richard Liu <r66033@freescale.com>
(cherry picked from commit 6fbb4058a21d24384e4c8f2d3fd8ef33c2141302)
(cherry picked from commit dde88d1e7c3173c16844c9a0fa7f84365fa4ed76)
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clock & power
GPU recovery is disabled by default, GPU kernel driver will dump hardware status,
but if GPU clock & power is truned off, system will get frozen unexpectedly.
this fix is to avoid system freeze by detecting clock & power state.
Date: Jul 14, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Shawn Guo
(cherry picked from commit 05fd7bf5615a9ccde4af97ff7dcae3e7e2c9a86a)
(cherry picked from commit 7c094ccb55e4a70ada5d7c2df8b6d3816956333a)
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fix invalid access issue in GPU kernel triggered with the certain condition,
memory extensive type exceed 256 and will cause memory overwriting issue
Date: Jul 14, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit 0db530ceadb9e1559793c725d4ab576370ffb1c2)
(cherry picked from commit 615fd2029d18cf7f1bcbda9773f11f04cb93d4d4)
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the root cause is video memory mutex is not global variable,
it will cause video memory managment problem with mixed 2D/3D/VG.
kernel panic with multiple instances stress test running glesx_viv.sh.
Date: Jul 31, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit 02bdc91149f077aba37c790aca1e59041d473f71)
(cherry picked from commit 26c25e084b4137bf19aaa20e5075bb3c16096066)
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Move wl_surface_commit to work thread.
Fix memory leak in wl_egl_window_resize.
Date: Jul 10, 2014
Signed-off-by Yong Gan <yong.gan@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit c114ec8a4c74fc2a2d0f64c60031c66d2225ff83)
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it is caused when multiple threads try to kill same one process,
the global semaphore is used to avoid this conflict.
Date: Jun 05, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit 48c860eba3aae80c85587a37a858082b3a8b7b08)
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GPU memory node should not be used after node structure is destoryed,
that will cause random GPU memory data corruption issue in Android platform.
the issue can be reproduced when run cts -p android.opengl repeatly(more than 100 times)
Date: May 28, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit 36dbe12f0dbd01dd7ef10b52a9c508fa5d7d19d0)
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fix android.media.cts.PresentationSyncTest#testThroughput cts fail,
root cause is dequeueBuffer and queueBuffer in Surface will acquire
the same mutex and in GPU driver dequeueBuffer and queueBuffer is work
at asynchronous mode, so queueBuffer maybe blocked by dequeueBuffer
and dequeueBuffer will return after 16ms (vsync time).
Date: May 16, 2014
Signed-off-by: Richard Liu <r66033@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit e62993b346e418f08cb88d25303a0541653a5468)
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suspend/resume
Many A9 errata require bits in the diagnostic control register to be set.
During a suspend/resume cycle, the A9 core may get power gated, implying
that the register needs to be maintained across a suspend/resume cycle.
Also ensure that power control register is saved/restored.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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Whenever DDR is explicitly put into self-refresh, we need to ensure
that no access are made to the DDR. All the bus masters excpet ARM
are shutdown gracefully.
The ARM core can continue to access the DDR due to:
1. Speculative accesses
This can be prevented by flushing the Branch Target Address Cache
2. Aggressive Prefetching
This can be minimized by adding nops.
Apart from this the TLB architecture in ARM does not guarantee that
an entry remains in the TLB unless its explicitly locked. Even if
free slots are available an entry maybe evicted. So flushing the TLB
does not guarantee a page table walk will not happen.
The solution is to put a minimized page table in IRAM that can be used when
DDR is in self-refresh. The IRAM page tables should have entries for IRAM,
AIPS1 and AIPS2 as these entries will be needed by the code that puts DDR
into self-refresh. It should not contain any entries that point to the DDR.
This patch set accomplishes the following:
1. Set the IRAM to be mapped as 1M sections in the high mem region.
This makes it possible to create entries for the IRAM code in the
IRAM page table. We need to ensure that both the DDR and IRAM page
table have mapping for the IRAM code.
2. Ensure the IRAM, AIPS1, AIPS2 have entries in the IRAM page table.
3. Save TTBR1
4. Set TTBR1 to point to the page tables stored in IRAM. Switch to using
TTBR1 before DDR is put into self-refresh. Ensure the following settings:
a. TTBCR.N = 1
This means the 0-2G virtual address space is translated using TTBR0
and 2G-4G is translated using TTBR1.
b. Set TTBCR.PD0 = 1
With this setting page table walks using TTBR0 are disabled.
4. After the DDR has exited self-refresh, reset TTBCR to 0 (TTBR0 will
be used for translations now).
5. Restore TTBR1
Even though TTBR1 is only used to decode the top 2G of virtual address
space, ARM requires that we allocate the entire 16KB for the page table.
To minimize IRAM/OCRAM required, we put the code in the bottom 8K and
page table entries in the top 8K.
This requires the low power code be optimized to occupy as little space
as possible. Only the WFI and suspend code that puts DDR into self-refresh
is located in this 8k. The DDR frequency code that also puts the DDR into
self-refresh need not be located in this 8K region. Currently this patch
allocates a separate 4K region in IRAM for the DDR frequency change code.
Additional conditions to be met:
1. Disable L2 when DDR is in self-refresh.
2. Ensure that L1 and branch prediction are disabled when we
are switching to IRAM page tables, based on recommendation from
ARM.
This patch also dynamically calculate size of all the code that puts
DDR into self-refresh (low power and ddr freq change).
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
(cherry picked from commit 67779bf67ebf4daddea33693f42cf01eced14bd9)
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Cpufreq code:
1. Busfreq can be dropped to 24MH only when CPU freq is at the lowest setpoint (396MHz). The
code was incorrectly releasing the request for high busfreq even when cpufreq was at 792MHz.
This caused incorrect pll2 behavior as the busfreq code expects CPUFREQ to be at 396MHz and
to be sourced from PLL2_PFD2_396M when the switch to low_bus_freq is requested.
Clock code:
1. Ensure osc_clk usecount is also updated when pll2 or pll1 usecount is changed.
This fixes a debug warning message when CLK_DEBUG is enabled.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
(cherry picked from commit d08a8a2ed28d9ea42dff9ff82a115072f84630a9)
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The abnormal flow with the monkey test freeze problem is as below:
gckKERNEL_DestroyProcessDB--> aquire mutex --> gckCOMMAND_Detach(gckEVENT_FreeContiguousMemory) -->
___RemoveRecordFromProcessDB --> gckKERNEL_RemoveProcessDB --> aquire the same mutex
the fix is to disable mutex lock when perform record destory operations
Date: May 19, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit 8d62ea9a655f1bb0ca86af222de7625abc8d2bc8)
(cherry picked from commit cd5a9a37525d4d2f79b6013f4bd93779b900b854)
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mutex operation is performed in gckKERNEL_QueryProcessDB
remove spinlock for gckKERNEL_QueryProcessDB to avoid scheduling issue
Date: May 08, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit 554581201c0a1c2c7caddad5750b1fd678e09c8c)
(cherry picked from commit 78ecaf1c6475ee188a6a2a1dfbe954e457a28997)
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Vivante patch name:
fix_fsl_2d_base_on_p13.v2.rls.diff
-Updated the outstanding request limit to 12.
-Refined the 2D chip feature check.
-Refine the 2D cache flush operation
(avoid FE and PE access memory through the same port).
-Enable cache flush for filterblt.
-Dynamic enabling SPLIT_RECT by checking chip feature(disable for us)
-Use brush stretch blt for clear operation.
-Enable SplitFilterBlit to workaround the 2d hang issue in filterblit case.
-Refine 2d line operation.
Date: May 05, 2014
Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Shawn Guo
(cherry picked from commit 479b9125caefc45451aa1c4a1b7f2704b57831fa)
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the potential risk is found in special case when application exit,
deleting record will cause the unexpected issue when process database is destoryed without atom protection
the enhanced database patch should be applied to avoid the unexpected kernel issue
Date: Apr 17, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit e799c1ae023264c0e1e1e41d448e30e2304944e1)
(cherry picked from commit 7eb5273b6dd61d61c2ffe778bdb6d5032bbc1aa0)
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this patch can fix NULL pointer issue in GPU kernel driver with the following log
[<7f240438>] (gckEVENT_AddList+0x0/0x810 [galcore]) from [<7f239ebc>] (gckCOMMAND_Commit+0xf28/0x118c [galcore])
[<7f238f94>] (gckCOMMAND_Commit+0x0/0x118c [galcore]) from [<7f2362dc>] (gckKERNEL_Dispatch+0x120c/0x24e4 [galcore])
[<7f2350d0>] (gckKERNEL_Dispatch+0x0/0x24e4 [galcore]) from [<7f222280>] (drv_ioctl+0x390/0x540 [galcore])
[<7f221ef0>] (drv_ioctl+0x0/0x540 [galcore]) from [<800facd0>] (vfs_ioctl+0x30/0x44)
The false code is at 0x217bc where the 0-pointer happens (r3 = 0)
gcuVIDMEM_NODE_PTR node = (gcuVIDMEM_NODE_PTR)(gcmUINT64_TO_PTR(Record->info.u.FreeVideoMemory.node));
217b8: e5953028 ldr r3, [r5, #40] ; 0x28
if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
217bc: e5932000 ldr r2, [r3]
217c0: e5922000 ldr r2, [r2]
217c4: e152000a cmp r2, sl
{
gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(Event->kernel,
Date: Apr 23, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit fcde214d8c793d4dd785e47175b5833f1f3f5f1f)
(cherry picked from commit 952142648d76fce2663ef649d9f988f1b7809815)
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Vivante patch name:000e-more-refinements-for-wclip-issue
Date: Apr 14, 2014
Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Shawn Guo
(cherry picked from commit 3fae441a3b6a40e4981473bf967c121e22a9eda7)
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Vivante patch name:0002-more-refinements-for-wclip-issue
Date: Apr 14, 2014
Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Shawn Guo
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Vivante patch name:0001-more-refinements-for-wclip-issue
Date: Apr 14, 2014
Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Shawn Guo
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Access GPU register will cause system hang(bus lock-up) without log when clock is off,
GPU kernel BUG_ON is added to check if GPU clock is off when read & write GPU registers,
GPU clock issue can be easily identified with the detailed kernel panic log as below:
kernel BUG at drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c:2423!
Unable to handle kernel NULL pointer dereference at virtual address 0000000
...
[<c0050008>] (__bug+0x1c/0x28) from [<c046bb3c>] (gckOS_ReadRegisterEx+0xbc/0xdc)
[<c046bb3c>] (gckOS_ReadRegisterEx+0xbc/0xdc) from [<c047eab4>] (gckHARDWARE_QueryIdle+0x4c/0xbc)
[<c047eab4>] (gckHARDWARE_QueryIdle+0x4c/0xbc) from [<c0475e0c>] (_TryToIdleGPU+0x70/0x12c)
Mutex protection is not necessary for interrupt handling, because GPU clock is only turned off
by interrupt worker thread during clock gating.
Date: Apr 11, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit 50c3767eb19bb22f395215755dac220f4bbb2f14)
(cherry picked from commit faf4eb3fd5a66661782f8d0395a27016d7a8fc52)
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