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2019-12-25arm64: dts: layerscape: apply dma-coherent for dwc3 nodesRan Wang
Since dwc3 cache type has been set to cacheable, apply dma-coherent to all dwc3 nodes accordingly. Note: For LS1043A and LS1046A, since QE-HDLC still doesn't support dma-coherent, we cannot directly revert cd1a4f3c (sdk: dts: ls104x move dma-coherent from soc to its child nodes) to recover dma-coherent for soc. Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2019-12-19LF-387-5 arm64: dts: layerscape: add chip-specific compatible string to usb ↵Ran Wang
nodes To allow USB dwc3 driver to conduct some chip-scpeific configuring. Cover all arm64 based Layerscape SoCs. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com> Reviewed-by: Leo Li <leo.li@nxp.com>
2019-11-25arm64: dts: ls1012a/ls1043a/ls1046a/ls1088a/ls208xa: replace ftm0 with ↵Biwen Li
ftm_alarm0 The patch replaces ftm0 with ftm_alarm0 DT node - replace ftm0 with ftm_alarm0 - add new rcpm node - remove old rcpm node - aliases ftm_alarm0 as rtc1 Signed-off-by: Biwen Li <biwen.li@nxp.com>
2019-11-25arm64: dts: Fix DWC3 IP VBUS glitch issue on Layerscape platformsRan Wang
Cover LS1012A, LS1043A, LS1046A, LS1088A, LS208xA, LX2160A Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2019-11-25arm64: dts: ls104x: constrain sata dma address sizeLaurentiu Tudor
Limit the dma mask size for sata to 40 bits to match the actual address size generated towards the interconnect. Re-use the already existing auxiliary simple bus meant for usb but drop the usb reference from the node name. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
2019-11-25arm64: dts: nxp: add more thermal zone supportYuantian Tang
To enable all the supported thermal sensors, add sensor id information to thermal zone node. Dts for ls1012a, ls1046a, ls1043a, ls1088a are updated. Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
2019-11-25arm64: dts: ls104x: use a pseudo-bus to constrain usb dma sizeLaurentiu Tudor
Wrap the usb controllers in an intermediate simple-bus and use it to constrain the dma address size of these usb controllers to the 40 bits that they generate toward the interconnect. This is required because the SoC uses 48 bits address sizes and this mismatch would lead to smmu context faults because the usb generates 40-bit addresses while the smmu page tables are populated with 48-bit wide addresses. Suggested-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
2019-11-25arm64: dts: ls104x: make dma-coherent global to the SoCLaurentiu Tudor
These SoCs are really completely dma coherent in their entirety so add the dma-coherent property at the soc level in the device tree and drop the instances where it's specifically added to a few select devices. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
2019-11-25arm64: dts: ls104x: add iommu-map to pci controllersLaurentiu Tudor
The pci controllers are also behind the smmu so add the iommu-map property to reflect this. The bootloader needs to patch the stream id ranges to some sane values. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
2019-11-25arm64: dts: ls104x: add missing dma ranges propertyLaurentiu Tudor
These chips have a 48-bit address size so make sure that the dma-ranges reflects this. Otherwise the linux kernel's dma sub-system will set the default dma masks to full 64-bit, badly breaking dmas. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
2019-11-25arm64: dts: ls104xa: set mask to drop TBU ID from StreamIDLaurentiu Tudor
The StreamID entering the SMMU is actually a concatenation of the SMMU TBU ID and the ICID configured in software. Since the TBU ID is internal to the SoC and since we want that the actual the ICID configured in software to enter the SMMU witout any additional set bits, mask out the TBU ID bits and leave only the relevant ICID bits to enter SMMU. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
2019-11-25arm64: dts: ls1043a: add smmu nodeLaurentiu Tudor
This allows for the SMMU device to be probed by the SMMU kernel driver. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
2019-11-25arm64: dts: ls1043a: accumulated change for ls1043a boardsLi Yang
commit 118e2f48ee8da3f5547c24888bd6fdb78f03b7ce Author: Peng Ma <peng.ma@nxp.com> Date: Wed Jul 25 08:53:07 2018 +0000 dts: fsl-ls1021a, fsl-ls1043a, fsl-ls1046a: add multi block node support add block-offset to support different virtual block offset for qdma base on soc; the interrupt named "qdma-queueN(N:0,1,2,3)" correspond to a virtual block,N based on block number of qdma; Signed-off-by: Peng Ma <peng.ma@nxp.com> Author: Zhang Ying-22455 <ying.zhang22455@nxp.com> Date: Mon Apr 2 16:22:40 2018 +0800 arm64: dts: ls1043a: add dts entry for A-010650 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> commit a47e4bd0b5d076feb6d81601c16d5b79e53a92c8 Author: Rajesh Bhagat <rajesh.bhagat@freescale.com> Date: Wed Jan 27 11:37:25 2016 +0530 arm64: dts: ls1043a: Add configure-gfladj property to USB3 node Add "configure-gfladj" boolean property to USB3 node. This property is used to determine whether frame length adjustent is required or not Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> commit 38566bbd5ca6747b30d2f0c251bbcfe0723df8c6 Author: Changming Huang <jerry.huang@nxp.com> Date: Wed Apr 19 12:49:50 2017 +0800 arm/arm64: dts: Add property snps incr burst type adjustment for INCR burst type for dwc3 Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> commit 8632d84e0fe187aa023a24f0dad0040c53e12450 Author: Abhimanyu Saini <abhimanyu.saini@nxp.com> Date: Thu Jan 25 11:31:13 2018 +0530 arm64: dts: freescale: ls1043a: Modify DT nodes for qspi Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> commit b1dc1ebed79e9aaab75fd06837d794ec2f1b624d Author: Ran Wang <ran.wang_1@nxp.com> Date: Fri Jan 5 15:14:48 2018 +0800 arm64: dts: ls1043a: Enable usb3-lpm-capable for usb3 node Enable USB3 HW LPM feature for ls1043a and active patch for snps erratum A-010131. It will disable U1/U2 temperary when initiate U3 request. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> commit 9b17a5fcf8da5656ff99ebef3d63ba040e9f676d Author: Zhang Ying-22455 <ying.zhang22455@nxp.com> Date: Tue Jun 13 13:14:26 2017 +0800 arm64: dts: correct the register range of dcfg Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> commit f60e39fd51ad702e3a2613faaca40871a4763735 Author: Zhang Ying-22455 <ying.zhang22455@nxp.com> Date: Tue Aug 22 18:04:02 2017 +0800 arm64: dts: ls1043a: add pcf85263 rtc nodes Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> commit 67c82e3c7b376139d7cee624589bedbc311f8868 Author: jiaheng.fan <jiaheng.fan@nxp.com> Date: Thu May 11 17:36:33 2017 +0800 arm64: dts: ls1021/ls1043/ls1046: add qdma nodes Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com> commit c6d9c2498ee83669f9853100301edff9a5905caf Author: Wang Dongsheng <dongsheng.wang@nxp.com> Date: Fri Apr 21 13:26:07 2017 +0800 arm64: dts: ls1043a: add ftm0 nodes Add rcpm and ftm0 nodes. The Power Management related features need these nodes. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> commit 3bcdc4de0a1c9e6f4a4ddc916e8efe8044d8bbfd Author: Po Liu <po.liu@nxp.com> Date: Fri Sep 30 17:11:36 2016 +0800 arm64: dts: ls1043/ls2080: add pcie aer/pme interrupt-name property Some platforms(NXP Layerscape for example) aer/pme interrupts was not MSI/MSI-X/INTx but using interrupt line independently. This patch add "aer", "pme" interrupt-names for aer/pme interrupt. With the interrupt-names "aer", "pme" code could probe aer/pme interrupt line for pcie root port, replace the aer/pme interrupt service irqs. This is intend to fixup the Layerscape platforms which aer/pmes interrupts was not MSI/MSI-X/INTx, but using interrupt line independently. Since the interrupt-names "intr" never been used. Remove it. Signed-off-by: Po Liu <po.liu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> commit 4d20ecf029f1255520b30c103e1724c618b981c7 Author: Zhao Qiang <qiang.zhao@nxp.com> Date: Sun Jun 12 15:51:44 2016 +0800 arm64: dts: ls1043ardb: add ds26522 node add ds26522 node to fsl-ls1043a-rdb.dts Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> commit ca470562646ab058814fc4a1195016fb3266cdf5 Author: Zhao Qiang <qiang.zhao@nxp.com> Date: Sun Jun 12 15:44:11 2016 +0800 arm64: dts: ls1043ardb: add qe node Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2019-08-22arm64: dts: fsl: Remove num-lanes property from PCIe nodesHou Zhiqiang
Remove the num-lanes property to avoid the driver setting the link width. On FSL Layerscape SoCs, the number of lanes assigned to PCIe controller is not fixed, it is determined by the selected SerDes protocol in the RCW (Reset Configuration Word). The PCIe link training is completed automatically through the selected SerDes protocol - the link width set-up is updated by hardware after power on reset, so the num-lanes property is not needed for Layerscape PCIe. The current num-lanes property was added erroneously, which actually indicates the maximum lanes the PCIe controller can support up to, instead of the lanes assigned to the PCIe controller. The link width set by SerDes protocol will be overridden by the num-lanes property, hence the subsequent re-training will fail when the assigned lanes do not match the value in the num-lanes property. Remove the property to fix the issue Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
2019-03-22arm64: dts: ls1043a: add crypto node alias also for qdsHoria Geantă
crypto node alias is needed by U-boot to identify the node and perform fix-ups, like adding "fsl,sec-era" property or deleting a job ring child node (in case ARM TF-A is running). Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-22arm64: dts: fsl: Remove unused properties from FSL QSPI nodesFrieder Schrempf
After switching to the new FSL QSPI driver the properties 'fsl,qspi-has-second-chip' and 'big-endian' are not used anymore. The driver now uses the 'reg' property to determine the bus and the chipselect. The endianness is selected by the driver depending on which SoC is used. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-12arm64: dts: layerscape: Add incr-burst-type-adjustment property to USB3 nodeRan Wang
Add this property to all layerscape platforms to improve USB read write performance. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-01-11arm64: dts: layerscape: add num-viewport property for PCIe DT nodesHou Zhiqiang
Add num-viewport property for PCIe DT nodes to specify how many viewports are implemented. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08arm64: dts: ls1043a: add qdma device tree nodesPeng Ma
add the qDMA device tree nodes for LS1043A devices. Signed-off-by: Wen He <wen.he_1@nxp.com> Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08arm64: dts: fsl: Add all CPUs in cooling mapsViresh Kumar
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08arm64: dts: layerscape: removed compatible string "snps,dw-pcie"Hou Zhiqiang
Removed the wrong compatible string "snps,dw-pcie", in case match incorrect driver. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-12-08arm64: dts: fsl: Add the status property disable PCIeBao Xiaowei
Add the status property disable the PCIe, the property will be enable by bootloader. Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-26arm64: dts: fsl: Fix I2C and SPI bus warningsRob Herring
dtc has new checks for I2C and SPI buses. Fix the SPI bus node names and warnings in unit-addresses. arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dtb: Warning (i2c_bus_reg): /soc/i2c@2180000/eeprom@57: I2C bus unit address format error, expected "53" arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dtb: Warning (i2c_bus_reg): /soc/i2c@2180000/eeprom@56: I2C bus unit address format error, expected "52" Cc: Shawn Guo <shawnguo@kernel.org> Cc: Li Yang <leoyang.li@nxp.com> Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-09-03arm64: dts: fsl: remove big-endian field from IFC controllerPrabhakar Kushwaha
As per IFC binding, Absence of "little-endian" field causes registers access in big-endian mode. So no need to set explicit big-endian field IFC node for LS1043A and LS1046A. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-08-25Merge tag 'armsoc-late' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late updates from Olof Johansson: "A couple of late-merged changes that would be useful to get in this merge window: - Driver support for reset of audio complex on Meson platforms. The audio driver went in this merge window, and these changes have been in -next for a while (just not in our tree). - Power management fixes for IOMMU on Rockchip platforms, getting closer to kexec working on them, including Chromebooks. - Another pass updating "arm,psci" -> "psci" for some properties that have snuck in since last time it was done" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: iommu/rockchip: Move irq request past pm_runtime_enable iommu/rockchip: Handle errors returned from PM framework arm64: rockchip: Force CONFIG_PM on Rockchip systems ARM: rockchip: Force CONFIG_PM on Rockchip systems arm64: dts: Fix various entry-method properties to reflect documentation reset: imx7: Fix always writing bits as 0 reset: meson: add meson audio arb driver reset: meson: add dt-bindings for meson-axg audio arb
2018-08-24arm64: dts: Fix various entry-method properties to reflect documentationAmit Kucheria
The idle-states binding documentation[1] mentions that the 'entry-method' property is required on 64-bit platforms and must be set to "psci". commit a13f18f59d26 ("Documentation: arm: Fix typo in the idle-states bindings examples") attempted to fix this earlier but clearly more is needed. Fix the cpu-capacity.txt documentation that uses the incorrect value so we don't get copy-paste errors like these. Clarify the language in idle-states.txt by removing the reference to the psci bindings that might be causing this confusion. Finally, fix devicetrees of various boards to reflect current documentation. [1] Documentation/devicetree/bindings/arm/idle-states.txt (see idle-states node) Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-07-03arm64: dts: freescale: Add missing cooling device properties for CPUsViresh Kumar
The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Do minor rearrangement as well to keep ordering consistent. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-06-19arm64: dts: freescale: Update to use SPDX identifiersLi Yang
Replace license text with corresponding SPDX identifiers and update the format of existing SPDX identifiers to follow the new guideline Documentation/process/license-rules.rst. Note that some of the files mentioned X11 license previously but the license text actually matches MIT license. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-24arm64: dts: fsl: update the cpu idle nodeYuantian Tang
According to PSCI standard v0.2, for CPU_SUSPEND call, which is used by cpu idle framework, bit[16] of state parameter must be 0. So update bit[16] of property 'arm,psci-suspend-param', which is used as state parameter, to 0. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-24arm64: dts: ls1043a: add cpu idle supportYuantian Tang
Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-12arm64: dts: ls1043a: Move cpu_thermal out of bus nodeFabio Estevam
Move cpu_thermal node from soc node to root node. cpu_thermal node does not have any register properties and thus shouldn't be placed on the bus. This fixes the following build warnings with W=1: arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-10-13arm64: dts: update the DPAA QBMan nodesMadalin Bucur
Use constants in the interrupt description. Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-09-22arm64: dts: ls: Add optee nodeSumit Garg
Add optee device tree node on ls1012a, ls1043a, ls1046a, ls1088a and ls208xa. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-08-31arm64: dts: ls1043a: Share all MSIsMinghuan Lian
In order to maximize the use of MSI, a PCIe controller will share all MSI controllers. The patch changes "msi-parent" to refer to all MSI controller dts nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-08-31arm64: dts: ls1043a: Fix typo of MSI compatible stringMinghuan Lian
"1" should be replaced by "l". This is a typo. The patch is to fix it. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-05-21arm64: dts: add LS1043A DPAA FMan supportMadalin Bucur
Add the DPAA 1.x FMan device tree nodes for LS1043A boards. Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-16arm64: dts: add LS1043A DPAA QBMan nodesMadalin Bucur
Add the DPAA 1.x QMan and BMan nodes in the LS1043A device tree. Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-15arm64: dts: Define big endian of IFC for LS1043a/LS1046aPrabhakar Kushwaha
Integrated flash controller present in LS1043A and LS1046A is big endian. So add big endian property in the devive tree. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-15arm64: dts: freescale: update the copyright claimsLi Yang
Update the copyright claims to comply with company policy. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-03-08arm64: dts: added ecc register address to sata node on ls1043aTang Yuantian
For ls1043 sata, ecc should be disabled due to a erratum. Provide the ecc register address for driver to use. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-11-18Merge tag 'imx-dt64-4.10' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64 Freescale arm64 device tree updates for 4.10: - Enable Thermal Monitoring Unit (TMU) for thermal management on LS1043A and LS2080A. - Add support for LS1046A SoC, which has similar peripherals as LS1043A but integrates 4 A72 cores. - Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB. * tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: ls2080a: Add TMU device tree support for LS2080A arm64: dts: ls1043a: Add TMU device tree support for LS1043A arm64: dts: add LS1046A-QDS board support Documentation: DT: Add entry for QorIQ LS1046A-QDS board arm64: dts: add LS1046A-RDB board support Documentation: DT: Add entry for QorIQ LS1046A-RDB board arm64: dts: add QorIQ LS1046A SoC support dt-bindings: ahci-fsl-qoriq: updated for SoC ls1046a dt-bindings: qoriq-clock: add LS1043A/LS1046A/LS2080A compatible for clockgen dt-bindings: i2c: adds two more nxp devices dt-bindings: fsl: add LS1043A/LS1046A/LS2080A compatible for SCFG and DCFG dt-bindings: fsl: Add LS1043A/LS1046A/LS2080A SoC compatible strings Signed-off-by: Olof Johansson <olof@lixom.net>
2016-11-15arm64: dts: ls1043a: Add TMU device tree support for LS1043AHongtao Jia
Also add nodes and properties for thermal management support. Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-10-21arm64: dts: Add timer erratum property for LS2080A and LS1043AScott Wood
Both the LS1043A and LS2080A platforms are affected by the Freescale A008585 erratum. Advertise it in their respective device trees. Signed-off-by: Scott Wood <oss@buserror.net> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-10-14Merge branch 'for-4.9' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata Pull libata updates from Tejun Heo: - Write same support added - Minor ahci MSIX irq handling updates - Non-critical SCSI command translation fixes - Controller specific changes * 'for-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: ahci: qoriq: Revert "ahci: qoriq: Disable NCQ on ls2080a SoC" libata: remove <asm-generic/libata-portmap.h> libata: remove unused definitions from <asm/libata-portmap.h> pata_at91: Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR ata: Replace BUG() with BUG_ON(). ata: sata_mv: Replacing dma_pool_alloc and memset with a single call dma_pool_zalloc. libata: Some drives failing on SCT Write Same ahci: use pci_alloc_irq_vectors libata: SCT Write Same handle ATA_DFLAG_PIO libata: SCT Write Same / DSM Trim libata: Add support for SCT Write Same libata: Safely overwrite attached page in WRITE SAME xlat ahci: also use a per-port lock for the multi-MSIX case ARM: dts: STiH407-family: Add ports-implemented property in sata nodes ahci: st: Add ports-implemented property in support ahci: qoriq: enable snoopable sata read and write ahci: qoriq: adjust sata parameter libata-scsi: fix MODE SELECT translation for Control mode page libata-scsi: use u8 array to store mode page copy
2016-09-14Merge branch 'dt/irq-fix' into next/dt64Arnd Bergmann
* dt/irq-fix: arm64: dts: Fix broken architected timer interrupt trigger This resolves a non-obvious conflict between a bugfix from v4.8 and a cleanup for the exynos7 platform.
2016-09-14arm64: dts: Fix broken architected timer interrupt triggerMarc Zyngier
The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition). A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high. The respective maintainers are of course welcome to prove me wrong. While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs). Acked-by: Duc Dang <dhdang@apm.com> Acked-by: Carlo Caione <carlo@endlessm.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-08-30arm64: dts: Add DDR memory controller for Layerscape SoCsYork Sun
Add DDR memory controller nodes to enable EDAC driver. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-08-10ahci: qoriq: enable snoopable sata read and writeTang Yuantian
By default the SATA IP on the qoriq SoCs does not generating coherent/snoopable transactions. This patch enable it in the sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-08-01Merge tag 'armsoc-dt64' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull 64-bit ARM DT updates from Olof Johansson: "Just as the 32-bit contents, the 64-bit device tree branch also contains a number of additions this release cycle. New platforms: - LG LG1313 - Mediatek MT6755 - Renesas r8a7796 - Broadcom 2837 Other platforms with larger updates are: - Nvidia X1 platforms (USB 3.0, regulators, display subsystem) - Mediatek MT8173 (display subsystem added) - Rockchip RK3399 (a lot of new peripherals) - ARM Juno reference implementation (SCPI power domains, coresight, thermal)" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (118 commits) arm64: tegra: Enable HDMI on Jetson TX1 arm64: tegra: Add sor1_src clock arm64: tegra: Add XUSB powergates on Tegra210 arm64: tegra: Add DPAUX pinctrl bindings arm64: tegra: Add ACONNECT bus node for Tegra210 arm64: tegra: Add audio powergate node for Tegra210 arm64: tegra: Add regulators for Tegra210 Smaug arm64: tegra: Correct Tegra210 XUSB mailbox interrupt arm64: tegra: Enable XUSB controller on Jetson TX1 arm64: tegra: Enable debug serial on Jetson TX1 arm64: tegra: Add Tegra210 XUSB controller arm64: tegra: Add Tegra210 XUSB pad controller arm64: tegra: Add DSI panel on Jetson TX1 arm64: tegra: p2597: Add SDMMC power supplies arm64: tegra: Add PMIC support on Jetson TX1 Revert "ARM64: DTS: meson-gxbb: switch ethernet to real clock" arm64: dts: hi6220: Add pl031 RTC support arm64: dts: r8a7796/salvator-x: Enable watchdog timer arm64: dts: r8a7796: Add RWDT node arm64: dts: r8a7796: Use SYSC "always-on" PM Domain ...
2016-06-21arm64: dts: ls1043a: Add cache nodes for cacheinfo supportLi Yang
Adds the cache nodes and next-level-cache property for the cacheinfo to work. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-11 23:36:39 +0000