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USBOTG2 PHY
USBOTG2 PHY's output name should be PHY ipg clock, but not controller
ahb clock, it is aligned with USBOTG1 PHY's output clock.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
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change the interrupts in imx8dxl-ss-conn for imx8dxl nand support.
Signed-off-by: Han Xu <han.xu@nxp.com>
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"fsl,imx8qm-usb" is not defined at driver, and "fsl,imx27-usb"
is older model. We need to use the closest model for it to get
the newer features, like runtime pm.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
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iMX8DXL does not have MLB in connectivity subsystem, remove mlb node
and mlb_lpcg node from imx8dxl conn DTSi.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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SLSLICE[2] cannot be accessed on 8DXL platform since it is
fixed and locked clock, but can be accessed on 8qm/8qxp platforms
who want to assign the clock to 250Mhz.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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Enable legacy enet0 port to support daughter RGMII AR8031
PHY board.
imx8dxl evk board rework:
- Remove U30, R181, R182
- Connect U30.2 -U30.7
- Connect U30.3 ->U30.6
- Change R178/R179 to 1.5K
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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basic host and peripheral work
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
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usb peripherial and host basic function work
Signed-off-by: Frank Li <Frank.Li@nxp.com>
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Add eqos support for imx8dxl evk board.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
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Add DT support for i.MX8DXL.
Signed-off-by: Teo Hall <teo.hall@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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