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irqsteer_lvds1 node
The irqsteer_lvds1 node's ipg clock source should be
lvds1_lis_lpcg_ipg_clk, instead of lvds0_lis_lpcg_ipg_clk.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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subsystems
Each LVDS subsystem should have ipg clock of their own.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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The LVDS region is the CSR(Control Status Registers) space.
The spec tells us that the CSR start address is 0x1000 and end address
is 0x1FFF according to the subsystem start address. However, it turns
out some space are inaccessible, which would accidently cause system
hang via kernel regmap debugfs. This patch corrects the LVDS region
start address and chooses a sensible size, which makes sure all exposed
registers are accessible.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds pwm_lvds0/1 support for
i.MX8QM LVDS subsystem device tree.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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This patch adds lvds0/1_pwm_lpcg clocks support for
i.MX8QM LVDS subsystem device tree.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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Add ipg clock config for all lpi2c bus.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
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This patch adds LVDS0/1 subsystems support for i.MX8qm.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
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