summaryrefslogtreecommitdiff
path: root/drivers/pci/controller/dwc/pci-imx6.c
AgeCommit message (Collapse)Author
2022-02-15pci: pci-imx6: fix PERST# start-up sequenceAndrejs Cainikovs
According to the PCI-E standard the PERST# signal (reset-gpio in fsl,imx6* compatible dts) should be kept asserted for at least 100 usec before the PCI-E refclock is stable, should be kept asserted for at least 100ms after the power rails are stable and the host should wait at least 100 msec after it is de-asserted before accessing the configuration space of any attached device. From PCI Express Card Electromechanical Specification T-PVPERL: Power stable to PERST# inactive - 100 msec T-PERST-CLK: REFCLK stable before PERST# inactive 100 usec. From PCI Express Base Specification: To allow components to perform internal initialization, system software must wait for at least 100 ms from the end of a Conventional Reset of one or more devices before it is permitted to issue Configuration Requests to those devices Failure to do so could prevent PCI-E devices to be working correctly, and this was experienced with real devices. Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2021-05-05Merge commit '28910e01c43d9735f06fddbeaa42df3e112d1b3e' into ↵Marcel Ziswiler
toradex_5.4-2.3.x-imx This basically contains NXP BSP Patch L5.4.70_2.3.2 plus kernel.org v5.4.115 from https://github.com/Freescale/linux-fslc/tree/5.4-2.3.x-imx. Related-to: ELB-3958 Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2021-04-27MLK-25349-3 PCI: imx: clear vreg bypass when pcie vph voltage is 3v3Richard Zhu
Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY. In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, the VREG_BYPASS bits of GPR registers should be cleared from default value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be turned on. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com> (cherry picked from commit 94e84f467b688ce79eb3239f1516f6009b75a19b) (cherry picked from commit 9ffc9044e99182f743ff272af71d8888f2d8665c) Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2021-04-27MLK-25334-2 PCI: imx: export one property to disable l1ss support or notRichard Zhu
Some HW boards might not support the L1.1 ASPM, although the L1.1 ASPM is supported by the SOC chip. So, export one property to disable L1.1 ASPM supported or not. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com> (cherry picked from commit 4e42c418396d545a48a4eb47a04ce73a27b0415e) (cherry picked from commit 3edfbde763cc6a7a687344a6207e12c10de04542) Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2021-04-27MLK-25283-4 PCI: imx: adjust the l1ss support to proper placeRichard Zhu
Add one final quirk to adjust the l1ss support to proper place. Only enable the L1sub support when both RC and EP supports the L1sub. In this case, remove the over-ride of the CLKREQ# signal, let HW to control it automatically. Since "dis_gpio" GPIO pin is used as M.2 Key-E interface PIN56 for power control of EP device, adjust active sequence just after the turn-on of the power domains. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com> (cherry picked from commit 02f7efffe67332a4daacae732cccd012d4cbf9db) (cherry picked from commit 9a6ced78cfb6e6fcffa35ed546e7d81c11dc4120) Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2021-02-02pci: pci-imx6: fix driver hangs in a register writeOleksandr Suvorov
During mirgarion to the NXP's 5.4.70-2.3.0 branch, the original fix of this problem was misapplied. Retune the original Philippe's fix for the new driver version. Related-to: ELB-3529 Fixed: 8879894c4dad ("pci-imx6: make sure driver exits if pll can't be locked") Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-01-28pci: pci-imx6: fix kernel hanging on imx6qOleksandr Suvorov
The resume from a suspend state on SoC i.MX6Q leads to a kernel hanging. Adding a 10ms delay after clearing the bit TEST_POWERDOWN of IOMUXC_GPR1 regiater fixes this issue. There is not enough information about the testing "powerdown" mode on i.MX6Q, but we can do some assumption. According to "49.6.1.2 Power-On Reset" section of the "i.MX6D/6Q APRM", the time between bringing up the PHY power supplies and the reference clock is up and stable is (< 10ms) + (> 10mks) ~= 10ms. So using this value seems reasonable. Related-to: ELB-3012 Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-01-28pci-imx6: fix goto-error-handling to also disable regulatorPhilippe Schenker
remove disabling regulator from imx6_pcie_establish_link function to prevent unbalanced regulator disabling. Related-to: ELB-3156 Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2021-01-28pci-imx6: make sure driver exits if pll can't be lockedPhilippe Schenker
Without this patch the driver hangs in a register write because PLL couldn't lock. Related-to: ELB-3156 Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Conflicts: drivers/pci/controller/dwc/pci-imx6.c Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-01-27PCI: pci-imx6: disable end point if not neededOleksandr Suvorov
In asserted state of core it is safe to disable an end point of pcie host, saving power consumption. Related-to: ELB-3025 Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-01-27PCI: pci-imx6: add power-on gpio optionOleksandr Suvorov
Regulator solution doesn't work for Colibri-iMX8X. Forward port supporting of power-on gpio option to drive power switch for WiFi chip directly. Related-to: ELB-3025 Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Conflicts: drivers/pci/controller/dwc/pci-imx6.c Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-01-27PCI: pci-imx6: probe hsio mix on imx8mp onlyOleksandr Suvorov
The HSIO MIX uses by iMX8MP only, so preform probing the node fsl,imx8mp-hsio-mix this SoC only. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-01-27pci: imx6q-pcie: fix extra probingOleksandr Suvorov
The driver pci-imx6 tries to get pcie-phy node for all variants of PCIe controller, whereas it has sense for iMX8MP variant only. Avoid probing pcie-phy for non-iMX8MP SoC. It also fixes false warnings "couldn't get pcie-phy" for other variants. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Conflicts: drivers/pci/controller/dwc/pci-imx6.c Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-01-27pci-imx6.c: allow clean initalisation sequence for colibri imx8qxp pcie/wifiMax Krummenacher
- Port the driver to use the gpiod framework This allows to choose the polarity of the power_on and disable gpio in the device tree. - Actually use the gpios in the initialisation sequence Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> (cherry picked from commit 91aedb97b4e65c4afc66f5a5b8d670061addd80d) (cherry picked from commit 15a9d28286bba122f15e342cd40c6da7294b9bb6) Fixed gpiod stuff after imx_4.14.98_2.3.0 resp. 4.14-2.3.x-imx merge. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> (cherry picked from commit e7ee6fdd1e892626c37c457473e4996818c32b09) Conflicts: drivers/pci/dwc/pci-imx6.c Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Conflicts: drivers/pci/controller/dwc/pci-imx6.c Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-01-27PCI: imx6: add external clock support for i.MX8QMStefan Agner
Add external reference clock via clock tree. This allows to model the shared reference clock provided via PCIE_SATA_REFCLK100M_P/N properly. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> (cherry picked from commit db22e75903386929c76188978f28b3bf355322a0) Conflicts: drivers/pci/host/pci-imx6.c Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> (cherry picked from commit 57364eca822fb2803b6aa93257e93e0d4242282d) (cherry picked from commit f32040d9607bf3e7de57cf05733ae0b5d27b5640) (cherry picked from commit 1c51d5cc8d041a5dfe3a1793bb3767450cab3c1a) (cherry picked from commit f178e6c2afcc37dc5c4771b5bad64286836b2120) Conflicts: drivers/pci/dwc/pci-imx6.c Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2020-10-30MLK-24937-4 pci: modify AMBA_ORDERING_CTRL_OFF register for rc/ep to avoid ↵Sherry Sun
vop iperf3 test hang We met system hang when doing vop iperf3 test, the root cause is there is a deadlock when non-posted reads can’t be completed before posted write completion for the PCIe ordering rules. Here is just a workaround to set the AMBA_ORDERING_CTRL_OFF register to disable ordering rules on AXI bridge. Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
2020-10-26MLK-24910-2 PCI: imx: refine pcie driverRichard Zhu
pci imx set the dbi_wr_en when re-configure the link gen Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-10-20MA-17597-5 pci: controller: dwc: support module buildJindong
Support build PCI_IMX6 as module. Also export the dw_pcie_link_up() function to be able to build drivers Signed-off-by: Jindong <jindong.yue@nxp.com> Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
2020-10-20MLK-24901 PCI: imx: use ep mem windown to setup the alignmentRichard Zhu
EP has it's own memory windown alignment, use it to refine the EP/RC validation codes. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2020-10-15MLK-16836 PCI: imx: add the bus freq sysfile interfaceRichard Zhu
To support the bus freq power saving mode, add the sysfile interface. Request bus high: echo 1 > /sys/devices/platform/xxxxxxxx.pcie/bus_freq Release bus high: echo 0 > /sys/devices/platform/xxxxxxxx.pcie/bus_freq Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-06-24MLK-24171-5 PCI: imx8mp: verify the pcie internal pll reference clockRichard Zhu
- Verify the both internal PLL_SYS and external OSC reference clock modes on iMX8MP EVK board, and pass the PCIe compliance tests. - Remove the no-needed bypass setting. - PHY configration should be completed before CMN_RSTN is set to 1b1 - To manually initiate the speed change to make sure GEN2 is linked up: - Write to LINK_CONTROL2_LINK_STATUS2_REG.PCIE_CAP_TARGET_LINK_SPEED in the local device - De-assert GEN2_CTRL_OFF.DIRECT_SPEED_CHANGE in the local device - Assert GEN2_CTRL_OFF.DIRECT_SPEED_CHANGE in the local device Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-06-17MLK-24197 PCI: imx: remove one info messageRichard Zhu
Remove one dev_info message Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-06-17MLK-24170 PCI: imx: configure the l1 latency for imx8m pcie rcRichard Zhu
Configure the L1 latency of iMX8M's RC to less than 64us, otherwise, the L1/L1SS wouldn't be enabled by ASPM. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-06-11MLK-24012-17 PCI: imx: add imx6 pcie ep supportRichard Zhu
Add the iMX6Q/DL/QP PCIe EP supports, and verify on sabresd board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-06-11MLK-24012-16 PCI: imx: add imx7d pcie ep supportRichard Zhu
Add the iMX7D PCIe EP mode support and verify on SDB board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-06-11MLK-24012-15 PCI: imx: add imx6sx pcie ep supportRichard Zhu
Add the iMX6SX PCIe EP support and verify on SDB board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-06-11MLK-24012-14 pci: imx: add imx8m pcie ep supportRichard Zhu
Add the iMX8MQ/MM/MP PCIe EP support Set the align to 64K since it is required by iMX8M PCIe inbound/outbound Remove the redundant codes of the CLKREQ_OVERRIDE setting, since these codes are duplicated. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-06-11MLK-24012-13 PCI: imx: add the imx8qm ep supportRichard Zhu
Add the iMX8QM PCIe EP mode support, and verify on iMX8QM MEK board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-06-11MLK-24012-12 pci: imx: add the imx8qxp ep supportRichard Zhu
Add the PCIe EP mode on iMX8QXP, and verify EP mode on iMX8QXP MEK board Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-05-14MLK-24008 PCI: imx: refine the codes to do compliance testsRichard Zhu
- Don't limit to only PCIe GEN1 when do the compliance tests. - Configure the TX drive level of iMX865 PHY, adjust the peak output voltage to pass the PCIe GEN1 compliance tests. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com>
2020-05-09MLK-23950 PCI: imx: refine the pd managementsRichard Zhu
- Return correct value before error out to fix the iMX6SX SDB boot hang issue. - Refine the PD management, add device link to the PCIe PER power domain too. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-05-06MLK-23901 PCI: imx: Initialize the variable value to fix build warningRichard Zhu
Initialize the variable value to fix build warning. CC drivers/pci/controller/dwc/pci-imx6.o drivers/pci/controller/dwc/pci-imx6.c: In function ‘imx6_pcie_probe’: drivers/pci/controller/dwc/pci-imx6.c:2676:5: warning: ‘ret’ may be used uninitialized in this function [-Wmaybe-uninitialized] Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-05-06MLK-23899 PCI: imx: fix the warn dump of the dev linkRichard Zhu
Fix the warn dump of the device driver bound link. Indroduced by kernel updates "515db266a9dace92b0cbaed9a6044dd5304b8ca9" Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-04-08MLK-23757 PCI: imx: remove the pd link automaticallyRichard Zhu
Replace DL_FLAG_STATELESS by DL_FLAG_AUTOREMOVE_CONSUMER. Thus, the link can be removed automatically on PCIe driver unbind, and the PDs of PCIe can be turned off accordingly. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Acked-by: Fugang Duan <fugang.duan@nxp.com>
2020-03-26MLK-23668-2 PCI: imx: add the pcieb for imx8qmRichard Zhu
Enable the second PCIe port PCIEB on i.MX8QM platforms. - PCIEB has one more PER clock, since that the PCIEA CSR register would be configuired when PCIEB is initialized. - Use CLKREQ override on i.MX8QM/i.MX8QXP - In the PCIEAX1PCIEBx1SATA usecase, the PHYX2_PCLK[0] is mandatory required by PCIEB. Otherwise PCIEB can't link up when exist from L2 mode when only PCIEB is used. - Regarding to the base board HW limitation(two Disable#) are not connected. Only the standard PCIe EP device is supported on PCIEB port. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-03-06LF-1088 PCI: imx: pcie rc can't access ep's memoryRichard Zhu
RC can't access EP's DDR memory on i.MX8MQ/i.MX8MM platforms. Rootcause: The BAR# of EP are not configured correct. The BAR# offset is 1Mbytes on i.MX8MQ/i.MX8MM, but is 4Kbytes on other i.MX platforms(e.x 6/7/8QM/8QXP/8MP). Correct the BAR# access offset on i.MX8MQ/i.MX8MM to fix it. Let DBI always be writeable in EP/RC validation system. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-02-26LF-721 drivers: pci: dwc: pci-imx6: remove the unnecessary header fileJason Liu
The #include <linux/uaccess.h> is unnecessary, which was included accidently. Fixes:1bf9d07f50a2("LF-228 drivers: pci: dwc: pci-imx6: handle the abort") Signed-off-by: Jason Liu <jason.hui.liu@nxp.com> Acked-by: Richard Zhu <hongxing.zhu@nxp.com> (cherry picked from commit 8b79ecfd377de7b9403d65491da305412b5340b8)
2020-02-26LF-228 drivers: pci: dwc: pci-imx6: handle the abort from user-spaceJason Liu
The driver install one hook to handle the external abort, but issue is that if the abort introduced from user space code, the following code unsigned long instr = *(unsigned long *)pc; which will created another data-abort(page domain fault) if CONFIG_CPU_SW_DOMAIN_PAN. The patch does not intent to use copy_from_user and then do the hack due to the security consideration. In fact, we can just return and report the external abort to user-space. Signed-off-by: Jason Liu <jason.hui.liu@nxp.com> Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> (cherry picked from commit 1bf9d07f50a24a08f9da2795bf39bf03ba2e7135)
2020-02-21LF-970 PCI: imx: make sure that the msi_en is setRichard Zhu
The PCI_MSI_FLAGS of some legacy platforms maybe mis-set to zero. Make sure that the MSI_EN is set on them at the end of the initialization. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Acked-by: Fugang Duan <fugang.duan@nxp.com>
2020-02-13MLK-23303-6 PCI: imx: add the imx8mp pcie supportRichard Zhu
Add the iMX8MP PCIe support. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <Fugang.duan@nxp.com>
2020-02-05LF-853 PCI: imx: do not enable ep mode on imx8mq evk pcie port0Richard Zhu
Since the PCIE port0 is hard-wired to connect one WIFI chip. Don't enable EP mode on iMX8MQ EVK PCIE port0. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2020-02-05LF-290 PCI: imx: add the pcie pm workaround for imx6qdlRichard Zhu
Add the PCIe PM workaround for iMX6QDL. ------ L2 can exit by 'reset' or inband beacon (from remote EP) toggling phy_powerdown has same effect as 'inband beacon' So, toggle bit18 of GPR1, used as a workaround of errata ERR005723 "PCIe PCIe does not support L2 Power Down" WARNING: This is not official workaround for ERR005723. Fortunately, we don't encounter issue with this workaround. User should take own risk to use it. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-12-30LF-625 PCI: imx: pcie ep probe failedRichard Zhu
The atu_base should be assigned if the iatu_unroll_enabled is true. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Acked-by: Fugang Duan <fugang.duan@nxp.com>
2019-12-24LF-583 PCI: imx6q: turn off the refclk and set testpd mode when link is downRichard Zhu
To save power consumption, turn off the REFCLK and set the test power down mode when link is down during the initialization. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Acked-by: Fugang Duan <fugang.duan@nxp.com>
2019-11-29LF-128 PCI: imx: turn off the clocks and regulators when link is downRichard Zhu
To save power consumption, disable pcie clocks and regulators when pcie link is down. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2019-11-27PCI: imx: add the imx pcie ep verification solutionRichard Zhu
Enable the PCIE EP RC for iMX - hw setup: * two imx boards, one is used as pcie rc, the other is used as pcie ep. RC TX N/P <--> EP RX N/P RX N/P <--> EP TX N/P - sw setup: * when build rc image, make sure that CONFIG_PCI_IMX6=y CONFIG_RC_MODE_IN_EP_RC_SYS=y * when build ep image CONFIG_PCI_IMX6=y CONFIG_EP_MODE_IN_EP_RC_SYS=y - features: * set-up link between rc and ep by their stand-alone ref clk running internally. * in ep's system, ep can access the reserved ddr memory (default address:0x4000_0000 on imx6q sd board, and 0xb000_0000 on imx6sx sdb and imx7d arm2 boards) of pcie rc's system, by the interconnection between pcie ep and pcie rc. * provide one example, howto configure the bar# of ep and so on, when pcie ep emaluates one memory ram ep device * setup one new outbound memory region at rc side, let imx pcie rc can access the memory of imx pcie ep in imx pcie rc ep validation system. - NOTE: * boot up ep platform firstly, then boot up rc platform. * For imx6q/6dl/6sx/7d sabresd boards, make sure that mem=768M is contained in the kernel command line, since the start address of the upper 256mb of the 1g ddr mem is reserved to do the pcie ep rc access operations in default. - RC access memory of EP: - EP: write the <ddr_region_address> to the bar0 of ep. echo <ddr_region_address> > /sys/devices/.../pcie/ep_bar0_addr - RC: access the <pcie_mem_base_addr>, and this address would be mapped to the <ddr_region_address> of ep. - Note: ddr_region_address pcie_mem_base_addr bar0_addr imx6qdl 0x4000_0000 0x0100_0000 0x01ff_c010 imx6sx 0xb000_0000 0x0800_0000 0x08ff_c010 imx7d 0xb000_0000 0x4000_0000 0x3380_0010 imx8mq 0xb820_0000 0x2000_0000 0x33c0_0010 imx8mm 0xb820_0000 0x1800_0000 0x3380_0010 imx8qm 0x9020_0000 0x6000_0000 0x5f00_0010 imx8qxp 0x9020_0000 0x7000_0000 0x5f01_0010 - The example of the RC access memory of EP step1: EP side: echo 0x90200000 > /sys/devices/platform/bus@5f000000/5f000000.pcie /ep_bar0_addr root@imx8_all:~# ./memtool 90200000 4 Reading 0x4 count starting at address 0x90200000 0x90200000: 00000000 00000000 00000000 00000000 RC side: ./memtool 60000000=55aa55aa Writing 32-bit value 0x55AA55AA to address 0x60000000 EP side: root@imx8_all:~# ./memtool 90200000 4 Reading 0x4 count starting at address 0x90200000 0x90200000: 55AA55AA 00000000 00000000 00000000 Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
2019-11-25MLK-22995: pci: controller: dwc: pci-imx6: fix regulator warning complains ↵Robin Gong
on i.mx6sx-sdb Commit 5eaa8f6f6dba("PCI: imx: enable the epdev_on regulator after possible -EPROBE_DEFER") still not enough on i.mx6sx-sdb: [ 1.168638] imx6q-pcie 8ffc000.pcie: 8ffc000.pcie supply epdev_on not found, using dummy regulator [ 1.173250] ------------[ cut here ]------------ [ 1.173387] WARNING: CPU: 0 PID: 7 at drivers/regulator/core.c:2042 _regulator_put.part.8+0x1a4/0x1c8 [ 1.173409] Modules linked in: [ 1.173439] CPU: 0 PID: 7 Comm: kworker/u2:0 Not tainted 5.4.0-rc7-03212-ga83f2b7 #55 [ 1.173457] Hardware name: Freescale i.MX6 SoloX (Device Tree) [ 1.173488] Workqueue: events_unbound async_run_entry_fn [ 1.173527] [<c0112b60>] (unwind_backtrace) from [<c010cccc>] (show_stack+0x10/0x14) [ 1.173555] [<c010cccc>] (show_stack) from [<c0d63420>] (dump_stack+0xe0/0x114) [ 1.173581] [<c0d63420>] (dump_stack) from [<c0137188>] (__warn+0xe4/0x10c) [ 1.173604] [<c0137188>] (__warn) from [<c0137254>] (warn_slowpath_fmt+0xa4/0xb4) [ 1.173630] [<c0137254>] (warn_slowpath_fmt) from [<c05fdb74>] (_regulator_put.part.8+0x1a4/0x1c8) [ 1.173658] [<c05fdb74>] (_regulator_put.part.8) from [<c05fdbc4>] (regulator_put+0x2c/0x3c) [ 1.173684] [<c05fdbc4>] (regulator_put) from [<c06f9fac>] (release_nodes+0x168/0x1f4) [ 1.173713] [<c06f9fac>] (release_nodes) from [<c06f598c>] (really_probe+0x118/0x350) [ 1.173739] [<c06f598c>] (really_probe) from [<c06f5d40>] (driver_probe_device+0x5c/0x164) [ 1.173763] [<c06f5d40>] (driver_probe_device) from [<c06f5e98>] (__driver_attach_async_helper+0x50/0x54) [ 1.173791] [<c06f5e98>] (__driver_attach_async_helper) from [<c0162030>] (async_run_entry_fn+0x3c/0x104) [ 1.173820] [<c0162030>] (async_run_entry_fn) from [<c0157b64>] (process_one_work+0x2c4/0x75c) [ 1.173844] [<c0157b64>] (process_one_work) from [<c0158030>] (worker_thread+0x34/0x574) [ 1.173868] [<c0158030>] (worker_thread) from [<c015f730>] (kthread+0x10c/0x148) [ 1.173891] [<c015f730>] (kthread) from [<c01010b4>] (ret_from_fork+0x14/0x20) [ 1.173909] Exception stack(0xd80d7fb0 to 0xd80d7ff8) [ 1.173929] 7fa0: 00000000 00000000 00000000 00000000 [ 1.173949] 7fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 1.173969] 7fe0: 00000000 00000000 00000000 00000000 00000013 0000000 Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-11-25Revert "MLK-11484-3 PCI: designware: Refine setup_rc and add msi data restore"richard zhu
This patch is not proper for 5.4 kernel, revert it by this commit. This reverts commit 8b76ca7ff3f7bb26223e5aa111d3bef987e62a4e. Signed-off-by: richard zhu <hongxing.zhu@nxp.com> Acked-by: Fugang Duan <fugang.duan@nxp.com>
2019-11-25PCI: imx: enable the epdev_on regulator after possible -EPROBE_DEFERrichard zhu
Enable the epdev_on regulator after possible -EPROBE_DEFER. Otherwise, there would kernel WARNING dump if there is -EPROBE_DEFER later during boot procedure. [ 1.335146] WARNING: CPU: 1 PID: 7 at drivers/regulator/core.c:2042 _regulator_put.part.27+0x140/0x148 [ 1.344423] Modules linked in: [ 1.347470] CPU: 1 PID: 7 Comm: kworker/u4:0 Not tainted 5.4.0-rc5-02973-ged0629621d25 #15 [ 1.355716] Hardware name: Freescale i.MX8DXL Phantom MEK (DT) [ 1.361547] Workqueue: events_unbound async_run_entry_fn [ 1.366838] pstate: 80000005 (Nzcv daif -PAN -UAO) [ 1.368962] Bus freq driver module loaded [ 1.371620] pc : _regulator_put.part.27+0x140/0x148 [ 1.371628] lr : regulator_put+0x34/0x48 [ 1.384384] sp : ffff80001005bc20 [ 1.387685] x29: ffff80001005bc20 x28: 0000000000000000 [ 1.391866] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled [ 1.392986] x27: 0000000000000000 x26: ffff8000100fddf0 [ 1.392992] x25: 0000000000000000 x24: 0000000000000007 [ 1.392997] x23: ffff80001005bcd8 x22: ffff000029844600 Signed-off-by: richard zhu <hongxing.zhu@nxp.com> Acked-by: Fugang Duan <fugang.duan@nxp.com>
2019-11-25MLK-15141-1: PCI: imx: Add epdev_on regulator for 8QM WiFiTiberiu Breana
Add the epdev_on regulator to power up the WiFi module on the iMX8QM board. This regulator needs to be powered up before the pcie link, in order for the WiFi module to work. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Tiberiu Breana <andrei-tiberiu.breana@nxp.com> rebase on v4.19 Signed-off-by: Vipul Kumar <vipul_kumar@mentor.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-29 00:22:41 +0000