From 3d63f3493ac677bc890a1f56d02b1b5facb1ca73 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 16 Jul 2020 09:43:25 +0800 Subject: MLK-24410 phy: pcie: imx8mp: correct the clock mode of the pcie phy Correct the clock mode of PCIe PHY. Signed-off-by: Richard Zhu Reviewed-by: Fugang Duan (cherry picked from commit 2c23d9de9fc41d5436a7d3f8510fc95f3bf1c56b) --- drivers/phy/freescale/phy-fsl-imx8-pcie.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-imx8-pcie.c b/drivers/phy/freescale/phy-fsl-imx8-pcie.c index 11f2bff151dd..f2e4d1ac2feb 100644 --- a/drivers/phy/freescale/phy-fsl-imx8-pcie.c +++ b/drivers/phy/freescale/phy-fsl-imx8-pcie.c @@ -181,14 +181,16 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev) return -ENOMEM; imx8_phy->flags &= ~IMX8MP_PCIE_PHY_FLAG_EXT_OSC; - if (of_property_read_u32(np, "clk_mode", &val) < 0) + if (of_property_read_u32(np, "ext_osc", &val) < 0) /* - * Not specify clk_mod, use the external OSC as default + * Not specify ext_osc, use the external OSC as default * CLK mode. */ imx8_phy->flags |= IMX8MP_PCIE_PHY_FLAG_EXT_OSC; if (val == 0) imx8_phy->flags &= ~IMX8MP_PCIE_PHY_FLAG_EXT_OSC; + else if (val == 1) + imx8_phy->flags |= IMX8MP_PCIE_PHY_FLAG_EXT_OSC; else dev_info(dev, "invalid clk mode %d.\n", val); -- cgit v1.2.3