From bf21bbbf66087db04c923270334fab8f06993736 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Mon, 17 Jun 2019 16:53:51 +0200 Subject: ARM: dts (ds): imx6ull*colibri*: Merge changes from 4.9-2.3.x-imx-next In 4.14 devicetress are based on the mainline DT's and only necessary stuff for downstream is put into those devicetrees. This commit holds the changes for imx6ull*colibri* from 4.9. Signed-off-by: Philippe Schenker (cherry picked from commit 2b1fa08bf92d264028e15a14a052a63f8380da65) Conflicts: arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi arch/arm/boot/dts/imx6ull-colibri.dtsi Squashed commit 'ARM: dts: imx6ull-colibri: add missing #endif' into this one. Signed-off-by: Philippe Schenker --- arch/arm/boot/dts/imx6ull-colibri.dtsi | 76 ++++++++++++++++++++++++++++++++-- 1 file changed, 73 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts/imx6ull-colibri.dtsi') diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index b178e130c948..17a28fdfd5d2 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -11,6 +11,29 @@ ethernet1 = &fec1; }; + memory { + reg = <0x80000000 0x10000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x08000000>; + linux,cma-default; + }; + }; + + cpus { + cpu0: cpu@0 { + dc-supply = <®_soc_in>; + }; + }; + bl: backlight { compatible = "pwm-backlight"; pinctrl-names = "default"; @@ -19,6 +42,12 @@ status = "disabled"; }; + pxp_v4l2_out { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", \ + "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; regulator-always-on; @@ -47,6 +76,26 @@ states = <1800000 0x1 3300000 0x0>; vin-supply = <®_module_3v3>; }; + + reg_soc_in: regulator-soc-in { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1275000>; + regulator-max-microvolt = <1275000>; + regulator-name = "soc_in"; + regulator-type = "voltage"; + vin-supply = <®_module_3v3>; + }; + + reg_eth_phy: regulator-eth-phy { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "eth_phy"; + regulator-type = "voltage"; + vin-supply = <®_module_3v3>; + clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; + startup-delay-us = <150000>; + }; }; &adc1 { @@ -67,6 +116,7 @@ pinctrl-1 = <&pinctrl_enet2_sleep>; phy-mode = "rmii"; phy-handle = <ðphy1>; + phy-supply = <®_eth_phy>; status = "okay"; mdio { @@ -81,6 +131,14 @@ }; }; +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ +}; + &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; @@ -156,6 +214,10 @@ #pwm-cells = <3>; }; +&pxp { + status = "okay"; +}; + &sdma { status = "okay"; }; @@ -167,14 +229,14 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; - uart-has-rtscts; + fsl,uart-has-rtscts; fsl,dte-mode; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; + fsl,uart-has-rtscts; fsl,dte-mode; }; @@ -208,6 +270,7 @@ }; &iomuxc { + imx6ull-colibri { pinctrl_can_int: canint-grp { fsl,pins = < MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14 /* SODIMM 73 */ @@ -523,7 +586,7 @@ MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059 - MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14 + MX6UL_PAD_GPIO1_IO03__REF_CLK_32K 0x14 >; }; @@ -532,6 +595,7 @@ MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 >; }; + }; /* imx6ull { */ }; &iomuxc_snvs { @@ -587,6 +651,12 @@ >; }; + pinctrl_snvs_cd_usdhc1_sleep: snvs-usdhc1-cd-grp-slp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 + >; + }; + pinctrl_snvs_usdhc1_sleep_cd: snvs-usdhc1-cd-grp-slp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 -- cgit v1.2.3