From 10f13c70c956131b2f5b49224496aa23bb953683 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Mon, 29 Jul 2019 18:46:23 +0200 Subject: ARM64: dts: colibri-imx8x: Add common eval-hardware to devicetree Signed-off-by: Philippe Schenker --- arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi') diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi index 75157b0e0d8b..8b7275dcd5f9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi @@ -271,6 +271,12 @@ >; }; + pinctrl_can_int: can-int-grp { + fsl,pins = < + SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */ + >; + }; + pinctrl_csi_ctl: csictlgrp { fsl,pins = < SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 */ @@ -278,6 +284,12 @@ >; }; + pinctrl_gpiokeys: gpiokeysgrp { + fsl,pins = < + SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x20 /* SODIMM 45 */ + >; + }; + /* Colibri UART_B */ pinctrl_lpuart0: lpuart0grp { fsl,pins = < @@ -364,11 +376,9 @@ pinctrl_hog1: hog1grp { fsl,pins = < - SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x20 /* SODIMM 45 */ SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */ SC_P_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */ SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */ - SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x20 /* SODIMM 73 */ SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */ SC_P_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */ SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */ -- cgit v1.2.3