// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Copyright 2019-2020 Toradex
 */

#include "dt-bindings/pwm/pwm.h"
#include "imx8mm.dtsi"

/ {
	chosen {
		bootargs = "console=ttymxc0,115200 earlycon";
		stdout-path = &uart1;
	};

	aliases {
		rtc0 = &rtc_i2c;
		rtc1 = &snvs_rtc;
	};

	/* fixed clock dedicated to SPI CAN controller */
	clk20m: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <20000000>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_keys>;

		wakeup {
			debounce-interval = <10>;
			gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
			label = "Wake-Up";
			linux,code = <KEY_WAKEUP>;
			wakeup-source;
		};
	};

	/* Carrier Board Supply */
	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "REG_3P3V";
	};

	reg_aux_usb: regulator-aux-usb {
		compatible = "regulator-fixed";
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "REG_AUX_USB";
	};

	reg_mipi_phy: regulator-mipi-phy {
		compatible = "regulator-fixed";
		regulator-max-microvolt = <1000000>;
		regulator-min-microvolt = <1000000>;
		regulator-name = "REG_MIPI_PHY";
	};

	reg_ethphy: regulator-ethphy {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
		off-on-delay = <500000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_eth>;
		regulator-boot-on;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "V3.3_ETH";
		startup-delay-us = <200000>;
	};

	reg_usb_otg1_vbus: regulator-usb-otg1 {
		compatible = "regulator-fixed";
		enable-active-high;
		/* Verdin USB1_EN */
		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb1_en>;
		regulator-max-microvolt = <5000000>;
		regulator-min-microvolt = <5000000>;
		regulator-name = "usb_otg1_vbus";
	};

	reg_usb_otg2_vbus: regulator-usb-otg2 {
		compatible = "regulator-fixed";
		enable-active-high;
		/* Verdin USB2_EN */
		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb2_en>;
		regulator-max-microvolt = <5000000>;
		regulator-min-microvolt = <5000000>;
		regulator-name = "usb_otg2_vbus";
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "V3.3_SD";
		startup-delay-us = <2000>;
		off-on-delay = <100000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		rpmsg_reserved: rpmsg@b8000000 {
			no-map;
			reg = <0 0xb8000000 0 0x400000>;
		};
	};

	sound_card: sound-card {
		compatible = "simple-audio-card";
		simple-audio-card,bitclock-master = <&dailink_master>;
		simple-audio-card,format = "i2s";
		simple-audio-card,frame-master = <&dailink_master>;
		simple-audio-card,name = "imx8mm-wm8904";
		simple-audio-card,routing =
			"Headphone Jack", "HPOUTL",
			"Headphone Jack", "HPOUTR",
			"IN2L", "Line In Jack",
			"IN2R", "Line In Jack",
			"Microphone Jack", "MICBIAS",
			"IN1L", "Microphone Jack",
			"IN1R", "Microphone Jack";
		simple-audio-card,widgets =
			"Microphone", "Microphone Jack",
			"Headphone", "Headphone Jack",
			"Line", "Line In Jack";

		dailink_master: simple-audio-card,codec {
			sound-dai = <&wm8904_1a>;
			clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
		};

		simple-audio-card,cpu {
			sound-dai = <&sai2>;
		};
	};
};

&A53_0 {
	cpu-supply = <&buck2_reg>;
};

/* Verdin SPI_1 */
&ecspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
};

/* On-module CAN controller 1 & 2 */
&ecspi3 {
	#address-cells = <1>;
	#size-cells = <0>;
	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>,
		   <&gpio1 5 GPIO_ACTIVE_LOW>;
	/* This property is required, even if marked as obsolete in the doku */
	fsl,spi-num-chipselects = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3>;
	status = "okay";

	can1: can@0 {
		compatible = "microchip,mcp2517fd";
		clocks = <&clk20m>;
		gpio-controller;
		interrupt-parent = <&gpio1>;
		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
		microchip,clock-allways-on;
		microchip,clock-out-div = <1>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_can1_int>;
		reg = <0>;
		spi-max-frequency = <2000000>;
	};

	can2: can@1 {
		compatible = "microchip,mcp2517fd";
		clocks = <&clk20m>;
		gpio-controller;
		interrupt-parent = <&gpio1>;
		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_can2_int>;
		reg = <1>;
		spi-max-frequency = <2000000>;
		/* not assembled */
		status = "disabled";
	};
};

&fec1 {
	fsl,magic-packet;
	phy-handle = <&ethphy0>;
	phy-mode = "rgmii-id";
	phy-supply = <&reg_ethphy>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_fec1>;
	pinctrl-1 = <&pinctrl_fec1_sleep>;

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@7 {
			compatible = "ethernet-phy-ieee802.3-c22";
			interrupt-parent = <&gpio1>;
			interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
			micrel,led-mode = <0>;
			reg = <7>;
		};
	};
};

/* Verdin QSPI_1 */
&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
#if 0
	flash0: mt25qu256aba@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,mt25qu256aba";
		reg = <0>;
		spi-max-frequency = <80000000>;
		spi-nor,ddr-quad-read-dummy = <6>;
	};
#endif
};

&gpio1 {
	gpio-line-names = "SODIMM_216",
			  "SODIMM_19",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_220",
			  "SODIMM_222",
			  "",
			  "SODIMM_218",
			  "SODIMM_155",
			  "SODIMM_157",
			  "SODIMM_185",
			  "SODIMM_187";
};

&gpio2 {
	gpio-line-names = "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_84",
			  "SODIMM_78",
			  "SODIMM_74",
			  "SODIMM_80",
			  "SODIMM_82",
			  "SODIMM_70",
			  "SODIMM_72";
};

&gpio5 {
	gpio-line-names = "SODIMM_131",
			  "",
			  "SODIMM_91",
			  "SODIMM_16",
			  "SODIMM_15",
			  "SODIMM_208",
			  "SODIMM_137",
			  "SODIMM_139",
			  "SODIMM_141",
			  "SODIMM_143",
			  "SODIMM_196",
			  "SODIMM_200",
			  "SODIMM_198",
			  "SODIMM_202",
			  "",
			  "",
			  "SODIMM_55",
			  "SODIMM_53",
			  "SODIMM_95",
			  "SODIMM_93",
			  "SODIMM_14",
			  "SODIMM_12",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_210",
			  "SODIMM_212",
			  "SODIMM_151",
			  "SODIMM_153";

	ctrl_sleep_moci {
		gpio-hog;
		gpios = <1 GPIO_ACTIVE_HIGH>;
		line-name = "CTRL_SLEEP_MOCI#";
		output-high;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
	};
};

/* On-module I2C */
&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	pmic: pca9450@25 {
		reg = <0x25>;
		compatible = "nxp,pca9450";
		/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
		pinctrl-0 = <&pinctrl_pmic>;
		gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
		i2c-lt-en = <0x101>;

		regulators {
			#address-cells = <1>;
			#size-cells = <0>;

			pca9450,pmic-buck2-uses-i2c-dvs;
			/* Run/Standby voltage */
			pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;

			buck1_reg: regulator@0 {
				reg = <0>;
				regulator-compatible = "buck1";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			buck2_reg: regulator@1 {
				reg = <1>;
				regulator-compatible = "buck2";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			buck3_reg: regulator@2 {
				reg = <2>;
				regulator-compatible = "buck3";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck4_reg: regulator@3 {
				reg = <3>;
				regulator-compatible = "buck4";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5_reg: regulator@4 {
				reg = <4>;
				regulator-compatible = "buck5";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6_reg: regulator@5 {
				reg = <5>;
				regulator-compatible = "buck6";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1_reg: regulator@6 {
				reg = <6>;
				regulator-compatible = "ldo1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2_reg: regulator@7 {
				reg = <7>;
				regulator-compatible = "ldo2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1150000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3_reg: regulator@8 {
				reg = <8>;
				regulator-compatible = "ldo3";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4_reg: regulator@9 {
				reg = <9>;
				regulator-compatible = "ldo4";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo5_reg: regulator@10 {
				reg = <10>;
				regulator-compatible = "ldo5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};

	rtc_i2c: rtc@32 {
		compatible = "epson,rx8130";
		reg = <0x32>;
	};

	adc@49 {
		compatible = "ti,ads1015";
		reg = <0x49>;
		#address-cells = <1>;
		#size-cells = <0>;

		/* Verdin I2C_1 (ADC_4 - ADC_3) */
		channel@0 {
			reg = <0>;
			ti,gain = <2>;
			ti,datarate = <4>;
		};

		/* Verdin I2C_1 (ADC_4 - ADC_1) */
		channel@1 {
			reg = <1>;
			ti,gain = <2>;
			ti,datarate = <4>;
		};

		/* Verdin I2C_1 (ADC_3 - ADC_1) */
		channel@2 {
			reg = <2>;
			ti,gain = <2>;
			ti,datarate = <4>;
		};

		/* Verdin I2C_1 (ADC_2 - ADC_1) */
		channel@3 {
			reg = <3>;
			ti,gain = <2>;
			ti,datarate = <4>;
		};

		/* Verdin I2C_1 ADC_4 */
		channel@4 {
			reg = <4>;
			ti,gain = <2>;
			ti,datarate = <4>;
		};

		/* Verdin I2C_1 ADC_3 */
		channel@5 {
			reg = <5>;
			ti,gain = <2>;
			ti,datarate = <4>;
		};

		/* Verdin I2C_1 ADC_2 */
		channel@6 {
			reg = <6>;
			ti,gain = <2>;
			ti,datarate = <4>;
		};

		/* Verdin I2C_1 ADC_1 */
		channel@7 {
			reg = <7>;
			ti,gain = <2>;
			ti,datarate = <4>;
		};
	};

	eeprom@50 {
		compatible = "st,24c02";
		pagesize = <16>;
		reg = <0x50>;
	};
};

/* Verdin I2C_3_HDMI N/A */

/* Verdin I2C_4_CSI */
&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};

/* Verdin I2C_1 */
&i2c4 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c4>;
	pinctrl-1 = <&pinctrl_i2c4_gpio>;
	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	/* Audio Codec */
	wm8904_1a: codec@1a {
		compatible = "wlf,wm8904";
		#sound-dai-cells = <0>;
		clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
		clock-names = "mclk";
		reg = <0x1a>;
		status = "disabled";
		DCVDD-supply = <&reg_3p3v>;
		DBVDD-supply = <&reg_3p3v>;
		AVDD-supply = <&reg_3p3v>;
		CPVDD-supply = <&reg_3p3v>;
		MICVDD-supply = <&reg_3p3v>;
	};

	gpio_expander_21: gpio-expander@21 {
		compatible = "nxp,pcal6416";
		#gpio-cells = <2>;
		gpio-controller;
		reg = <0x21>;
		status = "disabled";
		vcc-supply = <&reg_3p3v>;
	};

	/* Current measurement into module VCC */
	hwmon: hwmon@40 {
		compatible = "ti,ina219";
		reg = <0x40>;
		shunt-resistor = <10000>;
		status = "disabled";
	};

	/* EEPROM on display adapter (MIPI DSI Display Adapter) */
	eeprom_display_adapter: eeprom@50 {
		compatible = "st,24c02";
		pagesize = <16>;
		reg = <0x50>;
		status = "disabled";
	};

	/* EEPROM on carrier board */
	eeprom_carrier_board: eeprom@57 {
		compatible = "st,24c02";
		pagesize = <16>;
		reg = <0x57>;
		status = "disabled";
	};
};

&lcdif {
	status = "okay";
};

&mu {
	status = "okay";
};

/* Verdin PCIE_1 */
&pcie0 {
	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
		 <&clk IMX8MM_CLK_PCIE1_AUX>,
		 <&clk IMX8MM_CLK_PCIE1_PHY>,
		 <&clk IMX8MM_CLK_PCIE1_PHY>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	epdev_on-supply = <&reg_3p3v>;
	ext_osc = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reserved-region = <&rpmsg_reserved>;
	reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
};

/* Verdin PWM_3_DSI */
&pwm1 {
	#pwm-cells = <3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm_1>;
};

/* Verdin PWM_1 */
&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm_2>;
	#pwm-cells = <3>;
};

/* Verdin PWM_2 */
&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm_3>;
	#pwm-cells = <3>;
};

/* VERDIN I2S_1 */
&sai2 {
	#sound-dai-cells = <0>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
};

&snvs_pwrkey {
	status = "okay";
};

/* Verdin UART_3 */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
};

/* Verdin UART_1 */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	fsl,uart-has-rtscts;
};

/* Verdin UART_2 */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	fsl,uart-has-rtscts;
};

/* Verdin UART_4 */
/*
 * resource allocated to M4 by default, must not be accessed from A-35 or you
 * get an OOPS
 */
&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
};

&usbmisc1 {
	vbus-wakeup-supply = <&reg_aux_usb>;
};

&usbmisc2 {
	vbus-wakeup-supply = <&reg_aux_usb>;
};

/* Verdin USB_1 */
&usbotg1 {
	adp-disable;
	dr_mode = "otg";
	hnp-disable;
	over-current-active-low;
	picophy,dc-vol-level-adjust = <7>;
	picophy,pre-emp-curr-control = <3>;
	srp-disable;
	vbus-supply = <&reg_usb_otg1_vbus>;
};

/* Verdin USB_2 */
&usbotg2 {
	dr_mode = "host";
	over-current-active-low;
	picophy,dc-vol-level-adjust = <7>;
	picophy,pre-emp-curr-control = <3>;
	vbus-supply = <&reg_usb_otg2_vbus>;
};

&usbphynop1 {
	vcc-supply = <&reg_aux_usb>;
};

&usbphynop2 {
	vcc-supply = <&reg_aux_usb>;
};

/* On-module eMMC */
&usdhc1 {
	bus-width = <8>;
	keep-power-in-suspend;
	non-removable;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	pm-ignore-notify;
	status = "okay";
	/* TODO Strobe */
};

/* Verdin SD_1 */
&usdhc2 {
	bus-width = <4>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	disable-wp;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
};

&vpu_g1 {
	status = "okay";
};

&vpu_g2 {
	status = "okay";
};

&vpu_h1 {
	status = "okay";
};

&wdog1 {
	fsl,ext-reset-output;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio7>,
		    <&pinctrl_gpio8>, <&pinctrl_gpio_hog1>,
		    <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
		    <&pinctrl_sai5>, <&pinctrl_pmic_tpm_ena>;

	pinctrl_can1_int: can1intgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x1c4	/* CAN_1_SPI_INT#_1.8V */
		>;
	};

	pinctrl_can2_int: can2intgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x1c4	/* CAN_2_SPI_INT#_1.8V */
		>;
	};

	pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1			0x1c4	/* CTRL_SLEEP_MOCI */
		>;
	};

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x4	/* SODIMM 196 */
			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x4	/* SODIMM 200 */
			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x1c4	/* SODIMM 198 */
			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x1c4	/* SODIMM 202 */
		>;
	};

	pinctrl_ecspi3: ecspi3grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK		0x4
			MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI		0x4
			MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO		0x1c4
			MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25		0x1c4
			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x1c4
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x1c4
		>;
	};

	pinctrl_fec1_sleep: fec1-sleepgrp {
		fsl,pins = <
			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
			MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18		0x1f
			MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19		0x1f
			MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20		0x1f
			MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21		0x1f
			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23		0x1f
			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x1f
			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x184
		>;
	};

	pinctrl_flexspi0: flexspi0grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x1c2	/* SODIMM 52 */
			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B		0x82	/* SODIMM 54 */
			MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B		0x82	/* SODIMM 64 */
			MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS		0x82	/* SODIMM 66 */
			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0		0x82	/* SODIMM 56 */
			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1		0x82	/* SODIMM 58 */
			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2		0x82	/* SODIMM 60 */
			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3		0x82	/* SODIMM 62 */
		>;
	};

	pinctrl_gpio3: gpio3grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26		0x184	/* SODIMM 210 */
		>;
	};

	pinctrl_gpio4: gpio4grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27		0x184	/* SODIMM 212 */
		>;
	};

	pinctrl_gpio5: gpio5grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x184	/* SODIMM 216 */
		>;
	};

	pinctrl_gpio6: gpio6grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x184	/* SODIMM 218 */
		>;
	};

	pinctrl_gpio7: gpio7grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x184	/* SODIMM 220 */
		>;
	};

	pinctrl_gpio8: gpio8grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x184	/* SODIMM 222 */
		>;
	};

	pinctrl_gpio_hog1: gpiohog1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20		0x1c4	/* SODIMM 88 */
			MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1			0x1c4	/* SODIMM 90 */
			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2		0x1c4	/* SODIMM 92 */
			MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3		0x1c4	/* SODIMM 94 */
			MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4		0x1c4	/* SODIMM 96 */
			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5		0x1c4	/* SODIMM 100 */
			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0		0x1c4	/* SODIMM 102 */
			MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11		0x1c4	/* SODIMM 104 */
			MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12		0x1c4	/* SODIMM 106 */
			MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13		0x1c4	/* SODIMM 108 */
			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14		0x1c4	/* SODIMM 112 */
			MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15		0x1c4	/* SODIMM 114 */
			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16		0x1c4	/* SODIMM 116 */
			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x1c4	/* SODIMM 118 */
			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10		0x1c4	/* SODIMM 120 */
		>;
	};

	pinctrl_gpio_hog2: gpiohog2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x1c4	/* SODIMM 91 */
		>;
	};

	pinctrl_gpio_hog3: gpiohog3grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x1c4	/* SODIMM 157 */
			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x1c4	/* SODIMM 187 */
		>;
	};

	pinctrl_gpio_keys: gpiokeysgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x1c4	/* SODIMM 252 */
		>;
	};

	/* On-module I2C */
	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c6	/* PMIC_I2C_SCL */
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c6	/* PMIC_I2C_SDA */
		>;
	};

	pinctrl_i2c1_gpio: i2c1gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14		0x400001c6	/* PMIC_I2C_SCL */
			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15		0x400001c6	/* PMIC_I2C_SDA */
		>;
	};

	/* Verdin I2C_4_CSI */
	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c6	/* SODIMM 55 */
			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c6	/* SODIMM 53 */
		>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x400001c6	/* SODIMM 55 */
			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x400001c6	/* SODIMM 53 */
		>;
	};

	/* Verdin I2C_2_DSI */
	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c6	/* SODIMM 95 */
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c6	/* SODIMM 93 */
		>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18		0x400001c6	/* SODIMM 95 */
			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19		0x400001c6	/* SODIMM 93 */
		>;
	};

	/* Verdin I2C_1 */
	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x400001c6	/* SODIMM 14 */
			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x400001c6	/* SODIMM 12 */
		>;
	};

	pinctrl_i2c4_gpio: i2c4gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20		0x400001c6	/* SODIMM 14 */
			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21		0x400001c6	/* SODIMM 12 */
		>;
	};

	/* Verdin MEZ_DSI_1_BKL_EN */
	pinctrl_mez_dsi_1_bkl_en: mezdsi1bklengrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3		0x1c4	/* SODIMM 21 */
		>;
	};

	/* Verdin MEZ_DSI_1_INT HPD (pulled-down as active-high) */
	pinctrl_mez_dsi_1_int_hpd: mezdsi1inthpdgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15		0x184	/* SODIMM 17 */
		>;
	};

	/* Verdin MEZ_DSI_1_INT# (pulled-up as active-low) */
	pinctrl_mez_dsi_1_int_n: mezdsi1intngrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15		0x1c4	/* SODIMM 17 */
		>;
	};

	/* MEZ_GPIO_1 shared with MEZ_DSI_1_INT on Verdin DSI to HDMI Display Adapter */
	pinctrl_mez_gpio1: mezgpio1grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x184	/* SODIMM 206 */
		>;
	};

	pinctrl_mez_gpio2: mezgpio2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5		0x1c4	/* SODIMM 208 */
		>;
	};

	pinctrl_pcie0: pcie0grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19		0x6	/* SODIMM 244 */
			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x6	/* PMIC_EN_PCIe_CLK */
		>;
	};

	pinctrl_pmic: pmicirqgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41	/* PMIC_INT# */
		>;
	};

	pinctrl_pwm_1: pwm1grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT		0x6	/* SODIMM 19 */
		>;
	};

	pinctrl_pwm_2: pwm2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT			0x6	/* SODIMM 15 */
		>;
	};

	pinctrl_pwm_3: pwm3grp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT			0x6	/* SODIMM 16 */
		>;
	};

	pinctrl_reg_eth: regethgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_WP_GPIO2_IO20			0x184	/* PMIC_EN_ETH */
		>;
	};

	pinctrl_reg_usb1_en: regusb1engrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x184	/* SODIMM 155 */
		>;
	};

	pinctrl_reg_usb2_en: regusb2engrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x184	/* SODIMM 185 */
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0xd6	/* SODIMM 32 */
			MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0xd6	/* SODIMM 30 */
			MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK		0xd6	/* SODIMM 38 */
			MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0		0xd6	/* SODIMM 36 */
			MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0		0xd6	/* SODIMM 34 */
		>;
	};

	pinctrl_sai5: sai5grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0		0xd6	/* SODIMM 48 */
			MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC		0xd6	/* SODIMM 44 */
			MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK		0xd6	/* SODIMM 42 */
			MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0		0xd6	/* SODIMM 46 */
		>;
	};

	/* currently unused ctrl signal for SE050 or ATTPM20P */
	pinctrl_pmic_tpm_ena: pmictpmenagrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x1c4	/* PMIC_TPM_ENA */
		>;
	};

	pinctrl_tsp: tspgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6		0x140	/* SODIMM 148 */
			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7		0x140	/* SODIMM 152 */
			MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8		0x140	/* SODIMM 154 */
			MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x140	/* SODIMM 179 */
			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17		0x140	/* SODIMM 150 */
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI2_RXFS_UART1_TX			0x1c4	/* SODIMM 149 */
			MX8MM_IOMUXC_SAI2_RXC_UART1_RX			0x1c4	/* SODIMM 147 */
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_TX		0x1c4	/* SODIMM 129 */
			MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_RX		0x1c4	/* SODIMM 131 */
			MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B		0x1c4	/* SODIMM 133 */
			MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B		0x1c4	/* SODIMM 135 */
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX		0x1c4	/* SODIMM 137 */
			MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX		0x1c4	/* SODIMM 139 */
			MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x1c4	/* SODIMM 141 */
			MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x1c4	/* SODIMM 143 */
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x1c4	/* SODIMM 151 */
			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x1c4	/* SODIMM 153 */
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x190
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d0
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d0
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d0
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d0
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d0
			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d0
			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d0
			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d0
			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d0
			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 	0x1d1
			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x190
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x194
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d4
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d4
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d4
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d4
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d4
			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d4
			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d4
			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d4
			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d4
			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 	0x1d1
			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x194
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x196
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d6
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d6
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d6
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d6
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d6
			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d6
			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d6
			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d6
			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d6
			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 	0x1d1
			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x196
		>;
	};

	pinctrl_usdhc2_cd: usdhc2cdgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x1c4	/* SODIMM 84 */
		>;
	};

	pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5			0x184	/* SODIMM 76 */
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x190	/* SODIMM 78 */
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0	/* SODIMM 74 */
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0	/* SODIMM 80 */
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0	/* SODIMM 82 */
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0	/* SODIMM 70 */
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0	/* SODIMM 72 */
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x194
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x196
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0
		>;
	};

	/* On-module Wi-Fi/BT or SDHC interface on the X52 extention slot */
	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6	/* PMIC_WDI */
		>;
	};

	pinctrl_wifi_ctrl: wifictrlgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16		0x1c4		/* WIFI_WKUP_BT */
			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20		0x1c4		/* WIFI_WKUP_WLAN */
			MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x1c4		/* WIFI_W_WKUP_HOST */
		>;
	};

	pinctrl_wifi_i2s: bti2sgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK		0xd6		/* WIFI_TX_BCLK */
			MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0		0xd6		/* WIFI_TX_DATA0 */
			MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC		0xd6		/* WIFI_TX_SYNC */
			MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0		0xd6		/* WIFI_RX_DATA0 */
		>;
	};

	pinctrl_wifi_pwr_en: wifipwrengrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25		0x184		/* PMIC_EN_WIFI */
		>;
	};
};