// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2018 NXP * Richard Zhu */ &hsio_subsys { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; pciea_lpcg: clock-controller@5f050000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5f050000 0x10000>; #clock-cells = <1>; clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>; bit-offset = <16 20 24>; clock-output-names = "hsio_pciea_mstr_axi_clk", "hsio_pciea_slv_axi_clk", "hsio_pciea_dbi_axi_clk"; power-domains = <&pd IMX_SC_R_PCIE_A>; }; sata_lpcg: clock-controller@5f070000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5f070000 0x10000>; #clock-cells = <1>; clocks = <&hsio_axi_clk>; bit-offset = <16>; clock-output-names = "hsio_sata_clk"; power-domains = <&pd IMX_SC_R_SATA_0>; }; phyx2_lpcg: clock-controller@5f080000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5f080000 0x10000>; #clock-cells = <1>; clocks = <&hsio_refa_clk>, <&hsio_per_clk>, <&hsio_refa_clk>, <&hsio_per_clk>; bit-offset = <0 4 16 20>; clock-output-names = "hsio_phyx2_pclk_0", "hsio_phyx2_pclk_1", "hsio_phyx2_apbclk_0", "hsio_phyx2_apbclk_1"; power-domains = <&pd IMX_SC_R_SERDES_0>; }; phyx1_lpcg: clock-controller@5f090000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5f090000 0x10000>; #clock-cells = <1>; clocks = <&hsio_refa_clk>, <&hsio_per_clk>, <&hsio_per_clk>, <&hsio_per_clk>; bit-offset = <0 4 8 16>; clock-output-names = "hsio_phyx1_pclk", "hsio_phyx1_epcs_tx_clk", "hsio_phyx1_epcs_rx_clk", "hsio_phyx1_apb_clk"; power-domains = <&pd IMX_SC_R_SERDES_1>; }; phyx2_crr0_lpcg: clock-controller@5f0a0000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5f0a0000 0x10000>; #clock-cells = <1>; clocks = <&hsio_per_clk>; bit-offset = <16>; clock-output-names = "hsio_phyx2_per_clk"; power-domains = <&pd IMX_SC_R_SERDES_0>; }; pciea_crr2_lpcg: clock-controller@5f0c0000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5f0c0000 0x10000>; #clock-cells = <1>; clocks = <&hsio_per_clk>; bit-offset = <16>; clock-output-names = "hsio_pciea_per_clk"; power-domains = <&pd IMX_SC_R_PCIE_A>; }; sata_crr4_lpcg: clock-controller@5f0e0000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5f0e0000 0x10000>; #clock-cells = <1>; clocks = <&hsio_per_clk>; bit-offset = <16>; clock-output-names = "hsio_sata_per_clk"; power-domains = <&pd IMX_SC_R_SATA_0>; }; pciea: pcie@0x5f000000 { compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; reg = <0x5f000000 0x10000>, /* Controller reg */ <0x6ff00000 0x80000>, /* PCI cfg space */ <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */ reg-names = "dbi", "config", "hsio"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; ranges = <0x81000000 0 0x00000000 0x6ff80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x60000000 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */ num-lanes = <1>; num-viewport = <4>; interrupts = , ; /* eDMA */ interrupt-names = "msi", "dma"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic 0 73 4>, <0 0 0 2 &gic 0 74 4>, <0 0 0 3 &gic 0 75 4>, <0 0 0 4 &gic 0 76 4>; /* * Set these clocks in default, then clocks should be * refined for exact hw design of imx8 pcie. */ clocks = <&pciea_lpcg 0>, <&pciea_lpcg 1>, <&pciea_lpcg 2>, <&phyx2_lpcg 0>, <&phyx2_crr0_lpcg 0>, <&pciea_crr2_lpcg 0>, <&misc_crr5_lpcg 0>; clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", "pcie_phy", "phy_per", "pcie_per", "misc_per"; power-domains = <&pd IMX_SC_R_PCIE_A>, <&pd IMX_SC_R_SERDES_0>, <&pd IMX_SC_R_HSIO_GPIO>; power-domain-names = "pcie", "pcie_phy", "hsio_gpio"; fsl,max-link-speed = <3>; hsio-cfg = ; local-addr = <0x40000000>; status = "disabled"; }; pcieb: pcie@0x5f010000 { compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; reg = <0x5f010000 0x10000>, /* Controller reg */ <0x7ff00000 0x80000>, /* PCI cfg space */ <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */ reg-names = "dbi", "config", "hsio"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; ranges = <0x81000000 0 0x00000000 0x7ff80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x70000000 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ num-lanes = <1>; num-viewport = <4>; interrupts = , ; /* eDMA */ interrupt-names = "msi", "dma"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic 0 105 4>, <0 0 0 2 &gic 0 106 4>, <0 0 0 3 &gic 0 107 4>, <0 0 0 4 &gic 0 108 4>; clocks = <&pcieb_lpcg 0>, <&pcieb_lpcg 1>, <&pcieb_lpcg 2>, <&phyx2_lpcg 1>, <&phyx2_lpcg 0>, <&phyx2_crr0_lpcg 0>, <&pcieb_crr3_lpcg 0>, <&pciea_crr2_lpcg 0>, <&misc_crr5_lpcg 0>; clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", "pcie_phy", "pcie_phy_pclk", "phy_per", "pcie_per", "pciex2_per", "misc_per"; power-domains = <&pd IMX_SC_R_PCIE_B>, <&pd IMX_SC_R_PCIE_A>, <&pd IMX_SC_R_SERDES_0>, <&pd IMX_SC_R_HSIO_GPIO>; power-domain-names = "pcie", "pcie_per", "pcie_phy", "hsio_gpio"; fsl,max-link-speed = <3>; hsio-cfg = ; local-addr = <0x80000000>; status = "disabled"; }; sata: sata@5f020000 { compatible = "fsl,imx8qm-ahci"; reg = <0x5f020000 0x10000>, /* Controller reg */ <0x5f1a0000 0x10000>, /* PHY reg */ <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */ reg-names = "ctl", "phy", "hsio"; interrupts = ; clocks = <&sata_lpcg 0>, <&phyx1_lpcg 0>, <&phyx1_lpcg 1>, <&phyx1_lpcg 2>, <&phyx2_crr0_lpcg 0>, <&phyx1_crr1_lpcg 0>, <&pciea_crr2_lpcg 0>, <&pcieb_crr3_lpcg 0>, <&sata_crr4_lpcg 0>, <&misc_crr5_lpcg 0>, <&phyx2_lpcg 0>, <&phyx2_lpcg 1>, <&phyx1_lpcg 3>; clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", "per_clk0", "per_clk1", "per_clk2", "per_clk3", "per_clk4", "per_clk5", "phy_pclk0", "phy_pclk1", "phy_apbclk"; power-domains = <&pd IMX_SC_R_SATA_0>, <&pd IMX_SC_R_PCIE_A>, <&pd IMX_SC_R_PCIE_B>, <&pd IMX_SC_R_SERDES_0>, <&pd IMX_SC_R_SERDES_1>, <&pd IMX_SC_R_HSIO_GPIO>; fsl,sc_rsrc_id = ; iommus = <&smmu 0x13 0x7f80>; status = "disabled"; }; };