// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

&dma_ipg_clk {
	clock-frequency = <160000000>;
};

&audio_ipg_clk {
	clock-frequency = <160000000>;
};

&lpuart0 {
	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
};

&lpuart1 {
	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
};

&lpuart2 {
	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
};

&lpuart3 {
	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
};

&i2c0 {
	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};

&i2c1 {
	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};

&i2c2 {
	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};

&i2c3 {
	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};

&audio_subsys {

	dsp: dsp@596e8000 {
		compatible = "fsl,imx8qxp-dsp";
		reg = <0x596e8000 0x88000>;
		clocks = <&dsp_lpcg 1>,
			 <&dsp_ram_lpcg 0>,
			 <&dsp_lpcg 2>;
		clock-names = "ipg", "ocram", "core";
		fsl,dsp-firmware = "imx/dsp/hifi4.bin";
		power-domains = <&pd IMX_SC_R_MU_13A>,
				<&pd IMX_SC_R_MU_13B>,
				<&pd IMX_SC_R_DSP>,
				<&pd IMX_SC_R_DSP_RAM>,
				<&pd IMX_SC_R_IRQSTR_DSP>;
		mbox-names = "txdb0", "txdb1",
			"rxdb0", "rxdb1";
		mboxes = <&lsio_mu13 2 0>,
			<&lsio_mu13 2 1>,
			<&lsio_mu13 3 0>,
			<&lsio_mu13 3 1>;
		status = "disabled";
	};
};

&dma_subsys {
	lcdif_mux_regs: mux-regs@5a170000 {
		compatible = "fsl,imx8qxp-lcdif-mux-regs", "syscon";
		reg = <0x5a170000 0x4>;
	};

	adma_pwm: pwm@5a190000 {
		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
		reg = <0x5a190000 0x1000>;
		clocks = <&adma_pwm_lpcg 0>, <&adma_pwm_lpcg 1>;
		clock-names = "per", "ipg";
		assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		#pwm-cells = <2>;
		power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
		status = "disabled";
	};

	adma_pwm_lpcg: clock-controller@5a590000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a590000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "adma_pwm_lpcg_clk",
				     "adma_pwm_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
	};
};