diff options
| author | Jerry Huang <Chang-Ming.Huang@freescale.com> | 2010-03-17 16:07:10 +0800 |
|---|---|---|
| committer | Scott Sweeny <scott.sweeny@timesys.com> | 2010-09-29 17:32:29 -0400 |
| commit | ad58fa5e76b465acf259928975a78329a3b8fef1 (patch) | |
| tree | ddc028845965483adb91c3ab3800d0b143a9e405 | |
| parent | 5cb83814555b4970547780550428dea1f6bb1224 (diff) | |
eSDHC: add the reset function to reset the eSDHC controller
Reset the eSDHC controller first before initialize the eSDHC controller.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 22 | ||||
| -rw-r--r-- | include/fsl_esdhc.h | 1 |
2 files changed, 22 insertions, 1 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 3c068d6a17..c61461ff15 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, Freescale Semiconductor, Inc + * Copyright 2007, 2010 Freescale Semiconductor, Inc * Andy Fleming * * Based vaguely on the pxa mmc code: @@ -318,12 +318,32 @@ static int esdhc_init(struct mmc *mmc) return 0; } +static void esdhc_reset(struct fsl_esdhc *regs) +{ + unsigned long timeout; + + /* reset the controller */ + out_be32(®s->sysctl, SYSCTL_RSTA); + + /* wait max 100 ms */ + timeout = 100; + /* hardware clears the bit when it is done */ + while ((in_be32(®s->sysctl) & SYSCTL_RSTA) && timeout--) + udelay(1000); + if (!timeout) + printf("MMC/SD: Reset never completed.\n"); + udelay(1000); +} + static int esdhc_initialize(bd_t *bis) { struct fsl_esdhc *regs = (struct fsl_esdhc *)CONFIG_SYS_FSL_ESDHC_ADDR; struct mmc *mmc; u32 caps; + /* First reset the eSDHC controller */ + esdhc_reset(regs); + mmc = malloc(sizeof(struct mmc)); sprintf(mmc->name, "FSL_ESDHC"); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index eac6a2bd48..adb43d765c 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -36,6 +36,7 @@ #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 +#define SYSCTL_RSTA 0x01000000 #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) |