diff options
| author | Ye Li <ye.li@nxp.com> | 2018-07-04 18:55:16 -0700 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2018-07-05 18:48:09 -0700 |
| commit | dc53b0d89b044e387779d4751dd4c7d3bfe0d0a9 (patch) | |
| tree | 26c939e0844dcc6d471581f27ed56db679053fb0 | |
| parent | fc72bf2b5ce59994765da6c5e66745d037e05237 (diff) | |
MLK-18623-3 imx8mm: Set NOC clock root to 750Mhz
According to ADD, the target frequency for NOC bus clock is 750Mhz,
the default setting from ROM is selecting the PLL1_800M_clk as source.
This patch sets the PLL3 to 750Mhz and select it as the source of NOC
clock root.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
| -rw-r--r-- | arch/arm/cpu/armv8/imx8m/clock_imx8mm.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/imx8m/clock_imx8mm.c b/arch/arm/cpu/armv8/imx8m/clock_imx8mm.c index fb7d2ea0d4..9e5d96ee80 100644 --- a/arch/arm/cpu/armv8/imx8m/clock_imx8mm.c +++ b/arch/arm/cpu/armv8/imx8m/clock_imx8mm.c @@ -253,6 +253,7 @@ u32 decode_fracpll(enum clk_root_src frac_pll) } enum intpll_out_freq { + INTPLL_OUT_750M, INTPLL_OUT_800M, INTPLL_OUT_1200M, INTPLL_OUT_1000M, @@ -491,6 +492,11 @@ int intpll_configure(enum pll_clocks pll, enum intpll_out_freq freq) }; switch (freq) { + case INTPLL_OUT_750M: + /* 24 * 0xfa / 2 / 2 ^ 2 */ + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) | + INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(2); + break; case INTPLL_OUT_800M: /* 24 * 0x190 / 3 / 2 ^ 2 */ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190) | @@ -571,7 +577,8 @@ int clock_init() INTPLL_DIV20_CLKE_MASK; writel(val_cfg0, SYS_PLL2_GNRL_CTL); - intpll_configure(ANATOP_SYSTEM_PLL3, INTPLL_OUT_800M); + intpll_configure(ANATOP_SYSTEM_PLL3, INTPLL_OUT_750M); + clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2)); /* config GIC to sys_pll2_100m */ clock_enable(CCGR_GIC, 0); |