diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2019-06-05 11:26:12 +0800 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-11-27 17:40:45 +0100 |
| commit | 34b00d03e5a83abb2033337ebf258cda573554a4 (patch) | |
| tree | 1f2059a418f415a41e5f3ad6c3fc210ba732e697 | |
| parent | 45c7c5507126b21ea5736f69b2a38c913d95f697 (diff) | |
MLK-21950-01 driver: ddr: skip ddr_ss_gpr config on imx8mn
There is no DDR_SS_GPR0 exits on i.MX8MN, so skip setting
this register on i.MX8MN.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit a8040bc4524687ca026b9960fda18eb19606dade)
| -rw-r--r-- | drivers/ddr/imx8m/ddr_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c index 65d467e8dc..8349f29cb4 100644 --- a/drivers/ddr/imx8m/ddr_init.c +++ b/drivers/ddr/imx8m/ddr_init.c @@ -74,7 +74,7 @@ void ddr_init(struct dram_timing_info *dram_timing) /* if ddr type is LPDDR4, do it */ tmp = reg32_read(DDRC_MSTR(0)); - if (tmp & (0x1 << 5)) + if (tmp & (0x1 << 5) && !is_imx8mn()) reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ /* determine the initial boot frequency */ |