diff options
| author | Emanuele Ghidoli <emanuele.ghidoli@toradex.com> | 2024-05-16 13:52:16 +0200 |
|---|---|---|
| committer | Emanuele Ghidoli <emanuele.ghidoli@toradex.com> | 2024-05-17 08:05:25 +0200 |
| commit | 5b9576f1fc56bea87c5cc011bde37ffff5b41b3c (patch) | |
| tree | 7955c7d7da3cfca577d16b8858beaf9eac233c8a | |
| parent | 659050693db19620ace20fa785c097d967897b2e (diff) | |
board: aquila-am69: Read hardware configuration pins
There are 5 dedicated pins used for future hardware
configurations that cannot be autodetected.
Read these pins in the R5 and A72 SPL, and print the configuration.
Upstream-Status: Pending
This patch will be part of a series when Aquila AM69 support
will be upstreamed.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
| -rw-r--r-- | board/toradex/aquila-am69/aquila-am69.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/board/toradex/aquila-am69/aquila-am69.c b/board/toradex/aquila-am69/aquila-am69.c index 213a6984c9..baf7523ddd 100644 --- a/board/toradex/aquila-am69/aquila-am69.c +++ b/board/toradex/aquila-am69/aquila-am69.c @@ -6,6 +6,7 @@ */ #include <asm/arch/hardware.h> +#include <asm/gpio.h> #include <asm/io.h> #include <dm.h> #include <env.h> @@ -17,6 +18,34 @@ #define CTRL_MMR_CFG0_MCU_ADC1_CTRL 0x40F040B4 DECLARE_GLOBAL_DATA_PTR; +static u8 hw_cfg; + +static void read_hw_cfg(void) +{ + struct gpio_desc gpio_hw_cfg; + char gpio_name[20]; + int i; + + printf("HW CFG: "); + for (i = 0; i < 5; i++) { + sprintf(gpio_name, "gpio@42110000_%d", 82 + i); + if (dm_gpio_lookup_name(gpio_name, &gpio_hw_cfg) < 0) { + printf("Lookup named gpio error\n"); + return; + } + + if (dm_gpio_request(&gpio_hw_cfg, "hw_cfg")) { + printf("gpio request error\n"); + return; + } + + if (dm_gpio_get_value(&gpio_hw_cfg) == 1) + hw_cfg |= BIT(i); + + dm_gpio_free(NULL, &gpio_hw_cfg); + } + printf("0x%2x\n", hw_cfg); +} int board_init(void) { @@ -102,4 +131,6 @@ void spl_board_init(void) /* MCU_ADC1 pins used as General Purpose Inputs */ writel(readl(CTRL_MMR_CFG0_MCU_ADC1_CTRL) | BIT(16), CTRL_MMR_CFG0_MCU_ADC1_CTRL); + + read_hw_cfg(); } |