colibri-imx8qxp: add unused pins as gpio

This also enables pullups on the uart forceoff pins.

The UART transceivers on an Iris carrier board can be disabled by
controlling SODIMM pins 102 and/or 104. Make sure that the pins by
default have pullups to have the debug UART working.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>

1 files changed, 113 insertions, 74 deletions

diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts
index 514a14f681..e505ceb3b3 100644
--- a/arch/arm/dts/fsl-imx8qxp-colibri.dts
+++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts
@@ -61,7 +61,8 @@
 
 &iomuxc {
 	pinctrl-names = "default";
-	imx8qxp-mek {
+	pinctrl-0 = <&pinctrl_hog1>, <&pinctrl_hog2>;
+	imx8qxp-colibri {
 
 		pinctrl_lpuart0: lpuart0grp {
 			fsl,pins = <
@@ -77,38 +78,76 @@
 			>;
 		};
 
+		pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
+			fsl,pins = <
+				SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 /* DTR */
+				SC_P_SAI1_RXD_LSIO_GPIO0_IO29		0x00000020 /* CTS */
+				SC_P_SAI1_RXC_LSIO_GPIO0_IO30		0x00000020 /* RTS */
+				SC_P_CSI_RESET_LSIO_GPIO3_IO03		0x00000020 /* DSR */
+				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22	0x00000020 /* DCD */
+				SC_P_CSI_EN_LSIO_GPIO3_IO02		0x00000020 /* RI */
+			>;
+		};
+
 		pinctrl_fec1: fec1grp {
 			fsl,pins = <
-				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000048
-				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000048
-				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000048
-				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT	0x06000048
-				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000048
-				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000048
-				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000048
-				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000048
-				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000048
-				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER	0x06000048
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD      0x000014a0
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD      0x000014a0
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT	0x06000061
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000061
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000061
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000061
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000061
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000061
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER	0x00000061
 			>;
 		};
-#if 0
-		pinctrl_fec2: fec2grp {
+
+		pinctrl_hog1: hog1grp {
 			fsl,pins = <
-				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x06000048
-				SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x06000048
-				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x06000048
-				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x06000048
-				SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x06000048
-				SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x06000048
-				SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x06000048
-				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x06000048
-				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x06000048
-				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x06000048
-				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2	0x06000048
-				SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x06000048
+				SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10	0x00000020 /*  45 */
+				SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02	0x06000020 /*  65 */
+					SC_P_CSI_D07_CI_PI_D09		0x00000061
+				SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11	0x00000020 /*  69 */
+				SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13		0x00000020 /*  73 */
+				SC_P_SAI0_TXC_LSIO_GPIO0_IO26		0x00000020 /*  79 */
+					SC_P_CSI_D02_CI_PI_D04		0x00000061
+				SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03	0x06000020 /*  85 */
+					SC_P_CSI_D06_CI_PI_D08		0x00000061
+				SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17	0x00000020 /*  95 */
+				SC_P_SAI0_RXD_LSIO_GPIO0_IO27		0x00000020 /*  97 */
+					SC_P_CSI_D03_CI_PI_D05		0x00000061
+				SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18	0x00000020 /*  99 */
+				SC_P_SAI0_TXFS_LSIO_GPIO0_IO28		0x00000020 /* 101 */
+					SC_P_CSI_D00_CI_PI_D02          0x00000061
+				SC_P_SAI0_TXD_LSIO_GPIO0_IO25		0x00000020 /* 103 */
+					SC_P_CSI_D01_CI_PI_D03          0x00000061
+				SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19	0x00000020 /* 105 */
+				SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20	0x00000020 /* 107 */
+				SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05	0x00000020 /* 127 */
+				SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06	0x00000020 /* 131 */
+				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04	0x00000020 /* 133 */
+				SC_P_CSI_PCLK_LSIO_GPIO3_IO00		0x00000020 /*  96 */
+				SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21	0x00000020 /*  98 */
+				SC_P_SAI1_RXFS_LSIO_GPIO0_IO31		0x00000020 /* 100 */
+				SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22		0x00000020 /* 102 */
+				SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23	0x00000020 /* 104 */
+				SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24	0x00000020 /* 106 */
 			>;
 		};
-#endif
+
+		pinctrl_hog2: hog2grp {
+			fsl,pins = <
+				SC_P_CSI_MCLK_LSIO_GPIO3_IO01		0x00000020 /*  75 */
+				SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14	0x00000020 /*  77 */
+				SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15	0x00000020 /*  89 */
+				SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16	0x00000020 /*  93 */
+			>;
+		};
+
 
 		pinctrl_lpi2c1: lpi1cgrp {
 			fsl,pins = <
@@ -129,42 +168,42 @@
 				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
 				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
 				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
-				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000041
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
 				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
 			>;
 		};
 
 		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 			fsl,pins = <
-				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
-				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
-				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
-				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
-				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
-				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
-				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
-				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
-				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
-				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
-				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
-				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
 			>;
 		};
 
 		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 			fsl,pins = <
-				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
-				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
-				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
-				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
-				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
-				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
-				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
-				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
-				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
-				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
-				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
-				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
 			>;
 		};
 
@@ -177,36 +216,36 @@
 		pinctrl_usdhc2: usdhc2grp {
 			fsl,pins = <
 				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
-				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x06000021
-				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x06000021
-				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x06000021
-				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x06000021
-				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x06000021
-				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x06000021
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
 			>;
 		};
 
 		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 			fsl,pins = <
-				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
-				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x06000020
-				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x06000020
-				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x06000020
-				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x06000020
-				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x06000020
-				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x06000020
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
 			>;
 		};
 
 		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 			fsl,pins = <
-				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
-				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x06000020
-				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x06000020
-				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x06000020
-				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x06000020
-				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x06000020
-				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x06000020
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
 			>;
 		};
 #if 0
@@ -238,7 +277,7 @@
 			>;
 		};
 
-		pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp {
+		pinctrl_i2c0_mipi_csi: mipi_csi_i2c0_grp {
 			fsl,pins = <
 				SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020
 				SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020
@@ -255,7 +294,7 @@
 
 &lpuart3 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lpuart3>;
+	pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
 	status = "okay";
 };
 
@@ -333,7 +372,7 @@
 	#address-cells = <1>;
 	#size-cells = <0>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>;
+	pinctrl-0 = <&pinctrl_i2c0_mipi_csi>;
 	clock-frequency = <100000>;
 	status = "okay";
 };