diff options
412 files changed, 16865 insertions, 3937 deletions
@@ -21,6 +21,8 @@ Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com> Markus Klotzbuecher <mk@denx.de> Prabhakar Kushwaha <prabhakar@freescale.com> Rajeshwari Shinde <rajeshwari.s@samsung.com> +Ricardo Ribalda <ricardo.ribalda@uam.es> +Ricardo Ribalda <ricardo.ribalda@gmail.com> Sandeep Paulraj <s-paulraj@ti.com> Shaohui Xie <Shaohui.Xie@freescale.com> Stefan Roese <stroese> diff --git a/.travis.yml b/.travis.yml index 4e20e0926f..67674e2f58 100644 --- a/.travis.yml +++ b/.travis.yml @@ -5,23 +5,29 @@ language: c +addons: + apt: + packages: + - cppcheck + - sloccount + - sparse + - bc + - build-essential + - libsdl1.2-dev + cache: - apt install: - # install U-Boot build dependencies - - sudo apt-get install -qq cppcheck sloccount sparse bc libsdl-dev build-essential # install latest device tree compiler - git clone --depth=1 https://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc - make -j4 -C /tmp/dtc # prepare buildman environment - export BUILDMAN_ROOT="root:" - - export BUILDMAN_MIPS="mips:" - export BUILDMAN_PPC="ppc:" - export BUILDMAN_ARM="arm:" - export BUILDMAN_SANDBOX="sandbox:" - echo -e "[toolchain]\n${BUILDMAN_ROOT} /\n" > ~/.buildman - - echo -e "${BUILDMAN_MIPS} /opt/eldk-5.4/mips/sysroots/i686-eldk-linux/usr/bin/mips32-linux/\n" >> ~/.buildman - echo -e "${BUILDMAN_PPC} /opt/eldk-5.4/powerpc/sysroots/i686-eldk-linux/usr/bin/powerpc-linux/\n" >> ~/.buildman - echo -e "${BUILDMAN_ARM} /opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/\n" >> ~/.buildman - echo -e "${BUILDMAN_SANDBOX} /usr/bin/gcc\n" >> ~/.buildman @@ -35,165 +41,121 @@ env: global: - PATH=/tmp/dtc:$PATH - BUILD_DIR=build - - CROSS_COMPILE="" - HOSTCC="cc" - HOSTCXX="c++" - - TEST_CONFIG_CMD="" before_script: - # install toolchains based on INSTALL_TOOLCHAIN} variable - - if [[ "${INSTALL_TOOLCHAIN}" == *arm* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/armv5te/eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh ; fi - - if [[ "${INSTALL_TOOLCHAIN}" == *arm* ]]; then sh eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh -y ; fi - - if [[ "${INSTALL_TOOLCHAIN}" == *arm* ]]; then ls -al /opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi ; fi - - if [[ "${INSTALL_TOOLCHAIN}" == *avr32* ]]; then ./tools/buildman/buildman --fetch-arch avr32 ; fi - - if [[ "${INSTALL_TOOLCHAIN}" == *i386* ]]; then ./tools/buildman/buildman sandbox --fetch-arch i386 ; fi - - if [[ "${INSTALL_TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi - - if [[ "${INSTALL_TOOLCHAIN}" == *mips* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/mips/eldk-eglibc-i686-mips-toolchain-gmae-5.4.sh ; fi - - if [[ "${INSTALL_TOOLCHAIN}" == *mips* ]]; then sh eldk-eglibc-i686-mips-toolchain-gmae-5.4.sh -y ; fi - - if [[ "${INSTALL_TOOLCHAIN}" == *ppc* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/powerpc/eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh ; fi - - if [[ "${INSTALL_TOOLCHAIN}" == *ppc* ]]; then sh eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh -y ; fi + # install toolchains based on TOOLCHAIN} variable + - if [[ "${TOOLCHAIN}" == *aarch64* ]]; then ./tools/buildman/buildman --fetch-arch aarch64 ; fi + - if [[ "${TOOLCHAIN}" == *arm* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/armv5te/eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh ; fi + - if [[ "${TOOLCHAIN}" == *arm* ]]; then sh eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh -y ; fi + - if [[ "${TOOLCHAIN}" == *avr32* ]]; then ./tools/buildman/buildman --fetch-arch avr32 ; fi + - if [[ "${TOOLCHAIN}" == *i386* ]]; then ./tools/buildman/buildman sandbox --fetch-arch i386 ; fi + - if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi + - if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi + - if [[ "${TOOLCHAIN}" == *ppc* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/powerpc/eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh ; fi + - if [[ "${TOOLCHAIN}" == *ppc* ]]; then sh eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh -y ; fi script: # the execution sequence for each test - - echo ${TEST_CONFIG_CMD} - - ${TEST_CONFIG_CMD} - - echo ${TEST_CMD} - - ${TEST_CMD} + - if [[ "${TEST_CMD}" != "" ]]; then + ${TEST_CMD}; + fi + - if [[ "${BUILDMAN}" != "" ]]; then + tools/buildman/buildman ${BUILDMAN}; + fi matrix: include: # we need to build by vendor due to 50min time limit for builds # each env setting here is a dedicated build - env: - - TEST_CMD="./MAKEALL -a arm -v atmel" - INSTALL_TOOLCHAIN="arm" - CROSS_COMPILE="/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/arm-linux-gnueabi-" + - BUILDMAN="arm1136" + TOOLCHAIN="arm" + - env: + - BUILDMAN="arm1136" + TOOLCHAIN="arm" + - env: + - BUILDMAN="arm1176" + TOOLCHAIN="arm" - env: - - TEST_CMD="./MAKEALL -a arm -v denx" - INSTALL_TOOLCHAIN="arm" - CROSS_COMPILE="/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/arm-linux-gnueabi-" + - BUILDMAN="arm720t" + TOOLCHAIN="arm" - env: - - TEST_CMD="./MAKEALL -a arm -v freescale" - INSTALL_TOOLCHAIN="arm" - CROSS_COMPILE="/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/arm-linux-gnueabi-" + - BUILDMAN="arm920t" + TOOLCHAIN="arm" - env: - - TEST_CMD="./MAKEALL -a arm -v siemens" - INSTALL_TOOLCHAIN="arm" - CROSS_COMPILE="/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/arm-linux-gnueabi-" + - BUILDMAN="atmel -x avr32" + TOOLCHAIN="arm" - env: - - TEST_CMD="./MAKEALL -a arm -v ti" - INSTALL_TOOLCHAIN="arm" - CROSS_COMPILE="/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/arm-linux-gnueabi-" + - BUILDMAN="avr32" + TOOLCHAIN="avr32" - env: - - TEST_CONFIG_CMD="make sandbox_defconfig" - TEST_CMD="make -j4" - HOSTCC = "gcc" - HOSTCXX = "g++" + - BUILDMAN="davinci" + TOOLCHAIN="arm" - env: - - TEST_CONFIG_CMD="make sandbox_defconfig" - TEST_CMD="make -j4" - HOSTCC = "clang" - HOSTCXX = "clang++" + - BUILDMAN="denx" + TOOLCHAIN="arm" - env: - - TEST_CMD="./MAKEALL -a mips" - INSTALL_TOOLCHAIN="mips" - CROSS_COMPILE="/opt/eldk-5.4/mips/sysroots/i686-eldk-linux/usr/bin/mips32-linux/mips-linux-" + - BUILDMAN="freescale -x powerpc,m68k,aarch64" + TOOLCHAIN="arm" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman --list-error-boards arm1136" - INSTALL_TOOLCHAIN="arm" + - BUILDMAN="sandbox x86" + TOOLCHAIN="i386" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman --list-error-boards arm1176" - INSTALL_TOOLCHAIN="arm" + - BUILDMAN="kirkwood" + TOOLCHAIN="arm" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman --list-error-boards arm720t" - INSTALL_TOOLCHAIN="arm" + - BUILDMAN="m68k" + TOOLCHAIN="m68k" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman --list-error-boards arm920t" - INSTALL_TOOLCHAIN="arm" + - BUILDMAN="mips" + TOOLCHAIN="mips" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman --list-error-boards atmel -x avr32" - INSTALL_TOOLCHAIN="arm" + - BUILDMAN="mpc512x" + TOOLCHAIN="ppc" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman --list-error-boards avr32" - INSTALL_TOOLCHAIN="avr32" + - BUILDMAN="mpc5xx" + TOOLCHAIN="ppc" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman --list-error-boards davinci" - INSTALL_TOOLCHAIN="arm" + - BUILDMAN="mpc5xxx" + TOOLCHAIN="ppc" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman --list-error-boards denx" - INSTALL_TOOLCHAIN="arm" + - BUILDMAN="mpc8260" + TOOLCHAIN="ppc" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman --list-error-boards freescale -x powerpc,m68k,aarch64" - INSTALL_TOOLCHAIN="arm" + - BUILDMAN="mpc83xx" + TOOLCHAIN="ppc" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman --list-error-boards freescale -x arm,m68k,aarch64" - INSTALL_TOOLCHAIN="ppc" + - BUILDMAN="mpc85xx -x freescale" + TOOLCHAIN="ppc" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman --list-error-boards sandbox x86" - INSTALL_TOOLCHAIN="i386" + - BUILDMAN="mpc85xx -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x sbc8548 -x bsc91*" + TOOLCHAIN="ppc" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman --list-error-boards kirkwood" - INSTALL_TOOLCHAIN="arm" + - BUILDMAN="t208xrdb t4qds t102*" + TOOLCHAIN="ppc" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman --list-error-boards m68k" - INSTALL_TOOLCHAIN="m68k" + - BUILDMAN="p1_p2_rdb_pc p1010rdb" + TOOLCHAIN="ppc" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman mips" - INSTALL_TOOLCHAIN="mips" + - BUILDMAN="corenet_ds b4860qds sbc8548 bsc91*" + TOOLCHAIN="ppc" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman mpc512x" - INSTALL_TOOLCHAIN="ppc" + - BUILDMAN="mpc86xx" + TOOLCHAIN="ppc" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman mpc5xx" - INSTALL_TOOLCHAIN="ppc" + - BUILDMAN="mpc8xx" + TOOLCHAIN="ppc" - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman mpc5xxx" - INSTALL_TOOLCHAIN="ppc" - - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman mpc8260" - INSTALL_TOOLCHAIN="ppc" - - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman mpc83xx" - INSTALL_TOOLCHAIN="ppc" - - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman mpc85xx" - INSTALL_TOOLCHAIN="ppc" - - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman mpc86xx" - INSTALL_TOOLCHAIN="ppc" - - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman mpc8xx" - INSTALL_TOOLCHAIN="ppc" - - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman --list-error-boards siemens" - INSTALL_TOOLCHAIN="arm" - - env: - - TEST_CONFIG_CMD="tools/buildman/buildman --list-tool-chains" - TEST_CMD="tools/buildman/buildman --list-error-boards ti" - INSTALL_TOOLCHAIN="arm" + - BUILDMAN="siemens" + TOOLCHAIN="arm" + - env: + - BUILDMAN="ti" + TOOLCHAIN="arm" + - env: + - BUILDMAN="aarch64" + TOOLCHAIN="aarch64" # QA jobs for code analytics # static code analysis with cppcheck (we can add --enable=all later) @@ -214,7 +176,4 @@ matrix: - env: - TEST_CMD="sloccount ." -notifications: - email: false - # TODO make it perfect ;-r diff --git a/Licenses/OFL.txt b/Licenses/OFL.txt new file mode 100644 index 0000000000..07c881f8a1 --- /dev/null +++ b/Licenses/OFL.txt @@ -0,0 +1,97 @@ +Copyright (c) 2010, Andrey Makarov (makarov@bmstu.ru, mka-at-mailru@mail.ru), +with Reserved Font Name Anka/Coder Narrow. + +Copyright (c) 2011, Pablo Impallari (www.impallari.com|impallari@gmail.com), +Rodrigo Fuenzalida (www.rfuenzalida.com) with Reserved Font Name Cantora. + +This Font Software is licensed under the SIL Open Font License, Version 1.1. +This license is copied below, and is also available with a FAQ at: +http://scripts.sil.org/OFL + + +----------------------------------------------------------- +SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +----------------------------------------------------------- + +PREAMBLE +The goals of the Open Font License (OFL) are to stimulate worldwide +development of collaborative font projects, to support the font creation +efforts of academic and linguistic communities, and to provide a free and +open framework in which fonts may be shared and improved in partnership +with others. + +The OFL allows the licensed fonts to be used, studied, modified and +redistributed freely as long as they are not sold by themselves. The +fonts, including any derivative works, can be bundled, embedded, +redistributed and/or sold with any software provided that any reserved +names are not used by derivative works. The fonts and derivatives, +however, cannot be released under any other type of license. The +requirement for fonts to remain under this license does not apply +to any document created using the fonts or their derivatives. + +DEFINITIONS +"Font Software" refers to the set of files released by the Copyright +Holder(s) under this license and clearly marked as such. This may +include source files, build scripts and documentation. + +"Reserved Font Name" refers to any names specified as such after the +copyright statement(s). + +"Original Version" refers to the collection of Font Software components as +distributed by the Copyright Holder(s). + +"Modified Version" refers to any derivative made by adding to, deleting, +or substituting -- in part or in whole -- any of the components of the +Original Version, by changing formats or by porting the Font Software to a +new environment. + +"Author" refers to any designer, engineer, programmer, technical +writer or other person who contributed to the Font Software. + +PERMISSION & CONDITIONS +Permission is hereby granted, free of charge, to any person obtaining +a copy of the Font Software, to use, study, copy, merge, embed, modify, +redistribute, and sell modified and unmodified copies of the Font +Software, subject to the following conditions: + +1) Neither the Font Software nor any of its individual components, +in Original or Modified Versions, may be sold by itself. + +2) Original or Modified Versions of the Font Software may be bundled, +redistributed and/or sold with any software, provided that each copy +contains the above copyright notice and this license. These can be +included either as stand-alone text files, human-readable headers or +in the appropriate machine-readable metadata fields within text or +binary files as long as those fields can be easily viewed by the user. + +3) No Modified Version of the Font Software may use the Reserved Font +Name(s) unless explicit written permission is granted by the corresponding +Copyright Holder. This restriction only applies to the primary font name as +presented to the users. + +4) The name(s) of the Copyright Holder(s) or the Author(s) of the Font +Software shall not be used to promote, endorse or advertise any +Modified Version, except to acknowledge the contribution(s) of the +Copyright Holder(s) and the Author(s) or with their explicit written +permission. + +5) The Font Software, modified or unmodified, in part or in whole, +must be distributed entirely under this license, and must not be +distributed under any other license. The requirement for fonts to +remain under this license does not apply to any document created +using the Font Software. + +TERMINATION +This license becomes null and void if any of the above conditions are +not met. + +DISCLAIMER +THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT +OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL THE +COPYRIGHT HOLDER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL +DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM +OTHER DEALINGS IN THE FONT SOFTWARE. diff --git a/Licenses/README b/Licenses/README index 731d45c190..5ad921ddfc 100644 --- a/Licenses/README +++ b/Licenses/README @@ -67,4 +67,5 @@ BSD 3-clause "New" or "Revised" License BSD-3-Clause Y bsd-3-clause.txt http:/ IBM PIBS (PowerPC Initialization and IBM-pibs ibm-pibs.txt Boot Software) license ISC License ISC Y isc.txt https://spdx.org/licenses/ISC +SIL OPEN FONT LICENSE (OFL-1.1) OFL-1.1 Y OFL.txt https://spdx.org/licenses/OFL-1.1.html X11 License X11 x11.txt https://spdx.org/licenses/X11.html @@ -747,7 +747,7 @@ endif ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin -ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin +ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb ifeq ($(CONFIG_SPL_FRAMEWORK),y) ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img endif @@ -764,14 +764,9 @@ ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom endif # enable combined SPL/u-boot/dtb rules for tegra -ifneq ($(CONFIG_TEGRA),) -ifeq ($(CONFIG_SPL),y) -ifeq ($(CONFIG_OF_SEPARATE),y) -ALL-y += u-boot-dtb-tegra.bin -else -ALL-y += u-boot-nodtb-tegra.bin -endif -endif +ifeq ($(CONFIG_TEGRA)$(CONFIG_SPL),yy) +ALL-y += u-boot-tegra.bin u-boot-nodtb-tegra.bin +ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb-tegra.bin endif # Add optional build target if defined in board/cpu/soc headers @@ -828,15 +823,23 @@ PHONY += dtbs dtbs dts/dt.dtb: checkdtc u-boot $(Q)$(MAKE) $(build)=dts dtbs -u-boot-dtb.bin: u-boot.bin dts/dt.dtb FORCE +quiet_cmd_copy = COPY $@ + cmd_copy = cp $< $@ + +ifeq ($(CONFIG_OF_SEPARATE),y) +u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE $(call if_changed,cat) +u-boot.bin: u-boot-dtb.bin FORCE + $(call if_changed,copy) +else +u-boot.bin: u-boot-nodtb.bin FORCE + $(call if_changed,copy) +endif + %.imx: %.bin $(Q)$(MAKE) $(build)=arch/arm/imx-common $@ -quiet_cmd_copy = COPY $@ - cmd_copy = cp $< $@ - u-boot.dtb: dts/dt.dtb $(call cmd,copy) @@ -847,11 +850,11 @@ OBJCOPYFLAGS_u-boot.srec := -O srec u-boot.hex u-boot.srec: u-boot FORCE $(call if_changed,objcopy) -OBJCOPYFLAGS_u-boot.bin := -O binary \ +OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ $(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec) -binary_size_check: u-boot.bin FORCE - @file_size=$(shell wc -c u-boot.bin | awk '{print $$1}') ; \ +binary_size_check: u-boot-nodtb.bin FORCE + @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \ map_size=$(shell cat u-boot.map | \ awk '/_image_copy_start/ {start = $$1} /_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print "ibase=16; " toupper(end) " - " toupper(start)}' \ | sed 's/0X//g' \ @@ -859,12 +862,12 @@ binary_size_check: u-boot.bin FORCE if [ "" != "$$map_size" ]; then \ if test $$map_size -ne $$file_size; then \ echo "u-boot.map shows a binary size of $$map_size" >&2 ; \ - echo " but u-boot.bin shows $$file_size" >&2 ; \ + echo " but u-boot-nodtb.bin shows $$file_size" >&2 ; \ exit 1; \ fi \ fi -u-boot.bin: u-boot FORCE +u-boot-nodtb.bin: u-boot FORCE $(call if_changed,objcopy) $(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE)) $(BOARD_SIZE_CHECK) @@ -898,6 +901,8 @@ MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" +MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img) + MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \ -T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) @@ -907,15 +912,10 @@ MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage -u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE +u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE $(call if_changed,mkimage) -u-boot-spl.kwb: u-boot-dtb.img spl/u-boot-spl.bin FORCE - $(call if_changed,mkimage) - -MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img) - -u-boot-dtb.img: u-boot-dtb.bin FORCE +u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) u-boot.sha1: u-boot.bin @@ -1007,10 +1007,10 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE ifneq ($(CONFIG_ARCH_SOCFPGA),) quiet_cmd_socboot = SOCBOOT $@ -cmd_socboot = cat spl/u-boot-spl-dtb.sfp spl/u-boot-spl-dtb.sfp \ - spl/u-boot-spl-dtb.sfp spl/u-boot-spl-dtb.sfp \ - u-boot-dtb.img > $@ || rm -f $@ -u-boot-with-spl-dtb.sfp: spl/u-boot-spl-dtb.sfp u-boot-dtb.img FORCE +cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ + spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ + u-boot.img > $@ || rm -f $@ +u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE $(call if_changed,socboot) endif @@ -1023,7 +1023,7 @@ rom: u-boot.rom FORCE IFDTOOL=$(objtree)/tools/ifdtool IFDTOOL_FLAGS = -f 0:$(objtree)/u-boot.dtb IFDTOOL_FLAGS += -m 0x$(shell $(NM) u-boot |grep _dt_ucode_base_size |cut -d' ' -f1) -IFDTOOL_FLAGS += -U $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot.bin +IFDTOOL_FLAGS += -U $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-nodtb.bin IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin IFDTOOL_FLAGS += -C @@ -1056,7 +1056,7 @@ endif cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_FLAGS) u-boot.tmp; cmd_ifdtool += mv u-boot.tmp $@ -u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin +u-boot.rom: u-boot-x86-16bit.bin u-boot.bin $(call if_changed,ifdtool) OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec @@ -1067,27 +1067,28 @@ endif ifneq ($(CONFIG_SUNXI),) OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \ --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff -u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin \ - u-boot$(if $(CONFIG_OF_CONTROL),-dtb,).img FORCE +u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE $(call if_changed,pad_cat) endif ifneq ($(CONFIG_TEGRA),) OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE) -u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE +u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot-nodtb.bin FORCE $(call if_changed,pad_cat) -ifeq ($(CONFIG_OF_SEPARATE),y) -u-boot-dtb-tegra.bin: u-boot-nodtb-tegra.bin dts/dt.dtb FORCE - $(call if_changed,cat) -endif +OBJCOPYFLAGS_u-boot-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE) +u-boot-tegra.bin: spl/u-boot-spl u-boot.bin FORCE + $(call if_changed,pad_cat) + +u-boot-dtb-tegra.bin: u-boot-tegra.bin FORCE + $(call if_changed,copy) endif OBJCOPYFLAGS_u-boot-app.efi := $(OBJCOPYFLAGS_EFI) u-boot-app.efi: u-boot FORCE $(call if_changed,zobjcopy) -u-boot-dtb.bin.o: u-boot-dtb.bin FORCE +u-boot.bin.o: u-boot.bin FORCE $(call if_changed,efipayload) u-boot-payload.lds: $(LDSCRIPT_EFI) FORCE @@ -1097,10 +1098,10 @@ u-boot-payload.lds: $(LDSCRIPT_EFI) FORCE quiet_cmd_u-boot_payload ?= LD $@ cmd_u-boot_payload ?= $(LD) $(LDFLAGS_EFI_PAYLOAD) -o $@ \ -T u-boot-payload.lds arch/x86/cpu/call32.o \ - lib/efi/efi.o lib/efi/efi_stub.o u-boot-dtb.bin.o \ + lib/efi/efi.o lib/efi/efi_stub.o u-boot.bin.o \ $(addprefix arch/$(ARCH)/lib/efi/,$(EFISTUB)) -u-boot-payload: u-boot-dtb.bin.o u-boot-payload.lds FORCE +u-boot-payload: u-boot.bin.o u-boot-payload.lds FORCE $(call if_changed,u-boot_payload) OBJCOPYFLAGS_u-boot-payload.efi := $(OBJCOPYFLAGS_EFI) @@ -1121,11 +1122,7 @@ spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) ifeq ($(ARCH),arm) -ifdef CONFIG_OF_CONTROL -UBOOT_BINLOAD := u-boot-dtb.img -else UBOOT_BINLOAD := u-boot.img -endif else UBOOT_BINLOAD := u-boot.bin endif @@ -1317,7 +1314,7 @@ spl/u-boot-spl: tools prepare $(if $(CONFIG_OF_SEPARATE),dts/dt.dtb) spl/sunxi-spl.bin: spl/u-boot-spl @: -spl/u-boot-spl-dtb.sfp: spl/u-boot-spl +spl/u-boot-spl.sfp: spl/u-boot-spl @: spl/boot.bin: spl/u-boot-spl @@ -1423,6 +1423,17 @@ The following options need to be configured: CONFIG_TPM_TIS_I2C_BURST_LIMITATION Define the burst count bytes upper limit + CONFIG_TPM_ST33ZP24 + Support for STMicroelectronics TPM devices. Requires DM_TPM support. + + CONFIG_TPM_ST33ZP24_I2C + Support for STMicroelectronics ST33ZP24 I2C devices. + Requires TPM_ST33ZP24 and I2C. + + CONFIG_TPM_ST33ZP24_SPI + Support for STMicroelectronics ST33ZP24 SPI devices. + Requires TPM_ST33ZP24 and SPI. + CONFIG_TPM_ATMEL_TWI Support for Atmel TWI TPM device. Requires I2C support. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 876a620cf1..d2dbb1a5c2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -558,15 +558,15 @@ config ARCH_ZYNQ select CPU_V7 select SUPPORT_SPL select OF_CONTROL - select SPL_OF_CONTROL + select SPL_OF_CONTROL if SPL select DM select DM_ETH - select SPL_DM + select SPL_DM if SPL select DM_MMC select DM_SPI select DM_SERIAL select DM_SPI_FLASH - select SPL_SEPARATE_BSS + select SPL_SEPARATE_BSS if SPL config ARCH_ZYNQMP bool "Support Xilinx ZynqMP Platform" diff --git a/arch/arm/config.mk b/arch/arm/config.mk index a3e14a862b..8fa57ecfd8 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -107,6 +107,7 @@ ALL-y += checkarmreloc # instruction. Relocation is not supported for that case, so disable # such usage by requiring word relocations. PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations) +PLATFORM_CPPFLAGS += $(call cc-option, -fno-pic) endif # limit ourselves to the sections we want in the .bin. diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index a5aa4fa643..94ff48859e 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -16,6 +16,23 @@ #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4 #ifndef CONFIG_SYS_DCACHE_OFF +static int check_cache_range(unsigned long start, unsigned long stop) +{ + int ok = 1; + + if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (!ok) + debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", + start, stop); + + return ok; +} + /* * Write the level and type you want to Cache Size Selection Register(CSSELR) * to get size details from Current Cache Size ID Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void) */ void invalidate_dcache_range(unsigned long start, unsigned long stop) { + check_cache_range(start, stop); + v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); v7_outer_cache_inval_range(start, stop); @@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop) */ void flush_dcache_range(unsigned long start, unsigned long stop) { + check_cache_range(start, stop); + v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE); v7_outer_cache_flush_range(start, stop); diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 856abed941..ae5e794230 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -30,17 +30,13 @@ void ft_fixup_enet_phy_connect_type(void *fdt) int phy_node; int i = 0; uint32_t ph; + char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" }; - while ((dev = eth_get_dev_by_index(i++)) != NULL) { - if (strstr(dev->name, "eTSEC1")) { - strcpy(enet, "ethernet0"); - strcpy(phy, "enet0_rgmii_phy"); - } else if (strstr(dev->name, "eTSEC2")) { - strcpy(enet, "ethernet1"); - strcpy(phy, "enet1_rgmii_phy"); - } else if (strstr(dev->name, "eTSEC3")) { - strcpy(enet, "ethernet2"); - strcpy(phy, "enet2_rgmii_phy"); + for (; i < ARRAY_SIZE(name); i++) { + dev = eth_get_dev_by_name(name[i]); + if (dev) { + sprintf(enet, "ethernet%d", i); + sprintf(phy, "enet%d_rgmii_phy", i); } else { continue; } diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c index deeb674c69..144f2c368d 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c @@ -11,11 +11,11 @@ /* port register default value */ #define AHCI_PORT_PHY_1_CFG 0xa003fffe -#define AHCI_PORT_PHY_2_CFG 0x28183411 -#define AHCI_PORT_PHY_3_CFG 0x0e081004 -#define AHCI_PORT_PHY_4_CFG 0x00480811 -#define AHCI_PORT_PHY_5_CFG 0x192c96a4 -#define AHCI_PORT_TRANS_CFG 0x08000025 +#define AHCI_PORT_PHY_2_CFG 0x28183414 +#define AHCI_PORT_PHY_3_CFG 0x0e080e06 +#define AHCI_PORT_PHY_4_CFG 0x064a080b +#define AHCI_PORT_PHY_5_CFG 0x2aa86470 +#define AHCI_PORT_TRANS_CFG 0x08000029 #define SATA_ECC_REG_ADDR 0x20220520 #define SATA_ECC_DISABLE 0x00020000 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index eafdd71a84..4e4861d107 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -190,6 +190,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif + do_fixup_by_compat_u32(blob, "fixed-clock", + "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); + #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c index 8ef4f1c38f..ea3114cca4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c @@ -28,12 +28,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { SGMII1 } }, {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } }, {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } }, -#ifdef CONFIG_LS2080A - {0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } }, -#endif -#ifdef CONFIG_LS2085A {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, -#endif {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 23d6b73e3d..7ff01481be 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -12,6 +12,9 @@ #include <asm/io.h> #include <asm/global_data.h> #include <asm/arch-fsl-layerscape/config.h> +#ifdef CONFIG_CHAIN_OF_TRUST +#include <fsl_validate.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -219,6 +222,9 @@ void fsl_lsch2_early_init_f(void) init_early_memctl_regs(); /* tighten IFC timing */ #endif +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif /* Make SEC reads and writes snoopable */ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP); @@ -241,6 +247,9 @@ int board_late_init(void) #ifdef CONFIG_SCSI_AHCI_PLAT sata_init(); #endif +#ifdef CONFIG_CHAIN_OF_TRUST + fsl_setenv_chain_of_trust(); +#endif return 0; } diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 2ee60d60f1..67b166c7fd 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -168,6 +168,25 @@ apply_a57_core_errata: msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ #endif +#ifdef CONFIG_ARM_ERRATA_833471 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* FPSCR write flush. + * Note that in some cases where a flush is unnecessary this + could impact performance. */ + orr x0, x0, #1 << 38 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + +#ifdef CONFIG_ARM_ERRATA_829520 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* Disable Indirect Predictor bit will prevent this erratum + from occurring + * Note that in some cases where a flush is unnecessary this + could impact performance. */ + orr x0, x0, #1 << 4 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + #ifdef CONFIG_ARM_ERRATA_833069 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ /* Disable Enable Invalidates of BTB bit */ diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index e5a4fdd0fd..9a19dfa77f 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -20,10 +20,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP -config SECURE_IOU - bool "Configure ZynqMP secure IOU" - default n - config ZYNQMP_USB bool "Configure ZynqMP USB" diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c index 9218586e94..690c72dd66 100644 --- a/arch/arm/cpu/armv8/zynqmp/clk.c +++ b/arch/arm/cpu/armv8/zynqmp/clk.c @@ -21,9 +21,27 @@ unsigned long get_uart_clk(int dev_id) return 48000; case ZYNQMP_CSU_VERSION_EP108: return 25000000; + case ZYNQMP_CSU_VERSION_QEMU: + return 133000000; } - return 133000000; + return 100000000; +} + +unsigned long zynqmp_get_system_timer_freq(void) +{ + u32 ver = zynqmp_get_silicon_version(); + + switch (ver) { + case ZYNQMP_CSU_VERSION_VELOCE: + return 10000; + case ZYNQMP_CSU_VERSION_EP108: + return 4000000; + case ZYNQMP_CSU_VERSION_QEMU: + return 50000000; + } + + return 100000000; } #ifdef CONFIG_CLOCKS diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index f90cca36aa..c71f29152d 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -15,8 +15,22 @@ DECLARE_GLOBAL_DATA_PTR; +static unsigned int zynqmp_get_silicon_version_secure(void) +{ + u32 ver; + + ver = readl(&csu_base->version); + ver &= ZYNQMP_SILICON_VER_MASK; + ver >>= ZYNQMP_SILICON_VER_SHIFT; + + return ver; +} + unsigned int zynqmp_get_silicon_version(void) { + if (current_el() == 3) + return zynqmp_get_silicon_version_secure(); + gd->cpu_clk = get_tbclk(); switch (gd->cpu_clk) { @@ -24,9 +38,11 @@ unsigned int zynqmp_get_silicon_version(void) return ZYNQMP_CSU_VERSION_VELOCE; case 50000000: return ZYNQMP_CSU_VERSION_QEMU; + case 4000000: + return ZYNQMP_CSU_VERSION_EP108; } - return ZYNQMP_CSU_VERSION_EP108; + return ZYNQMP_CSU_VERSION_SILICON; } #ifndef CONFIG_SYS_DCACHE_OFF diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index d48a905cf3..e148ab7513 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -14,23 +14,24 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { +#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC) /* - * Discard the relocation entries for secure text. - * The secure code is bundled with u-boot image, so there will - * be relocations entries for the secure code, since we use - * "-mword-relocations" to compile and "-pie" to link into the - * final image. We do not need the relocation entries for secure - * code, because secure code will not be relocated, it only needs - * to be copied from loading address to CONFIG_ARMV7_SECURE_BASE, - * which is the linking and running address for secure code. - * If keep the relocation entries in .rel.dyn section, - * "relocation offset + linking address" may locates into an - * address that is reserved by SoC, then will trigger data abort. + * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not + * bundle with u-boot, and code offsets are fixed. Secure zone + * only needs to be copied from the loading address to + * CONFIG_ARMV7_SECURE_BASE, which is the linking and running + * address for secure code. * - * The reason that move .rel._secure at the beginning, is to - * avoid hole in the final image. + * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will + * be included in u-boot address space, and some absolute address + * were used in secure code. The absolute addresses of the secure + * code also needs to be relocated along with the accompanying u-boot + * code. + * + * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE. */ /DISCARD/ : { *(.rel._secure*) } +#endif . = 0x00000000; . = ALIGN(4); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1c7d359fa6..77efb292da 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -53,7 +53,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-388-gp.dtb \ armada-xp-gp.dtb \ armada-xp-maxbcm.dtb \ - armada-xp-synology-ds414.dtb + armada-xp-synology-ds414.dtb \ + armada-xp-theadorable.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-ld4-ref.dtb \ @@ -97,7 +98,8 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2080a-rdb.dtb -dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \ +dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ + fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb dtb-$(CONFIG_MACH_SUN4I) += \ diff --git a/arch/arm/dts/armada-xp-theadorable.dts b/arch/arm/dts/armada-xp-theadorable.dts new file mode 100644 index 0000000000..cf1be2a3d4 --- /dev/null +++ b/arch/arm/dts/armada-xp-theadorable.dts @@ -0,0 +1,143 @@ +/* + * Device Tree file for Marvell Armada XP theadorable board + * + * Copyright (C) 2013-2014 Marvell + * + * Lior Amsalem <alior@marvell.com> + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "armada-xp-mv78260.dtsi" + +/ { + model = "Marvell Armada XP theadorable"; + compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + spi0 = &spi0; + ethernet0 = ð0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x80000000>; + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 + MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; + + internal-regs { + serial@12000 { + status = "okay"; + u-boot,dm-pre-reloc; + }; + + serial@12100 { + status = "okay"; + }; + + serial@12200 { + status = "okay"; + }; + + serial@12300 { + status = "okay"; + }; + + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "sgmii"; + }; + + usb@50000 { + status = "okay"; + }; + + usb@51000 { + status = "okay"; + }; + + spi0: spi@10600 { + status = "okay"; + u-boot,dm-pre-reloc; + + spi-flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <27777777>; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/fsl-ls1043a-qds-duart.dts b/arch/arm/dts/fsl-ls1043a-qds-duart.dts new file mode 100644 index 0000000000..2124e38504 --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a-qds-duart.dts @@ -0,0 +1,16 @@ +/* + * Device Tree file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2015, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1043a-qds.dtsi" + +/ { + chosen { + stdout-path = &duart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts b/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts new file mode 100644 index 0000000000..18adb97d18 --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts @@ -0,0 +1,16 @@ +/* + * Device Tree file for Freescale Layerscape-1043A family SoC. + * + * Copyright (C) 2015, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1043a-qds.dtsi" + +/ { + chosen { + stdout-path = &lpuart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1043a-qds.dts b/arch/arm/dts/fsl-ls1043a-qds.dtsi index 74352227d4..66efe673d9 100644 --- a/arch/arm/dts/fsl-ls1043a-qds.dts +++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi @@ -10,11 +10,56 @@ * warranty of any kind, whether express or implied. */ -/dts-v1/; /include/ "fsl-ls1043a.dtsi" / { model = "LS1043A QDS Board"; + aliases { + spi0 = &qspi; + spi1 = &dspi0; + }; +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <1000000>; /* input clock */ + }; + + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3500000>; + reg = <1>; + }; + + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3500000>; + reg = <2>; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fl128s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; }; &i2c0 { @@ -122,3 +167,7 @@ &duart1 { status = "okay"; }; + +&lpuart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index 85ea81e2a6..66b409a05c 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -182,5 +182,69 @@ interrupts = <0 55 0x4>; clocks = <&clockgen 4 0>; }; + + lpuart0: serial@2950000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2950000 0x0 0x1000>; + interrupts = <0 48 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart1: serial@2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = <0 49 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@2970000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2970000 0x0 0x1000>; + interrupts = <0 50 0x4>; + clock-names = "ipg"; + clocks = <&sysclk>; + status = "disabled"; + }; + + lpuart3: serial@2980000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2980000 0x0 0x1000>; + interrupts = <0 51 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@2990000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2990000 0x0 0x1000>; + interrupts = <0 52 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@29a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x29a0000 0x0 0x1000>; + interrupts = <0 53 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + status = "disabled"; + }; + qspi: quadspi@1550000 { + compatible = "fsl,vf610-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1550000 0x10000>, + <0x40000000 0x4000000>; + num-cs = <2>; + big-endian; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 83be51ae9d..2d786f0fd1 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -234,7 +234,7 @@ interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; - } ; + }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; @@ -244,7 +244,7 @@ interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; - } ; + }; slcr: slcr@f8000000 { #address-cells = <1>; @@ -326,11 +326,11 @@ scutimer: timer@f8f00600 { interrupt-parent = <&intc>; - interrupts = < 1 13 0x301 >; + interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; - reg = < 0xf8f00600 0x20 >; + reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; - } ; + }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 07e2b7a738..b6982c0c45 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -21,9 +21,8 @@ }; chosen { - bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; - linux,stdout-path = &uart1; - stdout-path = &uart1; + bootargs = "root=/dev/ram rw earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index 77e3bb0e63..4fed221536 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -18,9 +18,8 @@ }; chosen { - bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; - linux,stdout-path = &uart1; - stdout-path = &uart1; + bootargs = "root=/dev/ram rw earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { @@ -34,12 +33,6 @@ }; }; -&spi0 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; -}; - &can0 { status = "okay"; }; @@ -54,6 +47,12 @@ }; }; +&spi0 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; +}; + &uart1 { u-boot,dm-pre-reloc; status = "okay"; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 3e1769acb5..8d69f0e0f5 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -20,9 +20,8 @@ }; chosen { - bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; - linux,stdout-path = &uart1; - stdout-path = &uart1; + bootargs = "root=/dev/ram rw earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { @@ -31,12 +30,6 @@ }; }; -&spi1 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; -}; - &can1 { status = "okay"; }; @@ -61,6 +54,12 @@ }; }; +&spi1 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; +}; + &uart1 { u-boot,dm-pre-reloc; status = "okay"; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index 288e248374..77fdfcc009 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -20,9 +20,8 @@ }; chosen { - bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk"; - linux,stdout-path = &uart0; - stdout-path = &uart0; + bootargs = "root=/dev/ram rw earlyprintk"; + stdout-path = "serial0:115200n8"; }; memory { @@ -31,21 +30,6 @@ }; }; -&spi0 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; - eeprom: at25@0 { - at25,byte-len = <8192>; - at25,addr-mode = <2>; - at25,page-size = <32>; - - compatible = "atmel,at25"; - reg = <2>; - spi-max-frequency = <1000000>; - }; -}; - &can1 { status = "okay"; }; @@ -74,6 +58,21 @@ }; }; +&spi0 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; + eeprom: at25@0 { + at25,byte-len = <8192>; + at25,addr-mode = <2>; + at25,page-size = <32>; + + compatible = "atmel,at25"; + reg = <2>; + spi-max-frequency = <1000000>; + }; +}; + &uart0 { u-boot,dm-pre-reloc; status = "okay"; diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts index 4481bd07c9..754604ea72 100644 --- a/arch/arm/dts/zynqmp-ep108.dts +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -41,7 +41,7 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: phy@0{ + phy0: phy@0 { reg = <0>; max-speed = <100>; }; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 24a34e6d85..8733604a57 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -520,7 +520,7 @@ }; uart0: serial@ff000000 { - compatible = "cdns,uart-r1p8"; + compatible = "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; @@ -529,7 +529,7 @@ }; uart1: serial@ff010000 { - compatible = "cdns,uart-r1p8"; + compatible = "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; @@ -559,7 +559,7 @@ compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 52 1>; + interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x1000>; timeout-sec = <10>; }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 49b113dc59..ff3b1bee3e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -118,6 +118,15 @@ #define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 #define CONFIG_SYS_FSL_ERRATUM_A009635 +#define CONFIG_SYS_FSL_ERRATUM_A009663 +#define CONFIG_SYS_FSL_ERRATUM_A009942 + +/* ARM A57 CORE ERRATA */ +#define CONFIG_ARM_ERRATA_826974 +#define CONFIG_ARM_ERRATA_828024 +#define CONFIG_ARM_ERRATA_829520 +#define CONFIG_ARM_ERRATA_833471 + #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 @@ -166,6 +175,7 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #define CONFIG_SYS_FSL_ERRATUM_A009929 #else #error SoC not defined diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index e030430786..15ade84c48 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -12,6 +12,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS2085, LS2085, 8), CPU_TYPE_ENTRY(LS2045, LS2045, 4), CPU_TYPE_ENTRY(LS1043, LS1043, 4), + CPU_TYPE_ENTRY(LS2040, LS2040, 4), }; #ifndef CONFIG_SYS_DCACHE_OFF @@ -150,6 +151,8 @@ static const struct sys_mmu_table early_mmu_table[] = { { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, + { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, + CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 21b803ff0f..0bad0c70b8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -218,6 +218,9 @@ struct ccsr_gur { #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 +#define RCW_SB_EN_REG_INDEX 7 +#define RCW_SB_EN_MASK 0x00200000 + u8 res_140[0x200-0x140]; u32 scratchrw[4]; /* Scratch Read/Write */ u8 res_210[0x300-0x210]; @@ -451,7 +454,8 @@ struct ccsr_serdes { u32 res_0c; /* 0x00c */ u32 pllcr3; u32 pllcr4; - u8 res_18[0x20-0x18]; + u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */ + u8 res_1c[0x20-0x1c]; } bank[2]; u8 res_40[0x90-0x40]; u32 srdstcalcr; /* 0x90 TX Calibration Control */ @@ -459,25 +463,25 @@ struct ccsr_serdes { u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ u8 res_a4[0xb0-0xa4]; u32 srdsgr0; /* 0xb0 General Register 0 */ - u8 res_b4[0xe0-0xb4]; - u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ - u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ - u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ - u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ - u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ - u8 res_f4[0x100-0xf4]; + u8 res_b4[0x100-0xb4]; struct { - u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ + u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */ u8 res_104[0x120-0x104]; - } srdslnpssr[4]; - u8 res_180[0x300-0x180]; - u32 srdspexeqcr; - u32 srdspexeqpcr[11]; - u8 res_330[0x400-0x330]; - u32 srdspexapcr; - u8 res_404[0x440-0x404]; - u32 srdspexbpcr; - u8 res_444[0x800-0x444]; + } lnpssr[4]; /* Lane A, B, C, D */ + u8 res_180[0x200-0x180]; + u32 srdspccr0; /* 0x200 Protocol Configuration 0 */ + u32 srdspccr1; /* 0x204 Protocol Configuration 1 */ + u32 srdspccr2; /* 0x208 Protocol Configuration 2 */ + u32 srdspccr3; /* 0x20c Protocol Configuration 3 */ + u32 srdspccr4; /* 0x210 Protocol Configuration 4 */ + u32 srdspccr5; /* 0x214 Protocol Configuration 5 */ + u32 srdspccr6; /* 0x218 Protocol Configuration 6 */ + u32 srdspccr7; /* 0x21c Protocol Configuration 7 */ + u32 srdspccr8; /* 0x220 Protocol Configuration 8 */ + u32 srdspccr9; /* 0x224 Protocol Configuration 9 */ + u32 srdspccra; /* 0x228 Protocol Configuration A */ + u32 srdspccrb; /* 0x22c Protocol Configuration B */ + u8 res_230[0x800-0x230]; struct { u32 gcr0; /* 0x800 General Control Register 0 */ u32 gcr1; /* 0x804 General Control Register 1 */ @@ -490,8 +494,34 @@ struct ccsr_serdes { u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ u8 res_824[0x83c-0x824]; u32 tcsr3; - } lane[4]; /* Lane A, B, C, D, E, F, G, H */ - u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ + } lane[4]; /* Lane A, B, C, D */ + u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */ + struct { + u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */ + u8 res_1004[0x1040-0x1004]; + } pcie[3]; + u8 res_10c0[0x1800-0x10c0]; + struct { + u8 res_1800[0x1804-0x1800]; + u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */ + u8 res_1808[0x180c-0x1808]; + u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */ + } sgmii[4]; /* Lane A, B, C, D */ + u8 res_1840[0x1880-0x1840]; + struct { + u8 res_1880[0x1884-0x1880]; + u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */ + u8 res_1888[0x188c-0x1888]; + u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */ + } qsgmii[2]; /* Lane A, B */ + u8 res_18a0[0x1980-0x18a0]; + struct { + u8 res_1980[0x1984-0x1980]; + u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */ + u8 res_1988[0x198c-0x1988]; + u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */ + } xfi[2]; /* Lane A, B */ + u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ }; #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 1565592996..ea78e15f49 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -45,6 +45,7 @@ struct cpu_type { #define SVR_LS2045 0x870120 #define SVR_LS2080 0x870110 #define SVR_LS2085 0x870100 +#define SVR_LS2040 0x870130 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index f066480c0c..424fe879dd 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -131,6 +131,7 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_ERRATUM_A008378 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 89339fe0ef..0a80772b51 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -120,6 +120,8 @@ struct ccsr_gur { u32 brrl; /* Boot release */ u8 res_0e8[0x100-0xe8]; u32 rcwsr[16]; /* Reset control word status */ +#define RCW_SB_EN_REG_INDEX 7 +#define RCW_SB_EN_MASK 0x00200000 u8 res_140[0x200-0x140]; u32 scratchrw[4]; /* Scratch Read/Write */ u8 res_210[0x300-0x210]; diff --git a/arch/arm/include/asm/arch-zynqmp/clk.h b/arch/arm/include/asm/arch-zynqmp/clk.h index d55bc31c43..b18333d1ca 100644 --- a/arch/arm/include/asm/arch-zynqmp/clk.h +++ b/arch/arm/include/asm/arch-zynqmp/clk.h @@ -9,5 +9,6 @@ #define _ASM_ARCH_CLK_H_ unsigned long get_uart_clk(int dev_id); +unsigned long zynqmp_get_system_timer_freq(void); #endif /* _ASM_ARCH_CLK_H_ */ diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index bbf89d9dd7..587938249e 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -41,11 +41,8 @@ struct crlapb_regs { #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) -#if defined(CONFIG_SECURE_IOU) -#define ZYNQMP_IOU_SCNTR 0xFF260000 -#else +#define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 #define ZYNQMP_IOU_SCNTR 0xFF250000 -#endif #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 @@ -57,9 +54,21 @@ struct iou_scntr { #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR) +struct iou_scntr_secure { + u32 counter_control_register; + u32 reserved0[7]; + u32 base_frequency_id_register; +}; + +#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) + /* Bootmode setting values */ #define BOOT_MODES_MASK 0x0000000F -#define SD_MODE 0x00000003 +#define QSPI_MODE_24BIT 0x00000001 +#define QSPI_MODE_32BIT 0x00000002 +#define SD_MODE 0x00000003 /* sd 0 */ +#define SD_MODE1 0x00000005 /* sd 1 */ +#define NAND_MODE 0x00000004 #define EMMC_MODE 0x00000006 #define JTAG_MODE 0x00000000 @@ -106,9 +115,20 @@ struct apu_regs { #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) /* Board version value */ +#define ZYNQMP_CSU_BASEADDR 0xFFCA0000 #define ZYNQMP_CSU_VERSION_SILICON 0x0 #define ZYNQMP_CSU_VERSION_EP108 0x1 #define ZYNQMP_CSU_VERSION_VELOCE 0x2 #define ZYNQMP_CSU_VERSION_QEMU 0x3 +#define ZYNQMP_SILICON_VER_MASK 0xF000 +#define ZYNQMP_SILICON_VER_SHIFT 12 + +struct csu_regs { + u32 reserved0[17]; + u32 version; +}; + +#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 806302bc61..0da0599738 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -8,7 +8,16 @@ #define __FSL_SECURE_BOOT_H #ifdef CONFIG_SECURE_BOOT + +#ifndef CONFIG_FIT_SIGNATURE +#define CONFIG_CHAIN_OF_TRUST +#endif + +#endif + +#ifdef CONFIG_CHAIN_OF_TRUST #define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_PROG_HW_ACCEL #define CONFIG_RSA @@ -34,7 +43,10 @@ #define CONFIG_FSL_ISBC_KEY_EXT #endif -#ifndef CONFIG_FIT_SIGNATURE +#ifdef CONFIG_LS1043A +/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ +#define CONFIG_ESBC_ADDR_64BIT +#endif #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xcfffffff;" \ @@ -44,8 +56,6 @@ /* The address needs to be modified according to NOR memory map */ #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a0000 -#include <config_fsl_secboot.h> -#endif -#endif - +#include <config_fsl_chain_trust.h> +#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 67cbbc2610..026e7ef83b 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -259,7 +259,7 @@ static inline void set_dacr(unsigned int val) isb(); } -#ifdef CONFIG_ARMV7 +#ifdef CONFIG_CPU_V7 /* Short-Descriptor Translation Table Level 1 Bits */ #define TTB_SECT_NS_MASK (1 << 19) #define TTB_SECT_NG_MASK (1 << 17) @@ -274,8 +274,7 @@ static inline void set_dacr(unsigned int val) /* options available for data cache on each page */ enum dcache_option { - DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) | - TTB_SECT_XN_MASK | TTB_SECT, + DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), @@ -296,7 +295,7 @@ enum { MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, }; -#ifdef CONFIG_ARMV7 +#ifdef CONFIG_CPU_V7 /* TTBR0 bits */ #define TTBR0_BASE_ADDR_MASK 0xFFFFC000 #define TTBR0_RGN_NC (0 << 3) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index c65e068857..8e185383a5 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -96,7 +96,7 @@ static inline void mmu_setup(void) dram_bank_mmu_setup(i); } -#ifdef CONFIG_ARMV7 +#ifdef CONFIG_CPU_V7 /* Set TTBR0 */ reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK; #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index b9628462ea..96a33133ae 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -46,6 +46,10 @@ config TARGET_MAXBCM bool "Support maxbcm" select MV78460 +config TARGET_THEADORABLE + bool "Support theadorable Armada XP" + select MV78260 + endchoice config SYS_BOARD @@ -54,6 +58,7 @@ config SYS_BOARD default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP default "ds414" if TARGET_DS414 default "maxbcm" if TARGET_MAXBCM + default "theadorable" if TARGET_THEADORABLE config SYS_CONFIG_NAME default "clearfog" if TARGET_CLEARFOG @@ -61,6 +66,7 @@ config SYS_CONFIG_NAME default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP default "ds414" if TARGET_DS414 default "maxbcm" if TARGET_MAXBCM + default "theadorable" if TARGET_THEADORABLE config SYS_VENDOR default "Marvell" if TARGET_DB_MV784MP_GP diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 48a387c957..0b2852c4da 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -52,6 +52,19 @@ config TEGRA210 endchoice +config TEGRA_DISCONNECT_UDC_ON_BOOT + bool "Disconnect USB device mode controller on boot" + default y + help + When loading U-Boot into RAM over USB protocols using tools such as + tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device + mode controller is initialized and enumerated by the host PC running + the tool. Unfortunately, these tools do not shut down the USB + controller before executing the downloaded code, and so the host PC + does not "de-enumerate" the USB device. This option shuts down the + USB controller when U-Boot boots to avoid leaving a stale USB device + present. + config SYS_MALLOC_F_LEN default 0x1800 diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index a650abd731..60e19c8387 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -34,8 +34,8 @@ #ifdef CONFIG_TEGRA_CLOCK_SCALING #include <asm/arch/emc.h> #endif -#ifdef CONFIG_USB_EHCI_TEGRA #include <asm/arch-tegra/usb.h> +#ifdef CONFIG_USB_EHCI_TEGRA #include <usb.h> #endif #ifdef CONFIG_TEGRA_MMC @@ -201,6 +201,14 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); int board_early_init_f(void) { +#if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) +#define USBCMD_FS2 (1 << 15) + { + struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000; + writel(USBCMD_FS2, &usbctlr->usb_cmd); + } +#endif + /* Do any special system timer/TSC setup */ #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) if (!tegra_cpu_is_non_secure()) diff --git a/arch/arm/mach-zynq/ddrc.c b/arch/arm/mach-zynq/ddrc.c index 5b20accbcb..d74f8dbbc4 100644 --- a/arch/arm/mach-zynq/ddrc.c +++ b/arch/arm/mach-zynq/ddrc.c @@ -42,8 +42,6 @@ void zynq_ddrc_init(void) */ /* cppcheck-suppress nullPointer */ memset((void *)0, 0, 1 * 1024 * 1024); - - gd->ram_size /= 2; } else { puts("ECC disabled "); } diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 604f6815af..30ea484f48 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -13,6 +13,7 @@ config TARGET_MICROBLAZE_GENERIC select SUPPORT_SPL select OF_CONTROL select DM + select DM_SERIAL endchoice diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile index 4955e81236..069721033f 100644 --- a/arch/microblaze/cpu/Makefile +++ b/arch/microblaze/cpu/Makefile @@ -7,5 +7,5 @@ extra-y = start.o obj-y = irq.o -obj-y += cpu.o interrupts.o cache.o exception.o timer.o +obj-y += interrupts.o cache.o exception.o timer.o obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/microblaze/cpu/cpu.c b/arch/microblaze/cpu/cpu.c deleted file mode 100644 index 8e459d807f..0000000000 --- a/arch/microblaze/cpu/cpu.c +++ /dev/null @@ -1,9 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI <yashi@atmark-techno.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* EMPTY FILE */ diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 206be3e3ee..e9923b65ef 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -155,6 +155,10 @@ clear_bss: cmp r6, r5, r4 /* check if we have reach the end */ bnei r6, 2b 3: /* jumping to board_init */ +#ifdef CONFIG_DEBUG_UART + bralid r15, debug_uart_init + nop +#endif #ifndef CONFIG_SPL_BUILD or r5, r0, r0 /* flags - empty */ addi r31, r0, _gd diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 1b39c4c0c6..f852a1f1bb 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -23,6 +23,7 @@ config TARGET_QEMU_MIPS config TARGET_MALTA bool "Support malta" + select DYNAMIC_IO_PORT_BASE select SUPPORTS_BIG_ENDIAN select SUPPORTS_LITTLE_ENDIAN select SUPPORTS_CPU_MIPS32_R1 @@ -54,6 +55,11 @@ config TARGET_PB1X00 select SYS_MIPS_CACHE_INIT_RAM_LOAD select MIPS_TUNE_4KC +config MACH_PIC32 + bool "Support Microchip PIC32" + select OF_CONTROL + select DM + endchoice source "board/dbau1x00/Kconfig" @@ -61,6 +67,7 @@ source "board/imgtec/malta/Kconfig" source "board/micronas/vct/Kconfig" source "board/pb1x00/Kconfig" source "board/qemu-mips/Kconfig" +source "arch/mips/mach-pic32/Kconfig" if MIPS @@ -217,6 +224,9 @@ config MIPS_L1_CACHE_SHIFT default "4" if MIPS_L1_CACHE_SHIFT_4 default "5" +config DYNAMIC_IO_PORT_BASE + bool + endif endmenu diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 2133e7e065..aec5a1517a 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/ libs-y += arch/mips/lib/ machine-$(CONFIG_SOC_AU1X00) += au1x00 +machine-$(CONFIG_MACH_PIC32) += pic32 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index e95cdca61e..d2c31ae781 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -115,7 +115,7 @@ reset: /* Clear watch registers */ MTC0 zero, CP0_WATCHLO - MTC0 zero, CP0_WATCHHI + mtc0 zero, CP0_WATCHHI /* WP(Watch Pending), SW0/1 should be cleared */ mtc0 zero, CP0_CAUSE @@ -161,14 +161,14 @@ reset: #endif /* Set up temporary stack */ - PTR_LI t0, -16 + li t0, -16 PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR and sp, t1, t0 # force 16 byte alignment PTR_SUB sp, sp, GD_SIZE # reserve space for gd and sp, sp, t0 # force 16 byte alignment move k0, sp # save gd pointer #ifdef CONFIG_SYS_MALLOC_F_LEN - PTR_LI t2, CONFIG_SYS_MALLOC_F_LEN + li t2, CONFIG_SYS_MALLOC_F_LEN PTR_SUB sp, sp, t2 # reserve space for early malloc and sp, sp, t0 # force 16 byte alignment #endif @@ -177,15 +177,15 @@ reset: /* Clear gd */ move t0, k0 1: - sw zero, 0(t0) + PTR_S zero, 0(t0) blt t0, t1, 1b - PTR_ADDI t0, 4 + PTR_ADDI t0, PTRSIZE #ifdef CONFIG_SYS_MALLOC_F_LEN - PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset - sw sp, 0(t0) + PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset #endif + move a0, zero # a0 <-- boot_flags = 0 PTR_LA t9, board_init_f jr t9 move ra, zero @@ -224,11 +224,11 @@ ENTRY(relocate_code) * t2 = source end address */ 1: - lw t3, 0(t0) - sw t3, 0(t1) - PTR_ADDU t0, 4 + PTR_L t3, 0(t0) + PTR_S t3, 0(t1) + PTR_ADDU t0, PTRSIZE blt t0, t2, 1b - PTR_ADDU t1, 4 + PTR_ADDU t1, PTRSIZE /* If caches were enabled, we would have to flush them here. */ PTR_SUB a1, t1, s2 # a1 <-- size diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 47b6eb50c3..b5139187c2 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -2,7 +2,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -dtb-y += +dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi new file mode 100644 index 0000000000..7d180d9918 --- /dev/null +++ b/arch/mips/dts/pic32mzda.dtsi @@ -0,0 +1,174 @@ +/* + * Copyright 2015 Microchip Technology, Inc. + * Purna Chandra Mandal, <purna.mandal@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/microchip,clock.h> +#include <dt-bindings/gpio/gpio.h> +#include "skeleton.dtsi" + +/ { + compatible = "microchip,pic32mzda", "microchip,pic32mz"; + + aliases { + gpio0 = &gpioA; + gpio1 = &gpioB; + gpio2 = &gpioC; + gpio3 = &gpioD; + gpio4 = &gpioE; + gpio5 = &gpioF; + gpio6 = &gpioG; + gpio7 = &gpioH; + gpio8 = &gpioJ; + gpio9 = &gpioK; + }; + + cpus { + cpu@0 { + compatible = "mips,mips14kc"; + }; + }; + + clock: clk@1f801200 { + compatible = "microchip,pic32mzda-clk"; + reg = <0x1f801200 0x1000>; + #clock-cells = <1>; + }; + + uart1: serial@1f822000 { + compatible = "microchip,pic32mzda-uart"; + reg = <0x1f822000 0x50>; + interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&clock PB2CLK>; + }; + + uart2: serial@1f822200 { + compatible = "microchip,pic32mzda-uart"; + reg = <0x1f822200 0x50>; + interrupts = <145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock PB2CLK>; + status = "disabled"; + }; + + uart6: serial@1f822a00 { + compatible = "microchip,pic32mzda-uart"; + reg = <0x1f822a00 0x50>; + interrupts = <188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock PB2CLK>; + status = "disabled"; + }; + + evic: interrupt-controller@1f810000 { + compatible = "microchip,pic32mzda-evic"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1f810000 0x1000>; + }; + + pinctrl: pinctrl@1f801400 { + compatible = "microchip,pic32mzda-pinctrl"; + reg = <0x1f801400 0x100>, /* in */ + <0x1f801500 0x200>, /* out */ + <0x1f860000 0xa00>; /* port */ + reg-names = "ppsin","ppsout","port"; + status = "disabled"; + + ranges = <0 0x1f860000 0xa00>; + #address-cells = <1>; + #size-cells = <1>; + gpioA: gpio0@0 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x000 0x48>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioB: gpio1@100 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x100 0x48>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioC: gpio2@200 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x200 0x48>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioD: gpio3@300 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x300 0x48>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioE: gpio4@400 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x400 0x48>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioF: gpio5@500 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x500 0x48>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioG: gpio6@600 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x600 0x48>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioH: gpio7@700 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x700 0x48>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioJ: gpio8@800 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x800 0x48>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioK: gpio9@900 { + compatible = "microchip,pic32mzda-gpio"; + reg = <0x900 0x48>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + sdhci: sdhci@1f8ec000 { + compatible = "microchip,pic32mzda-sdhci"; + reg = <0x1f8ec000 0x100>; + interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock REF4CLK>, <&clock PB5CLK>; + clock-names = "base_clk", "sys_clk"; + clock-freq-min-max = <25000000>,<25000000>; + bus-width = <4>; + status = "disabled"; + }; + + ethernet: ethernet@1f882000 { + compatible = "microchip,pic32mzda-eth"; + reg = <0x1f882000 0x1000>; + interrupts = <153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock PB5CLK>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts new file mode 100644 index 0000000000..e5ce0bdc2e --- /dev/null +++ b/arch/mips/dts/pic32mzda_sk.dts @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2015 Purna Chandra Mandal, purna.mandal@microchip.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "pic32mzda.dtsi" + +/ { + model = "Microchip PIC32MZDASK"; + compatible = "microchip,pic32mzdask", "microchip,pic32mzda"; + + aliases { + console = &uart2; + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&clock { + microchip,refo2-frequency = <50000000>; + microchip,refo4-frequency = <25000000>; + microchip,refo5-frequency = <40000000>; + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&pinctrl { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&uart2 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&sdhci { + status = "okay"; +}; + +ðernet { + reset-gpios = <&gpioJ 15 0>; + status = "okay"; + phy-mode = "rmii"; + phy-handle = <ðernet_phy>; + ethernet_phy: lan8740_phy@0 { + reg = <0>; + }; +};
\ No newline at end of file diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h index 2d9a0c9e75..a1ca257db5 100644 --- a/arch/mips/include/asm/global_data.h +++ b/arch/mips/include/asm/global_data.h @@ -12,6 +12,9 @@ /* Architecture-specific global data */ struct arch_global_data { +#ifdef CONFIG_DYNAMIC_IO_PORT_BASE + unsigned long io_port_base; +#endif #ifdef CONFIG_JZSOC /* There are other clocks in the jz4740 */ unsigned long per_clk; /* Peripheral bus clock */ diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index f71e34231b..723a60a199 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -26,11 +26,6 @@ #include <spaces.h> /* - * Slowdown I/O port space accesses for antique hardware. - */ -#undef CONF_SLOWDOWN_IO - -/* * Raw operations are never swapped in software. OTOH values that raw * operations are working on may or may not have been swapped by the bus * hardware. An example use would be for flash memory that's used for @@ -46,57 +41,36 @@ #define IO_SPACE_LIMIT 0xffff -/* - * On MIPS I/O ports are memory mapped, so we access them using normal - * load/store instructions. mips_io_port_base is the virtual address to - * which all ports are being mapped. For sake of efficiency some code - * assumes that this is an address that can be loaded with a single lui - * instruction, so the lower 16 bits must be zero. Should be true on - * on any sane architecture; generic code does not use this assumption. - */ -extern const unsigned long mips_io_port_base; +#ifdef CONFIG_DYNAMIC_IO_PORT_BASE + +static inline ulong mips_io_port_base(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + return gd->arch.io_port_base; +} -/* - * Gcc will generate code to load the value of mips_io_port_base after each - * function call which may be fairly wasteful in some cases. So we don't - * play quite by the book. We tell gcc mips_io_port_base is a long variable - * which solves the code generation issue. Now we need to violate the - * aliasing rules a little to make initialization possible and finally we - * will need the barrier() to fight side effects of the aliasing chat. - * This trickery will eventually collapse under gcc's optimizer. Oh well. - */ static inline void set_io_port_base(unsigned long base) { - * (unsigned long *) &mips_io_port_base = base; + DECLARE_GLOBAL_DATA_PTR; + + gd->arch.io_port_base = base; barrier(); } -/* - * Thanks to James van Artsdalen for a better timing-fix than - * the two short jumps: using outb's to a nonexistent port seems - * to guarantee better timings even on fast machines. - * - * On the other hand, I'd like to be sure of a non-existent port: - * I feel a bit unsafe about using 0x80 (should be safe, though) - * - * Linus - * - */ +#else /* !CONFIG_DYNAMIC_IO_PORT_BASE */ -#define __SLOW_DOWN_IO \ - __asm__ __volatile__( \ - "sb\t$0,0x80(%0)" \ - : : "r" (mips_io_port_base)); +static inline ulong mips_io_port_base(void) +{ + return 0; +} -#ifdef CONF_SLOWDOWN_IO -#ifdef REALLY_SLOW_IO -#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; } -#else -#define SLOW_DOWN_IO __SLOW_DOWN_IO -#endif -#else -#define SLOW_DOWN_IO -#endif +static inline void set_io_port_base(unsigned long base) +{ + BUG_ON(base); +} + +#endif /* !CONFIG_DYNAMIC_IO_PORT_BASE */ /* * virt_to_phys - map virtual addresses to physical @@ -316,7 +290,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ return pfx##ioswab##bwlq(__mem, __val); \ } -#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \ +#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p) \ \ static inline void pfx##out##bwlq##p(type val, unsigned long port) \ { \ @@ -325,7 +299,7 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \ \ war_octeon_io_reorder_wmb(); \ \ - __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ + __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base() + port); \ \ __val = pfx##ioswab##bwlq(__addr, val); \ \ @@ -333,7 +307,6 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \ BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ \ *__addr = __val; \ - slow; \ } \ \ static inline type pfx##in##bwlq##p(unsigned long port) \ @@ -341,12 +314,11 @@ static inline type pfx##in##bwlq##p(unsigned long port) \ volatile type *__addr; \ type __val; \ \ - __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ + __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base() + port); \ \ BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ \ __val = *__addr; \ - slow; \ \ return pfx##ioswab##bwlq(__addr, __val); \ } @@ -367,8 +339,8 @@ BUILDIO_MEM(l, u32) BUILDIO_MEM(q, u64) #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ - __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \ - __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO) + __BUILD_IOPORT_SINGLE(bus, bwlq, type, ) \ + __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p) #define BUILDIO_IOPORT(bwlq, type) \ __BUILD_IOPORT_PFX(, bwlq, type) \ diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index ac536da674..b7ce5df765 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -7,7 +7,6 @@ obj-y += cache.o obj-y += cache_init.o -obj-y += io.o obj-$(CONFIG_CMD_BOOTM) += bootm.o diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index bf8ff598ac..7482005b67 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -95,6 +95,10 @@ void flush_dcache_range(ulong start_addr, ulong stop) const void *addr = (const void *)(start_addr & ~(lsize - 1)); const void *aend = (const void *)((stop - 1) & ~(lsize - 1)); + /* aend will be miscalculated when size is zero, so we return here */ + if (start_addr == stop) + return; + while (1) { mips_cache(HIT_WRITEBACK_INV_D, addr); if (addr == aend) @@ -109,6 +113,10 @@ void invalidate_dcache_range(ulong start_addr, ulong stop) const void *addr = (const void *)(start_addr & ~(lsize - 1)); const void *aend = (const void *)((stop - 1) & ~(lsize - 1)); + /* aend will be miscalculated when size is zero, so we return here */ + if (start_addr == stop) + return; + while (1) { mips_cache(HIT_INVALIDATE_D, addr); if (addr == aend) diff --git a/arch/mips/lib/io.c b/arch/mips/lib/io.c deleted file mode 100644 index b2d4a094da..0000000000 --- a/arch/mips/lib/io.c +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mips_io_port_base is the begin of the address space to which x86 style - * I/O ports are mapped. - */ -const unsigned long mips_io_port_base = -1; diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig new file mode 100644 index 0000000000..2e38bb7eca --- /dev/null +++ b/arch/mips/mach-pic32/Kconfig @@ -0,0 +1,35 @@ +menu "Microchip PIC32 platforms" + depends on MACH_PIC32 + +config SYS_SOC + default "pic32mzda" if SOC_PIC32MZDA + +choice + prompt "PIC32 SoC select" + +config SOC_PIC32MZDA + bool "Microchip PIC32MZ[DA] family" + select SUPPORTS_LITTLE_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select MIPS_L1_CACHE_SHIFT_4 + select SYS_MIPS_CACHE_INIT_RAM_LOAD + help + This supports Microchip PIC32MZ[DA] family of microcontrollers. + +endchoice + +choice + prompt "Board select" + +config TARGET_PIC32MZDASK + bool "Microchip PIC32MZ[DA] Starter Kit" + depends on SOC_PIC32MZDA + help + This supports Microchip PIC32MZ[DA] Starter Kit. + +endchoice + +source "board/microchip/pic32mzda/Kconfig" + +endmenu diff --git a/arch/mips/mach-pic32/Makefile b/arch/mips/mach-pic32/Makefile new file mode 100644 index 0000000000..e321e65fd4 --- /dev/null +++ b/arch/mips/mach-pic32/Makefile @@ -0,0 +1,7 @@ +# (C) Copyright 2015 +# Purna Chandra Mandal, purna.mandal@microchip.com. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = cpu.o lowlevel_init.o reset.o
\ No newline at end of file diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c new file mode 100644 index 0000000000..f2ee911df4 --- /dev/null +++ b/arch/mips/mach-pic32/cpu.c @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2015 + * Purna Chandra Mandal <purna.mandal@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <mach/pic32.h> +#include <mach/ddr.h> +#include <dt-bindings/clock/microchip,clock.h> + +/* Flash prefetch */ +#define PRECON 0x00 + +/* Flash ECCCON */ +#define ECC_MASK 0x03 +#define ECC_SHIFT 4 + +#define CLK_MHZ(x) ((x) / 1000000) + +DECLARE_GLOBAL_DATA_PTR; + +static ulong clk_get_cpu_rate(void) +{ + int ret; + struct udevice *dev; + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + panic("uclass-clk: device not found\n"); + return 0; + } + + return clk_get_rate(dev); +} + +/* initialize prefetch module related to cpu_clk */ +static void prefetch_init(void) +{ + struct pic32_reg_atomic *regs; + const void __iomem *base; + int v, nr_waits; + ulong rate; + + /* cpu frequency in MHZ */ + rate = clk_get_cpu_rate() / 1000000; + + /* get flash ECC type */ + base = pic32_get_syscfg_base(); + v = (readl(base + CFGCON) >> ECC_SHIFT) & ECC_MASK; + + if (v < 2) { + if (rate < 66) + nr_waits = 0; + else if (rate < 133) + nr_waits = 1; + else + nr_waits = 2; + } else { + if (rate <= 83) + nr_waits = 0; + else if (rate <= 166) + nr_waits = 1; + else + nr_waits = 2; + } + + regs = ioremap(PREFETCH_BASE + PRECON, sizeof(*regs)); + writel(nr_waits, ®s->raw); + + /* Enable prefetch for all */ + writel(0x30, ®s->set); + iounmap(regs); +} + +/* arch specific CPU init after DM */ +int arch_cpu_init_dm(void) +{ + /* flash prefetch */ + prefetch_init(); + return 0; +} + +/* Un-gate DDR2 modules (gated by default) */ +static void ddr2_pmd_ungate(void) +{ + void __iomem *regs; + + regs = pic32_get_syscfg_base(); + writel(0, regs + PMD7); +} + +/* initialize the DDR2 Controller and DDR2 PHY */ +phys_size_t initdram(int board_type) +{ + ddr2_pmd_ungate(); + ddr2_phy_init(); + ddr2_ctrl_init(); + return ddr2_calculate_size(); +} + +int misc_init_r(void) +{ + set_io_port_base(0); + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +const char *get_core_name(void) +{ + u32 proc_id; + const char *str; + + proc_id = read_c0_prid(); + switch (proc_id) { + case 0x19e28: + str = "PIC32MZ[DA]"; + break; + default: + str = "UNKNOWN"; + } + + return str; +} +#endif +#ifdef CONFIG_CMD_CLK +int soc_clk_dump(void) +{ + int i, ret; + struct udevice *dev; + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + printf("clk-uclass not found\n"); + return ret; + } + + printf("PLL Speed: %lu MHz\n", + CLK_MHZ(clk_get_periph_rate(dev, PLLCLK))); + printf("CPU Speed: %lu MHz\n", CLK_MHZ(clk_get_rate(dev))); + printf("MPLL Speed: %lu MHz\n", + CLK_MHZ(clk_get_periph_rate(dev, MPLL))); + + for (i = PB1CLK; i <= PB7CLK; i++) + printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1, + CLK_MHZ(clk_get_periph_rate(dev, i))); + + for (i = REF1CLK; i <= REF5CLK; i++) + printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1, + CLK_MHZ(clk_get_periph_rate(dev, i))); + return 0; +} +#endif diff --git a/arch/mips/mach-pic32/include/mach/ddr.h b/arch/mips/mach-pic32/include/mach/ddr.h new file mode 100644 index 0000000000..00abfa3ca9 --- /dev/null +++ b/arch/mips/mach-pic32/include/mach/ddr.h @@ -0,0 +1,32 @@ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __MICROCHIP_PIC32_DDR_H +#define __MICROCHIP_PIC32_DDR_H + +/* called by initdram() function */ +void ddr2_phy_init(void); +void ddr2_ctrl_init(void); +phys_size_t ddr2_calculate_size(void); + +/* Maximum number of agents */ +#define NUM_AGENTS 5 + +/* Board can provide agent specific parameters for arbitration by + * filling struct ddr2_arbiter_params for all the agents and + * implementing board_get_ddr_arbiter_params() to return the filled + * structure. + */ +struct ddr2_arbiter_params { + u32 min_limit; /* min bursts to execute per arbitration */ + u32 req_period; /* request period threshold for accepted cmds */ + u32 min_cmd_acpt; /* min number of accepted cmds */ +}; + +const struct ddr2_arbiter_params *board_get_ddr_arbiter_params(void); + +#endif /* __MICROCHIP_PIC32_DDR_H */ diff --git a/arch/mips/mach-pic32/include/mach/pic32.h b/arch/mips/mach-pic32/include/mach/pic32.h new file mode 100644 index 0000000000..16bfacf818 --- /dev/null +++ b/arch/mips/mach-pic32/include/mach/pic32.h @@ -0,0 +1,79 @@ +/* + * (c) 2015 Paul Thacker <paul.thacker@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __PIC32_REGS_H__ +#define __PIC32_REGS_H__ + +#include <asm/io.h> + +/* System Configuration */ +#define PIC32_CFG_BASE 0x1f800000 + +/* System config register offsets */ +#define CFGCON 0x0000 +#define DEVID 0x0020 +#define SYSKEY 0x0030 +#define PMD1 0x0040 +#define PMD7 0x00a0 +#define CFGEBIA 0x00c0 +#define CFGEBIC 0x00d0 +#define CFGPG 0x00e0 +#define CFGMPLL 0x0100 + +/* Non Volatile Memory (NOR flash) */ +#define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600) +/* Oscillator Configuration */ +#define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200) +/* Peripheral Pin Select Input */ +#define PPS_IN_BASE 0x1f801400 +/* Peripheral Pin Select Output */ +#define PPS_OUT_BASE 0x1f801500 +/* Pin Config */ +#define PINCTRL_BASE 0x1f860000 + +/* USB Core */ +#define PIC32_USB_CORE_BASE 0x1f8e3000 +#define PIC32_USB_CTRL_BASE 0x1f884000 + +/* SPI1-SPI6 */ +#define PIC32_SPI1_BASE 0x1f821000 + +/* Prefetch Module */ +#define PREFETCH_BASE 0x1f8e0000 + +/* DDR2 Controller */ +#define PIC32_DDR2C_BASE 0x1f8e8000 + +/* DDR2 PHY */ +#define PIC32_DDR2P_BASE 0x1f8e9100 + +/* EBI */ +#define PIC32_EBI_BASE 0x1f8e1000 + +/* SQI */ +#define PIC32_SQI_BASE 0x1f8e2000 + +struct pic32_reg_atomic { + u32 raw; + u32 clr; + u32 set; + u32 inv; +}; + +#define _CLR_OFFSET 0x04 +#define _SET_OFFSET 0x08 +#define _INV_OFFSET 0x0c + +static inline void __iomem *pic32_get_syscfg_base(void) +{ + return (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE); +} + +/* Core */ +const char *get_core_name(void); + +#endif /* __PIC32_REGS_H__ */ diff --git a/arch/mips/mach-pic32/lowlevel_init.S b/arch/mips/mach-pic32/lowlevel_init.S new file mode 100644 index 0000000000..e37bebb539 --- /dev/null +++ b/arch/mips/mach-pic32/lowlevel_init.S @@ -0,0 +1,27 @@ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * +*/ + +#include <config.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/asm.h> + +LEAF(lowlevel_init) + /* + * Establish Cause + * (set IV bit) + */ + li t1, 0x00800000 + mtc0 t1, CP0_CAUSE + + /* Establish Wired (and Random) */ + mtc0 zero, CP0_WIRED + nop + + jr ra + nop + END(lowlevel_init) diff --git a/arch/mips/mach-pic32/reset.c b/arch/mips/mach-pic32/reset.c new file mode 100644 index 0000000000..66c6833746 --- /dev/null +++ b/arch/mips/mach-pic32/reset.c @@ -0,0 +1,36 @@ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <asm/io.h> +#include <mach/pic32.h> + +/* SYSKEY */ +#define UNLOCK_KEY1 0xaa996655 +#define UNLOCK_KEY2 0x556699aa +#define LOCK_KEY 0 + +#define RSWRST 0x1250 + +void _machine_restart(void) +{ + void __iomem *base; + + base = pic32_get_syscfg_base(); + + /* unlock sequence */ + writel(LOCK_KEY, base + SYSKEY); + writel(UNLOCK_KEY1, base + SYSKEY); + writel(UNLOCK_KEY2, base + SYSKEY); + + /* soft reset */ + writel(0x1, base + RSWRST); + (void) readl(base + RSWRST); + + while (1) + ; +} diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index a4935567f6..3b06ae42e4 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -326,6 +326,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS) puts("Work-around for Erratum XFI on B4860QDS enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 + puts("Work-around for Erratum A009663 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 8c6b678c89..80bbc1805f 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -31,6 +31,9 @@ #include <hwconfig.h> #include <linux/compiler.h> #include "mp.h" +#ifdef CONFIG_CHAIN_OF_TRUST +#include <fsl_validate.h> +#endif #ifdef CONFIG_FSL_CAAM #include <fsl_sec.h> #endif @@ -1020,3 +1023,14 @@ void cpu_secondary_init_r(void) qe_reset(); #endif } + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_CHAIN_OF_TRUST + fsl_setenv_chain_of_trust(); +#endif + + return 0; +} +#endif diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index efd316573c..36af1b9419 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -55,12 +55,6 @@ config TARGET_YOSEMITE config TARGET_YUCCA bool "Support yucca" -config TARGET_FX12MM - bool "Support fx12mm" - -config TARGET_V5FX30TEVAL - bool "Support v5fx30teval" - config TARGET_CPCI2DP bool "Support CPCI2DP" @@ -115,14 +109,19 @@ config TARGET_PIP405 config TARGET_XPEDITE1000 bool "Support xpedite1000" -config TARGET_ML507 - bool "Support ml507" - config TARGET_XILINX_PPC405_GENERIC bool "Support xilinx-ppc405-generic" + select SUPPORT_SPL + select OF_CONTROL + select DM + select DM_SERIAL config TARGET_XILINX_PPC440_GENERIC bool "Support xilinx-ppc440-generic" + select SUPPORT_SPL + select OF_CONTROL + select DM + select DM_SERIAL endchoice @@ -139,8 +138,6 @@ source "board/amcc/sequoia/Kconfig" source "board/amcc/walnut/Kconfig" source "board/amcc/yosemite/Kconfig" source "board/amcc/yucca/Kconfig" -source "board/avnet/fx12mm/Kconfig" -source "board/avnet/v5fx30teval/Kconfig" source "board/esd/cpci2dp/Kconfig" source "board/esd/cpci405/Kconfig" source "board/esd/plu405/Kconfig" @@ -158,7 +155,6 @@ source "board/mpl/mip405/Kconfig" source "board/mpl/pip405/Kconfig" source "board/t3corp/Kconfig" source "board/xes/xpedite1000/Kconfig" -source "board/xilinx/ml507/Kconfig" source "board/xilinx/ppc405-generic/Kconfig" source "board/xilinx/ppc440-generic/Kconfig" diff --git a/arch/powerpc/cpu/ppc4xx/interrupts.c b/arch/powerpc/cpu/ppc4xx/interrupts.c index d9b565468b..45997d6eae 100644 --- a/arch/powerpc/cpu/ppc4xx/interrupts.c +++ b/arch/powerpc/cpu/ppc4xx/interrupts.c @@ -9,7 +9,7 @@ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com * * (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX) - * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * Work supported by Qtechnology (htpp://qtec.com) * * SPDX-License-Identifier: GPL-2.0+ diff --git a/arch/powerpc/cpu/ppc4xx/uic.c b/arch/powerpc/cpu/ppc4xx/uic.c index bd955ed83f..fb453b1adf 100644 --- a/arch/powerpc/cpu/ppc4xx/uic.c +++ b/arch/powerpc/cpu/ppc4xx/uic.c @@ -9,7 +9,7 @@ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com * * (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX) - * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * Work supported by Qtechnology (htpp://qtec.com) * * SPDX-License-Identifier: GPL-2.0+ diff --git a/arch/powerpc/cpu/ppc4xx/xilinx_irq.c b/arch/powerpc/cpu/ppc4xx/xilinx_irq.c index 71e1be02a6..1a2e917eb2 100644 --- a/arch/powerpc/cpu/ppc4xx/xilinx_irq.c +++ b/arch/powerpc/cpu/ppc4xx/xilinx_irq.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de * SPDX-License-Identifier: GPL-2.0+ diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 5d9f5c2822..80b4c0c4e3 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -3,6 +3,8 @@ # dtb-$(CONFIG_TARGET_CANYONLANDS) += arches.dtb canyonlands.dtb glacier.dtb +dtb-$(CONFIG_TARGET_XILINX_PPC440_GENERIC) += xilinx-ppc440-generic.dtb +dtb-$(CONFIG_TARGET_XILINX_PPC405_GENERIC) += xilinx-ppc405-generic.dtb targets += $(dtb-y) diff --git a/arch/powerpc/dts/xilinx-ppc405-generic.dts b/arch/powerpc/dts/xilinx-ppc405-generic.dts new file mode 100644 index 0000000000..64983216b5 --- /dev/null +++ b/arch/powerpc/dts/xilinx-ppc405-generic.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + console = &uart0; + }; + + uart0: serial@84000000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + interrupts = <0 0>; + reg = <0x84000000 0x10000>; + }; +} ; diff --git a/arch/powerpc/dts/xilinx-ppc440-generic.dts b/arch/powerpc/dts/xilinx-ppc440-generic.dts new file mode 100644 index 0000000000..c83523a5a4 --- /dev/null +++ b/arch/powerpc/dts/xilinx-ppc440-generic.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + console = &uart0; + }; + + uart0: serial@8b000000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + interrupts = <0 0>; + reg = <0x8b000000 0x10000>; + }; +} ; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 674fac8828..eccc146dae 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -808,6 +808,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ERRATUM_A008378 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) @@ -856,6 +857,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ERRATUM_A008378 +#define CONFIG_SYS_FSL_ERRATUM_A009663 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 87415b123f..c45cace552 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -9,18 +9,11 @@ #include <asm/config_mpc85xx.h> #ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_ESBC_VALIDATE -#define CONFIG_FSL_SEC_MON -#define CONFIG_SHA_PROG_HW_ACCEL -#define CONFIG_DM -#define CONFIG_RSA -#define CONFIG_RSA_FREESCALE_EXP -#ifndef CONFIG_FSL_CAAM -#define CONFIG_FSL_CAAM -#endif + +#ifndef CONFIG_FIT_SIGNATURE +#define CONFIG_CHAIN_OF_TRUST #endif -#ifdef CONFIG_SECURE_BOOT #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 #elif defined(CONFIG_BSC9132QDS) @@ -75,8 +68,32 @@ */ #define CONFIG_FSL_ISBC_KEY_EXT #endif +#endif /* #ifdef CONFIG_SECURE_BOOT */ + +#ifdef CONFIG_CHAIN_OF_TRUST + +#define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_CMD_BLOB +#define CONFIG_FSL_SEC_MON +#define CONFIG_SHA_PROG_HW_ACCEL +#define CONFIG_RSA +#define CONFIG_RSA_FREESCALE_EXP + +#ifndef CONFIG_DM +#define CONFIG_DM +#endif + +#ifndef CONFIG_FSL_CAAM +#define CONFIG_FSL_CAAM +#endif + +/* fsl_setenv_chain_of_trust() must be called from + * board_late_init() + */ +#ifndef CONFIG_BOARD_LATE_INIT +#define CONFIG_BOARD_LATE_INIT +#endif -#ifndef CONFIG_FIT_SIGNATURE /* If Boot Script is not on NOR and is required to be copied on RAM */ #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BS_HDR_ADDR_RAM 0x00010000 @@ -104,10 +121,8 @@ #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000 #endif -#endif - -#include <config_fsl_secboot.h> -#endif +#endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */ -#endif +#include <config_fsl_chain_trust.h> +#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 101b8db0ee..fd8aba42a5 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1749,6 +1749,8 @@ typedef struct ccsr_gur { u32 brrl; /* Boot release */ u8 res17[24]; u32 rcwsr[16]; /* Reset control word status */ +#define RCW_SB_EN_REG_INDEX 7 +#define RCW_SB_EN_MASK 0x00200000 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 @@ -2194,6 +2196,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3 #endif +#define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000 /* The 8544 RM says this is bit 26, but it's really bit 24 */ #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 u8 res1[8]; diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/asm/interrupt.h index 1a6a93384e..9f370dd83c 100644 --- a/arch/powerpc/include/asm/interrupt.h +++ b/arch/powerpc/include/asm/interrupt.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de * diff --git a/arch/powerpc/include/asm/xilinx_irq.h b/arch/powerpc/include/asm/xilinx_irq.h index 333a0372b7..5766bde366 100644 --- a/arch/powerpc/include/asm/xilinx_irq.h +++ b/arch/powerpc/include/asm/xilinx_irq.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de * SPDX-License-Identifier: GPL-2.0+ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f07567c81a..a995e32bb9 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -358,6 +358,15 @@ config GENERATE_ACPI_TABLE by the operating system. It defines platform-independent interfaces for configuration and power management monitoring. +config QEMU_ACPI_TABLE + bool "Load ACPI table from QEMU fw_cfg interface" + depends on GENERATE_ACPI_TABLE && QEMU + default y + help + By default, U-Boot generates its own ACPI tables. This option, if + enabled, disables U-Boot's version and loads ACPI tables generated + by QEMU. + config GENERATE_SMBIOS_TABLE bool "Generate an SMBIOS (System Management BIOS) table" default y diff --git a/arch/x86/cpu/baytrail/early_uart.c b/arch/x86/cpu/baytrail/early_uart.c index b64a3a90db..471d592b49 100644 --- a/arch/x86/cpu/baytrail/early_uart.c +++ b/arch/x86/cpu/baytrail/early_uart.c @@ -59,11 +59,15 @@ static void x86_pci_write_config32(int dev, unsigned int where, u32 value) } /* This can be called after memory-mapped PCI is working */ -int setup_early_uart(void) +int setup_internal_uart(int enable) { - /* Enable the legacy UART hardware. */ + /* Enable or disable the legacy UART hardware */ x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, - 1); + enable); + + /* All done for the disable part, so just return */ + if (!enable) + return 0; /* * Set up the pads to the UART function. This allows the signals to diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig index 4f9862194a..6808c9a6b9 100644 --- a/arch/x86/cpu/qemu/Kconfig +++ b/arch/x86/cpu/qemu/Kconfig @@ -17,4 +17,11 @@ config SYS_CAR_SIZE hex default 0x10000 +config ACPI_PM1_BASE + hex + default 0xe400 + help + ACPI Power Managment 1 (PM1) i/o-mapped base address. + This device is defined in ACPI specification, with 16 bytes in size. + endif diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile index 176ea54ae4..801413a1cb 100644 --- a/arch/x86/cpu/qemu/Makefile +++ b/arch/x86/cpu/qemu/Makefile @@ -8,4 +8,6 @@ ifndef CONFIG_EFI_STUB obj-y += car.o dram.o endif obj-y += cpu.o fw_cfg.o qemu.o +ifndef CONFIG_QEMU_ACPI_TABLE obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o +endif diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c index 05992145cf..5ea7a6e2e5 100644 --- a/arch/x86/cpu/qemu/fw_cfg.c +++ b/arch/x86/cpu/qemu/fw_cfg.c @@ -10,10 +10,16 @@ #include <malloc.h> #include <asm/io.h> #include <asm/fw_cfg.h> +#include <asm/tables.h> +#include <asm/e820.h> +#include <linux/list.h> +#include <memalign.h> static bool fwcfg_present; static bool fwcfg_dma_present; +static LIST_HEAD(fw_list); + /* Read configuration item using fw_cfg PIO interface */ static void qemu_fwcfg_read_entry_pio(uint16_t entry, uint32_t size, void *address) @@ -162,29 +168,311 @@ static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr) return 0; } -static int qemu_fwcfg_list_firmware(void) +static int qemu_fwcfg_read_firmware_list(void) { int i; uint32_t count; - struct fw_cfg_files *files; + struct fw_file *file; + struct list_head *entry; + + /* don't read it twice */ + if (!list_empty(&fw_list)) + return 0; qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count); if (!count) return 0; count = be32_to_cpu(count); - files = malloc(count * sizeof(struct fw_cfg_file)); - if (!files) - return -ENOMEM; - - files->count = count; - qemu_fwcfg_read_entry(FW_CFG_INVALID, - count * sizeof(struct fw_cfg_file), - files->files); - - for (i = 0; i < files->count; i++) - printf("%-56s\n", files->files[i].name); - free(files); + for (i = 0; i < count; i++) { + file = malloc(sizeof(*file)); + if (!file) { + printf("error: allocating resource\n"); + goto err; + } + qemu_fwcfg_read_entry(FW_CFG_INVALID, + sizeof(struct fw_cfg_file), &file->cfg); + file->addr = 0; + list_add_tail(&file->list, &fw_list); + } + + return 0; + +err: + list_for_each(entry, &fw_list) { + file = list_entry(entry, struct fw_file, list); + free(file); + } + + return -ENOMEM; +} + +#ifdef CONFIG_QEMU_ACPI_TABLE +static struct fw_file *qemu_fwcfg_find_file(const char *name) +{ + struct list_head *entry; + struct fw_file *file; + + list_for_each(entry, &fw_list) { + file = list_entry(entry, struct fw_file, list); + if (!strcmp(file->cfg.name, name)) + return file; + } + + return NULL; +} + +/* + * This function allocates memory for ACPI tables + * + * @entry : BIOS linker command entry which tells where to allocate memory + * (either high memory or low memory) + * @addr : The address that should be used for low memory allcation. If the + * memory allocation request is 'ZONE_HIGH' then this parameter will + * be ignored. + * @return: 0 on success, or negative value on failure + */ +static int bios_linker_allocate(struct bios_linker_entry *entry, + unsigned long *addr) +{ + uint32_t size, align; + struct fw_file *file; + unsigned long aligned_addr; + + align = le32_to_cpu(entry->alloc.align); + /* align must be power of 2 */ + if (align & (align - 1)) { + printf("error: wrong alignment %u\n", align); + return -EINVAL; + } + + file = qemu_fwcfg_find_file(entry->alloc.file); + if (!file) { + printf("error: can't find file %s\n", entry->alloc.file); + return -ENOENT; + } + + size = be32_to_cpu(file->cfg.size); + + /* + * ZONE_HIGH means we need to allocate from high memory, since + * malloc space is already at the end of RAM, so we directly use it. + * If allocation zone is ZONE_FSEG, then we use the 'addr' passed + * in which is low memory + */ + if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) { + aligned_addr = (unsigned long)memalign(align, size); + if (!aligned_addr) { + printf("error: allocating resource\n"); + return -ENOMEM; + } + } else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) { + aligned_addr = ALIGN(*addr, align); + } else { + printf("error: invalid allocation zone\n"); + return -EINVAL; + } + + debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align %u, addr 0x%lx\n", + file->cfg.name, size, entry->alloc.zone, align, aligned_addr); + + qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select), + size, (void *)aligned_addr); + file->addr = aligned_addr; + + /* adjust address for low memory allocation */ + if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) + *addr = (aligned_addr + size); + + return 0; +} + +/* + * This function patches ACPI tables previously loaded + * by bios_linker_allocate() + * + * @entry : BIOS linker command entry which tells how to patch + * ACPI tables + * @return: 0 on success, or negative value on failure + */ +static int bios_linker_add_pointer(struct bios_linker_entry *entry) +{ + struct fw_file *dest, *src; + uint32_t offset = le32_to_cpu(entry->pointer.offset); + uint64_t pointer = 0; + + dest = qemu_fwcfg_find_file(entry->pointer.dest_file); + if (!dest || !dest->addr) + return -ENOENT; + src = qemu_fwcfg_find_file(entry->pointer.src_file); + if (!src || !src->addr) + return -ENOENT; + + debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx, offset 0x%x size %u, 0x%llx\n", + dest->addr, src->addr, offset, entry->pointer.size, pointer); + + memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size); + pointer = le64_to_cpu(pointer); + pointer += (unsigned long)src->addr; + pointer = cpu_to_le64(pointer); + memcpy((char *)dest->addr + offset, &pointer, entry->pointer.size); + + return 0; +} + +/* + * This function updates checksum fields of ACPI tables previously loaded + * by bios_linker_allocate() + * + * @entry : BIOS linker command entry which tells where to update ACPI table + * checksums + * @return: 0 on success, or negative value on failure + */ +static int bios_linker_add_checksum(struct bios_linker_entry *entry) +{ + struct fw_file *file; + uint8_t *data, cksum = 0; + uint8_t *cksum_start; + + file = qemu_fwcfg_find_file(entry->cksum.file); + if (!file || !file->addr) + return -ENOENT; + + data = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.offset)); + cksum_start = (uint8_t *)(file->addr + le32_to_cpu(entry->cksum.start)); + cksum = table_compute_checksum(cksum_start, + le32_to_cpu(entry->cksum.length)); + *data = cksum; + + return 0; +} + +unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) +{ + entries[0].addr = 0; + entries[0].size = ISA_START_ADDRESS; + entries[0].type = E820_RAM; + + entries[1].addr = ISA_START_ADDRESS; + entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS; + entries[1].type = E820_RESERVED; + + /* + * since we use memalign(malloc) to allocate high memory for + * storing ACPI tables, we need to reserve them in e820 tables, + * otherwise kernel will reclaim them and data will be corrupted + */ + entries[2].addr = ISA_END_ADDRESS; + entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS; + entries[2].type = E820_RAM; + + /* for simplicity, reserve entire malloc space */ + entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN; + entries[3].size = TOTAL_MALLOC_LEN; + entries[3].type = E820_RESERVED; + + entries[4].addr = gd->relocaddr; + entries[4].size = gd->ram_size - gd->relocaddr; + entries[4].type = E820_RESERVED; + + entries[5].addr = CONFIG_PCIE_ECAM_BASE; + entries[5].size = CONFIG_PCIE_ECAM_SIZE; + entries[5].type = E820_RESERVED; + + return 6; +} + +/* This function loads and patches ACPI tables provided by QEMU */ +unsigned long write_acpi_tables(unsigned long addr) +{ + int i, ret = 0; + struct fw_file *file; + struct bios_linker_entry *table_loader; + struct bios_linker_entry *entry; + uint32_t size; + struct list_head *list; + + /* make sure fw_list is loaded */ + ret = qemu_fwcfg_read_firmware_list(); + if (ret) { + printf("error: can't read firmware file list\n"); + return addr; + } + + file = qemu_fwcfg_find_file("etc/table-loader"); + if (!file) { + printf("error: can't find etc/table-loader\n"); + return addr; + } + + size = be32_to_cpu(file->cfg.size); + if ((size % sizeof(*entry)) != 0) { + printf("error: table-loader maybe corrupted\n"); + return addr; + } + + table_loader = malloc(size); + if (!table_loader) { + printf("error: no memory for table-loader\n"); + return addr; + } + + qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select), + size, table_loader); + + for (i = 0; i < (size / sizeof(*entry)); i++) { + entry = table_loader + i; + switch (le32_to_cpu(entry->command)) { + case BIOS_LINKER_LOADER_COMMAND_ALLOCATE: + ret = bios_linker_allocate(entry, &addr); + if (ret) + goto out; + break; + case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER: + ret = bios_linker_add_pointer(entry); + if (ret) + goto out; + break; + case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM: + ret = bios_linker_add_checksum(entry); + if (ret) + goto out; + break; + default: + break; + } + } + +out: + if (ret) { + list_for_each(list, &fw_list) { + file = list_entry(list, struct fw_file, list); + if (file->addr) + free((void *)file->addr); + } + } + + free(table_loader); + return addr; +} +#endif + +static int qemu_fwcfg_list_firmware(void) +{ + int ret; + struct list_head *entry; + struct fw_file *file; + + /* make sure fw_list is loaded */ + ret = qemu_fwcfg_read_firmware_list(); + if (ret) + return ret; + + list_for_each(entry, &fw_list) { + file = list_entry(entry, struct fw_file, list); + printf("%-56s\n", file->cfg.name); + } + return 0; } diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 5a7b92944a..f8af566dea 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -15,6 +15,31 @@ static bool i440fx; +static void enable_pm_piix(void) +{ + u8 en; + u16 cmd; + + /* Set the PM I/O base */ + x86_pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); + + /* Enable access to the PM I/O space */ + cmd = x86_pci_read_config16(PIIX_PM, PCI_COMMAND); + cmd |= PCI_COMMAND_IO; + x86_pci_write_config16(PIIX_PM, PCI_COMMAND, cmd); + + /* PM I/O Space Enable (PMIOSE) */ + en = x86_pci_read_config8(PIIX_PM, PMREGMISC); + en |= PMIOSE; + x86_pci_write_config8(PIIX_PM, PMREGMISC, en); +} + +static void enable_pm_ich9(void) +{ + /* Set the PM I/O base */ + x86_pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1); +} + static void qemu_chipset_init(void) { u16 device, xbcs; @@ -53,10 +78,14 @@ static void qemu_chipset_init(void) xbcs = x86_pci_read_config16(PIIX_ISA, XBCS); xbcs |= APIC_EN; x86_pci_write_config16(PIIX_ISA, XBCS, xbcs); + + enable_pm_piix(); } else { /* Configure PCIe ECAM base address */ x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, CONFIG_PCIE_ECAM_BASE | BAR_EN); + + enable_pm_ich9(); } qemu_fwcfg_init(); diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 9bf707bf0e..fbca46762c 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -21,7 +21,7 @@ aliases { serial0 = &serial; - spi0 = "/spi"; + spi0 = &spi; }; config { @@ -184,7 +184,7 @@ >; }; - spi { + spi: spi { #address-cells = <1>; #size-cells = <0>; compatible = "intel,ich-spi"; diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts index 4e9e410b70..7b2c51504b 100644 --- a/arch/x86/dts/broadwell_som-6896.dts +++ b/arch/x86/dts/broadwell_som-6896.dts @@ -10,7 +10,7 @@ compatible = "advantech,som-6896", "intel,broadwell"; aliases { - spi0 = "/spi"; + spi0 = &spi; }; config { @@ -34,7 +34,7 @@ reg = <0x0000f800 0 0 0 0>; compatible = "intel,pch9"; - spi { + spi: spi { #address-cells = <1>; #size-cells = <0>; compatible = "intel,ich-spi"; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index d148d6e349..58072031df 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -11,7 +11,7 @@ compatible = "google,link", "intel,celeron-ivybridge"; aliases { - spi0 = "/pci/pch/spi"; + spi0 = &spi; usb0 = &usb_0; usb1 = &usb_1; }; @@ -252,7 +252,7 @@ /* Enable EC SMI source */ intel,alt-gp-smi-enable = <0x0100>; - spi { + spi: spi { #address-cells = <1>; #size-cells = <0>; compatible = "intel,ich-spi"; diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index 23027016e5..48f0c77d45 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -10,7 +10,7 @@ compatible = "google,panther", "intel,haswell"; aliases { - spi0 = "/spi"; + spi0 = &spi; }; config { @@ -56,7 +56,7 @@ reg = <0x0000f800 0 0 0 0>; compatible = "intel,pch9"; - spi { + spi: spi { #address-cells = <1>; #size-cells = <0>; compatible = "intel,ich-spi"; diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index d6dd0b49f0..47fab0fda6 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -19,7 +19,7 @@ compatible = "intel,crownbay", "intel,queensbay"; aliases { - spi0 = "/spi"; + spi0 = &spi; }; config { @@ -227,7 +227,7 @@ >; }; - spi { + spi: spi { #address-cells = <1>; #size-cells = <0>; compatible = "intel,ich-spi"; diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index a2f5a1f223..dd75fc4dc9 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -18,7 +18,7 @@ compatible = "intel,galileo", "intel,quark"; aliases { - spi0 = "/spi"; + spi0 = &spi; }; config { @@ -115,7 +115,7 @@ >; }; - spi { + spi: spi { #address-cells = <1>; #size-cells = <0>; compatible = "intel,ich-spi"; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index e7ef7c987b..7afdf6c30b 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -20,7 +20,7 @@ aliases { serial0 = &serial; - spi0 = "/spi"; + spi0 = &spi; }; config { @@ -218,7 +218,7 @@ >; }; - spi { + spi: spi { #address-cells = <1>; #size-cells = <0>; compatible = "intel,ich-spi"; diff --git a/arch/x86/include/asm/arch-qemu/device.h b/arch/x86/include/asm/arch-qemu/device.h index 75a435e67b..38ab798994 100644 --- a/arch/x86/include/asm/arch-qemu/device.h +++ b/arch/x86/include/asm/arch-qemu/device.h @@ -13,6 +13,8 @@ #define PIIX_ISA PCI_BDF(0, 1, 0) #define PIIX_IDE PCI_BDF(0, 1, 1) #define PIIX_USB PCI_BDF(0, 1, 2) +#define PIIX_PM PCI_BDF(0, 1, 3) +#define ICH9_PM PCI_BDF(0, 0x1f, 0) #define I440FX_VGA PCI_BDF(0, 2, 0) #define QEMU_Q35 PCI_BDF(0, 0, 0) diff --git a/arch/x86/include/asm/arch-qemu/qemu.h b/arch/x86/include/asm/arch-qemu/qemu.h index b67d3428ee..a85eee8ec6 100644 --- a/arch/x86/include/asm/arch-qemu/qemu.h +++ b/arch/x86/include/asm/arch-qemu/qemu.h @@ -33,4 +33,9 @@ #define LOW_RAM_ADDR 0x34 #define HIGH_RAM_ADDR 0x35 +/* PM registers */ +#define PMBA 0x40 +#define PMREGMISC 0x80 +#define PMIOSE (1 << 0) + #endif /* _ARCH_QEMU_H_ */ diff --git a/arch/x86/include/asm/fw_cfg.h b/arch/x86/include/asm/fw_cfg.h index fb110fa8e7..e9450c6196 100644 --- a/arch/x86/include/asm/fw_cfg.h +++ b/arch/x86/include/asm/fw_cfg.h @@ -12,6 +12,8 @@ #define FW_DMA_PORT_LOW 0x514 #define FW_DMA_PORT_HIGH 0x518 +#include <linux/list.h> + enum qemu_fwcfg_items { FW_CFG_SIGNATURE = 0x00, FW_CFG_ID = 0x01, @@ -45,11 +47,23 @@ enum qemu_fwcfg_items { FW_CFG_INVALID = 0xffff, }; +enum { + BIOS_LINKER_LOADER_COMMAND_ALLOCATE = 0x1, + BIOS_LINKER_LOADER_COMMAND_ADD_POINTER = 0x2, + BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3, +}; + +enum { + BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1, + BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2, +}; + #define FW_CFG_FILE_SLOTS 0x10 #define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS) #define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL) #define FW_CFG_MAX_FILE_PATH 56 +#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH #define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U') @@ -67,9 +81,10 @@ struct fw_cfg_file { char name[FW_CFG_MAX_FILE_PATH]; }; -struct fw_cfg_files { - __be32 count; - struct fw_cfg_file files[]; +struct fw_file { + struct fw_cfg_file cfg; /* firmware file information */ + unsigned long addr; /* firmware file in-memory address */ + struct list_head list; /* list node to link to fw_list */ }; struct fw_cfg_dma_access { @@ -78,6 +93,55 @@ struct fw_cfg_dma_access { __be64 address; }; +struct bios_linker_entry { + __le32 command; + union { + /* + * COMMAND_ALLOCATE - allocate a table from @alloc.file + * subject to @alloc.align alignment (must be power of 2) + * and @alloc.zone (can be HIGH or FSEG) requirements. + * + * Must appear exactly once for each file, and before + * this file is referenced by any other command. + */ + struct { + char file[BIOS_LINKER_LOADER_FILESZ]; + __le32 align; + uint8_t zone; + } alloc; + + /* + * COMMAND_ADD_POINTER - patch the table (originating from + * @dest_file) at @pointer.offset, by adding a pointer to the + * table originating from @src_file. 1,2,4 or 8 byte unsigned + * addition is used depending on @pointer.size. + */ + struct { + char dest_file[BIOS_LINKER_LOADER_FILESZ]; + char src_file[BIOS_LINKER_LOADER_FILESZ]; + __le32 offset; + uint8_t size; + } pointer; + + /* + * COMMAND_ADD_CHECKSUM - calculate checksum of the range + * specified by @cksum_start and @cksum_length fields, + * and then add the value at @cksum.offset. + * Checksum simply sums -X for each byte X in the range + * using 8-bit math. + */ + struct { + char file[BIOS_LINKER_LOADER_FILESZ]; + __le32 offset; + __le32 start; + __le32 length; + } cksum; + + /* padding */ + char pad[124]; + }; +} __packed; + /** * Initialize QEMU fw_cfg interface */ diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 9c143caf67..031740b708 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -45,7 +45,7 @@ void dram_init_banksize(void); int default_print_cpuinfo(void); /* Set up a UART which can be used with printch(), printhex8(), etc. */ -int setup_early_uart(void); +int setup_internal_uart(int enable); void setup_pcat_compatibility(void); diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index d9fc296b6e..50bc69a659 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -32,7 +32,9 @@ obj-$(CONFIG_X86_RAMTEST) += ramtest.o obj-y += sfi.o obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o obj-y += string.o +ifndef CONFIG_QEMU_ACPI_TABLE obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o +endif obj-y += tables.o obj-$(CONFIG_CMD_ZBOOT) += zimage.o obj-$(CONFIG_HAVE_FSP) += fsp/ diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index ab1db7ec26..2ec5ad2fa4 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -331,6 +331,10 @@ static void acpi_create_ssdt_generator(acpi_header_t *ssdt, ssdt->checksum = table_compute_checksum((void *)ssdt, ssdt->length); } +/* + * QEMU's version of write_acpi_tables is defined in + * arch/x86/cpu/qemu/fw_cfg.c + */ unsigned long write_acpi_tables(unsigned long start) { unsigned long current; diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index 875c96a8f1..29fa06098d 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -111,7 +111,7 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) #endif #ifdef CONFIG_DEBUG_UART - setup_early_uart(); + setup_internal_uart(1); #endif fsp_hdr = find_fsp_header(); diff --git a/board/avnet/fx12mm/Kconfig b/board/avnet/fx12mm/Kconfig deleted file mode 100644 index 0b67ebde93..0000000000 --- a/board/avnet/fx12mm/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_FX12MM - -config SYS_BOARD - default "fx12mm" - -config SYS_VENDOR - default "avnet" - -config SYS_CONFIG_NAME - default "fx12mm" - -endif diff --git a/board/avnet/fx12mm/MAINTAINERS b/board/avnet/fx12mm/MAINTAINERS deleted file mode 100644 index c92e258df9..0000000000 --- a/board/avnet/fx12mm/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -FX12MM BOARD -M: Georg Schardt <schardt@team-ctech.de> -S: Maintained -F: board/avnet/fx12mm/ -F: include/configs/fx12mm.h -F: configs/fx12mm_defconfig -F: configs/fx12mm_flash_defconfig diff --git a/board/avnet/fx12mm/Makefile b/board/avnet/fx12mm/Makefile deleted file mode 100644 index 618b42f891..0000000000 --- a/board/avnet/fx12mm/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2008 -# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es -# This work has been supported by: Qtechnology http://qtec.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += fx12mm.o - -include $(srctree)/board/xilinx/ppc405-generic/Makefile diff --git a/board/avnet/fx12mm/fx12mm.c b/board/avnet/fx12mm/fx12mm.c deleted file mode 100644 index 92e1cfb75f..0000000000 --- a/board/avnet/fx12mm/fx12mm.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2008 - * - * Author: Xilinx Inc. - * - * Modified by: - * Georg Schardt <schardt@team-ctech.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <asm/processor.h> - -int checkboard(void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - if (l < 0) { - printf("Avnet Virtex4 FX12 with no serial #"); - } else { - printf("Avnet Virtex4 FX12 Minimodul # "); - for (i = 0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc(buf[i]); - } - } - putc('\n'); - return 0; -} diff --git a/board/avnet/fx12mm/xparameters.h b/board/avnet/fx12mm/xparameters.h deleted file mode 100644 index 94f682f8ec..0000000000 --- a/board/avnet/fx12mm/xparameters.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * (C) Copyright 2008 - * - * Georg Schardt <schardt@team-ctech.de> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * CAUTION: This file is based on the xparameters.h automatically - * generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5 - */ - -#ifndef __XPARAMETER_H__ -#define __XPARAMETER_H__ - -/* RS232 */ -#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 -#define XPAR_UARTNS550_0_BASEADDR 0x83E00000 - - -/* INT_C */ -#define XPAR_XPS_INTC_0_DEVICE_ID 0 -#define XPAR_XPS_INTC_0_BASEADDR 0x81800000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2 - -/* CPU core clock */ -#define XPAR_CORE_CLOCK_FREQ_HZ 300000000 -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 - -/* RAM */ -#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 - -/* FLASH */ -#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000 - -#endif diff --git a/board/avnet/v5fx30teval/Kconfig b/board/avnet/v5fx30teval/Kconfig deleted file mode 100644 index 079387b707..0000000000 --- a/board/avnet/v5fx30teval/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_V5FX30TEVAL - -config SYS_BOARD - default "v5fx30teval" - -config SYS_VENDOR - default "avnet" - -config SYS_CONFIG_NAME - default "v5fx30teval" - -endif diff --git a/board/avnet/v5fx30teval/MAINTAINERS b/board/avnet/v5fx30teval/MAINTAINERS deleted file mode 100644 index 91dde7a5c8..0000000000 --- a/board/avnet/v5fx30teval/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -V5FX30TEVAL BOARD -M: Ricardo Ribalda <ricardo.ribalda@uam.es> -S: Maintained -F: board/avnet/v5fx30teval/ -F: include/configs/v5fx30teval.h -F: configs/v5fx30teval_defconfig -F: configs/v5fx30teval_flash_defconfig diff --git a/board/avnet/v5fx30teval/Makefile b/board/avnet/v5fx30teval/Makefile deleted file mode 100644 index 8c41af02d4..0000000000 --- a/board/avnet/v5fx30teval/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2008 -# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es -# This work has been supported by: Qtechnology http://qtec.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += v5fx30teval.o - -include $(srctree)/board/xilinx/ppc440-generic/Makefile diff --git a/board/avnet/v5fx30teval/v5fx30teval.c b/board/avnet/v5fx30teval/v5fx30teval.c deleted file mode 100644 index 68b0eb959d..0000000000 --- a/board/avnet/v5fx30teval/v5fx30teval.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <config.h> -#include <common.h> -#include <asm/processor.h> - - -int checkboard(void) -{ - puts("Avnet Virtex 5 FX30 Evaluation Board\n"); - return 0; -} diff --git a/board/avnet/v5fx30teval/xparameters.h b/board/avnet/v5fx30teval/xparameters.h deleted file mode 100644 index 95b8c285ad..0000000000 --- a/board/avnet/v5fx30teval/xparameters.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * based on xparameters.h by Xilinx - * - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef XPARAMETER_H -#define XPARAMETER_H - -#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 -#define XPAR_INTC_0_BASEADDR 0x81800000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 -#define XPAR_FLASH_MEM0_BASEADDR 0xFF000000 -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 -#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 -#define XPAR_UARTLITE_0_BAUDRATE 9600 - -#endif diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c index 586daccb4a..71a7bb55c4 100644 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -227,9 +227,9 @@ int checkboard(void) return 0; } -#ifdef CONFIG_TSEC_ENET int board_eth_init(bd_t *bis) { +#ifdef CONFIG_TSEC_ENET struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[4]; int num = 0; @@ -250,6 +250,7 @@ int board_eth_init(bd_t *bis) fsl_pq_mdio_init(bis, &mdio_info); tsec_eth_init(bis, tsec_info, num); +#endif #ifdef CONFIG_PCI pci_eth_init(bis); @@ -257,7 +258,6 @@ int board_eth_init(bd_t *bis) return 0; } -#endif #define USBMUX_SEL_MASK 0xc0 #define USBMUX_SEL_UART2 0xc0 diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c index f42d373daf..e325b4db4a 100644 --- a/board/freescale/c29xpcie/c29xpcie.c +++ b/board/freescale/c29xpcie/c29xpcie.c @@ -83,9 +83,9 @@ void pci_init_board(void) } #endif /* ifdef CONFIG_PCI */ -#ifdef CONFIG_TSEC_ENET int board_eth_init(bd_t *bis) { +#ifdef CONFIG_TSEC_ENET struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[2]; int num = 0; @@ -110,10 +110,10 @@ int board_eth_init(bd_t *bis) fsl_pq_mdio_init(bis, &mdio_info); tsec_eth_init(bis, tsec_info, num); +#endif return pci_eth_init(bis); } -#endif #if defined(CONFIG_OF_BOARD_SETUP) void fdt_del_sec(void *blob, int offset) diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 51d2814a43..be114cebef 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -76,5 +76,6 @@ obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o ifdef CONFIG_SECURE_BOOT obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o endif +obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o endif diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c index 8bbe85bb3b..dfa3e2100e 100644 --- a/board/freescale/common/cmd_esbc_validate.c +++ b/board/freescale/common/cmd_esbc_validate.c @@ -11,6 +11,11 @@ static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + if (fsl_check_boot_mode_secure() == 0) { + printf("Boot Mode is Non-Secure. Not entering spin loop.\n"); + return 0; + } + printf("Core is entering spin loop.\n"); loop: goto loop; @@ -21,10 +26,29 @@ loop: static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + char *hash_str = NULL; + uintptr_t haddr; + int ret; + if (argc < 2) return cmd_usage(cmdtp); + else if (argc > 2) + /* Second arg - Optional - Hash Str*/ + hash_str = argv[2]; + + /* First argument - header address -32/64bit */ + haddr = (uintptr_t)simple_strtoul(argv[1], NULL, 16); - return fsl_secboot_validate(cmdtp, flag, argc, argv); + /* With esbc_validate command, Image address must be + * part of header. So, the function is called + * by passing this argument as 0. + */ + ret = fsl_secboot_validate(haddr, hash_str, 0); + if (ret) + return 1; + + printf("esbc_validate command successful\n"); + return 0; } /***************************************************/ @@ -45,6 +69,6 @@ U_BOOT_CMD( U_BOOT_CMD( esbc_halt, 1, 0, do_esbc_halt, - "Put the core in spin loop ", + "Put the core in spin loop (Secure Boot Only)", "" ); diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c new file mode 100644 index 0000000000..ecfcc8253a --- /dev/null +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -0,0 +1,70 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fsl_validate.h> +#include <fsl_sfp.h> + +#ifdef CONFIG_LS102XA +#include <asm/arch/immap_ls102xa.h> +#endif + +#if defined(CONFIG_MPC85xx) +#define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#else +#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR +#endif + +#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE +#define gur_in32(a) in_le32(a) +#else +#define gur_in32(a) in_be32(a) +#endif + +/* Check the Boot Mode. If Secure, return 1 else return 0 */ +int fsl_check_boot_mode_secure(void) +{ + uint32_t val; + struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR); + + val = sfp_in32(&sfp_regs->ospr) & ITS_MASK; + if (val == ITS_MASK) + return 1; + +#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx) + /* For PBL based platforms check the SB_EN bit in RCWSR */ + val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK; + if (val == RCW_SB_EN_MASK) + return 1; +#endif + +#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET) + /* For Non-PBL Platforms, check the Device Status register 2*/ + val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK; + if (val != MPC85xx_PORDEVSR2_SBC_MASK) + return 1; + +#endif + return 0; +} + +int fsl_setenv_chain_of_trust(void) +{ + /* Check Boot Mode + * If Boot Mode is Non-Secure, no changes are required + */ + if (fsl_check_boot_mode_secure() == 0) + return 0; + + /* If Boot mode is Secure, set the environment variables + * bootdelay = 0 (To disable Boot Prompt) + * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) + */ + setenv("bootdelay", "0"); + setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD); + return 0; +} diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index b510c71c40..8fd6dd63b1 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -24,6 +24,10 @@ #define SHA256_NIBBLES (256/4) #define NUM_HEX_CHARS (sizeof(ulong) * 2) +#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \ + ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \ + ((key_len) == 2 * KEY_SIZE_BYTES)) + /* This array contains DER value for SHA-256 */ static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, @@ -179,20 +183,97 @@ static u32 is_key_revoked(u32 keynum, u32 rev_flag) return 0; } -/* It validates srk_table key lengths.*/ -static u32 validate_srk_tbl(struct srk_table *tbl, u32 num_entries) +/* It read validates srk_table key lengths.*/ +static u32 read_validate_srk_tbl(struct fsl_secboot_img_priv *img) { int i = 0; - for (i = 0; i < num_entries; i++) { - if (!((tbl[i].key_len == 2 * KEY_SIZE_BYTES/4) || - (tbl[i].key_len == 2 * KEY_SIZE_BYTES/2) || - (tbl[i].key_len == 2 * KEY_SIZE_BYTES))) + u32 ret, key_num, key_revoc_flag, size; + struct fsl_secboot_img_hdr *hdr = &img->hdr; + void *esbc = (u8 *)(uintptr_t)img->ehdrloc; + + if ((hdr->len_kr.num_srk == 0) || + (hdr->len_kr.num_srk > MAX_KEY_ENTRIES)) + return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY; + + key_num = hdr->len_kr.srk_sel; + if (key_num == 0 || key_num > hdr->len_kr.num_srk) + return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM; + + /* Get revoc key from sfp */ + key_revoc_flag = get_key_revoc(); + ret = is_key_revoked(key_num, key_revoc_flag); + if (ret) + return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED; + + size = hdr->len_kr.num_srk * sizeof(struct srk_table); + + memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size); + + for (i = 0; i < hdr->len_kr.num_srk; i++) { + if (!CHECK_KEY_LEN(img->srk_tbl[i].key_len)) return ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN; } + + img->key_len = img->srk_tbl[key_num - 1].key_len; + + memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey), + img->key_len); + + return 0; +} +#endif + +static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) +{ + struct fsl_secboot_img_hdr *hdr = &img->hdr; + void *esbc = (u8 *)(uintptr_t)img->ehdrloc; + + /* check key length */ + if (!CHECK_KEY_LEN(hdr->key_len)) + return ERROR_ESBC_CLIENT_HEADER_KEY_LEN; + + memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len); + + img->key_len = hdr->key_len; + + return 0; +} + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img) +{ + struct fsl_secboot_img_hdr *hdr = &img->hdr; + u32 ie_key_len, ie_revoc_flag, ie_num; + struct ie_key_info *ie_info; + + if (get_ie_info_addr(&img->ie_addr)) + return ERROR_IE_TABLE_NOT_FOUND; + ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; + if (ie_info->num_keys == 0 || ie_info->num_keys > 32) + return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; + + ie_num = hdr->ie_key_sel; + if (ie_num == 0 || ie_num > ie_info->num_keys) + return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM; + + ie_revoc_flag = ie_info->key_revok; + if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag) + return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED; + + ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len; + + if (!CHECK_KEY_LEN(ie_key_len)) + return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN; + + memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey), + ie_key_len); + + img->key_len = ie_key_len; return 0; } #endif + /* This function return length of public key.*/ static inline u32 get_key_len(struct fsl_secboot_img_priv *img) { @@ -289,6 +370,13 @@ void fsl_secboot_handle_error(int error) printf("ERROR :: %x :: %s\n", error, e->name); } + /* If Boot Mode is secure, transition the SNVS state and issue + * reset based on type of failure and ITS setting. + * If Boot mode is non-secure, return from this function. + */ + if (fsl_check_boot_mode_secure() == 0) + return; + switch (error) { case ERROR_ESBC_CLIENT_HEADER_BARKER: case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE: @@ -455,13 +543,8 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) return ret; /* Update hash for actual Image */ -#ifdef CONFIG_ESBC_ADDR_64BIT - ret = algo->hash_update(algo, ctx, - (u8 *)(uintptr_t)img->hdr.pimg64, img->hdr.img_size, 1); -#else ret = algo->hash_update(algo, ctx, - (u8 *)(uintptr_t)img->hdr.pimg, img->hdr.img_size, 1); -#endif + (u8 *)img->img_addr, img->img_size, 1); if (ret) return ret; @@ -541,13 +624,9 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) struct fsl_secboot_img_hdr *hdr = &img->hdr; void *esbc = (u8 *)(uintptr_t)img->ehdrloc; u8 *k, *s; + u32 ret = 0; + #ifdef CONFIG_KEY_REVOCATION - u32 ret; - u32 key_num, key_revoc_flag, size; -#endif -#if defined(CONFIG_FSL_ISBC_KEY_EXT) - struct ie_key_info *ie_info; - u32 ie_num, ie_revoc_flag, ie_key_len; #endif int key_found = 0; @@ -555,93 +634,48 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN)) return ERROR_ESBC_CLIENT_HEADER_BARKER; -#ifdef CONFIG_ESBC_ADDR_64BIT - sprintf(buf, "%llx", hdr->pimg64); -#else - sprintf(buf, "%x", hdr->pimg); -#endif + /* If Image Address is not passed as argument to function, + * then Address and Size must be read from the Header. + */ + if (img->img_addr == 0) { + #ifdef CONFIG_ESBC_ADDR_64BIT + img->img_addr = hdr->pimg64; + #else + img->img_addr = hdr->pimg; + #endif + } + + sprintf(buf, "%lx", img->img_addr); setenv("img_addr", buf); if (!hdr->img_size) return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE; + img->img_size = hdr->img_size; + /* Key checking*/ #ifdef CONFIG_KEY_REVOCATION if (check_srk(img)) { - if ((hdr->len_kr.num_srk == 0) || - (hdr->len_kr.num_srk > MAX_KEY_ENTRIES)) - return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY; - - key_num = hdr->len_kr.srk_sel; - if (key_num == 0 || key_num > hdr->len_kr.num_srk) - return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM; - - /* Get revoc key from sfp */ - key_revoc_flag = get_key_revoc(); - ret = is_key_revoked(key_num, key_revoc_flag); - if (ret) - return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED; - - size = hdr->len_kr.num_srk * sizeof(struct srk_table); - - memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size); - - ret = validate_srk_tbl(img->srk_tbl, hdr->len_kr.num_srk); - + ret = read_validate_srk_tbl(img); if (ret != 0) return ret; - - img->key_len = img->srk_tbl[key_num - 1].key_len; - - memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey), - img->key_len); - key_found = 1; } #endif #if defined(CONFIG_FSL_ISBC_KEY_EXT) if (!key_found && check_ie(img)) { - if (get_ie_info_addr(&img->ie_addr)) - return ERROR_IE_TABLE_NOT_FOUND; - ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; - if (ie_info->num_keys == 0 || ie_info->num_keys > 32) - return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; - - ie_num = hdr->ie_key_sel; - if (ie_num == 0 || ie_num > ie_info->num_keys) - return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM; - - ie_revoc_flag = ie_info->key_revok; - if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag) - return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED; - - ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len; - - if (!((ie_key_len == 2 * KEY_SIZE_BYTES / 4) || - (ie_key_len == 2 * KEY_SIZE_BYTES / 2) || - (ie_key_len == 2 * KEY_SIZE_BYTES))) - return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN; - - memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey), - ie_key_len); - - img->key_len = ie_key_len; + ret = read_validate_ie_tbl(img); + if (ret != 0) + return ret; key_found = 1; } #endif if (key_found == 0) { - /* check key length */ - if (!((hdr->key_len == 2 * KEY_SIZE_BYTES / 4) || - (hdr->key_len == 2 * KEY_SIZE_BYTES / 2) || - (hdr->key_len == 2 * KEY_SIZE_BYTES))) - return ERROR_ESBC_CLIENT_HEADER_KEY_LEN; - - memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len); - - img->key_len = hdr->key_len; - + ret = read_validate_single_key(img); + if (ret != 0) + return ret; key_found = 1; } @@ -698,27 +732,73 @@ static inline int str2longbe(const char *p, ulong *num) return *p != '\0' && *endptr == '\0'; } +/* Function to calculate the ESBC Image Hash + * and hash from Digital signature. + * The Two hash's are compared to yield the + * result of signature validation. + */ +static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img) +{ + int ret; + uint32_t key_len; + struct key_prop prop; +#if !defined(USE_HOSTCC) + struct udevice *mod_exp_dev; +#endif + ret = calc_esbchdr_esbc_hash(img); + if (ret) + return ret; + + /* Construct encoded hash EM' wrt PKCSv1.5 */ + construct_img_encoded_hash_second(img); + + /* Fill prop structure for public key */ + memset(&prop, 0, sizeof(struct key_prop)); + key_len = get_key_len(img) / 2; + prop.modulus = img->img_key; + prop.public_exponent = img->img_key + key_len; + prop.num_bits = key_len * 8; + prop.exp_len = key_len; + + ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev); + if (ret) { + printf("RSA: Can't find Modular Exp implementation\n"); + return -EINVAL; + } + + ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len, + &prop, img->img_encoded_hash); + if (ret) + return ret; + + /* + * compare the encoded messages EM' and EM wrt RSA PKCSv1.5 + * memcmp returns zero on success + * memcmp returns non-zero on failure + */ + ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash, + img->hdr.sign_len); -int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) + if (ret) + return ERROR_ESBC_CLIENT_HASH_COMPARE_EM; + + return 0; +} + +int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, + uintptr_t img_addr) { struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); ulong hash[SHA256_BYTES/sizeof(ulong)]; char hash_str[NUM_HEX_CHARS + 1]; - ulong addr = simple_strtoul(argv[1], NULL, 16); struct fsl_secboot_img_priv *img; struct fsl_secboot_img_hdr *hdr; void *esbc; int ret, i, hash_cmd = 0; u32 srk_hash[8]; - uint32_t key_len; - struct key_prop prop; -#if !defined(USE_HOSTCC) - struct udevice *mod_exp_dev; -#endif - if (argc == 3) { - char *cp = argv[2]; + if (arg_hash_str != NULL) { + const char *cp = arg_hash_str; int i = 0; if (*cp == '0' && *(cp + 1) == 'x') @@ -731,7 +811,7 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, */ if (strlen(cp) != SHA256_NIBBLES) { printf("%s is not a 256 bits hex string as expected\n", - argv[2]); + arg_hash_str); return -1; } @@ -741,7 +821,7 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, hash_str[NUM_HEX_CHARS] = '\0'; if (!str2longbe(hash_str, &hash[i])) { printf("%s is not a 256 bits hex string ", - argv[2]); + arg_hash_str); return -1; } } @@ -756,9 +836,11 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, memset(img, 0, sizeof(struct fsl_secboot_img_priv)); + /* Update the information in Private Struct */ hdr = &img->hdr; - img->ehdrloc = addr; - esbc = (u8 *)(uintptr_t)img->ehdrloc; + img->ehdrloc = haddr; + img->img_addr = img_addr; + esbc = (u8 *)img->ehdrloc; memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr)); @@ -800,51 +882,12 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, goto exit; } - ret = calc_esbchdr_esbc_hash(img); + ret = calculate_cmp_img_sig(img); if (ret) { - fsl_secblk_handle_error(ret); - goto exit; - } - - /* Construct encoded hash EM' wrt PKCSv1.5 */ - construct_img_encoded_hash_second(img); - - /* Fill prop structure for public key */ - memset(&prop, 0, sizeof(struct key_prop)); - key_len = get_key_len(img) / 2; - prop.modulus = img->img_key; - prop.public_exponent = img->img_key + key_len; - prop.num_bits = key_len * 8; - prop.exp_len = key_len; - - ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev); - if (ret) { - printf("RSA: Can't find Modular Exp implementation\n"); - return -EINVAL; - } - - ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len, - &prop, img->img_encoded_hash); - if (ret) { - fsl_secblk_handle_error(ret); - goto exit; - } - - /* - * compare the encoded messages EM' and EM wrt RSA PKCSv1.5 - * memcmp returns zero on success - * memcmp returns non-zero on failure - */ - ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash, - img->hdr.sign_len); - - if (ret) { - fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_EM); + fsl_secboot_handle_error(ret); goto exit; } - printf("esbc_validate command successful\n"); - exit: - return 0; + return ret; } diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 9f6b0e7f31..113295f64a 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -216,6 +216,39 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #else printf("Not implemented\n"); #endif + } else if (strcmp(argv[1], "sd") == 0) { +#ifdef QIXIS_LBMAP_SD + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_SD); + set_rcw_src(QIXIS_RCW_SRC_SD); + QIXIS_WRITE(rcfg_ctl, 0x20); + QIXIS_WRITE(rcfg_ctl, 0x21); +#else + printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "sd_qspi") == 0) { +#ifdef QIXIS_LBMAP_SD_QSPI + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_SD_QSPI); + set_rcw_src(QIXIS_RCW_SRC_SD); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); +#else + printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "qspi") == 0) { +#ifdef QIXIS_LBMAP_QSPI + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_QSPI); + set_rcw_src(QIXIS_RCW_SRC_QSPI); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); +#else + printf("Not implemented\n"); +#endif } else if (strcmp(argv[1], "watchdog") == 0) { static char *period[9] = {"2s", "4s", "8s", "16s", "32s", "1min", "2min", "4min", "8min"}; @@ -255,6 +288,9 @@ U_BOOT_CMD( "- hard reset to default bank\n" "qixis_reset altbank - reset to alternate bank\n" "qixis_reset nand - reset to nand\n" + "qixis_reset sd - reset to sd\n" + "qixis_reset sd_qspi - reset to sd with qspi support\n" + "qixis_reset qspi - reset to qspi\n" "qixis watchdog <watchdog_period> - set the watchdog period\n" " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n" "qixis_reset dump - display the QIXIS registers\n" diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index be3358a564..5f4ec9d878 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -22,6 +22,7 @@ #include <fsl_sec.h> #include <spl.h> #include <fsl_devdis.h> +#include <fsl_validate.h> #include "../common/sleep.h" #include "../common/qixis.h" @@ -369,6 +370,9 @@ int board_late_init(void) #ifdef CONFIG_SCSI_AHCI_PLAT ls1021a_sata_init(); #endif +#ifdef CONFIG_CHAIN_OF_TRUST + fsl_setenv_chain_of_trust(); +#endif return 0; } diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 8eaff5f0ce..616e0bfd39 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -30,6 +30,7 @@ #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" #endif +#include <fsl_validate.h> DECLARE_GLOBAL_DATA_PTR; @@ -243,9 +244,9 @@ int board_mmc_init(bd_t *bis) } #endif -#ifdef CONFIG_TSEC_ENET int board_eth_init(bd_t *bis) { +#ifdef CONFIG_TSEC_ENET struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[4]; int num = 0; @@ -280,10 +281,10 @@ int board_eth_init(bd_t *bis) fsl_pq_mdio_init(bis, &mdio_info); tsec_eth_init(bis, tsec_info, num); +#endif return pci_eth_init(bis); } -#endif #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) int config_serdes_mux(void) @@ -549,6 +550,9 @@ int board_late_init(void) #ifdef CONFIG_SCSI_AHCI_PLAT ls1021a_sata_init(); #endif +#ifdef CONFIG_CHAIN_OF_TRUST + fsl_setenv_chain_of_trust(); +#endif return 0; } diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS index 0c7f648b6c..65a0af1930 100644 --- a/board/freescale/ls1043aqds/MAINTAINERS +++ b/board/freescale/ls1043aqds/MAINTAINERS @@ -7,3 +7,5 @@ F: configs/ls1043aqds_defconfig F: configs/ls1043aqds_nor_ddr3_defconfig F: configs/ls1043aqds_nand_defconfig F: configs/ls1043aqds_sdcard_ifc_defconfig +F: configs/ls1043aqds_sdcard_qspi_defconfig +F: configs/ls1043aqds_qspi_defconfig diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README index 6261a778aa..a6fd7a35f5 100644 --- a/board/freescale/ls1043aqds/README +++ b/board/freescale/ls1043aqds/README @@ -94,3 +94,4 @@ a) Promjet Boot b) NOR boot c) NAND boot d) SD boot +e) QSPI boot diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 42d906824a..3d3c53385a 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -132,9 +132,22 @@ void dram_init_banksize(void) * The address needs to add the offset of its bank. */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->secure_ram = gd->bd->bi_dram[1].start + + gd->secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } } diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index d6696ca812..01db078222 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -40,11 +40,14 @@ enum { #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */ #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */ #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */ +#define CFG_UART_MUX_MASK 0x6 +#define CFG_UART_MUX_SHIFT 1 +#define CFG_LPUART_EN 0x1 int checkboard(void) { char buf[64]; -#ifndef CONFIG_SD_BOOT +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) u8 sw; #endif @@ -52,6 +55,8 @@ int checkboard(void) #ifdef CONFIG_SD_BOOT puts("SD\n"); +#elif defined(CONFIG_QSPI_BOOT) + puts("QSPI\n"); #else sw = QIXIS_READ(brdcfg[0]); sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; @@ -218,7 +223,17 @@ void board_retimer_init(void) int board_early_init_f(void) { +#ifdef CONFIG_LPUART + u8 uart; +#endif fsl_lsch2_early_init_f(); +#ifdef CONFIG_LPUART + /* We use lpuart0 as system console */ + uart = QIXIS_READ(brdcfg[14]); + uart &= ~CFG_UART_MUX_MASK; + uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; + QIXIS_WRITE(brdcfg[14], uart); +#endif return 0; } @@ -303,6 +318,16 @@ int board_init(void) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg new file mode 100644 index 0000000000..7783521b95 --- /dev/null +++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +# Enable QSPI; disable IFC +08100010 0a000000 00000000 00000000 +14550002 80004012 60040000 c1002000 +00000000 00000000 00000000 00038800 +20124000 00001100 00000096 00000001 diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index ca9b43c6b6..de76d36174 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -301,9 +301,9 @@ void configure_rgmii(void) return; } -#ifdef CONFIG_TSEC_ENET int board_eth_init(bd_t *bis) { +#ifdef CONFIG_TSEC_ENET struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[4]; int num = 0; @@ -345,10 +345,10 @@ int board_eth_init(bd_t *bis) tsec_eth_init(bis, tsec_info, num); configure_rgmii(); +#endif return pci_eth_init(bis); } -#endif #if defined(CONFIG_OF_BOARD_SETUP) void ft_pci_setup(void *blob, bd_t *bd) diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 3f68cf496a..ed6836a930 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -171,9 +171,9 @@ int board_early_init_r(void) return 0; } -#ifdef CONFIG_TSEC_ENET int board_eth_init(bd_t *bis) { +#ifdef CONFIG_TSEC_ENET struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[4]; int num = 0; @@ -226,10 +226,10 @@ int board_eth_init(bd_t *bis) fsl_pq_mdio_init(bis, &mdio_info); tsec_eth_init(bis, tsec_info, num); +#endif return pci_eth_init(bis); } -#endif #if defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, bd_t *bd) diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index ebffe9a58a..1ae15407db 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -326,9 +326,9 @@ int checkboard(void) return 0; } -#ifdef CONFIG_TSEC_ENET int board_eth_init(bd_t *bis) { +#ifdef CONFIG_TSEC_ENET struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[4]; struct cpu_type *cpu; @@ -362,10 +362,10 @@ int board_eth_init(bd_t *bis) fsl_pq_mdio_init(bis, &mdio_info); tsec_eth_init(bis, tsec_info, num); +#endif return pci_eth_init(bis); } -#endif #if defined(CONFIG_OF_BOARD_SETUP) void fdt_del_flexcan(void *blob) diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index cae4a21c3d..e31331aec1 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -130,24 +130,26 @@ void _machine_restart(void) int board_early_init_f(void) { - void *io_base; + ulong io_base; /* choose correct PCI I/O base */ switch (malta_sys_con()) { case SYSCON_GT64120: - io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE); + io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE); break; case SYSCON_MSC01: - io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); + io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); break; default: return -1; } + set_io_port_base(io_base); + /* setup FDC37M817 super I/O controller */ - malta_superio_init(io_base); + malta_superio_init(); return 0; } @@ -179,8 +181,6 @@ void pci_init_board(void) switch (malta_sys_con()) { case SYSCON_GT64120: - set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE)); - gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, 0x10000000, 0x10000000, 128 * 1024 * 1024, @@ -189,8 +189,6 @@ void pci_init_board(void) default: case SYSCON_MSC01: - set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE)); - msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE), 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, MALTA_MSC01_PCIMEM_MAP, diff --git a/board/imgtec/malta/superio.c b/board/imgtec/malta/superio.c index eaa14df39e..7865ae2b70 100644 --- a/board/imgtec/malta/superio.c +++ b/board/imgtec/malta/superio.c @@ -45,19 +45,19 @@ static struct { { SIOCONF_ACTIVATE, 0x01 }, }; -void malta_superio_init(void *io_base) +void malta_superio_init(void) { unsigned i; /* enter config state */ - writeb(SIOCONF_ENTER_SETUP, io_base + SIO_CONF_PORT); + outb(SIOCONF_ENTER_SETUP, SIO_CONF_PORT); /* configure peripherals */ for (i = 0; i < ARRAY_SIZE(sio_config); i++) { - writeb(sio_config[i].key, io_base + SIO_CONF_PORT); - writeb(sio_config[i].data, io_base + SIO_DATA_PORT); + outb(sio_config[i].key, SIO_CONF_PORT); + outb(sio_config[i].data, SIO_DATA_PORT); } /* exit config state */ - writeb(SIOCONF_EXIT_SETUP, io_base + SIO_CONF_PORT); + outb(SIOCONF_EXIT_SETUP, SIO_CONF_PORT); } diff --git a/board/imgtec/malta/superio.h b/board/imgtec/malta/superio.h index 1450da56dd..271c462eac 100644 --- a/board/imgtec/malta/superio.h +++ b/board/imgtec/malta/superio.h @@ -10,6 +10,6 @@ #ifndef __BOARD_MALTA_SUPERIO_H__ #define __BOARD_MALTA_SUPERIO_H__ -extern void malta_superio_init(void *io_base); +void malta_superio_init(void); #endif /* __BOARD_MALTA_SUPERIO_H__ */ diff --git a/board/microchip/pic32mzda/Kconfig b/board/microchip/pic32mzda/Kconfig new file mode 100644 index 0000000000..8acb393369 --- /dev/null +++ b/board/microchip/pic32mzda/Kconfig @@ -0,0 +1,13 @@ + +if TARGET_PIC32MZDASK + +config SYS_BOARD + default "pic32mzda" + +config SYS_VENDOR + default "microchip" + +config SYS_CONFIG_NAME + default "pic32mzdask" + +endif diff --git a/board/microchip/pic32mzda/MAINTAINERS b/board/microchip/pic32mzda/MAINTAINERS new file mode 100644 index 0000000000..c934f1a1f5 --- /dev/null +++ b/board/microchip/pic32mzda/MAINTAINERS @@ -0,0 +1,6 @@ +PIC32MZDASK BOARD +M: Purna Chandra Mandal <purna.mandal@microchip.com> +S: Maintained +F: board/microchip/pic32mzda/ +F: include/configs/pic32mzdask.h +F: configs/pic32mzdask_defconfig diff --git a/board/microchip/pic32mzda/Makefile b/board/microchip/pic32mzda/Makefile new file mode 100644 index 0000000000..36295302a1 --- /dev/null +++ b/board/microchip/pic32mzda/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 +# Purna Chandra Mandal, purna.mandal@microchip.com. +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y := pic32mzda.o diff --git a/board/microchip/pic32mzda/README b/board/microchip/pic32mzda/README new file mode 100644 index 0000000000..91d16ab7dc --- /dev/null +++ b/board/microchip/pic32mzda/README @@ -0,0 +1,22 @@ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> + */ + +PIC32MZ[DA] Starter Kit +---------------------------------------- +PIC32MZ[DA] Starter Kit is based on PIC32MZ[DA] family of micro-controller. +This family is powered by MIPS M14KEC 32bit general purpose core and has +advanced microcontroller features and peripherals. + +This processor boots with proprietary stage1 bootloader running from internal +boot-flash. Stage1 bootloader inturns locates and jumps to U-Boot programmed +on internal program-flash. Finally U-Boot loads OS image (along with other +required files for booting) from either uSD card, or ethernet, or from USB +storage. + +To boot Linux following three files are mandatory - uEnv.txt (custom U-Boot +environment file), uImage, *.dtb (platform device-tree-blob file). + +U-Boot jumps to Linux using UHI specification. + +Visit http://microchip.com for details. diff --git a/board/microchip/pic32mzda/pic32mzda.c b/board/microchip/pic32mzda/pic32mzda.c new file mode 100644 index 0000000000..afe2ab8b71 --- /dev/null +++ b/board/microchip/pic32mzda/pic32mzda.c @@ -0,0 +1,31 @@ +/* + * Microchip PIC32MZ[DA] Starter Kit board + * + * Copyright (C) 2015, Microchip Technology Inc. + * Purna Chandra Mandal <purna.mandal@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <dm.h> +#include <clk.h> +#include <mach/pic32.h> + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + ulong rate = 0; + struct udevice *dev; + + printf("Core: %s\n", get_core_name()); + + if (!uclass_get_device(UCLASS_CLK, 0, &dev)) { + rate = clk_get_rate(dev); + printf("CPU Speed: %lu MHz\n", rate / 1000000); + } + + return 0; +} +#endif diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index 6f189aa74e..14f0ce5455 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -57,19 +57,6 @@ int tegra_pcie_board_init(void) return err; } - err = as3722_gpio_configure(pmic, 1, AS3722_GPIO_OUTPUT_VDDH | - AS3722_GPIO_INVERT); - if (err < 0) { - error("failed to configure GPIO#1 as output: %d\n", err); - return err; - } - - err = as3722_gpio_direction_output(pmic, 2, 1); - if (err < 0) { - error("failed to set GPIO#2 high: %d\n", err); - return err; - } - return 0; } #endif /* PCI */ diff --git a/board/theadorable/MAINTAINERS b/board/theadorable/MAINTAINERS new file mode 100644 index 0000000000..5ae6b6487c --- /dev/null +++ b/board/theadorable/MAINTAINERS @@ -0,0 +1,7 @@ +THEADORABLE BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/theadorable/ +F: include/configs/theadorable.h +F: configs/theadorable_debug_defconfig +F: configs/theadorable_defconfig diff --git a/board/theadorable/Makefile b/board/theadorable/Makefile new file mode 100644 index 0000000000..9d5b39e696 --- /dev/null +++ b/board/theadorable/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := theadorable.o diff --git a/board/theadorable/kwbimage.cfg b/board/theadorable/kwbimage.cfg new file mode 100644 index 0000000000..4f3b7b23f3 --- /dev/null +++ b/board/theadorable/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c new file mode 100644 index 0000000000..0e232656fc --- /dev/null +++ b/board/theadorable/theadorable.c @@ -0,0 +1,171 @@ +/* + * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#ifdef CONFIG_NET +#include <netdev.h> +#endif + +#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" +#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780 +#define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0 +#define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0)) + +#define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f +#define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c +#define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000 + +/* DDR3 static configuration */ +static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = { + {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */ + {0x00001404, 0x30000800}, /* Dunit Control Low Register */ + {0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */ + {0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */ + {0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */ + {0x00001424, 0x0000f3ff}, /* Dunit Control High Register */ + {0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */ + {0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */ + {0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */ + + {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */ + {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */ + {0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */ + {0x000014A8, 0x00000101}, /* AXI Control Register */ + + /* + * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the + * training sequence + */ + {0x000200e8, 0x3fff0e01}, + {0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */ + + {0x0001504, 0x7fffffe1}, /* CS0 Size */ + {0x000150C, 0x00000000}, /* CS1 Size */ + {0x0001514, 0x00000000}, /* CS2 Size */ + {0x000151C, 0x00000000}, /* CS3 Size */ + + {0x00020220, 0x00000007}, /* Reserved */ + + {0x00001538, 0x00000009}, /* Read Data Sample Delays Register */ + {0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */ + + {0x000015D0, 0x00000650}, /* MR0 */ + {0x000015D4, 0x00000044}, /* MR1 */ + {0x000015D8, 0x00000010}, /* MR2 */ + {0x000015DC, 0x00000000}, /* MR3 */ + {0x000015E0, 0x00000001}, + {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */ + {0x000015EC, 0xf800a225}, /* DDR PHY */ + + /* Recommended Settings from Marvell for 4 x 16 bit devices: */ + {0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/ + {0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */ + + {0x0, 0x0} +}; + +static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = { + {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL}, +}; + +extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[]; + +/* + * Lane0 - PCIE0.0 X1 (to WIFI Module) + * Lane5 - SATA0 + * Lane6 - SATA1 + * Lane7 - SGMII0 (to Ethernet Phy) + * Lane8-11 - PCIE2.0 X4 (to PEX Switch) + * all other lanes are disabled + */ +MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = { + { MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111, + { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, + PEX_BUS_DISABLED }, + 0x0060, serdes_change_m_phy + }, +}; + +MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) +{ + /* Only one mode supported for this board */ + return &board_ddr_modes[0]; +} + +MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +{ + return &theadorable_serdes_cfg[0]; +} + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x00000000, MVEBU_MPP_BASE + 0x00); + writel(0x03300000, MVEBU_MPP_BASE + 0x04); + writel(0x00000033, MVEBU_MPP_BASE + 0x08); + writel(0x00000000, MVEBU_MPP_BASE + 0x0c); + writel(0x11110000, MVEBU_MPP_BASE + 0x10); + writel(0x00221100, MVEBU_MPP_BASE + 0x14); + writel(0x00000000, MVEBU_MPP_BASE + 0x18); + writel(0x00000000, MVEBU_MPP_BASE + 0x1c); + writel(0x00000000, MVEBU_MPP_BASE + 0x20); + + /* Configure GPIO */ + writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00); + writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: theadorable\n"); + + return 0; +} + +#ifdef CONFIG_NET +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Built in controller(s) come first */ + return pci_eth_init(bis); +} +#endif + +int board_video_init(void) +{ + struct mvebu_lcd_info lcd_info; + + /* Reserved memory area via CONFIG_SYS_MEM_TOP_HIDE */ + lcd_info.fb_base = gd->ram_size; + lcd_info.x_res = 240; + lcd_info.x_fp = 1; + lcd_info.x_bp = 45; + lcd_info.y_res = 320; + lcd_info.y_fp = 1; + lcd_info.y_bp = 3; + + return mvebu_lcd_register_init(&lcd_info); +} diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index dfa6293222..ccd4ec955b 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -12,7 +12,6 @@ #include <common.h> #include <config.h> #include <fdtdec.h> -#include <netdev.h> #include <asm/processor.h> #include <asm/microblaze_intc.h> #include <asm/asm.h> @@ -24,7 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; static int reset_pin = -1; #endif -#if CONFIG_IS_ENABLED(OF_CONTROL) ulong ram_base; void dram_init_banksize(void) @@ -58,14 +56,6 @@ int dram_init(void) return 0; }; -#else -int dram_init(void) -{ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - - return 0; -} -#endif int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -86,7 +76,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -int gpio_init (void) +static int gpio_init(void) { #ifdef CONFIG_XILINX_GPIO reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1); @@ -96,32 +86,9 @@ int gpio_init (void) return 0; } -void board_init(void) +int board_late_init(void) { gpio_init(); -} -int board_eth_init(bd_t *bis) -{ - int ret = 0; - -#ifdef CONFIG_XILINX_AXIEMAC - ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, - XILINX_AXIDMA_BASEADDR); -#endif - -#if defined(CONFIG_XILINX_EMACLITE) && defined(XILINX_EMACLITE_BASEADDR) - u32 txpp = 0; - u32 rxpp = 0; -# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG - txpp = 1; -# endif -# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG - rxpp = 1; -# endif - ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, - txpp, rxpp); -#endif - - return ret; + return 0; } diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index 8ba146cb88..ccb528ed92 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -28,15 +28,6 @@ #define XILINX_TIMER_BASEADDR 0x41c00000 #define XILINX_TIMER_IRQ 0 -/* Uart pheriphery is RS232_Uart */ -#define XILINX_UARTLITE_BASEADDR 0x40600000 -#define XILINX_UARTLITE_BAUDRATE 115200 - -/* IIC pheriphery is IIC_EEPROM */ -#define XILINX_IIC_0_BASEADDR 0x40800000 -#define XILINX_IIC_0_FREQ 100000 -#define XILINX_IIC_0_BIT 0 - /* GPIO is LEDs_4Bit*/ #define XILINX_GPIO_BASEADDR 0x40000000 @@ -44,18 +35,6 @@ #define XILINX_FLASH_START 0x2c000000 #define XILINX_FLASH_SIZE 0x00800000 -/* Main Memory is DDR_SDRAM_64Mx32 */ -#define XILINX_RAM_START 0x28000000 -#define XILINX_RAM_SIZE 0x04000000 - -/* Sysace Controller is SysACE_CompactFlash */ -#define XILINX_SYSACE_BASEADDR 0x41800000 -#define XILINX_SYSACE_HIGHADDR 0x4180ffff -#define XILINX_SYSACE_MEM_WIDTH 16 - -/* Ethernet controller is Ethernet_MAC */ -#define XILINX_EMACLITE_BASEADDR 0x40C00000 - /* Watchdog IP is wxi_timebase_wdt_0 */ #define XILINX_WATCHDOG_BASEADDR 0x50000000 #define XILINX_WATCHDOG_IRQ 1 diff --git a/board/xilinx/ml507/Kconfig b/board/xilinx/ml507/Kconfig deleted file mode 100644 index d580a7beaf..0000000000 --- a/board/xilinx/ml507/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ML507 - -config SYS_BOARD - default "ml507" - -config SYS_VENDOR - default "xilinx" - -config SYS_CONFIG_NAME - default "ml507" - -endif diff --git a/board/xilinx/ml507/MAINTAINERS b/board/xilinx/ml507/MAINTAINERS deleted file mode 100644 index 8b40f44500..0000000000 --- a/board/xilinx/ml507/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -ML507 BOARD -M: Ricardo Ribalda <ricardo.ribalda@uam.es> -S: Maintained -F: board/xilinx/ml507/ -F: include/configs/ml507.h -F: configs/ml507_defconfig -F: configs/ml507_flash_defconfig diff --git a/board/xilinx/ml507/Makefile b/board/xilinx/ml507/Makefile deleted file mode 100644 index 9a3809f3c0..0000000000 --- a/board/xilinx/ml507/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2008 -# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es -# This work has been supported by: Qtechnology http://qtec.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ml507.o - -include $(srctree)/board/xilinx/ppc440-generic/Makefile diff --git a/board/xilinx/ml507/ml507.c b/board/xilinx/ml507/ml507.c deleted file mode 100644 index 83b764b733..0000000000 --- a/board/xilinx/ml507/ml507.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <config.h> -#include <common.h> -#include <asm/processor.h> - - -int checkboard(void) -{ - puts("Xilinx ML507 Board\n"); - return 0; -} diff --git a/board/xilinx/ml507/xparameters.h b/board/xilinx/ml507/xparameters.h deleted file mode 100644 index e30e592bbe..0000000000 --- a/board/xilinx/ml507/xparameters.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * based on xparameters-ml507.h by Xilinx - * - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef XPARAMETER_H -#define XPARAMETER_H - -#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 -#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 -#define XPAR_INTC_0_BASEADDR 0x81800000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 -#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 -#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 -#define XPAR_UARTLITE_0_BAUDRATE 9600 - -#endif diff --git a/board/xilinx/ppc405-generic/MAINTAINERS b/board/xilinx/ppc405-generic/MAINTAINERS index 2b0c98dc8b..ba48f50c29 100644 --- a/board/xilinx/ppc405-generic/MAINTAINERS +++ b/board/xilinx/ppc405-generic/MAINTAINERS @@ -1,5 +1,5 @@ PPC405-GENERIC BOARD -M: Ricardo Ribalda <ricardo.ribalda@uam.es> +M: Ricardo Ribalda <ricardo.ribalda@gmail.com> S: Maintained F: board/xilinx/ppc405-generic/ F: include/configs/xilinx-ppc405-generic.h diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile index c9da870657..2800f68626 100644 --- a/board/xilinx/ppc405-generic/Makefile +++ b/board/xilinx/ppc405-generic/Makefile @@ -3,10 +3,10 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com # Work supported by Qtechnology http://www.qtec.com # # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o +obj-y += xilinx_ppc405_generic.o diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c index e3dd468f1e..3729f07624 100644 --- a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c +++ b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * SPDX-License-Identifier: GPL-2.0+ @@ -10,39 +10,32 @@ #include <common.h> #include <asm/processor.h> -ulong __get_PCI_freq(void) +ulong get_PCI_freq(void) { return 0; } -ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq"))); - -int __board_pre_init(void) -{ - return 0; -} -int board_pre_init(void) __attribute__((weak, alias("__board_pre_init"))); - -int __checkboard(void) +int checkboard(void) { puts("Xilinx PPC405 Generic Board\n"); return 0; } -int checkboard(void) __attribute__((weak, alias("__checkboard"))); -phys_size_t __initdram(int board_type) +phys_size_t initdram(int board_type) { return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); } -phys_size_t initdram(int) __attribute__((weak, alias("__initdram"))); -void __get_sys_info(sys_info_t *sysInfo) +void get_sys_info(sys_info_t *sys_info) { - sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; - sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; - sysInfo->freqPCI = 0; + sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; + sys_info->freqPCI = 0; return; } -void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); + +int get_serial_clock(void){ + return XPAR_UARTNS550_0_CLOCK_FREQ_HZ; +} diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h index f0ff78fca5..c3df9e5109 100644 --- a/board/xilinx/ppc405-generic/xparameters.h +++ b/board/xilinx/ppc405-generic/xparameters.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * based on xparameters-ml507.h by Xilinx * @@ -14,12 +14,11 @@ #define XPAR_IIC_EEPROM_BASEADDR 0x81600000 #define XPAR_INTC_0_BASEADDR 0x81800000 #define XPAR_SPI_0_BASEADDR 0x83400000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 #define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 #define XPAR_PLB_CLOCK_FREQ_HZ 100000000 #define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 -#define XPAR_UARTLITE_0_BAUDRATE 9600 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32 #define XPAR_SPI_0_NUM_TRANSFER_BITS 8 +#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 #endif diff --git a/board/xilinx/ppc440-generic/MAINTAINERS b/board/xilinx/ppc440-generic/MAINTAINERS index 2d0b11af91..0258c8204a 100644 --- a/board/xilinx/ppc440-generic/MAINTAINERS +++ b/board/xilinx/ppc440-generic/MAINTAINERS @@ -1,5 +1,5 @@ PPC440-GENERIC BOARD -M: Ricardo Ribalda <ricardo.ribalda@uam.es> +M: Ricardo Ribalda <ricardo.ribalda@gmail.com> S: Maintained F: board/xilinx/ppc440-generic/ F: include/configs/xilinx-ppc440-generic.h diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile index 0acd95d6e4..4d5f41029a 100644 --- a/board/xilinx/ppc440-generic/Makefile +++ b/board/xilinx/ppc440-generic/Makefile @@ -3,11 +3,11 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com # Work supported by Qtechnology http://www.qtec.com # # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o -extra-y += ../../xilinx/ppc440-generic/init.o +obj-y += xilinx_ppc440_generic.o +extra-y += init.o diff --git a/board/xilinx/ppc440-generic/init.S b/board/xilinx/ppc440-generic/init.S index 4598a37684..f9ff35f51b 100644 --- a/board/xilinx/ppc440-generic/init.S +++ b/board/xilinx/ppc440-generic/init.S @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c index 74df2f4ff7..d823352930 100644 --- a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c +++ b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * SPDX-License-Identifier: GPL-2.0+ @@ -8,34 +8,51 @@ #include <config.h> #include <common.h> +#include <netdev.h> #include <asm/processor.h> -int __board_pre_init(void) -{ - return 0; -} -int board_pre_init(void) __attribute__((weak, alias("__board_pre_init"))); - -int __checkboard(void) +int checkboard(void) { puts("Xilinx PPC440 Generic Board\n"); return 0; } -int checkboard(void) __attribute__((weak, alias("__checkboard"))); -phys_size_t __initdram(int board_type) +phys_size_t initdram(int board_type) { return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); } -phys_size_t initdram(int) __attribute__((weak, alias("__initdram"))); -void __get_sys_info(sys_info_t *sysInfo) +void get_sys_info(sys_info_t *sys_info) { - sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; - sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; - sysInfo->freqPCI = 0; + sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; + sys_info->freqPCI = 0; return; } -void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); + +int get_serial_clock(void){ + return XPAR_UARTNS550_0_CLOCK_FREQ_HZ; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; + + puts("Init xilinx temac\n"); +#ifdef XPAR_LLTEMAC_0_BASEADDR + ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_0_BASEADDR, + XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB, + XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR); + +#endif + +#ifdef XPAR_LLTEMAC_1_BASEADDR + ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_1_BASEADDR, + XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB, + XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR); +#endif + + return ret; +} diff --git a/board/xilinx/ppc440-generic/xparameters.h b/board/xilinx/ppc440-generic/xparameters.h index e30e592bbe..b45a6a1d76 100644 --- a/board/xilinx/ppc440-generic/xparameters.h +++ b/board/xilinx/ppc440-generic/xparameters.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * based on xparameters-ml507.h by Xilinx * @@ -12,12 +12,15 @@ #define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 #define XPAR_IIC_EEPROM_BASEADDR 0x81600000 -#define XPAR_INTC_0_BASEADDR 0x81800000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 -#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 +#define XPAR_INTC_0_BASEADDR 0x87000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xF0000000 #define XPAR_PLB_CLOCK_FREQ_HZ 100000000 #define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 -#define XPAR_UARTLITE_0_BAUDRATE 9600 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32 +#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 +#define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x80 +#define XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR 0x98 +#define XPAR_LLTEMAC_0_BASEADDR 0x83000000 +#define XPAR_LLTEMAC_1_BASEADDR 0x83000040 #endif diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 414f5302a0..01bae5d67e 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -8,7 +8,6 @@ #include <fdtdec.h> #include <fpga.h> #include <mmc.h> -#include <netdev.h> #include <zynqpl.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> @@ -94,34 +93,11 @@ int board_late_init(void) #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard(void) { - puts("Board:\tXilinx Zynq\n"); + puts("Board: Xilinx Zynq\n"); return 0; } #endif -int board_eth_init(bd_t *bis) -{ - u32 ret = 0; - -#ifdef CONFIG_XILINX_AXIEMAC - ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, - XILINX_AXIDMA_BASEADDR); -#endif -#ifdef CONFIG_XILINX_EMACLITE - u32 txpp = 0; - u32 rxpp = 0; -# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG - txpp = 1; -# endif -# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG - rxpp = 1; -# endif - ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, - txpp, rxpp); -#endif - return ret; -} - int dram_init(void) { #if CONFIG_IS_ENABLED(OF_CONTROL) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 2cf47125d4..44d347ed3b 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -9,6 +9,7 @@ #include <netdev.h> #include <ahci.h> #include <scsi.h> +#include <asm/arch/clk.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> @@ -28,10 +29,18 @@ int board_early_init_r(void) { u32 val; - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - + if (current_el() == 3) { + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + /* Program freq register in System counter */ + writel(zynqmp_get_system_timer_freq(), + &iou_scntr_secure->base_frequency_id_register); + /* And enable system counter */ + writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, + &iou_scntr_secure->counter_control_register); + } /* Program freq register in System counter and enable system counter */ writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register); writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG | @@ -48,11 +57,6 @@ int dram_init(void) return 0; } -int timer_init(void) -{ - return 0; -} - void reset_cpu(ulong addr) { } @@ -73,11 +77,36 @@ int board_late_init(void) reg = readl(&crlapb_base->boot_mode); bootmode = reg & BOOT_MODES_MASK; + puts("Bootmode: "); switch (bootmode) { - case SD_MODE: + case JTAG_MODE: + puts("JTAG_MODE\n"); + setenv("modeboot", "jtagboot"); + break; + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + setenv("modeboot", "qspiboot"); + puts("QSPI_MODE\n"); + break; case EMMC_MODE: + puts("EMMC_MODE\n"); + setenv("modeboot", "sdboot"); + break; + case SD_MODE: + puts("SD_MODE\n"); setenv("modeboot", "sdboot"); break; + case SD_MODE1: + puts("SD_MODE1\n"); +#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) + setenv("sdbootdev", "1"); +#endif + setenv("modeboot", "sdboot"); + break; + case NAND_MODE: + puts("NAND_MODE\n"); + setenv("modeboot", "nandboot"); + break; default: printf("Invalid Boot Mode:0x%x\n", bootmode); break; @@ -88,7 +117,7 @@ int board_late_init(void) int checkboard(void) { - puts("Board:\tXilinx ZynqMP\n"); + puts("Board: Xilinx ZynqMP\n"); return 0; } diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index deed6d8255..8eda68b4f9 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -205,7 +205,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_num("sram start ", (ulong)bd->bi_sramstart); print_num("sram size ", (ulong)bd->bi_sramsize); #endif -#if defined(CONFIG_CMD_NET) +#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH) print_eths(); #endif printf("baudrate = %u bps\n", gd->baudrate); diff --git a/cmd/ethsw.c b/cmd/ethsw.c index 8e452e95be..491cb8eac3 100644 --- a/cmd/ethsw.c +++ b/cmd/ethsw.c @@ -71,7 +71,7 @@ static int ethsw_vlan_help_key_func(struct ethsw_command_def *parsed_cmd) #define ETHSW_PORT_UNTAG_HELP "ethsw [port <port_no>] untagged " \ "{ [help] | show | all | none | pvid } " \ -" - set egress tagging mod for a port" +" - set egress tagging mode for a port" static int ethsw_port_untag_help_key_func(struct ethsw_command_def *parsed_cmd) { @@ -114,6 +114,17 @@ static int ethsw_ingr_fltr_help_key_func(struct ethsw_command_def *parsed_cmd) return CMD_RET_SUCCESS; } +#define ETHSW_PORT_AGGR_HELP "ethsw [port <port_no>] aggr" \ +" { [help] | show | <lag_group_no> } " \ +"- get/set LAG group for a port" + +static int ethsw_port_aggr_help_key_func(struct ethsw_command_def *parsed_cmd) +{ + printf(ETHSW_PORT_AGGR_HELP"\n"); + + return CMD_RET_SUCCESS; +} + static struct keywords_to_function { enum ethsw_keyword_id cmd_keyword[ETHSW_MAX_CMD_PARAMS]; int cmd_func_offset; @@ -532,6 +543,39 @@ static struct keywords_to_function { .cmd_func_offset = offsetof(struct ethsw_command_func, port_ingr_filt_set), .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_aggr, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_port_aggr_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_aggr, + ethsw_id_help, + ethsw_id_key_end, + }, + .cmd_func_offset = -1, + .keyword_function = ðsw_port_aggr_help_key_func, + }, { + .cmd_keyword = { + ethsw_id_aggr, + ethsw_id_show, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_aggr_show), + .keyword_function = NULL, + }, { + .cmd_keyword = { + ethsw_id_aggr, + ethsw_id_aggr_no, + ethsw_id_key_end, + }, + .cmd_func_offset = offsetof(struct ethsw_command_func, + port_aggr_set), + .keyword_function = NULL, }, }; @@ -576,6 +620,9 @@ static int keyword_match_pvid(enum ethsw_keyword_id key_id, int argc, static int keyword_match_mac_addr(enum ethsw_keyword_id key_id, int argc, char *const argv[], int *argc_nr, struct ethsw_command_def *parsed_cmd); +static int keyword_match_aggr(enum ethsw_keyword_id key_id, int argc, + char *const argv[], int *argc_nr, + struct ethsw_command_def *parsed_cmd); /* * Define properties for each keyword; @@ -661,6 +708,9 @@ struct keyword_def { }, { .keyword_name = "filtering", .match = &keyword_match_gen, + }, { + .keyword_name = "aggr", + .match = &keyword_match_aggr, }, }; @@ -826,6 +876,28 @@ static int keyword_match_mac_addr(enum ethsw_keyword_id key_id, int argc, return 1; } +/* Function used to match the command's aggregation number */ +static int keyword_match_aggr(enum ethsw_keyword_id key_id, int argc, + char *const argv[], int *argc_nr, + struct ethsw_command_def *parsed_cmd) +{ + unsigned long val; + + if (!keyword_match_gen(key_id, argc, argv, argc_nr, parsed_cmd)) + return 0; + + if (*argc_nr + 1 >= argc) + return 1; + + if (strict_strtoul(argv[*argc_nr + 1], 10, &val) != -EINVAL) { + parsed_cmd->aggr_grp = val; + (*argc_nr)++; + parsed_cmd->cmd_to_keywords[*argc_nr] = ethsw_id_aggr_no; + } + + return 1; +} + /* Finds optional keywords and modifies *argc_va to skip them */ static void cmd_keywords_opt_check(const struct ethsw_command_def *parsed_cmd, int *argc_val) @@ -984,6 +1056,7 @@ static void command_def_init(struct ethsw_command_def *parsed_cmd) parsed_cmd->port = ETHSW_CMD_PORT_ALL; parsed_cmd->vid = ETHSW_CMD_VLAN_ALL; + parsed_cmd->aggr_grp = ETHSW_CMD_AGGR_GRP_NONE; parsed_cmd->cmd_function = NULL; /* We initialize the MAC address with the Broadcast address */ @@ -1010,7 +1083,7 @@ static int do_ethsw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #define ETHSW_PORT_CONF_HELP "[port <port_no>] { enable | disable | show } " \ -"- enable/disable a port; show shows a port's configuration" +"- enable/disable a port; show a port's configuration" U_BOOT_CMD(ethsw, ETHSW_MAX_CMD_PARAMS, 0, do_ethsw, "Ethernet l2 switch commands", @@ -1024,4 +1097,5 @@ U_BOOT_CMD(ethsw, ETHSW_MAX_CMD_PARAMS, 0, do_ethsw, ETHSW_EGR_VLAN_TAG_HELP"\n" ETHSW_VLAN_FDB_HELP"\n" ETHSW_PORT_INGR_FLTR_HELP"\n" + ETHSW_PORT_AGGR_HELP"\n" ); diff --git a/cmd/fpga.c b/cmd/fpga.c index 7f99aabf8a..8956eb1b65 100644 --- a/cmd/fpga.c +++ b/cmd/fpga.c @@ -86,7 +86,7 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) debug("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data); } - debug("%s: fpga_data = 0x%x\n", __func__, (uint)fpga_data); + debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data); case 3: /* fpga <op> <dev | data addr> */ dev = (int)simple_strtoul(argv[2], NULL, 16); @@ -107,13 +107,13 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) } else #endif { - fpga_data = (void *)dev; + fpga_data = (void *)(uintptr_t)dev; debug("* fpga: cmdline image addr = 0x%08lx\n", (ulong)fpga_data); } - debug("%s: fpga_data = 0x%x\n", - __func__, (uint)fpga_data); + debug("%s: fpga_data = 0x%lx\n", + __func__, (ulong)fpga_data); dev = FPGA_INVALID_DEVICE; /* reset device num */ } @@ -578,9 +578,10 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if ((bdf = get_pci_dev(argv[2])) == -1) return 1; break; -#ifdef CONFIG_CMD_PCI_ENUM +#if defined(CONFIG_CMD_PCI_ENUM) || defined(CONFIG_DM_PCI) case 'e': - break; + pci_init(); + return 0; #endif default: /* scan bus */ value = 1; /* short listing */ @@ -621,15 +622,6 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) break; case 'd': /* display */ return pci_cfg_display(dev, addr, size, value); -#ifdef CONFIG_CMD_PCI_ENUM - case 'e': -# ifdef CONFIG_DM_PCI - printf("This command is not yet supported with driver model\n"); -# else - pci_init(); -# endif - break; -#endif case 'n': /* next */ if (argc < 4) goto usage; @@ -665,9 +657,9 @@ static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) static char pci_help_text[] = "[bus] [long]\n" " - short or long list of PCI devices on bus 'bus'\n" -#ifdef CONFIG_CMD_PCI_ENUM +#if defined(CONFIG_CMD_PCI_ENUM) || defined(CONFIG_DM_PCI) "pci enum\n" - " - re-enumerate PCI buses\n" + " - Enumerate PCI buses\n" #endif "pci header b.d.f\n" " - show header of PCI device 'bus.device.function'\n" @@ -448,7 +448,7 @@ static int get_tpm(struct udevice **devp) int rc; rc = uclass_first_device(UCLASS_TPM, devp); - if (rc) { + if (rc || !*devp) { printf("Could not find TPM (ret=%d)\n", rc); return CMD_RET_FAILURE; } diff --git a/common/dlmalloc.c b/common/dlmalloc.c index b5bb05191c..2b964d16b1 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -2829,6 +2829,28 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; nb = request2size(bytes); m = (char*)(mALLOc(nb + alignment + MINSIZE)); + /* + * The attempt to over-allocate (with a size large enough to guarantee the + * ability to find an aligned region within allocated memory) failed. + * + * Try again, this time only allocating exactly the size the user wants. If + * the allocation now succeeds and just happens to be aligned, we can still + * fulfill the user's request. + */ + if (m == NULL) { + /* + * Use bytes not nb, since mALLOc internally calls request2size too, and + * each call increases the size to allocate, to account for the header. + */ + m = (char*)(mALLOc(bytes)); + /* Aligned -> return it */ + if ((((unsigned long)(m)) % alignment) == 0) + return m; + /* Otherwise, fail */ + fREe(m); + return NULL; + } + if (m == NULL) return NULL; /* propagate failure */ p = mem2chunk(m); diff --git a/common/env_sf.c b/common/env_sf.c index 940983124f..892e6cbfb8 100644 --- a/common/env_sf.c +++ b/common/env_sf.c @@ -16,6 +16,7 @@ #include <spi_flash.h> #include <search.h> #include <errno.h> +#include <dm/device-internal.h> #ifndef CONFIG_ENV_SPI_BUS # define CONFIG_ENV_SPI_BUS 0 @@ -51,6 +52,19 @@ int saveenv(void) char *saved_buffer = NULL, flag = OBSOLETE_FLAG; u32 saved_size, saved_offset, sector = 1; int ret; +#ifdef CONFIG_DM_SPI_FLASH + struct udevice *new; + + ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, + CONFIG_ENV_SPI_MODE, &new); + if (ret) { + set_default_env("!spi_flash_probe_bus_cs() failed"); + return 1; + } + + env_flash = dev_get_uclass_priv(new); +#else if (!env_flash) { env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, @@ -61,6 +75,7 @@ int saveenv(void) return 1; } } +#endif ret = env_export(&env_new); if (ret) @@ -227,6 +242,19 @@ int saveenv(void) char *saved_buffer = NULL; int ret = 1; env_t env_new; +#ifdef CONFIG_DM_SPI_FLASH + struct udevice *new; + + ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, + CONFIG_ENV_SPI_MODE, &new); + if (ret) { + set_default_env("!spi_flash_probe_bus_cs() failed"); + return 1; + } + + env_flash = dev_get_uclass_priv(new); +#else if (!env_flash) { env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, @@ -237,6 +265,7 @@ int saveenv(void) return 1; } } +#endif /* Is the sector larger than the env (i.e. embedded) */ if (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) { diff --git a/configs/fx12mm_defconfig b/configs/fx12mm_defconfig deleted file mode 100644 index c714d0d35e..0000000000 --- a/configs/fx12mm_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_FX12MM=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o" -CONFIG_SYS_PROMPT="FX12MM:/# " -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set -CONFIG_SYS_NS16550=y diff --git a/configs/fx12mm_flash_defconfig b/configs/fx12mm_flash_defconfig deleted file mode 100644 index ac3841260d..0000000000 --- a/configs/fx12mm_flash_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_FX12MM=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set -CONFIG_SYS_NS16550=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 60fb0ada85..f7113c5a0c 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -2,5 +2,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_ARM=y CONFIG_TARGET_LS1043AQDS=y CONFIG_SYS_NS16550=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds" +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig new file mode 100644 index 0000000000..21d6407c5e --- /dev/null +++ b/configs/ls1043aqds_lpuart_defconfig @@ -0,0 +1,10 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y +CONFIG_DM_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart" +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_FSL_LPUART=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index e9d5afd43a..8d4370fdcc 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -3,3 +3,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1043AQDS=y CONFIG_SYS_NS16550=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 5221ddb434..bc7699698a 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -1,3 +1,8 @@ CONFIG_ARM=y CONFIG_TARGET_LS1043AQDS=y CONFIG_SYS_NS16550=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig new file mode 100644 index 0000000000..cb076c9d07 --- /dev/null +++ b/configs/ls1043aqds_qspi_defconfig @@ -0,0 +1,9 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT" +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_SYS_NS16550=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 6765d3dc68..0409e33f1b 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -3,3 +3,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" CONFIG_ARM=y CONFIG_TARGET_LS1043AQDS=y CONFIG_SYS_NS16550=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig new file mode 100644 index 0000000000..09fb1ed763 --- /dev/null +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -0,0 +1,10 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1043AQDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart" +CONFIG_SYS_NS16550=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_SPI=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index ed336e6bc4..39c2ad2813 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -1,10 +1,24 @@ CONFIG_MICROBLAZE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_DM=y CONFIG_TARGET_MICROBLAZE_GENERIC=y CONFIG_SYS_TEXT_BASE=0x29000000 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot-mONStR> " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y +CONFIG_NETCONSOLE=y +CONFIG_DM_ETH=y +CONFIG_XILINX_AXIEMAC=y +CONFIG_XILINX_EMACLITE=y +CONFIG_SYS_NS16550=y +CONFIG_XILINX_UARTLITE=y diff --git a/configs/ml507_defconfig b/configs/ml507_defconfig deleted file mode 100644 index d1e4e30371..0000000000 --- a/configs/ml507_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_ML507=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o" -CONFIG_SYS_PROMPT="ml507:/# " -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set diff --git a/configs/ml507_flash_defconfig b/configs/ml507_flash_defconfig deleted file mode 100644 index 442e0ce1fa..0000000000 --- a/configs/ml507_flash_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_ML507=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig new file mode 100644 index 0000000000..169a2ac3dd --- /dev/null +++ b/configs/pic32mzdask_defconfig @@ -0,0 +1,34 @@ +CONFIG_MIPS=y +CONFIG_SYS_MALLOC_F_LEN=0x600 +CONFIG_DM_SERIAL=y +CONFIG_DM_GPIO=y +CONFIG_MACH_PIC32=y +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk" +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="dask # " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_SAVEENV is not set +CONFIG_LOOPW=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_RARP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_DM_MMC=y +CONFIG_PIC32_SDHCI=y +CONFIG_DM_ETH=y +CONFIG_PIC32_ETH=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_FULL is not set +CONFIG_SYS_VSNPRINTF=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 09ced0184a..b5b81caaae 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -77,7 +77,9 @@ CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL=y CONFIG_DM_VIDEO=y -CONFIG_VIDEO_ROTATION=y +CONFIG_CONSOLE_ROTATION=y +CONFIG_CONSOLE_TRUETYPE=y +CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y CONFIG_VIDEO_SANDBOX_SDL=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig new file mode 100644 index 0000000000..fbed23cbbc --- /dev/null +++ b/configs/theadorable_debug_defconfig @@ -0,0 +1,28 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_THEADORABLE=y +CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_VIDEO_MVEBU=y diff --git a/configs/theadorable_defconfig b/configs/theadorable_defconfig new file mode 100644 index 0000000000..cce4669c41 --- /dev/null +++ b/configs/theadorable_defconfig @@ -0,0 +1,26 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_THEADORABLE=y +CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_VIDEO_MVEBU=y +CONFIG_REGEX=y +CONFIG_LIB_RAND=y diff --git a/configs/v5fx30teval_defconfig b/configs/v5fx30teval_defconfig deleted file mode 100644 index 3e2ce7d2fe..0000000000 --- a/configs/v5fx30teval_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_V5FX30TEVAL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o" -CONFIG_SYS_PROMPT="v5fx30t:/# " -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set diff --git a/configs/v5fx30teval_flash_defconfig b/configs/v5fx30teval_flash_defconfig deleted file mode 100644 index b9b05e8b39..0000000000 --- a/configs/v5fx30teval_flash_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_V5FX30TEVAL=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set diff --git a/configs/xilinx-ppc405-generic_defconfig b/configs/xilinx-ppc405-generic_defconfig index 53fafc324e..e7132cd611 100644 --- a/configs/xilinx-ppc405-generic_defconfig +++ b/configs/xilinx-ppc405-generic_defconfig @@ -7,3 +7,11 @@ CONFIG_SYS_PROMPT="xlx-ppc405:/# " # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_SYS_MALLOC_SIMPLE=y +CONFIG_XILINX_UARTLITE=y +CONFIG_SYS_NS16550=y +CONFIG_OF_EMBED=y +CONFIG_OF_CONTROL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic" diff --git a/configs/xilinx-ppc405-generic_flash_defconfig b/configs/xilinx-ppc405-generic_flash_defconfig deleted file mode 100644 index 37084fb0a8..0000000000 --- a/configs/xilinx-ppc405-generic_flash_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_XILINX_PPC405_GENERIC=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set diff --git a/configs/xilinx-ppc440-generic_defconfig b/configs/xilinx-ppc440-generic_defconfig index 79be48a995..3bf2c4f8b8 100644 --- a/configs/xilinx-ppc440-generic_defconfig +++ b/configs/xilinx-ppc440-generic_defconfig @@ -3,7 +3,15 @@ CONFIG_4xx=y CONFIG_TARGET_XILINX_PPC440_GENERIC=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1" CONFIG_SYS_PROMPT="board:/# " -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set +CONFIG_SYS_MALLOC_SIMPLE=y +CONFIG_XILINX_UARTLITE=y +CONFIG_SYS_NS16550=y +CONFIG_OF_EMBED=y +CONFIG_OF_CONTROL=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic" +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_NETCONSOLE=y diff --git a/configs/xilinx-ppc440-generic_flash_defconfig b/configs/xilinx-ppc440-generic_flash_defconfig deleted file mode 100644 index 629903344b..0000000000 --- a/configs/xilinx-ppc440-generic_flash_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_XILINX_PPC440_GENERIC=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 30995babd4..a3a66ec41a 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index 339e399889..fbc603fd95 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_ZYNQ=y CONFIG_TARGET_ZYNQ_PICOZED=y CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed" CONFIG_SPL=y +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 065f855194..3540653e22 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y @@ -12,6 +13,7 @@ CONFIG_CMD_GPIO=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 1059689aad..f333b7a2bf 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y @@ -13,6 +14,7 @@ CONFIG_CMD_GPIO=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index a9dbda5eaa..ebfdeb098b 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y @@ -14,6 +15,7 @@ CONFIG_CMD_GPIO=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index 6ff00c64b4..2bc88b8dd2 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011" +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 75d6c5531c..b0fa661064 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" +CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index dd65929958..9672940e91 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -7,10 +7,13 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_ZYNQ_GEM=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 73b17e20b2..58680127aa 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y @@ -13,6 +14,7 @@ CONFIG_CMD_GPIO=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 577c5a958e..ebaae49da1 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -6,17 +6,18 @@ CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_ZYNQ_GEM=y CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xe0001000 CONFIG_DEBUG_UART_CLOCK=50000000 -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_SPANSION=y CONFIG_ZYNQ_QSPI=y diff --git a/doc/README.distro b/doc/README.distro index 9e4722a86e..3715c8c3ba 100644 --- a/doc/README.distro +++ b/doc/README.distro @@ -341,6 +341,21 @@ scan_dev_for_scripts: If you want to disable boot.scr on all disks, set the value to something innocuous, e.g. setenv scan_dev_for_scripts true. +boot_net_usb_start: + + If you want to prevent USB enumeration by distro boot commands which execute + network operations, set the value to something innocuous, e.g. setenv + boot_net_usb_start true. This would be useful if you know your Ethernet + device is not attached to USB, and you wish to increase boot speed by + avoiding unnecessary actions. + +boot_net_pci_enum: + + If you want to prevent PCI enumeration by distro boot commands which execute + network operations, set the value to something innocuous, e.g. setenv + boot_net_pci_enum true. This would be useful if you know your Ethernet + device is not attached to PCI, and you wish to increase boot speed by + avoiding unnecessary actions. Interactively booting from a specific device at the u-boot prompt ================================================================= diff --git a/doc/README.t1040-l2switch b/doc/README.t1040-l2switch index 14dbf31bf2..6f03de239e 100644 --- a/doc/README.t1040-l2switch +++ b/doc/README.t1040-l2switch @@ -24,16 +24,31 @@ Switch interfaces: Commands Overview: ============= Commands supported - - enable/disable a port - - check a port's link speed, duplexity and status. + - enable/disable a port or show its configuration (speed, duplexity, status, etc.) + - port statistics + - MAC learning + - add/remove FDB entries + - Port-based VLAN + - Private/Shared VLAN learning + - VLAN ingress filtering + - Port LAG Commands syntax - ethsw port <port_nr> enable|disable - enable/disable an l2 switch port - ethsw port <port_nr> show - show an l2 switch port's configuration +ethsw [port <port_no>] { enable | disable | show } - enable/disable a port; show a port's configuration +ethsw [port <port_no>] statistics { [help] | [clear] } - show an l2 switch port's statistics +ethsw [port <port_no>] learning { [help] | show | auto | disable } - enable/disable/show learning configuration on a port +ethsw [port <port_no>] [vlan <vid>] fdb { [help] | show | flush | { add | del } <mac> } - add/delete a mac entry in FDB; use show to see FDB entries; + if [vlan <vid>] is missing, VID 1 will be used +ethsw [port <port_no>] pvid { [help] | show | <pvid> } - set/show PVID (ingress and egress VLAN tagging) for a port +ethsw [port <port_no>] vlan { [help] | show | add <vid> | del <vid> } - add a VLAN to a port (VLAN members) +ethsw [port <port_no>] untagged { [help] | show | all | none | pvid } - set egress tagging mode for a port +ethsw [port <port_no>] egress tag { [help] | show | pvid | classified } - configure VID source for egress tag. + Tag's VID could be the frame's classified VID or the PVID of the port +ethsw vlan fdb { [help] | show | shared | private } - make VLAN learning shared or private +ethsw [port <port_no>] ingress filtering { [help] | show | enable | disable } - enable/disable VLAN ingress filtering on port +ethsw [port <port_no>] aggr { [help] | show | <lag_group_no> } - get/set LAG group for a port - port_nr=0..9; use "all" for all ports - -=> ethsw port all show +=> ethsw show Port Status Link Speed Duplex 0 enabled down 10 half 1 enabled down 10 half diff --git a/doc/README.x86 b/doc/README.x86 index 36aaef011d..6d9cb10edc 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -706,7 +706,7 @@ the board, then you can use post_code() calls from C or assembler to monitor boot progress. This can be good for debugging. If not, you can try to get serial working as early as possible. The early -debug serial port may be useful here. See setup_early_uart() for an example. +debug serial port may be useful here. See setup_internal_uart() for an example. During the U-Boot porting, one of the important steps is to write correct PIRQ routing information in the board device tree. Without it, device drivers in the diff --git a/doc/device-tree-bindings/clock/microchip,pic32-clock.txt b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt new file mode 100644 index 0000000000..f185ce0ae1 --- /dev/null +++ b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt @@ -0,0 +1,33 @@ +* Microchip PIC32 Clock and Oscillator + +Microchip PIC32 clock tree consists of few oscillators, PLLs, +multiplexers and few divider modules capable of supplying clocks +to various controllers within SoC and also to off-chip. + +PIC32 clock controller output is defined by indices as defined +in [0] + +[0] include/dt-bindings/clock/microchip,clock.h + +Required Properties: +- compatible: should be "microchip,pic32mzda_clk" +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. + +Example: Clock controller node: + + clock: clk@1f801200 { + compatible = "microchip,pic32mzda-clk"; + reg = <0x1f801200 0x1000>; + }; + +Example: UART controller node that consumes the clock generated by the clock +controller: + + uart1: serial@1f822000 { + compatible = "microchip,pic32mzda-uart"; + reg = <0xbf822000 0x50>; + interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock PB2CLK>; + }; diff --git a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt index b44b5b5431..07fa46ef7e 100644 --- a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt +++ b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt @@ -74,12 +74,41 @@ discovered by the FSP and used to setup main memory. # Integer properties: - - fsp,dram-speed + - fsp,dram-speed: + 0x0: "800 MHz" + 0x1: "1066 MHz" + 0x2: "1333 MHz" + 0x3: "1600 MHz" + - fsp,dram-type + 0x0: "DDR3" + 0x1: "DDR3L" + 0x2: "DDR3U" + 0x4: "LPDDR2" + 0x5: "LPDDR3" + 0x6: "DDR4" + - fsp,dimm-width + 0x0: "x8" + 0x1: "x16" + 0x2: "x32" + - fsp,dimm-density + 0x0: "1 Gbit" + 0x1: "2 Gbit" + 0x2: "4 Gbit" + 0x3: "8 Gbit" + - fsp,dimm-bus-width + 0x0: "8 bits" + 0x1: "16 bits" + 0x2: "32 bits" + 0x3: "64 bits" + - fsp,dimm-sides + 0x0: "1 rank" + 0x1: "2 ranks" + - fsp,dimm-tcl - fsp,dimm-trpt-rcd - fsp,dimm-twr diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt b/doc/device-tree-bindings/net/fsl-tsec-phy.txt new file mode 100644 index 0000000000..c5bf48c3cb --- /dev/null +++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt @@ -0,0 +1,64 @@ +* TSEC-compatible ethernet nodes + +Properties: + + - compatible : Should be "fsl,tsec" + - reg : Offset and length of the register set for the device + - phy-handle : See ethernet.txt file in the same directory. + - phy-connection-type : See ethernet.txt file in the same directory. This + property is only really needed if the connection is of type "rgmii-id", + "rgmii-rxid" and "rgmii-txid" as all other connection types are detected + by hardware. + +Example: + ethernet@24000 { + compatible = "fsl,tsec"; + reg = <0x24000 0x1000>; + phy-handle = <&phy0>; + phy-connection-type = "sgmii"; + }; + +Child nodes of the TSEC controller are typically the individual PHY devices +connected via the MDIO bus (sometimes the MDIO bus controller is separate). + +* MDIO IO device + +The MDIO is a bus to which the PHY devices are connected. For each +device that exists on this bus, a PHY node should be created. + +Required properties: + - compatible : Should define the compatible device type for the + mdio. Currently supported string/device is "fsl,tsec-mdio". + - reg : Offset and length of the register set for the device + +Example: + + mdio@24520 { + compatible = "fsl,tsec-mdio"; + reg = <0x24520 0x20>; + + ethernet-phy@0 { + reg = <0>; + }; + }; + +* TBI Internal MDIO bus + +As of this writing, every tsec is associated with an internal TBI PHY. +This PHY is accessed through the local MDIO bus. These buses are defined +similarly to the mdio buses. The TBI PHYs underneath them are similar to +normal PHYs, but the reg property is considered instructive, rather than +descriptive. The reg property should be chosen so it doesn't interfere +with other PHYs on the bus. The TBI PHYs are referred to by a "tbi-handle" +property under the tsec node, which has a similar meaning of "phy-handle". + +Example: + ethernet@24000 { + phy-handle = <&tbi1>; + }; + + mdio@24520 { + tbi1: tbi-phy@1f { + reg = <0x1f>; + }; + }; diff --git a/doc/device-tree-bindings/net/micrel-ksz90x1.txt b/doc/device-tree-bindings/net/micrel-ksz90x1.txt new file mode 100644 index 0000000000..307f53f726 --- /dev/null +++ b/doc/device-tree-bindings/net/micrel-ksz90x1.txt @@ -0,0 +1,165 @@ +Micrel KSZ9021/KSZ9031 Gigabit Ethernet PHY + +Some boards require special tuning values, particularly when it comes to +clock delays. You can specify clock delay values by adding +micrel-specific properties to an Ethernet OF device node. + +Note that these settings are applied after any phy-specific fixup from +phy_fixup_list (see phy_init_hw() from drivers/net/phy/phy_device.c), +and therefore may overwrite them. + +KSZ9021: + + All skew control options are specified in picoseconds. The minimum + value is 0, the maximum value is 1800, and it is incremented by 120ps + steps. + + Optional properties: + + - rxc-skew-ps : Skew control of RXC pad + - rxdv-skew-ps : Skew control of RX CTL pad + - txc-skew-ps : Skew control of TXC pad + - txen-skew-ps : Skew control of TX CTL pad + - rxd0-skew-ps : Skew control of RX data 0 pad + - rxd1-skew-ps : Skew control of RX data 1 pad + - rxd2-skew-ps : Skew control of RX data 2 pad + - rxd3-skew-ps : Skew control of RX data 3 pad + - txd0-skew-ps : Skew control of TX data 0 pad + - txd1-skew-ps : Skew control of TX data 1 pad + - txd2-skew-ps : Skew control of TX data 2 pad + - txd3-skew-ps : Skew control of TX data 3 pad + +KSZ9031: + + All skew control options are specified in picoseconds. The minimum + value is 0, and the maximum is property-dependent. The increment + step is 60ps. + + The KSZ9031 hardware supports a range of skew values from negative to + positive, where the specific range is property dependent. All values + specified in the devicetree are offset by the minimum value so they + can be represented as positive integers in the devicetree since it's + difficult to represent a negative number in the devictree. + + The following 5-bit values table apply to rxc-skew-ps and txc-skew-ps. + + Pad Skew Value Delay (ps) Devicetree Value + ------------------------------------------------------ + 0_0000 -900ps 0 + 0_0001 -840ps 60 + 0_0010 -780ps 120 + 0_0011 -720ps 180 + 0_0100 -660ps 240 + 0_0101 -600ps 300 + 0_0110 -540ps 360 + 0_0111 -480ps 420 + 0_1000 -420ps 480 + 0_1001 -360ps 540 + 0_1010 -300ps 600 + 0_1011 -240ps 660 + 0_1100 -180ps 720 + 0_1101 -120ps 780 + 0_1110 -60ps 840 + 0_1111 0ps 900 + 1_0000 60ps 960 + 1_0001 120ps 1020 + 1_0010 180ps 1080 + 1_0011 240ps 1140 + 1_0100 300ps 1200 + 1_0101 360ps 1260 + 1_0110 420ps 1320 + 1_0111 480ps 1380 + 1_1000 540ps 1440 + 1_1001 600ps 1500 + 1_1010 660ps 1560 + 1_1011 720ps 1620 + 1_1100 780ps 1680 + 1_1101 840ps 1740 + 1_1110 900ps 1800 + 1_1111 960ps 1860 + + The following 4-bit values table apply to the txdX-skew-ps, rxdX-skew-ps + data pads, and the rxdv-skew-ps, txen-skew-ps control pads. + + Pad Skew Value Delay (ps) Devicetree Value + ------------------------------------------------------ + 0000 -420ps 0 + 0001 -360ps 60 + 0010 -300ps 120 + 0011 -240ps 180 + 0100 -180ps 240 + 0101 -120ps 300 + 0110 -60ps 360 + 0111 0ps 420 + 1000 60ps 480 + 1001 120ps 540 + 1010 180ps 600 + 1011 240ps 660 + 1100 300ps 720 + 1101 360ps 780 + 1110 420ps 840 + 1111 480ps 900 + + Optional properties: + + Maximum value of 1860: + + - rxc-skew-ps : Skew control of RX clock pad + - txc-skew-ps : Skew control of TX clock pad + + Maximum value of 900: + + - rxdv-skew-ps : Skew control of RX CTL pad + - txen-skew-ps : Skew control of TX CTL pad + - rxd0-skew-ps : Skew control of RX data 0 pad + - rxd1-skew-ps : Skew control of RX data 1 pad + - rxd2-skew-ps : Skew control of RX data 2 pad + - rxd3-skew-ps : Skew control of RX data 3 pad + - txd0-skew-ps : Skew control of TX data 0 pad + - txd1-skew-ps : Skew control of TX data 1 pad + - txd2-skew-ps : Skew control of TX data 2 pad + - txd3-skew-ps : Skew control of TX data 3 pad + +Examples: + + /* Attach to an Ethernet device with autodetected PHY */ + &enet { + rxc-skew-ps = <1800>; + rxdv-skew-ps = <0>; + txc-skew-ps = <1800>; + txen-skew-ps = <0>; + status = "okay"; + }; + + /* Attach to an explicitly-specified PHY */ + mdio { + phy0: ethernet-phy@0 { + rxc-skew-ps = <1800>; + rxdv-skew-ps = <0>; + txc-skew-ps = <1800>; + txen-skew-ps = <0>; + reg = <0>; + }; + }; + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + +References + + Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014. + http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf + + Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014. + http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf + +Notes: + + Note that a previous version of the Micrel ksz9021rl/rn Data Sheet + was missing extended register 106 (transmit data pad skews), and + incorrectly specified the ps per step as 200ps/step instead of + 120ps/step. The latest update to this document reflects the latest + revision of the Micrel specification even though usage in the kernel + still reflects that incorrect document. diff --git a/doc/device-tree-bindings/serial/microchip,pic32-uart.txt b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt new file mode 100644 index 0000000000..f00e215cf6 --- /dev/null +++ b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt @@ -0,0 +1,5 @@ +* Microchip PIC32 serial UART + +Required properties: +- compatible: must be "microchip,pic32mzda-uart". +- reg: exactly one register range. diff --git a/doc/device-tree-bindings/serial/xilinx_uartlite.txt b/doc/device-tree-bindings/serial/xilinx_uartlite.txt new file mode 100644 index 0000000000..d15753c8c3 --- /dev/null +++ b/doc/device-tree-bindings/serial/xilinx_uartlite.txt @@ -0,0 +1,13 @@ +Binding for Xilinx Uartlite Controller + +Required properties: +- compatible : should be "xlnx,xps-uartlite-1.00.a", or "xlnx,opb-uartlite-1.00.b" +- reg: Should contain UART controller registers location and length. +- interrupts: Should contain UART controller interrupts. + +Example: + serial@40600000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + interrupts = <1 0>; + reg = <0x40600000 0x10000>; + }; diff --git a/doc/driver-model/serial-howto.txt b/doc/driver-model/serial-howto.txt index c933b9081b..e5e482e30b 100644 --- a/doc/driver-model/serial-howto.txt +++ b/doc/driver-model/serial-howto.txt @@ -15,7 +15,6 @@ is time for maintainers to start converting over the remaining serial drivers: serial_pxa.c serial_s3c24x0.c serial_sa1100.c - serial_xuartlite.c usbtty.c You should complete this by the end of January 2016. diff --git a/drivers/Makefile b/drivers/Makefile index 6294048f26..e7eab6603e 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -69,4 +69,5 @@ obj-y += soc/ obj-$(CONFIG_REMOTEPROC) += remoteproc/ obj-y += thermal/ +obj-$(CONFIG_MACH_PIC32) += ddr/microchip/ endif diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 8aa81f49f4..c9144e3e1d 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_CLK) += clk-uclass.o clk_fixed_rate.o obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o +obj-$(CONFIG_MACH_PIC32) += clk_pic32.o diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c new file mode 100644 index 0000000000..5d883544d5 --- /dev/null +++ b/drivers/clk/clk_pic32.c @@ -0,0 +1,433 @@ +/* + * Copyright (C) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <div64.h> +#include <wait_bit.h> +#include <dm/lists.h> +#include <asm/io.h> +#include <mach/pic32.h> +#include <dt-bindings/clock/microchip,clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Primary oscillator */ +#define SYS_POSC_CLK_HZ 24000000 + +/* FRC clk rate */ +#define SYS_FRC_CLK_HZ 8000000 + +/* Clock Registers */ +#define OSCCON 0x0000 +#define OSCTUNE 0x0010 +#define SPLLCON 0x0020 +#define REFO1CON 0x0080 +#define REFO1TRIM 0x0090 +#define PB1DIV 0x0140 + +/* SPLL */ +#define ICLK_MASK 0x00000080 +#define PLLIDIV_MASK 0x00000007 +#define PLLODIV_MASK 0x00000007 +#define CUROSC_MASK 0x00000007 +#define PLLMUL_MASK 0x0000007F +#define FRCDIV_MASK 0x00000007 + +/* PBCLK */ +#define PBDIV_MASK 0x00000007 + +/* SYSCLK MUX */ +#define SCLK_SRC_FRC1 0 +#define SCLK_SRC_SPLL 1 +#define SCLK_SRC_POSC 2 +#define SCLK_SRC_FRC2 7 + +/* Reference Oscillator Control Reg fields */ +#define REFO_SEL_MASK 0x0f +#define REFO_SEL_SHIFT 0 +#define REFO_ACTIVE BIT(8) +#define REFO_DIVSW_EN BIT(9) +#define REFO_OE BIT(12) +#define REFO_ON BIT(15) +#define REFO_DIV_SHIFT 16 +#define REFO_DIV_MASK 0x7fff + +/* Reference Oscillator Trim Register Fields */ +#define REFO_TRIM_REG 0x10 +#define REFO_TRIM_MASK 0x1ff +#define REFO_TRIM_SHIFT 23 +#define REFO_TRIM_MAX 511 + +#define ROCLK_SRC_SCLK 0x0 +#define ROCLK_SRC_SPLL 0x7 +#define ROCLK_SRC_ROCLKI 0x8 + +/* Memory PLL */ +#define MPLL_IDIV 0x3f +#define MPLL_MULT 0xff +#define MPLL_ODIV1 0x7 +#define MPLL_ODIV2 0x7 +#define MPLL_VREG_RDY BIT(23) +#define MPLL_RDY BIT(31) +#define MPLL_IDIV_SHIFT 0 +#define MPLL_MULT_SHIFT 8 +#define MPLL_ODIV1_SHIFT 24 +#define MPLL_ODIV2_SHIFT 27 +#define MPLL_IDIV_INIT 0x03 +#define MPLL_MULT_INIT 0x32 +#define MPLL_ODIV1_INIT 0x02 +#define MPLL_ODIV2_INIT 0x01 + +struct pic32_clk_priv { + void __iomem *iobase; + void __iomem *syscfg_base; +}; + +static ulong pic32_get_pll_rate(struct pic32_clk_priv *priv) +{ + u32 iclk, idiv, odiv, mult; + ulong plliclk, v; + + v = readl(priv->iobase + SPLLCON); + iclk = (v & ICLK_MASK); + idiv = ((v >> 8) & PLLIDIV_MASK) + 1; + odiv = ((v >> 24) & PLLODIV_MASK); + mult = ((v >> 16) & PLLMUL_MASK) + 1; + + plliclk = iclk ? SYS_FRC_CLK_HZ : SYS_POSC_CLK_HZ; + + if (odiv < 2) + odiv = 2; + else if (odiv < 5) + odiv = (1 << odiv); + else + odiv = 32; + + return ((plliclk / idiv) * mult) / odiv; +} + +static ulong pic32_get_sysclk(struct pic32_clk_priv *priv) +{ + ulong v; + ulong hz; + ulong div, frcdiv; + ulong curr_osc; + + /* get clk source */ + v = readl(priv->iobase + OSCCON); + curr_osc = (v >> 12) & CUROSC_MASK; + switch (curr_osc) { + case SCLK_SRC_FRC1: + case SCLK_SRC_FRC2: + frcdiv = ((v >> 24) & FRCDIV_MASK); + div = ((1 << frcdiv) + 1) + (128 * (frcdiv == 7)); + hz = SYS_FRC_CLK_HZ / div; + break; + + case SCLK_SRC_SPLL: + hz = pic32_get_pll_rate(priv); + break; + + case SCLK_SRC_POSC: + hz = SYS_POSC_CLK_HZ; + break; + + default: + hz = 0; + printf("clk: unknown sclk_src.\n"); + break; + } + + return hz; +} + +static ulong pic32_get_pbclk(struct pic32_clk_priv *priv, int periph) +{ + void __iomem *reg; + ulong div, clk_freq; + + WARN_ON((periph < PB1CLK) || (periph > PB7CLK)); + + clk_freq = pic32_get_sysclk(priv); + + reg = priv->iobase + PB1DIV + (periph - PB1CLK) * 0x10; + div = (readl(reg) & PBDIV_MASK) + 1; + + return clk_freq / div; +} + +static ulong pic32_get_cpuclk(struct pic32_clk_priv *priv) +{ + return pic32_get_pbclk(priv, PB7CLK); +} + +static ulong pic32_set_refclk(struct pic32_clk_priv *priv, int periph, + int parent_rate, int rate, int parent_id) +{ + void __iomem *reg; + u32 div, trim, v; + u64 frac; + + WARN_ON((periph < REF1CLK) || (periph > REF5CLK)); + + /* calculate dividers, + * rate = parent_rate / [2 * (div + (trim / 512))] + */ + if (parent_rate <= rate) { + div = 0; + trim = 0; + } else { + div = parent_rate / (rate << 1); + frac = parent_rate; + frac <<= 8; + do_div(frac, rate); + frac -= (u64)(div << 9); + trim = (frac >= REFO_TRIM_MAX) ? REFO_TRIM_MAX : (u32)frac; + } + + reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20; + + /* disable clk */ + writel(REFO_ON | REFO_OE, reg + _CLR_OFFSET); + + /* wait till previous src change is active */ + wait_for_bit(__func__, reg, REFO_DIVSW_EN | REFO_ACTIVE, + false, CONFIG_SYS_HZ, false); + + /* parent_id */ + v = readl(reg); + v &= ~(REFO_SEL_MASK << REFO_SEL_SHIFT); + v |= (parent_id << REFO_SEL_SHIFT); + + /* apply rodiv */ + v &= ~(REFO_DIV_MASK << REFO_DIV_SHIFT); + v |= (div << REFO_DIV_SHIFT); + writel(v, reg); + + /* apply trim */ + v = readl(reg + REFO_TRIM_REG); + v &= ~(REFO_TRIM_MASK << REFO_TRIM_SHIFT); + v |= (trim << REFO_TRIM_SHIFT); + writel(v, reg + REFO_TRIM_REG); + + /* enable clk */ + writel(REFO_ON | REFO_OE, reg + _SET_OFFSET); + + /* switch divider */ + writel(REFO_DIVSW_EN, reg + _SET_OFFSET); + + /* wait for divider switching to complete */ + return wait_for_bit(__func__, reg, REFO_DIVSW_EN, false, + CONFIG_SYS_HZ, false); +} + +static ulong pic32_get_refclk(struct pic32_clk_priv *priv, int periph) +{ + u32 rodiv, rotrim, rosel, v, parent_rate; + void __iomem *reg; + u64 rate64; + + WARN_ON((periph < REF1CLK) || (periph > REF5CLK)); + + reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20; + v = readl(reg); + /* get rosel */ + rosel = (v >> REFO_SEL_SHIFT) & REFO_SEL_MASK; + /* get div */ + rodiv = (v >> REFO_DIV_SHIFT) & REFO_DIV_MASK; + + /* get trim */ + v = readl(reg + REFO_TRIM_REG); + rotrim = (v >> REFO_TRIM_SHIFT) & REFO_TRIM_MASK; + + if (!rodiv) + return 0; + + /* get parent rate */ + switch (rosel) { + case ROCLK_SRC_SCLK: + parent_rate = pic32_get_cpuclk(priv); + break; + case ROCLK_SRC_SPLL: + parent_rate = pic32_get_pll_rate(priv); + break; + default: + parent_rate = 0; + break; + } + + /* Calculation + * rate = parent_rate / [2 * (div + (trim / 512))] + */ + if (rotrim) { + rodiv <<= 9; + rodiv += rotrim; + rate64 = parent_rate; + rate64 <<= 8; + do_div(rate64, rodiv); + v = (u32)rate64; + } else { + v = parent_rate / (rodiv << 1); + } + return v; +} + +static ulong pic32_get_mpll_rate(struct pic32_clk_priv *priv) +{ + u32 v, idiv, mul; + u32 odiv1, odiv2; + u64 rate; + + v = readl(priv->syscfg_base + CFGMPLL); + idiv = v & MPLL_IDIV; + mul = (v >> MPLL_MULT_SHIFT) & MPLL_MULT; + odiv1 = (v >> MPLL_ODIV1_SHIFT) & MPLL_ODIV1; + odiv2 = (v >> MPLL_ODIV2_SHIFT) & MPLL_ODIV2; + + rate = (SYS_POSC_CLK_HZ / idiv) * mul; + do_div(rate, odiv1); + do_div(rate, odiv2); + + return (ulong)rate; +} + +static int pic32_mpll_init(struct pic32_clk_priv *priv) +{ + u32 v, mask; + + /* initialize */ + v = (MPLL_IDIV_INIT << MPLL_IDIV_SHIFT) | + (MPLL_MULT_INIT << MPLL_MULT_SHIFT) | + (MPLL_ODIV1_INIT << MPLL_ODIV1_SHIFT) | + (MPLL_ODIV2_INIT << MPLL_ODIV2_SHIFT); + + writel(v, priv->syscfg_base + CFGMPLL); + + /* Wait for ready */ + mask = MPLL_RDY | MPLL_VREG_RDY; + return wait_for_bit(__func__, priv->syscfg_base + CFGMPLL, mask, + true, get_tbclk(), false); +} + +static void pic32_clk_init(struct udevice *dev) +{ + const void *blob = gd->fdt_blob; + struct pic32_clk_priv *priv; + ulong rate, pll_hz; + char propname[50]; + int i; + + priv = dev_get_priv(dev); + pll_hz = pic32_get_pll_rate(priv); + + /* Initialize REFOs as not initialized and enabled on reset. */ + for (i = REF1CLK; i <= REF5CLK; i++) { + snprintf(propname, sizeof(propname), + "microchip,refo%d-frequency", i - REF1CLK + 1); + rate = fdtdec_get_int(blob, dev->of_offset, propname, 0); + if (rate) + pic32_set_refclk(priv, i, pll_hz, rate, ROCLK_SRC_SPLL); + } + + /* Memory PLL */ + pic32_mpll_init(priv); +} + +static ulong pic32_clk_get_rate(struct udevice *dev) +{ + struct pic32_clk_priv *priv = dev_get_priv(dev); + + return pic32_get_cpuclk(priv); +} + +static ulong pic32_get_periph_rate(struct udevice *dev, int periph) +{ + struct pic32_clk_priv *priv = dev_get_priv(dev); + ulong rate; + + switch (periph) { + case PB1CLK ... PB7CLK: + rate = pic32_get_pbclk(priv, periph); + break; + case REF1CLK ... REF5CLK: + rate = pic32_get_refclk(priv, periph); + break; + case PLLCLK: + rate = pic32_get_pll_rate(priv); + break; + case MPLL: + rate = pic32_get_mpll_rate(priv); + break; + default: + rate = 0; + break; + } + + return rate; +} + +static ulong pic32_set_periph_rate(struct udevice *dev, int periph, ulong rate) +{ + struct pic32_clk_priv *priv = dev_get_priv(dev); + ulong pll_hz; + + switch (periph) { + case REF1CLK ... REF5CLK: + pll_hz = pic32_get_pll_rate(priv); + pic32_set_refclk(priv, periph, pll_hz, rate, ROCLK_SRC_SPLL); + break; + default: + break; + } + + return rate; +} + +static struct clk_ops pic32_pic32_clk_ops = { + .get_rate = pic32_clk_get_rate, + .set_periph_rate = pic32_set_periph_rate, + .get_periph_rate = pic32_get_periph_rate, +}; + +static int pic32_clk_probe(struct udevice *dev) +{ + struct pic32_clk_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->iobase = ioremap(addr, size); + if (!priv->iobase) + return -EINVAL; + + priv->syscfg_base = pic32_get_syscfg_base(); + + /* initialize clocks */ + pic32_clk_init(dev); + + return 0; +} + +static const struct udevice_id pic32_clk_ids[] = { + { .compatible = "microchip,pic32mzda-clk"}, + {} +}; + +U_BOOT_DRIVER(pic32_clk) = { + .name = "pic32_clk", + .id = UCLASS_CLK, + .of_match = pic32_clk_ids, + .flags = DM_FLAG_PRE_RELOC, + .ops = &pic32_pic32_clk_ops, + .probe = pic32_clk_probe, + .priv_auto_alloc_size = sizeof(struct pic32_clk_priv), +}; diff --git a/drivers/core/device.c b/drivers/core/device.c index f5def35b5b..cb24a617ce 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -223,7 +223,7 @@ static void *alloc_priv(int size, uint flags) return priv; } -int device_probe_child(struct udevice *dev, void *parent_priv) +int device_probe(struct udevice *dev) { const struct driver *drv; int size = 0; @@ -270,8 +270,6 @@ int device_probe_child(struct udevice *dev, void *parent_priv) ret = -ENOMEM; goto fail; } - if (parent_priv) - memcpy(dev->parent_priv, parent_priv, size); } ret = device_probe(dev->parent); @@ -349,11 +347,6 @@ fail: return ret; } -int device_probe(struct udevice *dev) -{ - return device_probe_child(dev, NULL); -} - void *dev_get_platdata(struct udevice *dev) { if (!dev) { diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 3fca5c2684..6f76980d31 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -55,6 +55,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */ u32 *vref_seq = vref_seq1; #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + ulong ddr_freq; + u32 tmp; +#endif #ifdef CONFIG_FSL_DDR_BIST u32 mtcr, err_detect, err_sbe; u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config; @@ -151,7 +155,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 + ddr_out32(&ddr->sdram_interval, + regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE); +#else ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); +#endif ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); #ifndef CONFIG_SYS_FSL_DDR_EMU @@ -227,6 +236,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->debug[25], 0x9000); } #endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + ddr_freq = get_ddr_freq(ctrl_num) / 1000000; + tmp = ddr_in32(&ddr->debug[28]); + if (ddr_freq <= 1333) + ddr_out32(&ddr->debug[28], tmp | 0x0080006a); + else if (ddr_freq <= 1600) + ddr_out32(&ddr->debug[28], tmp | 0x0070006f); + else if (ddr_freq <= 1867) + ddr_out32(&ddr->debug[28], tmp | 0x00700076); + else if (ddr_freq <= 2133) + ddr_out32(&ddr->debug[28], tmp | 0x0060007b); +#endif + /* * For RDIMMs, JEDEC spec requires clocks to be stable before reset is * deasserted. Clocks start when any chip select is enabled and clock @@ -379,6 +402,11 @@ step2: if (timeout <= 0) printf("Waiting for D_INIT timeout. Memory may not work.\n"); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 + ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); +#endif + #ifdef CONFIG_DEEP_SLEEP if (is_warm_boot()) { /* exit self-refresh */ diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 139a3a7f5a..479184f4ed 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -857,6 +857,7 @@ fsl_ddr_sdram_size(void) info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS; info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR; info.board_need_mem_reset = NULL; + remove_unused_controllers(&info); /* Compute it once normally. */ total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); diff --git a/drivers/ddr/microchip/Makefile b/drivers/ddr/microchip/Makefile new file mode 100644 index 0000000000..305c48b164 --- /dev/null +++ b/drivers/ddr/microchip/Makefile @@ -0,0 +1,6 @@ +# +# Copyright (C) 2015 Microchip Technology Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-$(CONFIG_MACH_PIC32) += ddr2.o diff --git a/drivers/ddr/microchip/ddr2.c b/drivers/ddr/microchip/ddr2.c new file mode 100644 index 0000000000..6056418588 --- /dev/null +++ b/drivers/ddr/microchip/ddr2.c @@ -0,0 +1,278 @@ +/* + * (c) 2015 Paul Thacker <paul.thacker@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#include <common.h> +#include <wait_bit.h> +#include <linux/kernel.h> +#include <linux/bitops.h> +#include <mach/pic32.h> +#include <mach/ddr.h> + +#include "ddr2_regs.h" +#include "ddr2_timing.h" + +/* init DDR2 Phy */ +void ddr2_phy_init(void) +{ + struct ddr2_phy_regs *ddr2_phy; + u32 pad_ctl; + + ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy)); + + /* PHY_DLL_RECALIB */ + writel(DELAY_START_VAL(3) | DISABLE_RECALIB(0) | + RECALIB_CNT(0x10), &ddr2_phy->dll_recalib); + + /* PHY_PAD_CTRL */ + pad_ctl = ODT_SEL | ODT_EN | DRIVE_SEL(0) | + ODT_PULLDOWN(2) | ODT_PULLUP(3) | + EXTRA_OEN_CLK(0) | NOEXT_DLL | + DLR_DFT_WRCMD | HALF_RATE | + DRVSTR_PFET(0xe) | DRVSTR_NFET(0xe) | + RCVR_EN | PREAMBLE_DLY(2); + writel(pad_ctl, &ddr2_phy->pad_ctrl); + + /* SCL_CONFIG_0 */ + writel(SCL_BURST8 | SCL_DDR_CONNECTED | SCL_RCAS_LAT(RL) | + SCL_ODTCSWW, &ddr2_phy->scl_config_1); + + /* SCL_CONFIG_1 */ + writel(SCL_CSEN | SCL_WCAS_LAT(WL), &ddr2_phy->scl_config_2); + + /* SCL_LAT */ + writel(SCL_CAPCLKDLY(3) | SCL_DDRCLKDLY(4), &ddr2_phy->scl_latency); +} + +/* start phy self calibration logic */ +static int ddr2_phy_calib_start(void) +{ + struct ddr2_phy_regs *ddr2_phy; + + ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy)); + + /* DDR Phy SCL Start */ + writel(SCL_START | SCL_EN, &ddr2_phy->scl_start); + + /* Wait for SCL for data byte to pass */ + return wait_for_bit(__func__, &ddr2_phy->scl_start, SCL_LUBPASS, + true, CONFIG_SYS_HZ, false); +} + +/* DDR2 Controller initialization */ + +/* Target Agent Arbiter */ +static void ddr_set_arbiter(struct ddr2_ctrl_regs *ctrl, + const struct ddr2_arbiter_params *const param) +{ + int i; + + for (i = 0; i < NUM_AGENTS; i++) { + /* set min burst size */ + writel(i * MIN_LIM_WIDTH, &ctrl->tsel); + writel(param->min_limit, &ctrl->minlim); + + /* set request period (4 * req_period clocks) */ + writel(i * RQST_PERIOD_WIDTH, &ctrl->tsel); + writel(param->req_period, &ctrl->reqprd); + + /* set number of burst accepted */ + writel(i * MIN_CMDACPT_WIDTH, &ctrl->tsel); + writel(param->min_cmd_acpt, &ctrl->mincmd); + } +} + +const struct ddr2_arbiter_params *__weak board_get_ddr_arbiter_params(void) +{ + /* default arbiter parameters */ + static const struct ddr2_arbiter_params arb_params[] = { + { .min_limit = 0x1f, .req_period = 0xff, .min_cmd_acpt = 0x04,}, + { .min_limit = 0x1f, .req_period = 0xff, .min_cmd_acpt = 0x10,}, + { .min_limit = 0x1f, .req_period = 0xff, .min_cmd_acpt = 0x10,}, + { .min_limit = 0x04, .req_period = 0xff, .min_cmd_acpt = 0x04,}, + { .min_limit = 0x04, .req_period = 0xff, .min_cmd_acpt = 0x04,}, + }; + + return &arb_params[0]; +} + +static void host_load_cmd(struct ddr2_ctrl_regs *ctrl, u32 cmd_idx, + u32 hostcmd2, u32 hostcmd1, u32 delay) +{ + u32 hc_delay; + + hc_delay = max_t(u32, DIV_ROUND_UP(delay, T_CK), 2) - 2; + writel(hostcmd1, &ctrl->cmd10[cmd_idx]); + writel((hostcmd2 & 0x7ff) | (hc_delay << 11), &ctrl->cmd20[cmd_idx]); +} + +/* init DDR2 Controller */ +void ddr2_ctrl_init(void) +{ + u32 wr2prech, rd2prech, wr2rd, wr2rd_cs; + u32 ras2ras, ras2cas, prech2ras, temp; + const struct ddr2_arbiter_params *arb_params; + struct ddr2_ctrl_regs *ctrl; + + ctrl = ioremap(PIC32_DDR2C_BASE, sizeof(*ctrl)); + + /* PIC32 DDR2 controller always work in HALF_RATE */ + writel(HALF_RATE_MODE, &ctrl->memwidth); + + /* Set arbiter configuration per target */ + arb_params = board_get_ddr_arbiter_params(); + ddr_set_arbiter(ctrl, arb_params); + + /* Address Configuration, model {CS, ROW, BA, COL} */ + writel((ROW_ADDR_RSHIFT | (BA_RSHFT << 8) | (CS_ADDR_RSHIFT << 16) | + (COL_HI_RSHFT << 24) | (SB_PRI << 29) | + (EN_AUTO_PRECH << 30)), &ctrl->memcfg0); + + writel(ROW_ADDR_MASK, &ctrl->memcfg1); + writel(COL_HI_MASK, &ctrl->memcfg2); + writel(COL_LO_MASK, &ctrl->memcfg3); + writel(BA_MASK | (CS_ADDR_MASK << 8), &ctrl->memcfg4); + + /* Refresh Config */ + writel(REFCNT_CLK(DIV_ROUND_UP(T_RFI, T_CK_CTRL) - 2) | + REFDLY_CLK(DIV_ROUND_UP(T_RFC_MIN, T_CK_CTRL) - 2) | + MAX_PEND_REF(7), + &ctrl->refcfg); + + /* Power Config */ + writel(ECC_EN(0) | ERR_CORR_EN(0) | EN_AUTO_PWR_DN(0) | + EN_AUTO_SELF_REF(3) | PWR_DN_DLY(8) | + SELF_REF_DLY(17) | PRECH_PWR_DN_ONLY(0), + &ctrl->pwrcfg); + + /* Delay Config */ + wr2rd = max_t(u32, DIV_ROUND_UP(T_WTR, T_CK_CTRL), + DIV_ROUND_UP(T_WTR_TCK, 2)) + WL + BL; + wr2rd_cs = max_t(u32, wr2rd - 1, 3); + wr2prech = DIV_ROUND_UP(T_WR, T_CK_CTRL) + WL + BL; + rd2prech = max_t(u32, DIV_ROUND_UP(T_RTP, T_CK_CTRL), + DIV_ROUND_UP(T_RTP_TCK, 2)) + BL - 2; + ras2ras = max_t(u32, DIV_ROUND_UP(T_RRD, T_CK_CTRL), + DIV_ROUND_UP(T_RRD_TCK, 2)) - 1; + ras2cas = DIV_ROUND_UP(T_RCD, T_CK_CTRL) - 1; + prech2ras = DIV_ROUND_UP(T_RP, T_CK_CTRL) - 1; + + writel(((wr2rd & 0x0f) | + ((wr2rd_cs & 0x0f) << 4) | + ((BL - 1) << 8) | + (BL << 12) | + ((BL - 1) << 16) | + ((BL - 1) << 20) | + ((BL + 2) << 24) | + ((RL - WL + 3) << 28)), &ctrl->dlycfg0); + + writel(((T_CKE_TCK - 1) | + (((DIV_ROUND_UP(T_DLLK, 2) - 2) & 0xff) << 8) | + ((T_CKE_TCK - 1) << 16) | + ((max_t(u32, T_XP_TCK, T_CKE_TCK) - 1) << 20) | + ((wr2prech >> 4) << 26) | + ((wr2rd >> 4) << 27) | + ((wr2rd_cs >> 4) << 28) | + (((RL + 5) >> 4) << 29) | + ((DIV_ROUND_UP(T_DLLK, 2) >> 8) << 30)), &ctrl->dlycfg1); + + writel((DIV_ROUND_UP(T_RP, T_CK_CTRL) | + (rd2prech << 8) | + ((wr2prech & 0x0f) << 12) | + (ras2ras << 16) | + (ras2cas << 20) | + (prech2ras << 24) | + ((RL + 3) << 28)), &ctrl->dlycfg2); + + writel(((DIV_ROUND_UP(T_RAS_MIN, T_CK_CTRL) - 1) | + ((DIV_ROUND_UP(T_RC, T_CK_CTRL) - 1) << 8) | + ((DIV_ROUND_UP(T_FAW, T_CK_CTRL) - 1) << 16)), + &ctrl->dlycfg3); + + /* ODT Config */ + writel(0x0, &ctrl->odtcfg); + writel(BIT(16), &ctrl->odtencfg); + writel(ODTRDLY(RL - 3) | ODTWDLY(WL - 3) | ODTRLEN(2) | ODTWLEN(3), + &ctrl->odtcfg); + + /* Transfer Configuration */ + writel(NXTDATRQDLY(2) | NXDATAVDLY(4) | RDATENDLY(2) | + MAX_BURST(3) | (7 << 28) | BIG_ENDIAN(0), + &ctrl->xfercfg); + + /* DRAM Initialization */ + /* CKE high after reset and wait 400 nsec */ + host_load_cmd(ctrl, 0, 0, IDLE_NOP, 400000); + + /* issue precharge all command */ + host_load_cmd(ctrl, 1, 0x04, PRECH_ALL_CMD, T_RP + T_CK); + + /* initialize EMR2 */ + host_load_cmd(ctrl, 2, 0x200, LOAD_MODE_CMD, T_MRD_TCK * T_CK); + + /* initialize EMR3 */ + host_load_cmd(ctrl, 3, 0x300, LOAD_MODE_CMD, T_MRD_TCK * T_CK); + + /* + * RDQS disable, DQSB enable, OCD exit, 150 ohm termination, + * AL=0, DLL enable + */ + host_load_cmd(ctrl, 4, 0x100, + LOAD_MODE_CMD | (0x40 << 24), T_MRD_TCK * T_CK); + /* + * PD fast exit, WR REC = T_WR in clocks -1, + * DLL reset, CAS = RL, burst = 4 + */ + temp = ((DIV_ROUND_UP(T_WR, T_CK) - 1) << 1) | 1; + host_load_cmd(ctrl, 5, temp, LOAD_MODE_CMD | (RL << 28) | (2 << 24), + T_MRD_TCK * T_CK); + + /* issue precharge all command */ + host_load_cmd(ctrl, 6, 4, PRECH_ALL_CMD, T_RP + T_CK); + + /* issue refresh command */ + host_load_cmd(ctrl, 7, 0, REF_CMD, T_RFC_MIN); + + /* issue refresh command */ + host_load_cmd(ctrl, 8, 0, REF_CMD, T_RFC_MIN); + + /* Mode register programming as before without DLL reset */ + host_load_cmd(ctrl, 9, temp, LOAD_MODE_CMD | (RL << 28) | (3 << 24), + T_MRD_TCK * T_CK); + + /* extended mode register same as before with OCD default */ + host_load_cmd(ctrl, 10, 0x103, LOAD_MODE_CMD | (0xc << 24), + T_MRD_TCK * T_CK); + + /* extended mode register same as before with OCD exit */ + host_load_cmd(ctrl, 11, 0x100, LOAD_MODE_CMD | (0x4 << 28), + 140 * T_CK); + + writel(CMD_VALID | NUMHOSTCMD(11), &ctrl->cmdissue); + + /* start memory initialization */ + writel(INIT_START, &ctrl->memcon); + + /* wait for all host cmds to be transmitted */ + wait_for_bit(__func__, &ctrl->cmdissue, CMD_VALID, false, + CONFIG_SYS_HZ, false); + + /* inform all cmds issued, ready for normal operation */ + writel(INIT_START | INIT_DONE, &ctrl->memcon); + + /* perform phy caliberation */ + if (ddr2_phy_calib_start()) + printf("ddr2: phy calib failed\n"); +} + +phys_size_t ddr2_calculate_size(void) +{ + u32 temp; + + temp = 1 << (COL_BITS + BA_BITS + ROW_BITS); + /* 16-bit data width between controller and DIMM */ + temp = temp * CS_BITS * (16 / 8); + return (phys_size_t)temp; +} diff --git a/drivers/ddr/microchip/ddr2_regs.h b/drivers/ddr/microchip/ddr2_regs.h new file mode 100644 index 0000000000..0f4b159048 --- /dev/null +++ b/drivers/ddr/microchip/ddr2_regs.h @@ -0,0 +1,148 @@ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __MICROCHIP_DDR2_REGS_H +#define __MICROCHIP_DDR2_REGS_H + +#include <linux/bitops.h> + +/* DDR2 Controller */ +struct ddr2_ctrl_regs { + u32 tsel; + u32 minlim; + u32 reqprd; + u32 mincmd; + u32 memcon; + u32 memcfg0; + u32 memcfg1; + u32 memcfg2; + u32 memcfg3; + u32 memcfg4; + u32 refcfg; + u32 pwrcfg; + u32 dlycfg0; + u32 dlycfg1; + u32 dlycfg2; + u32 dlycfg3; + u32 odtcfg; + u32 xfercfg; + u32 cmdissue; + u32 odtencfg; + u32 memwidth; + u32 unused[11]; + u32 cmd10[16]; + u32 cmd20[16]; +}; + +/* Arbiter Config */ +#define MIN_LIM_WIDTH 5 +#define RQST_PERIOD_WIDTH 8 +#define MIN_CMDACPT_WIDTH 8 + +/* Refresh Config */ +#define REFCNT_CLK(x) (x) +#define REFDLY_CLK(x) ((x) << 16) +#define MAX_PEND_REF(x) ((x) << 24) + +/* Power Config */ +#define PRECH_PWR_DN_ONLY(x) ((x) << 22) +#define SELF_REF_DLY(x) ((x) << 12) +#define PWR_DN_DLY(x) ((x) << 4) +#define EN_AUTO_SELF_REF(x) ((x) << 3) +#define EN_AUTO_PWR_DN(x) ((x) << 2) +#define ERR_CORR_EN(x) ((x) << 1) +#define ECC_EN(x) (x) + +/* Memory Width */ +#define HALF_RATE_MODE BIT(3) + +/* Delay Config */ +#define ODTWLEN(x) ((x) << 20) +#define ODTRLEN(x) ((x) << 16) +#define ODTWDLY(x) ((x) << 12) +#define ODTRDLY(x) ((x) << 8) + +/* Xfer Config */ +#define BIG_ENDIAN(x) ((x) << 31) +#define MAX_BURST(x) ((x) << 24) +#define RDATENDLY(x) ((x) << 16) +#define NXDATAVDLY(x) ((x) << 4) +#define NXTDATRQDLY(x) ((x) << 0) + +/* Host Commands */ +#define IDLE_NOP 0x00ffffff +#define PRECH_ALL_CMD 0x00fff401 +#define REF_CMD 0x00fff801 +#define LOAD_MODE_CMD 0x00fff001 +#define CKE_LOW 0x00ffeffe + +#define NUM_HOST_CMDS 12 + +/* Host CMD Issue */ +#define CMD_VALID BIT(4) +#define NUMHOSTCMD(x) (x) + +/* Memory Control */ +#define INIT_DONE BIT(1) +#define INIT_START BIT(0) + +/* Address Control */ +#define EN_AUTO_PRECH 0 +#define SB_PRI 1 + +/* DDR2 Phy Register */ +struct ddr2_phy_regs { + u32 scl_start; + u32 unused1[2]; + u32 scl_latency; + u32 unused2[2]; + u32 scl_config_1; + u32 scl_config_2; + u32 pad_ctrl; + u32 dll_recalib; +}; + +/* PHY PAD CONTROL */ +#define ODT_SEL BIT(0) +#define ODT_EN BIT(1) +#define DRIVE_SEL(x) ((x) << 2) +#define ODT_PULLDOWN(x) ((x) << 4) +#define ODT_PULLUP(x) ((x) << 6) +#define EXTRA_OEN_CLK(x) ((x) << 8) +#define NOEXT_DLL BIT(9) +#define DLR_DFT_WRCMD BIT(13) +#define HALF_RATE BIT(14) +#define DRVSTR_PFET(x) ((x) << 16) +#define DRVSTR_NFET(x) ((x) << 20) +#define RCVR_EN BIT(28) +#define PREAMBLE_DLY(x) ((x) << 29) + +/* PHY DLL RECALIBRATE */ +#define RECALIB_CNT(x) ((x) << 8) +#define DISABLE_RECALIB(x) ((x) << 26) +#define DELAY_START_VAL(x) ((x) << 28) + +/* PHY SCL CONFIG1 */ +#define SCL_BURST8 BIT(0) +#define SCL_DDR_CONNECTED BIT(1) +#define SCL_RCAS_LAT(x) ((x) << 4) +#define SCL_ODTCSWW BIT(24) + +/* PHY SCL CONFIG2 */ +#define SCL_CSEN BIT(0) +#define SCL_WCAS_LAT(x) ((x) << 8) + +/* PHY SCL Latency */ +#define SCL_CAPCLKDLY(x) ((x) << 0) +#define SCL_DDRCLKDLY(x) ((x) << 4) + +/* PHY SCL START */ +#define SCL_START BIT(28) +#define SCL_EN BIT(26) +#define SCL_LUBPASS (BIT(1) | BIT(0)) + +#endif /* __MICROCHIP_DDR2_REGS_H */ diff --git a/drivers/ddr/microchip/ddr2_timing.h b/drivers/ddr/microchip/ddr2_timing.h new file mode 100644 index 0000000000..5895f9d592 --- /dev/null +++ b/drivers/ddr/microchip/ddr2_timing.h @@ -0,0 +1,65 @@ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __MICROCHIP_DDR2_TIMING_H +#define __MICROCHIP_DDR2_TIMING_H + +/* MPLL freq is 400MHz */ +#define T_CK 2500 /* 2500 psec */ +#define T_CK_CTRL (T_CK * 2) + +/* Burst length in cycles */ +#define BL 2 +/* default CAS latency for all speed grades */ +#define RL 5 +/* default write latency for all speed grades = CL-1 */ +#define WL 4 + +/* From Micron MT47H64M16HR-3 data sheet */ +#define T_RFC_MIN 127500 /* psec */ +#define T_WR 15000 /* psec */ +#define T_RP 12500 /* psec */ +#define T_RCD 12500 /* psec */ +#define T_RRD 7500 /* psec */ +/* T_RRD_TCK is minimum of 2 clk periods, regardless of freq */ +#define T_RRD_TCK 2 +#define T_WTR 7500 /* psec */ +/* T_WTR_TCK is minimum of 2 clk periods, regardless of freq */ +#define T_WTR_TCK 2 +#define T_RTP 7500 /* psec */ +#define T_RTP_TCK (BL / 2) +#define T_XP_TCK 2 /* clocks */ +#define T_CKE_TCK 3 /* clocks */ +#define T_XSNR (T_RFC_MIN + 10000) /* psec */ +#define T_DLLK 200 /* clocks */ +#define T_RAS_MIN 45000 /* psec */ +#define T_RC 57500 /* psec */ +#define T_FAW 35000 /* psec */ +#define T_MRD_TCK 2 /* clocks */ +#define T_RFI 7800000 /* psec */ + +/* DDR Addressing */ +#define COL_BITS 10 +#define BA_BITS 3 +#define ROW_BITS 13 +#define CS_BITS 1 + +/* DDR Addressing scheme: {CS, ROW, BA, COL} */ +#define COL_HI_RSHFT 0 +#define COL_HI_MASK 0 +#define COL_LO_MASK ((1 << COL_BITS) - 1) + +#define BA_RSHFT COL_BITS +#define BA_MASK ((1 << BA_BITS) - 1) + +#define ROW_ADDR_RSHIFT (BA_RSHFT + BA_BITS) +#define ROW_ADDR_MASK ((1 << ROW_BITS) - 1) + +#define CS_ADDR_RSHIFT 0 +#define CS_ADDR_MASK 0 + +#endif /* __MICROCHIP_DDR2_TIMING_H */ diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index c765a74a25..d459a2f7a5 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -75,8 +75,8 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, buffer[i] = *dataptr++; if (xdesc->name) { - i = strncmp(buffer, xdesc->name, strlen(xdesc->name)); - if (i) { + i = (ulong)strstr(buffer, xdesc->name); + if (!i) { printf("%s: Wrong bitstream ID for this device\n", __func__); printf("%s: Bitstream ID %s, current device ID %d/%s\n", diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e60e9fd86c..845dc725c5 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -83,4 +83,11 @@ config VYBRID_GPIO help Say yes here to support Vybrid vf610 GPIOs. +config PIC32_GPIO + bool "Microchip PIC32 GPIO driver" + depends on DM_GPIO && MACH_PIC32 + default y + help + Say yes here to support Microchip PIC32 GPIOs. + endmenu diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index fb4fd255df..845a6d4493 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -46,4 +46,4 @@ obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o - +obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o diff --git a/drivers/gpio/pic32_gpio.c b/drivers/gpio/pic32_gpio.c new file mode 100644 index 0000000000..499b4fa5ad --- /dev/null +++ b/drivers/gpio/pic32_gpio.c @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2015 Microchip Technology Inc + * Purna Chandra Mandal <purna.mandal@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/compat.h> +#include <dt-bindings/gpio/gpio.h> +#include <mach/pic32.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Peripheral Pin Control */ +struct pic32_reg_port { + struct pic32_reg_atomic ansel; + struct pic32_reg_atomic tris; + struct pic32_reg_atomic port; + struct pic32_reg_atomic lat; + struct pic32_reg_atomic open_drain; + struct pic32_reg_atomic cnpu; + struct pic32_reg_atomic cnpd; + struct pic32_reg_atomic cncon; +}; + +enum { + MICROCHIP_GPIO_DIR_OUT, + MICROCHIP_GPIO_DIR_IN, + MICROCHIP_GPIOS_PER_BANK = 16, +}; + +struct pic32_gpio_priv { + struct pic32_reg_port *regs; + char name[2]; +}; + +static int pic32_gpio_get_value(struct udevice *dev, unsigned offset) +{ + struct pic32_gpio_priv *priv = dev_get_priv(dev); + + return !!(readl(&priv->regs->port.raw) & BIT(offset)); +} + +static int pic32_gpio_set_value(struct udevice *dev, unsigned offset, + int value) +{ + struct pic32_gpio_priv *priv = dev_get_priv(dev); + int mask = BIT(offset); + + if (value) + writel(mask, &priv->regs->port.set); + else + writel(mask, &priv->regs->port.clr); + + return 0; +} + +static int pic32_gpio_direction(struct udevice *dev, unsigned offset) +{ + struct pic32_gpio_priv *priv = dev_get_priv(dev); + + /* pin in analog mode ? */ + if (readl(&priv->regs->ansel.raw) & BIT(offset)) + return -EPERM; + + if (readl(&priv->regs->tris.raw) & BIT(offset)) + return MICROCHIP_GPIO_DIR_IN; + else + return MICROCHIP_GPIO_DIR_OUT; +} + +static int pic32_gpio_direction_input(struct udevice *dev, unsigned offset) +{ + struct pic32_gpio_priv *priv = dev_get_priv(dev); + int mask = BIT(offset); + + writel(mask, &priv->regs->ansel.clr); + writel(mask, &priv->regs->tris.set); + + return 0; +} + +static int pic32_gpio_direction_output(struct udevice *dev, + unsigned offset, int value) +{ + struct pic32_gpio_priv *priv = dev_get_priv(dev); + int mask = BIT(offset); + + writel(mask, &priv->regs->ansel.clr); + writel(mask, &priv->regs->tris.clr); + + pic32_gpio_set_value(dev, offset, value); + return 0; +} + +static int pic32_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct fdtdec_phandle_args *args) +{ + desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; + + return 0; +} + +static int pic32_gpio_get_function(struct udevice *dev, unsigned offset) +{ + int ret = GPIOF_UNUSED; + + switch (pic32_gpio_direction(dev, offset)) { + case MICROCHIP_GPIO_DIR_OUT: + ret = GPIOF_OUTPUT; + break; + case MICROCHIP_GPIO_DIR_IN: + ret = GPIOF_INPUT; + break; + default: + ret = GPIOF_UNUSED; + break; + } + return ret; +} + +static const struct dm_gpio_ops gpio_pic32_ops = { + .direction_input = pic32_gpio_direction_input, + .direction_output = pic32_gpio_direction_output, + .get_value = pic32_gpio_get_value, + .set_value = pic32_gpio_set_value, + .get_function = pic32_gpio_get_function, + .xlate = pic32_gpio_xlate, +}; + +static int pic32_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct pic32_gpio_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + fdt_size_t size; + char *end; + int bank; + + addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = ioremap(addr, size); + + uc_priv->gpio_count = MICROCHIP_GPIOS_PER_BANK; + /* extract bank name */ + end = strrchr(dev->name, '@'); + bank = trailing_strtoln(dev->name, end); + priv->name[0] = 'A' + bank; + uc_priv->bank_name = priv->name; + + return 0; +} + +static const struct udevice_id pic32_gpio_ids[] = { + { .compatible = "microchip,pic32mzda-gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_pic32) = { + .name = "gpio_pic32", + .id = UCLASS_GPIO, + .of_match = pic32_gpio_ids, + .ops = &gpio_pic32_ops, + .probe = pic32_gpio_probe, + .priv_auto_alloc_size = sizeof(struct pic32_gpio_priv), +}; diff --git a/drivers/hwmon/adt7460.c b/drivers/hwmon/adt7460.c index fd05c17794..9b2c5b69ce 100644 --- a/drivers/hwmon/adt7460.c +++ b/drivers/hwmon/adt7460.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid, ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid, ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index cba236334c..af8667f030 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -130,4 +130,12 @@ config RESET effect a reset. The uclass will try all available drivers when reset_walk() is called. +config WINBOND_W83627 + bool "Enable Winbond Super I/O driver" + help + If you say Y here, you will get support for the Winbond + W83627 Super I/O driver. This can be used to enable the + legacy UART or other devices in the Winbond Super IO chips + on X86 platforms. + endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index cd4846b4a8..e1e3c6b70f 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -41,3 +41,4 @@ obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o obj-$(CONFIG_RESET) += reset-uclass.o obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o +obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o diff --git a/drivers/misc/winbond_w83627.c b/drivers/misc/winbond_w83627.c new file mode 100644 index 0000000000..59db7d971c --- /dev/null +++ b/drivers/misc/winbond_w83627.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/pnp_def.h> + +#define WINBOND_ENTRY_KEY 0x87 +#define WINBOND_EXIT_KEY 0xaa + +/* Enable configuration: pass entry key '0x87' into index port dev twice */ +static void pnp_enter_conf_state(u16 dev) +{ + u16 port = dev >> 8; + + outb(WINBOND_ENTRY_KEY, port); + outb(WINBOND_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev */ +static void pnp_exit_conf_state(u16 dev) +{ + u16 port = dev >> 8; + + outb(WINBOND_EXIT_KEY, port); +} + +/* Bring up early serial debugging output before the RAM is initialized */ +void winbond_enable_serial(uint dev, uint iobase, uint irq) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_irq(dev, PNP_IDX_IRQ0, irq); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index ceae7bcaec..9f4b766f7a 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -31,4 +31,10 @@ config SH_SDHI help Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform +config PIC32_SDHCI + bool "Microchip PIC32 on-chip SDHCI support" + depends on DM_MMC && MACH_PIC32 + help + Support for Microchip PIC32 SDHCI controller. + endmenu diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 5d357056dd..c9c3e3e938 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -48,4 +48,4 @@ obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o else obj-$(CONFIG_GENERIC_MMC) += mmc_write.o endif - +obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 1ccc576c34..ea5f4bf6c0 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -105,12 +105,9 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) else if (cmd->resp_type & MMC_RSP_PRESENT) xfertyp |= XFERTYP_RSPTYP_48; -#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \ - defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE) || \ - defined(CONFIG_PPC_T4160) if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) xfertyp |= XFERTYP_CMDTYP_ABORT; -#endif + return XFERTYP_CMD(cmd->cmdidx) | xfertyp; } @@ -252,8 +249,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) * Rounding up to next power of 2 * => timeout + 13 = log2(mmc->clock/4) + 1 * => timeout + 13 = fls(mmc->clock/4) + * + * However, the MMC spec "It is strongly recommended for hosts to + * implement more than 500ms timeout value even if the card + * indicates the 250ms maximum busy length." Even the previous + * value of 300ms is known to be insufficient for some cards. + * So, we use + * => timeout + 13 = fls(mmc->clock/2) */ - timeout = fls(mmc->clock/4); + timeout = fls(mmc->clock/2); timeout -= 13; if (timeout > 14) diff --git a/drivers/mmc/pic32_sdhci.c b/drivers/mmc/pic32_sdhci.c new file mode 100644 index 0000000000..28da55d2db --- /dev/null +++ b/drivers/mmc/pic32_sdhci.c @@ -0,0 +1,58 @@ +/* + * Support of SDHCI for Microchip PIC32 SoC. + * + * Copyright (C) 2015 Microchip Technology Inc. + * Andrei Pistirica <andrei.pistirica@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm.h> +#include <common.h> +#include <sdhci.h> +#include <asm/errno.h> +#include <mach/pic32.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int pic32_sdhci_probe(struct udevice *dev) +{ + struct sdhci_host *host = dev_get_priv(dev); + const void *fdt = gd->fdt_blob; + u32 f_min_max[2]; + fdt_addr_t addr; + fdt_size_t size; + int ret; + + addr = fdtdec_get_addr_size(fdt, dev->of_offset, "reg", &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + host->ioaddr = ioremap(addr, size); + host->name = (char *)dev->name; + host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_NO_CD; + host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "bus-width", 4); + + ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, + "clock-freq-min-max", f_min_max, 2); + if (ret) { + printf("sdhci: clock-freq-min-max not found\n"); + return ret; + } + + return add_sdhci(host, f_min_max[1], f_min_max[0]); +} + +static const struct udevice_id pic32_sdhci_ids[] = { + { .compatible = "microchip,pic32mzda-sdhci" }, + { } +}; + +U_BOOT_DRIVER(pic32_sdhci_drv) = { + .name = "pic32_sdhci", + .id = UCLASS_MMC, + .of_match = pic32_sdhci_ids, + .probe = pic32_sdhci_probe, + .priv_auto_alloc_size = sizeof(struct sdhci_host), +}; diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 02d71b9344..8586d898fd 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -443,6 +443,12 @@ static int sdhci_init(struct mmc *mmc) sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); if (host->quirks & SDHCI_QUIRK_NO_CD) { +#if defined(CONFIG_PIC32_SDHCI) + /* PIC32 SDHCI CD errata: + * - set CD_TEST and clear CD_TEST_INS bit + */ + sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL); +#else unsigned int status; sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST, @@ -453,6 +459,7 @@ static int sdhci_init(struct mmc *mmc) (!(status & SDHCI_CARD_STATE_STABLE)) || (!(status & SDHCI_CARD_DETECT_PIN_LEVEL))) status = sdhci_readl(host, SDHCI_PRESENT_STATE); +#endif } /* Enable only interrupts served by the SD controller */ @@ -530,6 +537,10 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) if (caps & SDHCI_CAN_DO_8BIT) host->cfg.host_caps |= MMC_MODE_8BIT; } + + if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) + host->cfg.host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz); + if (host->host_caps) host->cfg.host_caps |= host->host_caps; diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 4fe3da93b2..039ec16e91 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -13,6 +13,10 @@ #include <malloc.h> #include <sdhci.h> +#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ +# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0 +#endif + static int arasan_sdhci_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); @@ -20,9 +24,15 @@ static int arasan_sdhci_probe(struct udevice *dev) host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; + +#ifdef CONFIG_ZYNQ_HISPD_BROKEN + host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; +#endif + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); - add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, 0); + add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, + CONFIG_ZYNQ_SDHCI_MIN_FREQ); upriv->mmc = host->mmc; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index de54ca8014..bc2f51d958 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -102,6 +102,22 @@ config PCH_GBE This MAC is present in Intel Platform Controller Hub EG20T. It supports 10/100/1000 Mbps operation. +config XILINX_AXIEMAC + depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP) + select PHYLIB + select MII + bool "Xilinx AXI Ethernet" + help + This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. + +config XILINX_EMACLITE + depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP) + select PHYLIB + select MII + bool "Xilinx Ethernetlite" + help + This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. + config ZYNQ_GEM depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP) select PHYLIB @@ -109,4 +125,12 @@ config ZYNQ_GEM help This MAC is present in Xilinx Zynq and ZynqMP SoCs. +config PIC32_ETH + bool "Microchip PIC32 Ethernet Support" + depends on DM_ETH && MACH_PIC32 + select PHYLIB + help + This driver implements 10/100 Mbps Ethernet and MAC layer for + Microchip PIC32 microcontrollers. + endif # NETDEVICES diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 150470c24b..33a81ee547 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -72,3 +72,4 @@ obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/ obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o obj-$(CONFIG_VSC9953) += vsc9953.o +obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 68b6548309..77b98c94c0 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -196,6 +196,8 @@ static void dw_adjust_link(struct eth_mac_regs *mac_p, if (phydev->speed != 1000) conf |= MII_PORTSELECT; + else + conf &= ~MII_PORTSELECT; if (phydev->speed == 100) conf |= FES_100; @@ -404,7 +406,7 @@ static int _dw_free_pkt(struct dw_eth_dev *priv) static int dw_phy_init(struct dw_eth_dev *priv, void *dev) { struct phy_device *phydev; - int mask = 0xffffffff; + int mask = 0xffffffff, ret; #ifdef CONFIG_PHY_ADDR mask = 1 << CONFIG_PHY_ADDR; @@ -417,6 +419,11 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) phy_connect_dev(phydev, dev); phydev->supported &= PHY_GBIT_FEATURES; + if (priv->max_speed) { + ret = phy_set_supported(phydev, priv->max_speed); + if (ret) + return ret; + } phydev->advertising = phydev->supported; priv->phydev = phydev; @@ -599,6 +606,7 @@ static int designware_eth_probe(struct udevice *dev) priv->mac_regs_p = (struct eth_mac_regs *)iobase; priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET); priv->interface = pdata->phy_interface; + priv->max_speed = pdata->max_speed; dw_mdio_init(dev->name, priv->mac_regs_p); priv->bus = miiphy_get_dev_by_name(dev->name); @@ -633,6 +641,7 @@ static int designware_eth_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); const char *phy_mode; + const fdt32_t *cell; pdata->iobase = dev_get_addr(dev); pdata->phy_interface = -1; @@ -644,6 +653,11 @@ static int designware_eth_ofdata_to_platdata(struct udevice *dev) return -EINVAL; } + pdata->max_speed = 0; + cell = fdt_getprop(gd->fdt_blob, dev->of_offset, "max-speed", NULL); + if (cell) + pdata->max_speed = fdt32_to_cpu(*cell); + return 0; } diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 4b9ec39cc8..ed6344cc28 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -223,6 +223,7 @@ struct dw_eth_dev { char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); u32 interface; + u32 max_speed; u32 tx_currdescnum; u32 rx_currdescnum; diff --git a/drivers/net/fsl-mc/dpio/qbman_portal.c b/drivers/net/fsl-mc/dpio/qbman_portal.c index 449ff8a8ba..4b64c8ae73 100644 --- a/drivers/net/fsl-mc/dpio/qbman_portal.c +++ b/drivers/net/fsl-mc/dpio/qbman_portal.c @@ -102,12 +102,14 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) void *qbman_swp_mc_start(struct qbman_swp *p) { void *ret; + int *return_val; #ifdef QBMAN_CHECKING BUG_ON(p->mc.check != swp_mc_can_start); #endif ret = qbman_cena_write_start(&p->sys, QBMAN_CENA_SWP_CR); #ifdef QBMAN_CHECKING - if (!ret) + return_val = (int *)ret; + if (!(*return_val)) p->mc.check = swp_mc_can_submit; #endif return ret; diff --git a/drivers/net/fsl-mc/dpni.c b/drivers/net/fsl-mc/dpni.c index eacb3c8bb2..41bf56abf5 100644 --- a/drivers/net/fsl-mc/dpni.c +++ b/drivers/net/fsl-mc/dpni.c @@ -8,6 +8,26 @@ #include <fsl-mc/fsl_mc_cmd.h> #include <fsl-mc/fsl_dpni.h> +int dpni_prepare_extended_cfg(const struct dpni_extended_cfg *cfg, + uint8_t *ext_cfg_buf) +{ + uint64_t *ext_params = (uint64_t *)ext_cfg_buf; + + DPNI_PREP_EXTENDED_CFG(ext_params, cfg); + + return 0; +} + +int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg, + const uint8_t *ext_cfg_buf) +{ + uint64_t *ext_params = (uint64_t *)ext_cfg_buf; + + DPNI_EXT_EXTENDED_CFG(ext_params, cfg); + + return 0; +} + int dpni_open(struct fsl_mc_io *mc_io, uint32_t cmd_flags, int dpni_id, @@ -162,6 +182,7 @@ int dpni_get_attributes(struct fsl_mc_io *mc_io, cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_ATTR, cmd_flags, token); + DPNI_CMD_GET_ATTR(cmd, attr); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -174,6 +195,23 @@ int dpni_get_attributes(struct fsl_mc_io *mc_io, return 0; } +int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_error_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_ERRORS_BEHAVIOR, + cmd_flags, + token); + DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + int dpni_get_rx_buffer_layout(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, @@ -602,3 +640,46 @@ int dpni_get_rx_flow(struct fsl_mc_io *mc_io, return 0; } + +int dpni_set_tx_conf(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint16_t flow_id, + const struct dpni_tx_conf_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONF, + cmd_flags, + token); + DPNI_CMD_SET_TX_CONF(cmd, flow_id, cfg); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_get_tx_conf(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint16_t flow_id, + struct dpni_tx_conf_attr *attr) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_CONF, + cmd_flags, + token); + DPNI_CMD_GET_TX_CONF(cmd, flow_id); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + DPNI_RSP_GET_TX_CONF(cmd, attr); + + return 0; +} diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 4b9b3720f7..fdbd584186 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -656,6 +656,26 @@ int fsl_mc_ldpaa_init(bd_t *bis) return 0; } +static int dprc_version_check(struct fsl_mc_io *mc_io, uint16_t handle) +{ + struct dprc_attributes attr; + int error; + + memset(&attr, 0, sizeof(struct dprc_attributes)); + error = dprc_get_attributes(mc_io, MC_CMD_NO_FLAGS, handle, &attr); + if (error == 0) { + if ((attr.version.major != DPRC_VER_MAJOR) || + (attr.version.minor != DPRC_VER_MINOR)) { + printf("DPRC version mismatch found %u.%u,", + attr.version.major, + attr.version.minor); + printf("supported version is %u.%u\n", + DPRC_VER_MAJOR, DPRC_VER_MINOR); + } + } + return error; +} + static int dpio_init(void) { struct qbman_swp_desc p_des; @@ -689,11 +709,18 @@ static int dpio_init(void) goto err_get_attr; } + if ((attr.version.major != DPIO_VER_MAJOR) || + (attr.version.minor != DPIO_VER_MINOR)) { + printf("DPIO version mismatch found %u.%u,", + attr.version.major, attr.version.minor); + printf("supported version is %u.%u\n", + DPIO_VER_MAJOR, DPIO_VER_MINOR); + } + dflt_dpio->dpio_id = attr.id; #ifdef DEBUG printf("Init: DPIO id=0x%d\n", dflt_dpio->dpio_id); #endif - err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); if (err < 0) { printf("dpio_enable() failed %d\n", err); @@ -785,11 +812,18 @@ static int dprc_init(void) goto err_root_open; } + err = dprc_version_check(root_mc_io, root_dprc_handle); + if (err < 0) { + printf("dprc_version_check() failed: %d\n", err); + goto err_root_open; + } + + memset(&cfg, 0, sizeof(struct dprc_cfg)); cfg.options = DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED | DPRC_CFG_OPT_OBJ_CREATE_ALLOWED | DPRC_CFG_OPT_ALLOC_ALLOWED; cfg.icid = DPRC_GET_ICID_FROM_POOL; - cfg.portal_id = 250; + cfg.portal_id = DPRC_GET_PORTAL_ID_FROM_POOL; err = dprc_create_container(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle, &cfg, @@ -907,6 +941,14 @@ static int dpbp_init(void) goto err_get_attr; } + if ((dpbp_attr.version.major != DPBP_VER_MAJOR) || + (dpbp_attr.version.minor != DPBP_VER_MINOR)) { + printf("DPBP version mismatch found %u.%u,", + dpbp_attr.version.major, dpbp_attr.version.minor); + printf("supported version is %u.%u\n", + DPBP_VER_MAJOR, DPBP_VER_MINOR); + } + dflt_dpbp->dpbp_attr.id = dpbp_attr.id; #ifdef DEBUG printf("Init: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id); @@ -964,6 +1006,8 @@ static int dpni_init(void) { int err; struct dpni_attr dpni_attr; + uint8_t ext_cfg_buf[256] = {0}; + struct dpni_extended_cfg dpni_extended_cfg; struct dpni_cfg dpni_cfg; dflt_dpni = (struct fsl_dpni_obj *)malloc(sizeof(struct fsl_dpni_obj)); @@ -973,10 +1017,19 @@ static int dpni_init(void) goto err_malloc; } + memset(&dpni_extended_cfg, 0, sizeof(dpni_extended_cfg)); + err = dpni_prepare_extended_cfg(&dpni_extended_cfg, &ext_cfg_buf[0]); + if (err < 0) { + err = -ENODEV; + printf("dpni_prepare_extended_cfg() failed: %d\n", err); + goto err_prepare_extended_cfg; + } + memset(&dpni_cfg, 0, sizeof(dpni_cfg)); dpni_cfg.adv.options = DPNI_OPT_UNICAST_FILTER | DPNI_OPT_MULTICAST_FILTER; + dpni_cfg.adv.ext_cfg_iova = (uint64_t)&ext_cfg_buf[0]; err = dpni_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpni_cfg, &dflt_dpni->dpni_handle); @@ -995,6 +1048,14 @@ static int dpni_init(void) goto err_get_attr; } + if ((dpni_attr.version.major != DPNI_VER_MAJOR) || + (dpni_attr.version.minor != DPNI_VER_MINOR)) { + printf("DPNI version mismatch found %u.%u,", + dpni_attr.version.major, dpni_attr.version.minor); + printf("supported version is %u.%u\n", + DPNI_VER_MAJOR, DPNI_VER_MINOR); + } + dflt_dpni->dpni_id = dpni_attr.id; #ifdef DEBUG printf("Init: DPNI id=0x%d\n", dflt_dpni->dpni_id); @@ -1009,11 +1070,12 @@ static int dpni_init(void) return 0; err_close: - free(dflt_dpni); err_get_attr: dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); err_create: +err_prepare_extended_cfg: + free(dflt_dpni); err_malloc: return err; } @@ -1099,7 +1161,7 @@ int fsl_mc_ldpaa_exit(bd_t *bd) err = dpbp_exit(); if (err < 0) { - printf("dpni_exit() failed: %d\n", err); + printf("dpbp_exit() failed: %d\n", err); goto err; } diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c index f48bbc3123..77b9739a24 100644 --- a/drivers/net/fsl_mdio.c +++ b/drivers/net/fsl_mdio.c @@ -5,6 +5,7 @@ * * SPDX-License-Identifier: GPL-2.0+ */ + #include <common.h> #include <miiphy.h> #include <phy.h> @@ -32,8 +33,7 @@ int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr, int value; int timeout = 1000000; - /* Put the address of the phy, and the register - * number into MIIMADD */ + /* Put the address of the phy, and the register number into MIIMADD */ out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f)); /* Clear the command register, and wait */ diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 3857122bd0..7f96883d34 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -100,6 +100,83 @@ static void ldpaa_eth_get_dpni_counter(void) } printf("DPNI_CNT_EGR_FRAME_DISCARD =%lld\n", value); } + +static void ldpaa_eth_get_dpmac_counter(struct eth_device *net_dev) +{ + struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; + int err = 0; + u64 value; + + err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, + DPMAC_CNT_ING_BYTE, + &value); + if (err < 0) { + printf("dpmac_get_counter: DPMAC_CNT_ING_BYTE failed\n"); + return; + } + printf("DPMAC_CNT_ING_BYTE=%lld\n", value); + + err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, + DPMAC_CNT_ING_FRAME_DISCARD, + &value); + if (err < 0) { + printf("dpmac_get_counter: DPMAC_CNT_ING_FRAME_DISCARD failed\n"); + return; + } + printf("DPMAC_CNT_ING_FRAME_DISCARD=%lld\n", value); + + err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, + DPMAC_CNT_ING_ALIGN_ERR, + &value); + if (err < 0) { + printf("dpmac_get_counter: DPMAC_CNT_ING_ALIGN_ERR failed\n"); + return; + } + printf("DPMAC_CNT_ING_ALIGN_ERR =%lld\n", value); + + err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, + DPMAC_CNT_ING_BYTE, + &value); + if (err < 0) { + printf("dpmac_get_counter: DPMAC_CNT_ING_BYTE failed\n"); + return; + } + printf("DPMAC_CNT_ING_BYTE=%lld\n", value); + + err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, + DPMAC_CNT_ING_ERR_FRAME, + &value); + if (err < 0) { + printf("dpmac_get_counter: DPMAC_CNT_ING_ERR_FRAME failed\n"); + return; + } + printf("DPMAC_CNT_ING_ERR_FRAME=%lld\n", value); + + err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, + DPMAC_CNT_EGR_BYTE , + &value); + if (err < 0) { + printf("dpmac_get_counter: DPMAC_CNT_EGR_BYTE failed\n"); + return; + } + printf("DPMAC_CNT_EGR_BYTE =%lld\n", value); + + err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, + DPMAC_CNT_EGR_ERR_FRAME , + &value); + if (err < 0) { + printf("dpmac_get_counter: DPMAC_CNT_EGR_ERR_FRAME failed\n"); + return; + } + printf("DPMAC_CNT_EGR_ERR_FRAME =%lld\n", value); +} #endif static void ldpaa_eth_rx(struct ldpaa_eth_priv *priv, @@ -436,6 +513,7 @@ static void ldpaa_eth_stop(struct eth_device *net_dev) #ifdef DEBUG ldpaa_eth_get_dpni_counter(); + ldpaa_eth_get_dpmac_counter(net_dev); #endif err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS, @@ -599,6 +677,29 @@ static void ldpaa_dpbp_free(void) dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); } +static int ldpaa_dpmac_version_check(struct fsl_mc_io *mc_io, + struct ldpaa_eth_priv *priv) +{ + struct dpmac_attr attr; + int error; + + memset(&attr, 0, sizeof(struct dpmac_attr)); + error = dpmac_get_attributes(mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, + &attr); + if (error == 0) { + if ((attr.version.major != DPMAC_VER_MAJOR) || + (attr.version.minor != DPMAC_VER_MINOR)) { + printf("DPMAC version mismatch found %u.%u,", + attr.version.major, attr.version.minor); + printf("supported version is %u.%u\n", + DPMAC_VER_MAJOR, DPMAC_VER_MINOR); + } + } + + return error; +} + static int ldpaa_dpmac_setup(struct ldpaa_eth_priv *priv) { int err = 0; @@ -609,6 +710,11 @@ static int ldpaa_dpmac_setup(struct ldpaa_eth_priv *priv) &priv->dpmac_handle); if (err) printf("dpmac_create() failed\n"); + + err = ldpaa_dpmac_version_check(dflt_mc_io, priv); + if (err < 0) + printf("ldpaa_dpmac_version_check() failed: %d\n", err); + return err; } @@ -755,6 +861,7 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv) { struct dpni_pools_cfg pools_params; struct dpni_tx_flow_cfg dflt_tx_flow; + struct dpni_tx_conf_cfg tx_conf_cfg; int err = 0; pools_params.num_dpbp = 1; @@ -770,9 +877,7 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv) priv->tx_flow_id = DPNI_NEW_FLOW_ID; memset(&dflt_tx_flow, 0, sizeof(dflt_tx_flow)); - dflt_tx_flow.options = DPNI_TX_FLOW_OPT_ONLY_TX_ERROR; - dflt_tx_flow.conf_err_cfg.use_default_queue = 0; - dflt_tx_flow.conf_err_cfg.errors_only = 1; + dflt_tx_flow.use_common_tx_conf_queue = 0; err = dpni_set_tx_flow(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, &priv->tx_flow_id, &dflt_tx_flow); @@ -781,6 +886,17 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv) return err; } + memset(&tx_conf_cfg, 0, sizeof(struct dpni_tx_conf_cfg)); + tx_conf_cfg.errors_only = true; + /*Set tx-conf and error configuration*/ + err = dpni_set_tx_conf(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + priv->tx_flow_id, &tx_conf_cfg); + if (err) { + printf("dpni_set_tx_conf() failed\n"); + return err; + } + return 0; } diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h b/drivers/net/ldpaa_eth/ldpaa_eth.h index af41b27844..3b16150735 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.h +++ b/drivers/net/ldpaa_eth/ldpaa_eth.h @@ -24,7 +24,7 @@ enum ldpaa_eth_type { }; /* Arbitrary values for now, but we'll need to tune */ -#define LDPAA_ETH_NUM_BUFS (2 * 7) +#define LDPAA_ETH_NUM_BUFS (7 * 7) #define LDPAA_ETH_REFILL_THRESH (LDPAA_ETH_NUM_BUFS/2) #define LDPAA_ETH_RX_BUFFER_SIZE 2048 diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index 447ecfbeb6..f975fd8209 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -257,6 +257,12 @@ int cs4340_config(struct phy_device *phydev) return 0; } +int cs4340_probe(struct phy_device *phydev) +{ + phydev->flags = PHY_FLAG_BROKEN_RESET; + return 0; +} + int cs4340_startup(struct phy_device *phydev) { phydev->link = 1; @@ -276,6 +282,7 @@ struct phy_driver cs4340_driver = { MDIO_DEVS_PHYXS | MDIO_DEVS_AN | MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2), .config = &cs4340_config, + .probe = &cs4340_probe, .startup = &cs4340_startup, .shutdown = &gen10g_shutdown, }; diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 19b6bc7472..c3da1606dc 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -27,12 +27,31 @@ static struct phy_driver KSZ804_driver = { .shutdown = &genphy_shutdown, }; +#define MII_KSZPHY_OMSO 0x16 +#define KSZPHY_OMSO_B_CAST_OFF (1 << 9) + +static int ksz_genconfig_bcastoff(struct phy_device *phydev) +{ + int ret; + + ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO, + ret | KSZPHY_OMSO_B_CAST_OFF); + if (ret < 0) + return ret; + + return genphy_config(phydev); +} + static struct phy_driver KSZ8031_driver = { .name = "Micrel KSZ8021/KSZ8031", .uid = 0x221550, .mask = 0xfffff0, .features = PHY_BASIC_FEATURES, - .config = &genphy_config, + .config = &ksz_genconfig_bcastoff, .startup = &genphy_startup, .shutdown = &genphy_shutdown, }; @@ -70,7 +89,7 @@ static struct phy_driver KSZ8081_driver = { .uid = 0x221560, .mask = 0xfffff0, .features = PHY_BASIC_FEATURES, - .config = &genphy_config, + .config = &ksz_genconfig_bcastoff, .startup = &genphy_startup, .shutdown = &genphy_shutdown, }; @@ -211,7 +230,7 @@ static int ksz90x1_of_config_group(struct phy_device *phydev, { struct udevice *dev = phydev->dev; struct phy_driver *drv = phydev->drv; - const int ps_to_regval = 200; + const int ps_to_regval = 60; int val[4]; int i, changed = 0, offset, max; u16 regval = 0; diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 51b5746a5a..17866a244b 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -38,16 +38,16 @@ DECLARE_GLOBAL_DATA_PTR; static int genphy_config_advert(struct phy_device *phydev) { u32 advertise; - int oldadv, adv; + int oldadv, adv, bmsr; int err, changed = 0; - /* Only allow advertising what - * this PHY supports */ + /* Only allow advertising what this PHY supports */ phydev->advertising &= phydev->supported; advertise = phydev->advertising; /* Setup standard advertisement */ - oldadv = adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE); + adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE); + oldadv = adv; if (adv < 0) return adv; @@ -79,29 +79,40 @@ static int genphy_config_advert(struct phy_device *phydev) changed = 1; } + bmsr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); + if (bmsr < 0) + return bmsr; + + /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all + * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a + * logical 1. + */ + if (!(bmsr & BMSR_ESTATEN)) + return changed; + /* Configure gigabit if it's supported */ - if (phydev->supported & (SUPPORTED_1000baseT_Half | - SUPPORTED_1000baseT_Full)) { - oldadv = adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); + adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); + oldadv = adv; + + if (adv < 0) + return adv; - if (adv < 0) - return adv; + adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); - adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); + if (phydev->supported & (SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full)) { if (advertise & SUPPORTED_1000baseT_Half) adv |= ADVERTISE_1000HALF; if (advertise & SUPPORTED_1000baseT_Full) adv |= ADVERTISE_1000FULL; + } - if (adv != oldadv) { - err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, - adv); + if (adv != oldadv) + changed = 1; - if (err < 0) - return err; - changed = 1; - } - } + err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, adv); + if (err < 0) + return err; return changed; } @@ -117,7 +128,7 @@ static int genphy_config_advert(struct phy_device *phydev) static int genphy_setup_forced(struct phy_device *phydev) { int err; - int ctl = 0; + int ctl = BMCR_ANRESTART; phydev->pause = phydev->asym_pause = 0; @@ -224,7 +235,8 @@ int genphy_update_link(struct phy_device *phydev) if (phydev->link && mii_reg & BMSR_LSTATUS) return 0; - if ((mii_reg & BMSR_ANEGCAPABLE) && !(mii_reg & BMSR_ANEGCOMPLETE)) { + if ((phydev->autoneg == AUTONEG_ENABLE) && + !(mii_reg & BMSR_ANEGCOMPLETE)) { int i = 0; printf("%s Waiting for PHY auto negotiation to complete", @@ -280,7 +292,7 @@ int genphy_parse_link(struct phy_device *phydev) int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); /* We're using autonegotiation */ - if (phydev->supported & SUPPORTED_Autoneg) { + if (phydev->autoneg == AUTONEG_ENABLE) { u32 lpa = 0; int gblpa = 0; u32 estatus = 0; @@ -371,8 +383,6 @@ int genphy_config(struct phy_device *phydev) int val; u32 features; - /* For now, I'll claim that the generic driver supports - * all possible port types */ features = (SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_AUI | SUPPORTED_FIBRE | SUPPORTED_BNC); @@ -411,8 +421,8 @@ int genphy_config(struct phy_device *phydev) features |= SUPPORTED_1000baseX_Half; } - phydev->supported = features; - phydev->advertising = features; + phydev->supported &= features; + phydev->advertising &= features; genphy_config_aneg(phydev); @@ -436,7 +446,9 @@ static struct phy_driver genphy_driver = { .uid = 0xffffffff, .mask = 0xffffffff, .name = "Generic PHY", - .features = 0, + .features = PHY_GBIT_FEATURES | SUPPORTED_MII | + SUPPORTED_AUI | SUPPORTED_FIBRE | + SUPPORTED_BNC, .config = genphy_config, .startup = genphy_startup, .shutdown = genphy_shutdown, @@ -517,6 +529,30 @@ int phy_register(struct phy_driver *drv) return 0; } +int phy_set_supported(struct phy_device *phydev, u32 max_speed) +{ + /* The default values for phydev->supported are provided by the PHY + * driver "features" member, we want to reset to sane defaults first + * before supporting higher speeds. + */ + phydev->supported &= PHY_DEFAULT_FEATURES; + + switch (max_speed) { + default: + return -ENOTSUPP; + case SPEED_1000: + phydev->supported |= PHY_1000BT_FEATURES; + /* fall through */ + case SPEED_100: + phydev->supported |= PHY_100BT_FEATURES; + /* fall through */ + case SPEED_10: + phydev->supported |= PHY_10BT_FEATURES; + } + + return 0; +} + static int phy_probe(struct phy_device *phydev) { int err = 0; @@ -707,6 +743,9 @@ int phy_reset(struct phy_device *phydev) int timeout = 500; int devad = MDIO_DEVAD_NONE; + if (phydev->flags & PHY_FLAG_BROKEN_RESET) + return 0; + #ifdef CONFIG_PHYLIB_10G /* If it's 10G, we need to issue reset through one of the MMDs */ if (is_10g_interface(phydev->interface)) { @@ -717,15 +756,7 @@ int phy_reset(struct phy_device *phydev) } #endif - reg = phy_read(phydev, devad, MII_BMCR); - if (reg < 0) { - debug("PHY status read failed\n"); - return -1; - } - - reg |= BMCR_RESET; - - if (phy_write(phydev, devad, MII_BMCR, reg) < 0) { + if (phy_write(phydev, devad, MII_BMCR, BMCR_RESET) < 0) { debug("PHY reset failed\n"); return -1; } @@ -738,6 +769,7 @@ int phy_reset(struct phy_device *phydev) * auto-clearing). This should happen within 0.5 seconds per the * IEEE spec. */ + reg = phy_read(phydev, devad, MII_BMCR); while ((reg & BMCR_RESET) && timeout--) { reg = phy_read(phydev, devad, MII_BMCR); diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c index bfd9815abf..34986a29fc 100644 --- a/drivers/net/phy/smsc.c +++ b/drivers/net/phy/smsc.c @@ -69,11 +69,21 @@ static struct phy_driver lan8710_driver = { .shutdown = &genphy_shutdown, }; +static struct phy_driver lan8740_driver = { + .name = "SMSC LAN8740", + .uid = 0x0007c110, + .mask = 0xffff0, + .features = PHY_BASIC_FEATURES, + .config = &genphy_config_aneg, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; int phy_smsc_init(void) { phy_register(&lan8710_driver); phy_register(&lan911x_driver); phy_register(&lan8700_driver); + phy_register(&lan8740_driver); return 0; } diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index 541a57f980..c3912d52f3 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -41,6 +41,8 @@ /* PHY CTRL bits */ #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 +#define DP83867_MDI_CROSSOVER 5 +#define DP83867_MDI_CROSSOVER_AUTO 2 /* RGMIIDCTL bits */ #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 @@ -149,6 +151,7 @@ static int dp83867_config(struct phy_device *phydev) if (phy_interface_is_rgmii(phydev)) { ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, + (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) | (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); if (ret) return ret; diff --git a/drivers/net/pic32_eth.c b/drivers/net/pic32_eth.c new file mode 100644 index 0000000000..167af8bde5 --- /dev/null +++ b/drivers/net/pic32_eth.c @@ -0,0 +1,605 @@ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#include <common.h> +#include <errno.h> +#include <dm.h> +#include <net.h> +#include <miiphy.h> +#include <console.h> +#include <wait_bit.h> +#include <asm/gpio.h> + +#include "pic32_eth.h" + +#define MAX_RX_BUF_SIZE 1536 +#define MAX_RX_DESCR PKTBUFSRX +#define MAX_TX_DESCR 2 + +DECLARE_GLOBAL_DATA_PTR; + +struct pic32eth_dev { + struct eth_dma_desc rxd_ring[MAX_RX_DESCR]; + struct eth_dma_desc txd_ring[MAX_TX_DESCR]; + u32 rxd_idx; /* index of RX desc to read */ + /* regs */ + struct pic32_ectl_regs *ectl_regs; + struct pic32_emac_regs *emac_regs; + /* Phy */ + struct phy_device *phydev; + phy_interface_t phyif; + u32 phy_addr; + struct gpio_desc rst_gpio; +}; + +void __weak board_netphy_reset(void *dev) +{ + struct pic32eth_dev *priv = dev; + + if (!dm_gpio_is_valid(&priv->rst_gpio)) + return; + + /* phy reset */ + dm_gpio_set_value(&priv->rst_gpio, 0); + udelay(300); + dm_gpio_set_value(&priv->rst_gpio, 1); + udelay(300); +} + +/* Initialize mii(MDIO) interface, discover which PHY is + * attached to the device, and configure it properly. + */ +static int pic32_mii_init(struct pic32eth_dev *priv) +{ + struct pic32_ectl_regs *ectl_p = priv->ectl_regs; + struct pic32_emac_regs *emac_p = priv->emac_regs; + + /* board phy reset */ + board_netphy_reset(priv); + + /* disable RX, TX & all transactions */ + writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); + + /* wait till busy */ + wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false, + CONFIG_SYS_HZ, false); + + /* turn controller ON to access PHY over MII */ + writel(ETHCON_ON, &ectl_p->con1.set); + + mdelay(10); + + /* reset MAC */ + writel(EMAC_SOFTRESET, &emac_p->cfg1.set); /* reset assert */ + mdelay(10); + writel(EMAC_SOFTRESET, &emac_p->cfg1.clr); /* reset deassert */ + + /* initialize MDIO/MII */ + if (priv->phyif == PHY_INTERFACE_MODE_RMII) { + writel(EMAC_RMII_RESET, &emac_p->supp.set); + mdelay(10); + writel(EMAC_RMII_RESET, &emac_p->supp.clr); + } + + return pic32_mdio_init(PIC32_MDIO_NAME, (ulong)&emac_p->mii); +} + +static int pic32_phy_init(struct pic32eth_dev *priv, struct udevice *dev) +{ + struct mii_dev *mii; + + mii = miiphy_get_dev_by_name(PIC32_MDIO_NAME); + + /* find & connect PHY */ + priv->phydev = phy_connect(mii, priv->phy_addr, + dev, priv->phyif); + if (!priv->phydev) { + printf("%s: %s: Error, PHY connect\n", __FILE__, __func__); + return 0; + } + + /* Wait for phy to complete reset */ + mdelay(10); + + /* configure supported modes */ + priv->phydev->supported = SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_Autoneg; + + priv->phydev->advertising = ADVERTISED_10baseT_Half | + ADVERTISED_10baseT_Full | + ADVERTISED_100baseT_Half | + ADVERTISED_100baseT_Full | + ADVERTISED_Autoneg; + + priv->phydev->autoneg = AUTONEG_ENABLE; + + return 0; +} + +/* Configure MAC based on negotiated speed and duplex + * reported by PHY. + */ +static int pic32_mac_adjust_link(struct pic32eth_dev *priv) +{ + struct phy_device *phydev = priv->phydev; + struct pic32_emac_regs *emac_p = priv->emac_regs; + + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return -EINVAL; + } + + if (phydev->duplex) { + writel(EMAC_FULLDUP, &emac_p->cfg2.set); + writel(FULLDUP_GAP_TIME, &emac_p->ipgt.raw); + } else { + writel(EMAC_FULLDUP, &emac_p->cfg2.clr); + writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw); + } + + switch (phydev->speed) { + case SPEED_100: + writel(EMAC_RMII_SPD100, &emac_p->supp.set); + break; + case SPEED_10: + writel(EMAC_RMII_SPD100, &emac_p->supp.clr); + break; + default: + printf("%s: Speed was bad\n", phydev->dev->name); + return -EINVAL; + } + + printf("pic32eth: PHY is %s with %dbase%s, %s\n", + phydev->drv->name, phydev->speed, + (phydev->port == PORT_TP) ? "T" : "X", + (phydev->duplex) ? "full" : "half"); + + return 0; +} + +static void pic32_mac_init(struct pic32eth_dev *priv, u8 *macaddr) +{ + struct pic32_emac_regs *emac_p = priv->emac_regs; + u32 stat = 0, v; + u64 expire; + + v = EMAC_TXPAUSE | EMAC_RXPAUSE | EMAC_RXENABLE; + writel(v, &emac_p->cfg1.raw); + + v = EMAC_EXCESS | EMAC_AUTOPAD | EMAC_PADENABLE | + EMAC_CRCENABLE | EMAC_LENGTHCK | EMAC_FULLDUP; + writel(v, &emac_p->cfg2.raw); + + /* recommended back-to-back inter-packet gap for 10 Mbps half duplex */ + writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw); + + /* recommended non-back-to-back interpacket gap is 0xc12 */ + writel(0xc12, &emac_p->ipgr.raw); + + /* recommended collision window retry limit is 0x370F */ + writel(0x370f, &emac_p->clrt.raw); + + /* set maximum frame length: allow VLAN tagged frame */ + writel(0x600, &emac_p->maxf.raw); + + /* set the mac address */ + writel(macaddr[0] | (macaddr[1] << 8), &emac_p->sa2.raw); + writel(macaddr[2] | (macaddr[3] << 8), &emac_p->sa1.raw); + writel(macaddr[4] | (macaddr[5] << 8), &emac_p->sa0.raw); + + /* default, enable 10 Mbps operation */ + writel(EMAC_RMII_SPD100, &emac_p->supp.clr); + + /* wait until link status UP or deadline elapsed */ + expire = get_ticks() + get_tbclk() * 2; + for (; get_ticks() < expire;) { + stat = phy_read(priv->phydev, priv->phy_addr, MII_BMSR); + if (stat & BMSR_LSTATUS) + break; + } + + if (!(stat & BMSR_LSTATUS)) + printf("MAC: Link is DOWN!\n"); + + /* delay to stabilize before any tx/rx */ + mdelay(10); +} + +static void pic32_mac_reset(struct pic32eth_dev *priv) +{ + struct pic32_emac_regs *emac_p = priv->emac_regs; + struct mii_dev *mii; + + /* Reset MAC */ + writel(EMAC_SOFTRESET, &emac_p->cfg1.raw); + mdelay(10); + + /* clear reset */ + writel(0, &emac_p->cfg1.raw); + + /* Reset MII */ + mii = priv->phydev->bus; + if (mii && mii->reset) + mii->reset(mii); +} + +/* initializes the MAC and PHY, then establishes a link */ +static void pic32_ctrl_reset(struct pic32eth_dev *priv) +{ + struct pic32_ectl_regs *ectl_p = priv->ectl_regs; + u32 v; + + /* disable RX, TX & any other transactions */ + writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); + + /* wait till busy */ + wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false, + CONFIG_SYS_HZ, false); + /* decrement received buffcnt to zero. */ + while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT) + writel(ETHCON_BUFCDEC, &ectl_p->con1.set); + + /* clear any existing interrupt event */ + writel(0xffffffff, &ectl_p->irq.clr); + + /* clear RX/TX start address */ + writel(0xffffffff, &ectl_p->txst.clr); + writel(0xffffffff, &ectl_p->rxst.clr); + + /* clear the receive filters */ + writel(0x00ff, &ectl_p->rxfc.clr); + + /* set the receive filters + * ETH_FILT_CRC_ERR_REJECT + * ETH_FILT_RUNT_REJECT + * ETH_FILT_UCAST_ACCEPT + * ETH_FILT_MCAST_ACCEPT + * ETH_FILT_BCAST_ACCEPT + */ + v = ETHRXFC_BCEN | ETHRXFC_MCEN | ETHRXFC_UCEN | + ETHRXFC_RUNTEN | ETHRXFC_CRCOKEN; + writel(v, &ectl_p->rxfc.set); + + /* turn controller ON to access PHY over MII */ + writel(ETHCON_ON, &ectl_p->con1.set); +} + +static void pic32_rx_desc_init(struct pic32eth_dev *priv) +{ + struct pic32_ectl_regs *ectl_p = priv->ectl_regs; + struct eth_dma_desc *rxd; + u32 idx, bufsz; + + priv->rxd_idx = 0; + for (idx = 0; idx < MAX_RX_DESCR; idx++) { + rxd = &priv->rxd_ring[idx]; + + /* hw owned */ + rxd->hdr = EDH_NPV | EDH_EOWN | EDH_STICKY; + + /* packet buffer address */ + rxd->data_buff = virt_to_phys(net_rx_packets[idx]); + + /* link to next desc */ + rxd->next_ed = virt_to_phys(rxd + 1); + + /* reset status */ + rxd->stat1 = 0; + rxd->stat2 = 0; + + /* decrement bufcnt */ + writel(ETHCON_BUFCDEC, &ectl_p->con1.set); + } + + /* link last descr to beginning of list */ + rxd->next_ed = virt_to_phys(&priv->rxd_ring[0]); + + /* flush rx ring */ + flush_dcache_range((ulong)priv->rxd_ring, + (ulong)priv->rxd_ring + sizeof(priv->rxd_ring)); + + /* set rx desc-ring start address */ + writel((ulong)virt_to_phys(&priv->rxd_ring[0]), &ectl_p->rxst.raw); + + /* RX Buffer size */ + bufsz = readl(&ectl_p->con2.raw); + bufsz &= ~(ETHCON_RXBUFSZ << ETHCON_RXBUFSZ_SHFT); + bufsz |= ((MAX_RX_BUF_SIZE / 16) << ETHCON_RXBUFSZ_SHFT); + writel(bufsz, &ectl_p->con2.raw); + + /* enable the receiver in hardware which allows hardware + * to DMA received pkts to the descriptor pointer address. + */ + writel(ETHCON_RXEN, &ectl_p->con1.set); +} + +static int pic32_eth_start(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct pic32eth_dev *priv = dev_get_priv(dev); + + /* controller */ + pic32_ctrl_reset(priv); + + /* reset MAC */ + pic32_mac_reset(priv); + + /* configure PHY */ + phy_config(priv->phydev); + + /* initialize MAC */ + pic32_mac_init(priv, &pdata->enetaddr[0]); + + /* init RX descriptor; TX descriptors are handled in xmit */ + pic32_rx_desc_init(priv); + + /* Start up & update link status of PHY */ + phy_startup(priv->phydev); + + /* adjust mac with phy link status */ + return pic32_mac_adjust_link(priv); +} + +static void pic32_eth_stop(struct udevice *dev) +{ + struct pic32eth_dev *priv = dev_get_priv(dev); + struct pic32_ectl_regs *ectl_p = priv->ectl_regs; + struct pic32_emac_regs *emac_p = priv->emac_regs; + + /* Reset the phy if the controller is enabled */ + if (readl(&ectl_p->con1.raw) & ETHCON_ON) + phy_reset(priv->phydev); + + /* Shut down the PHY */ + phy_shutdown(priv->phydev); + + /* Stop rx/tx */ + writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); + mdelay(10); + + /* reset MAC */ + writel(EMAC_SOFTRESET, &emac_p->cfg1.raw); + + /* clear reset */ + writel(0, &emac_p->cfg1.raw); + mdelay(10); + + /* disable controller */ + writel(ETHCON_ON, &ectl_p->con1.clr); + mdelay(10); + + /* wait until everything is down */ + wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false, + 2 * CONFIG_SYS_HZ, false); + + /* clear any existing interrupt event */ + writel(0xffffffff, &ectl_p->irq.clr); +} + +static int pic32_eth_send(struct udevice *dev, void *packet, int length) +{ + struct pic32eth_dev *priv = dev_get_priv(dev); + struct pic32_ectl_regs *ectl_p = priv->ectl_regs; + struct eth_dma_desc *txd; + u64 deadline; + + txd = &priv->txd_ring[0]; + + /* set proper flags & length in descriptor header */ + txd->hdr = EDH_SOP | EDH_EOP | EDH_EOWN | EDH_BCOUNT(length); + + /* pass buffer address to hardware */ + txd->data_buff = virt_to_phys(packet); + + debug("%s: %d / .hdr %x, .data_buff %x, .stat %x, .nexted %x\n", + __func__, __LINE__, txd->hdr, txd->data_buff, txd->stat2, + txd->next_ed); + + /* cache flush (packet) */ + flush_dcache_range((ulong)packet, (ulong)packet + length); + + /* cache flush (txd) */ + flush_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd)); + + /* pass descriptor table base to h/w */ + writel(virt_to_phys(txd), &ectl_p->txst.raw); + + /* ready to send enabled, hardware can now send the packet(s) */ + writel(ETHCON_TXRTS | ETHCON_ON, &ectl_p->con1.set); + + /* wait until tx has completed and h/w has released ownership + * of the tx descriptor or timeout elapsed. + */ + deadline = get_ticks() + get_tbclk(); + for (;;) { + /* check timeout */ + if (get_ticks() > deadline) + return -ETIMEDOUT; + + if (ctrlc()) + return -EINTR; + + /* tx completed ? */ + if (readl(&ectl_p->con1.raw) & ETHCON_TXRTS) { + udelay(1); + continue; + } + + /* h/w not released ownership yet? */ + invalidate_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd)); + if (!(txd->hdr & EDH_EOWN)) + break; + } + + return 0; +} + +static int pic32_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct pic32eth_dev *priv = dev_get_priv(dev); + struct eth_dma_desc *rxd; + u32 idx = priv->rxd_idx; + u32 rx_count; + + /* find the next ready to receive */ + rxd = &priv->rxd_ring[idx]; + + invalidate_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd)); + /* check if owned by MAC */ + if (rxd->hdr & EDH_EOWN) + return -EAGAIN; + + /* Sanity check on header: SOP and EOP */ + if ((rxd->hdr & (EDH_SOP | EDH_EOP)) != (EDH_SOP | EDH_EOP)) { + printf("%s: %s, rx pkt across multiple descr\n", + __FILE__, __func__); + return 0; + } + + debug("%s: %d /idx %i, hdr=%x, data_buff %x, stat %x, nexted %x\n", + __func__, __LINE__, idx, rxd->hdr, + rxd->data_buff, rxd->stat2, rxd->next_ed); + + /* Sanity check on rx_stat: OK, CRC */ + if (!RSV_RX_OK(rxd->stat2) || RSV_CRC_ERR(rxd->stat2)) { + debug("%s: %s: Error, rx problem detected\n", + __FILE__, __func__); + return 0; + } + + /* invalidate dcache */ + rx_count = RSV_RX_COUNT(rxd->stat2); + invalidate_dcache_range((ulong)net_rx_packets[idx], + (ulong)net_rx_packets[idx] + rx_count); + + /* Pass the packet to protocol layer */ + *packetp = net_rx_packets[idx]; + + /* increment number of bytes rcvd (ignore CRC) */ + return rx_count - 4; +} + +static int pic32_eth_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct pic32eth_dev *priv = dev_get_priv(dev); + struct pic32_ectl_regs *ectl_p = priv->ectl_regs; + struct eth_dma_desc *rxd; + int idx = priv->rxd_idx; + + /* sanity check */ + if (packet != net_rx_packets[idx]) { + printf("rxd_id %d: packet is not matched,\n", idx); + return -EAGAIN; + } + + /* prepare for receive */ + rxd = &priv->rxd_ring[idx]; + rxd->hdr = EDH_STICKY | EDH_NPV | EDH_EOWN; + + flush_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd)); + + /* decrement rx pkt count */ + writel(ETHCON_BUFCDEC, &ectl_p->con1.set); + + debug("%s: %d / idx %i, hdr %x, data_buff %x, stat %x, nexted %x\n", + __func__, __LINE__, idx, rxd->hdr, rxd->data_buff, + rxd->stat2, rxd->next_ed); + + priv->rxd_idx = (priv->rxd_idx + 1) % MAX_RX_DESCR; + + return 0; +} + +static const struct eth_ops pic32_eth_ops = { + .start = pic32_eth_start, + .send = pic32_eth_send, + .recv = pic32_eth_recv, + .free_pkt = pic32_eth_free_pkt, + .stop = pic32_eth_stop, +}; + +static int pic32_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct pic32eth_dev *priv = dev_get_priv(dev); + const char *phy_mode; + void __iomem *iobase; + fdt_addr_t addr; + fdt_size_t size; + int offset = 0; + int phy_addr = -1; + + addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + iobase = ioremap(addr, size); + pdata->iobase = (phys_addr_t)addr; + + /* get phy mode */ + pdata->phy_interface = -1; + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + /* get phy addr */ + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, + "phy-handle"); + if (offset > 0) + phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); + + /* phy reset gpio */ + gpio_request_by_name_nodev(gd->fdt_blob, dev->of_offset, + "reset-gpios", 0, + &priv->rst_gpio, GPIOD_IS_OUT); + + priv->phyif = pdata->phy_interface; + priv->phy_addr = phy_addr; + priv->ectl_regs = iobase; + priv->emac_regs = iobase + PIC32_EMAC1CFG1; + + pic32_mii_init(priv); + + return pic32_phy_init(priv, dev); +} + +static int pic32_eth_remove(struct udevice *dev) +{ + struct pic32eth_dev *priv = dev_get_priv(dev); + struct mii_dev *bus; + + dm_gpio_free(dev, &priv->rst_gpio); + phy_shutdown(priv->phydev); + free(priv->phydev); + bus = miiphy_get_dev_by_name(PIC32_MDIO_NAME); + mdio_unregister(bus); + mdio_free(bus); + iounmap(priv->ectl_regs); + return 0; +} + +static const struct udevice_id pic32_eth_ids[] = { + { .compatible = "microchip,pic32mzda-eth" }, + { } +}; + +U_BOOT_DRIVER(pic32_ethernet) = { + .name = "pic32_ethernet", + .id = UCLASS_ETH, + .of_match = pic32_eth_ids, + .probe = pic32_eth_probe, + .remove = pic32_eth_remove, + .ops = &pic32_eth_ops, + .priv_auto_alloc_size = sizeof(struct pic32eth_dev), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/drivers/net/pic32_eth.h b/drivers/net/pic32_eth.h new file mode 100644 index 0000000000..be2a1872d8 --- /dev/null +++ b/drivers/net/pic32_eth.h @@ -0,0 +1,164 @@ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __MICROCHIP_PIC32_ETH_H_ +#define __MICROCHIP_PIC32_ETH_H_ + +#include <mach/pic32.h> + +/* Ethernet */ +struct pic32_ectl_regs { + struct pic32_reg_atomic con1; /* 0x00 */ + struct pic32_reg_atomic con2; /* 0x10 */ + struct pic32_reg_atomic txst; /* 0x20 */ + struct pic32_reg_atomic rxst; /* 0x30 */ + struct pic32_reg_atomic ht0; /* 0x40 */ + struct pic32_reg_atomic ht1; /* 0x50 */ + struct pic32_reg_atomic pmm0; /* 0x60 */ + struct pic32_reg_atomic pmm1; /* 0x70 */ + struct pic32_reg_atomic pmcs; /* 0x80 */ + struct pic32_reg_atomic pmo; /* 0x90 */ + struct pic32_reg_atomic rxfc; /* 0xa0 */ + struct pic32_reg_atomic rxwm; /* 0xb0 */ + struct pic32_reg_atomic ien; /* 0xc0 */ + struct pic32_reg_atomic irq; /* 0xd0 */ + struct pic32_reg_atomic stat; /* 0xe0 */ +}; + +struct pic32_mii_regs { + struct pic32_reg_atomic mcfg; /* 0x280 */ + struct pic32_reg_atomic mcmd; /* 0x290 */ + struct pic32_reg_atomic madr; /* 0x2a0 */ + struct pic32_reg_atomic mwtd; /* 0x2b0 */ + struct pic32_reg_atomic mrdd; /* 0x2c0 */ + struct pic32_reg_atomic mind; /* 0x2d0 */ +}; + +struct pic32_emac_regs { + struct pic32_reg_atomic cfg1; /* 0x200*/ + struct pic32_reg_atomic cfg2; /* 0x210*/ + struct pic32_reg_atomic ipgt; /* 0x220*/ + struct pic32_reg_atomic ipgr; /* 0x230*/ + struct pic32_reg_atomic clrt; /* 0x240*/ + struct pic32_reg_atomic maxf; /* 0x250*/ + struct pic32_reg_atomic supp; /* 0x260*/ + struct pic32_reg_atomic test; /* 0x270*/ + struct pic32_mii_regs mii; /* 0x280 - 0x2d0 */ + struct pic32_reg_atomic res1; /* 0x2e0 */ + struct pic32_reg_atomic res2; /* 0x2f0 */ + struct pic32_reg_atomic sa0; /* 0x300 */ + struct pic32_reg_atomic sa1; /* 0x310 */ + struct pic32_reg_atomic sa2; /* 0x320 */ +}; + +/* ETHCON1 Reg field */ +#define ETHCON_BUFCDEC BIT(0) +#define ETHCON_RXEN BIT(8) +#define ETHCON_TXRTS BIT(9) +#define ETHCON_ON BIT(15) + +/* ETHCON2 Reg field */ +#define ETHCON_RXBUFSZ 0x7f +#define ETHCON_RXBUFSZ_SHFT 0x4 + +/* ETHSTAT Reg field */ +#define ETHSTAT_BUSY BIT(7) +#define ETHSTAT_BUFCNT 0x00ff0000 + +/* ETHRXFC Register fields */ +#define ETHRXFC_BCEN BIT(0) +#define ETHRXFC_MCEN BIT(1) +#define ETHRXFC_UCEN BIT(3) +#define ETHRXFC_RUNTEN BIT(4) +#define ETHRXFC_CRCOKEN BIT(5) + +/* EMAC1CFG1 register offset */ +#define PIC32_EMAC1CFG1 0x0200 + +/* EMAC1CFG1 register fields */ +#define EMAC_RXENABLE BIT(0) +#define EMAC_RXPAUSE BIT(2) +#define EMAC_TXPAUSE BIT(3) +#define EMAC_SOFTRESET BIT(15) + +/* EMAC1CFG2 register fields */ +#define EMAC_FULLDUP BIT(0) +#define EMAC_LENGTHCK BIT(1) +#define EMAC_CRCENABLE BIT(4) +#define EMAC_PADENABLE BIT(5) +#define EMAC_AUTOPAD BIT(7) +#define EMAC_EXCESS BIT(14) + +/* EMAC1IPGT register magic */ +#define FULLDUP_GAP_TIME 0x15 +#define HALFDUP_GAP_TIME 0x12 + +/* EMAC1SUPP register fields */ +#define EMAC_RMII_SPD100 BIT(8) +#define EMAC_RMII_RESET BIT(11) + +/* MII Management Configuration Register */ +#define MIIMCFG_RSTMGMT BIT(15) +#define MIIMCFG_CLKSEL_DIV40 0x0020 /* 100Mhz / 40 */ + +/* MII Management Command Register */ +#define MIIMCMD_READ BIT(0) +#define MIIMCMD_SCAN BIT(1) + +/* MII Management Address Register */ +#define MIIMADD_REGADDR 0x1f +#define MIIMADD_REGADDR_SHIFT 0 +#define MIIMADD_PHYADDR_SHIFT 8 + +/* MII Management Indicator Register */ +#define MIIMIND_BUSY BIT(0) +#define MIIMIND_NOTVALID BIT(2) +#define MIIMIND_LINKFAIL BIT(3) + +/* Packet Descriptor */ +/* Received Packet Status */ +#define _RSV1_PKT_CSUM 0xffff +#define _RSV2_CRC_ERR BIT(20) +#define _RSV2_LEN_ERR BIT(21) +#define _RSV2_RX_OK BIT(23) +#define _RSV2_RX_COUNT 0xffff + +#define RSV_RX_CSUM(__rsv1) ((__rsv1) & _RSV1_PKT_CSUM) +#define RSV_RX_COUNT(__rsv2) ((__rsv2) & _RSV2_RX_COUNT) +#define RSV_RX_OK(__rsv2) ((__rsv2) & _RSV2_RX_OK) +#define RSV_CRC_ERR(__rsv2) ((__rsv2) & _RSV2_CRC_ERR) + +/* Ethernet Hardware Descriptor Header bits */ +#define EDH_EOWN BIT(7) +#define EDH_NPV BIT(8) +#define EDH_STICKY BIT(9) +#define _EDH_BCOUNT 0x07ff0000 +#define EDH_EOP BIT(30) +#define EDH_SOP BIT(31) +#define EDH_BCOUNT_SHIFT 16 +#define EDH_BCOUNT(len) ((len) << EDH_BCOUNT_SHIFT) + +/* Ethernet Hardware Descriptors + * ref: PIC32 Family Reference Manual Table 35-7 + * This structure represents the layout of the DMA + * memory shared between the CPU and the Ethernet + * controller. + */ +/* TX/RX DMA descriptor */ +struct eth_dma_desc { + u32 hdr; /* header */ + u32 data_buff; /* data buffer address */ + u32 stat1; /* transmit/receive packet status */ + u32 stat2; /* transmit/receive packet status */ + u32 next_ed; /* next descriptor */ +}; + +#define PIC32_MDIO_NAME "PIC32_EMAC" + +int pic32_mdio_init(const char *name, ulong ioaddr); + +#endif /* __MICROCHIP_PIC32_ETH_H_*/ diff --git a/drivers/net/pic32_mdio.c b/drivers/net/pic32_mdio.c new file mode 100644 index 0000000000..578fc96905 --- /dev/null +++ b/drivers/net/pic32_mdio.c @@ -0,0 +1,121 @@ +/* + * pic32_mdio.c: PIC32 MDIO/MII driver, part of pic32_eth.c. + * + * Copyright 2015 Microchip Inc. + * Purna Chandra Mandal <purna.mandal@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <phy.h> +#include <miiphy.h> +#include <errno.h> +#include <wait_bit.h> +#include <asm/io.h> +#include "pic32_eth.h" + +static int pic32_mdio_write(struct mii_dev *bus, + int addr, int dev_addr, + int reg, u16 value) +{ + u32 v; + struct pic32_mii_regs *mii_regs = bus->priv; + + /* Wait for the previous operation to finish */ + wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY, + false, CONFIG_SYS_HZ, true); + + /* Put phyaddr and regaddr into MIIMADD */ + v = (addr << MIIMADD_PHYADDR_SHIFT) | (reg & MIIMADD_REGADDR); + writel(v, &mii_regs->madr.raw); + + /* Initiate a write command */ + writel(value, &mii_regs->mwtd.raw); + + /* Wait 30 clock cycles for busy flag to be set */ + udelay(12); + + /* Wait for write to complete */ + wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY, + false, CONFIG_SYS_HZ, true); + + return 0; +} + +static int pic32_mdio_read(struct mii_dev *bus, int addr, int devaddr, int reg) +{ + u32 v; + struct pic32_mii_regs *mii_regs = bus->priv; + + /* Wait for the previous operation to finish */ + wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY, + false, CONFIG_SYS_HZ, true); + + /* Put phyaddr and regaddr into MIIMADD */ + v = (addr << MIIMADD_PHYADDR_SHIFT) | (reg & MIIMADD_REGADDR); + writel(v, &mii_regs->madr.raw); + + /* Initiate a read command */ + writel(MIIMCMD_READ, &mii_regs->mcmd.raw); + + /* Wait 30 clock cycles for busy flag to be set */ + udelay(12); + + /* Wait for read to complete */ + wait_for_bit(__func__, &mii_regs->mind.raw, + MIIMIND_NOTVALID | MIIMIND_BUSY, + false, CONFIG_SYS_HZ, false); + + /* Clear the command register */ + writel(0, &mii_regs->mcmd.raw); + + /* Grab the value read from the PHY */ + v = readl(&mii_regs->mrdd.raw); + return v; +} + +static int pic32_mdio_reset(struct mii_dev *bus) +{ + struct pic32_mii_regs *mii_regs = bus->priv; + + /* Reset MII (due to new addresses) */ + writel(MIIMCFG_RSTMGMT, &mii_regs->mcfg.raw); + + /* Wait for the operation to finish */ + wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY, + false, CONFIG_SYS_HZ, true); + + /* Clear reset bit */ + writel(0, &mii_regs->mcfg); + + /* Wait for the operation to finish */ + wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY, + false, CONFIG_SYS_HZ, true); + + /* Set the MII Management Clock (MDC) - no faster than 2.5 MHz */ + writel(MIIMCFG_CLKSEL_DIV40, &mii_regs->mcfg.raw); + + /* Wait for the operation to finish */ + wait_for_bit(__func__, &mii_regs->mind.raw, MIIMIND_BUSY, + false, CONFIG_SYS_HZ, true); + return 0; +} + +int pic32_mdio_init(const char *name, ulong ioaddr) +{ + struct mii_dev *bus; + + bus = mdio_alloc(); + if (!bus) { + printf("Failed to allocate PIC32-MDIO bus\n"); + return -ENOMEM; + } + + bus->read = pic32_mdio_read; + bus->write = pic32_mdio_write; + bus->reset = pic32_mdio_reset; + strncpy(bus->name, name, sizeof(bus->name)); + bus->priv = (void *)ioaddr; + + return mdio_register(bus); +} diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 9b09caf8c8..be0f38288f 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -1,18 +1,16 @@ /* * Freescale Three Speed Ethernet Controller driver * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * author Andy Fleming * + * SPDX-License-Identifier: GPL-2.0+ */ #include <config.h> #include <common.h> +#include <dm.h> #include <malloc.h> #include <net.h> #include <command.h> @@ -24,21 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; -#define TX_BUF_CNT 2 - -static uint rx_idx; /* index of the current RX buffer */ -static uint tx_idx; /* index of the current TX buffer */ - -#ifdef __GNUC__ -static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8); -static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8); - -#else -#error "rtx must be 64-bit aligned" -#endif - -static int tsec_send(struct eth_device *dev, void *packet, int length); - +#ifndef CONFIG_DM_ETH /* Default initializations for TSEC controllers. */ static struct tsec_info_struct tsec_info[] = { @@ -64,6 +48,7 @@ static struct tsec_info_struct tsec_info[] = { STD_TSEC_INFO(4), /* TSEC4 */ #endif }; +#endif /* CONFIG_DM_ETH */ #define TBIANA_SETTINGS ( \ TBIANA_ASYMMETRIC_PAUSE \ @@ -84,8 +69,10 @@ static struct tsec_info_struct tsec_info[] = { /* Configure the TBI for SGMII operation */ static void tsec_configure_serdes(struct tsec_private *priv) { - /* Access TBI PHY registers at given TSEC register offset as opposed - * to the register offset used for external PHY accesses */ + /* + * Access TBI PHY registers at given TSEC register offset as opposed + * to the register offset used for external PHY accesses + */ tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), 0, TBI_ANA, TBIANA_SETTINGS); tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), @@ -100,7 +87,8 @@ static void tsec_configure_serdes(struct tsec_private *priv) /* Set the appropriate hash bit for the given addr */ -/* The algorithm works like so: +/* + * The algorithm works like so: * 1) Take the Destination Address (ie the multicast address), and * do a CRC on it (little endian), and reverse the bits of the * result. @@ -111,9 +99,13 @@ static void tsec_configure_serdes(struct tsec_private *priv) * hash index which gaddr register to use, and the 5 other bits * indicate which bit (assuming an IBM numbering scheme, which * for PowerPC (tm) is usually the case) in the register holds - * the entry. */ -static int -tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set) + * the entry. + */ +#ifndef CONFIG_DM_ETH +static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set) +#else +static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int set) +#endif { struct tsec_private *priv = (struct tsec_private *)dev->priv; struct tsec __iomem *regs = priv->regs; @@ -135,7 +127,8 @@ tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set) } #endif /* Multicast TFTP ? */ -/* Initialized required registers to appropriate values, zeroing +/* + * Initialized required registers to appropriate values, zeroing * those we don't care about (unless zero is bad, in which case, * choose a more appropriate value) */ @@ -181,7 +174,8 @@ static void init_registers(struct tsec __iomem *regs) } -/* Configure maccfg2 based on negotiated speed and duplex +/* + * Configure maccfg2 based on negotiated speed and duplex * reported by PHY handling code */ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) @@ -212,7 +206,8 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) case 10: maccfg2 |= MACCFG2_MII; - /* Set R100 bit in all modes although + /* + * Set R100 bit in all modes although * it is only used in RGMII mode */ if (phydev->speed == 100) @@ -231,15 +226,174 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); } +/* + * This returns the status bits of the device. The return value + * is never checked, and this is what the 8260 driver did, so we + * do the same. Presumably, this would be zero if there were no + * errors + */ +#ifndef CONFIG_DM_ETH +static int tsec_send(struct eth_device *dev, void *packet, int length) +#else +static int tsec_send(struct udevice *dev, void *packet, int length) +#endif +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + struct tsec __iomem *regs = priv->regs; + uint16_t status; + int result = 0; + int i; + + /* Find an empty buffer descriptor */ + for (i = 0; + in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY; + i++) { + if (i >= TOUT_LOOP) { + debug("%s: tsec: tx buffers full\n", dev->name); + return result; + } + } + + out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet); + out_be16(&priv->txbd[priv->tx_idx].length, length); + status = in_be16(&priv->txbd[priv->tx_idx].status); + out_be16(&priv->txbd[priv->tx_idx].status, status | + (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT)); + + /* Tell the DMA to go */ + out_be32(®s->tstat, TSTAT_CLEAR_THALT); + + /* Wait for buffer to be transmitted */ + for (i = 0; + in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY; + i++) { + if (i >= TOUT_LOOP) { + debug("%s: tsec: tx error\n", dev->name); + return result; + } + } + + priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT; + result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS; + + return result; +} + +#ifndef CONFIG_DM_ETH +static int tsec_recv(struct eth_device *dev) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + struct tsec __iomem *regs = priv->regs; + + while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) { + int length = in_be16(&priv->rxbd[priv->rx_idx].length); + uint16_t status = in_be16(&priv->rxbd[priv->rx_idx].status); + uchar *packet = net_rx_packets[priv->rx_idx]; + + /* Send the packet up if there were no errors */ + if (!(status & RXBD_STATS)) + net_process_received_packet(packet, length - 4); + else + printf("Got error %x\n", (status & RXBD_STATS)); + + out_be16(&priv->rxbd[priv->rx_idx].length, 0); + + status = RXBD_EMPTY; + /* Set the wrap bit if this is the last element in the list */ + if ((priv->rx_idx + 1) == PKTBUFSRX) + status |= RXBD_WRAP; + out_be16(&priv->rxbd[priv->rx_idx].status, status); + + priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX; + } + + if (in_be32(®s->ievent) & IEVENT_BSY) { + out_be32(®s->ievent, IEVENT_BSY); + out_be32(®s->rstat, RSTAT_CLEAR_RHALT); + } + + return -1; +} +#else +static int tsec_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + struct tsec __iomem *regs = priv->regs; + int ret = -1; + + if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) { + int length = in_be16(&priv->rxbd[priv->rx_idx].length); + uint16_t status = in_be16(&priv->rxbd[priv->rx_idx].status); + uint32_t buf; + + /* Send the packet up if there were no errors */ + if (!(status & RXBD_STATS)) { + buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr); + *packetp = (uchar *)buf; + ret = length - 4; + } else { + printf("Got error %x\n", (status & RXBD_STATS)); + } + } + + if (in_be32(®s->ievent) & IEVENT_BSY) { + out_be32(®s->ievent, IEVENT_BSY); + out_be32(®s->rstat, RSTAT_CLEAR_RHALT); + } + + return ret; +} + +static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + uint16_t status; + + out_be16(&priv->rxbd[priv->rx_idx].length, 0); + + status = RXBD_EMPTY; + /* Set the wrap bit if this is the last element in the list */ + if ((priv->rx_idx + 1) == PKTBUFSRX) + status |= RXBD_WRAP; + out_be16(&priv->rxbd[priv->rx_idx].status, status); + + priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX; + + return 0; +} +#endif + +/* Stop the interface */ +#ifndef CONFIG_DM_ETH +static void tsec_halt(struct eth_device *dev) +#else +static void tsec_halt(struct udevice *dev) +#endif +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + struct tsec __iomem *regs = priv->regs; + + clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); + setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); + + while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) + != (IEVENT_GRSC | IEVENT_GTSC)) + ; + + clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN); + + /* Shut down the PHY, as needed */ + phy_shutdown(priv->phydev); +} + #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 /* * When MACCFG1[Rx_EN] is enabled during system boot as part * of the eTSEC port initialization sequence, * the eTSEC Rx logic may not be properly initialized. */ -void redundant_init(struct eth_device *dev) +void redundant_init(struct tsec_private *priv) { - struct tsec_private *priv = dev->priv; struct tsec __iomem *regs = priv->regs; uint t, count = 0; int fail = 1; @@ -274,25 +428,27 @@ void redundant_init(struct eth_device *dev) do { uint16_t status; - tsec_send(dev, (void *)pkt, sizeof(pkt)); + tsec_send(priv->dev, (void *)pkt, sizeof(pkt)); /* Wait for buffer to be received */ - for (t = 0; in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY; t++) { + for (t = 0; + in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY; + t++) { if (t >= 10 * TOUT_LOOP) { - printf("%s: tsec: rx error\n", dev->name); + printf("%s: tsec: rx error\n", priv->dev->name); break; } } - if (!memcmp(pkt, (void *)net_rx_packets[rx_idx], sizeof(pkt))) + if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt))) fail = 0; - out_be16(&rxbd[rx_idx].length, 0); + out_be16(&priv->rxbd[priv->rx_idx].length, 0); status = RXBD_EMPTY; - if ((rx_idx + 1) == PKTBUFSRX) + if ((priv->rx_idx + 1) == PKTBUFSRX) status |= RXBD_WRAP; - out_be16(&rxbd[rx_idx].status, status); - rx_idx = (rx_idx + 1) % PKTBUFSRX; + out_be16(&priv->rxbd[priv->rx_idx].status, status); + priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX; if (in_be32(®s->ievent) & IEVENT_BSY) { out_be32(®s->ievent, IEVENT_BSY); @@ -315,49 +471,49 @@ void redundant_init(struct eth_device *dev) } #endif -/* Set up the buffers and their descriptors, and bring up the +/* + * Set up the buffers and their descriptors, and bring up the * interface */ -static void startup_tsec(struct eth_device *dev) +static void startup_tsec(struct tsec_private *priv) { - struct tsec_private *priv = (struct tsec_private *)dev->priv; struct tsec __iomem *regs = priv->regs; uint16_t status; int i; /* reset the indices to zero */ - rx_idx = 0; - tx_idx = 0; + priv->rx_idx = 0; + priv->tx_idx = 0; #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 uint svr; #endif /* Point to the buffer descriptors */ - out_be32(®s->tbase, (u32)&txbd[0]); - out_be32(®s->rbase, (u32)&rxbd[0]); + out_be32(®s->tbase, (u32)&priv->txbd[0]); + out_be32(®s->rbase, (u32)&priv->rxbd[0]); /* Initialize the Rx Buffer descriptors */ for (i = 0; i < PKTBUFSRX; i++) { - out_be16(&rxbd[i].status, RXBD_EMPTY); - out_be16(&rxbd[i].length, 0); - out_be32(&rxbd[i].bufptr, (u32)net_rx_packets[i]); + out_be16(&priv->rxbd[i].status, RXBD_EMPTY); + out_be16(&priv->rxbd[i].length, 0); + out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]); } - status = in_be16(&rxbd[PKTBUFSRX - 1].status); - out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP); + status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status); + out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP); /* Initialize the TX Buffer Descriptors */ for (i = 0; i < TX_BUF_CNT; i++) { - out_be16(&txbd[i].status, 0); - out_be16(&txbd[i].length, 0); - out_be32(&txbd[i].bufptr, 0); + out_be16(&priv->txbd[i].status, 0); + out_be16(&priv->txbd[i].length, 0); + out_be32(&priv->txbd[i].bufptr, 0); } - status = in_be16(&txbd[TX_BUF_CNT - 1].status); - out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP); + status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status); + out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP); #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 svr = get_svr(); if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) - redundant_init(dev); + redundant_init(priv); #endif /* Enable Transmit and Receive */ setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); @@ -369,113 +525,22 @@ static void startup_tsec(struct eth_device *dev) clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); } -/* This returns the status bits of the device. The return value - * is never checked, and this is what the 8260 driver did, so we - * do the same. Presumably, this would be zero if there were no - * errors - */ -static int tsec_send(struct eth_device *dev, void *packet, int length) -{ - struct tsec_private *priv = (struct tsec_private *)dev->priv; - struct tsec __iomem *regs = priv->regs; - uint16_t status; - int result = 0; - int i; - - /* Find an empty buffer descriptor */ - for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) { - if (i >= TOUT_LOOP) { - debug("%s: tsec: tx buffers full\n", dev->name); - return result; - } - } - - out_be32(&txbd[tx_idx].bufptr, (u32)packet); - out_be16(&txbd[tx_idx].length, length); - status = in_be16(&txbd[tx_idx].status); - out_be16(&txbd[tx_idx].status, status | - (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT)); - - /* Tell the DMA to go */ - out_be32(®s->tstat, TSTAT_CLEAR_THALT); - - /* Wait for buffer to be transmitted */ - for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) { - if (i >= TOUT_LOOP) { - debug("%s: tsec: tx error\n", dev->name); - return result; - } - } - - tx_idx = (tx_idx + 1) % TX_BUF_CNT; - result = in_be16(&txbd[tx_idx].status) & TXBD_STATS; - - return result; -} - -static int tsec_recv(struct eth_device *dev) -{ - struct tsec_private *priv = (struct tsec_private *)dev->priv; - struct tsec __iomem *regs = priv->regs; - - while (!(in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY)) { - int length = in_be16(&rxbd[rx_idx].length); - uint16_t status = in_be16(&rxbd[rx_idx].status); - - /* Send the packet up if there were no errors */ - if (!(status & RXBD_STATS)) - net_process_received_packet(net_rx_packets[rx_idx], - length - 4); - else - printf("Got error %x\n", (status & RXBD_STATS)); - - out_be16(&rxbd[rx_idx].length, 0); - - status = RXBD_EMPTY; - /* Set the wrap bit if this is the last element in the list */ - if ((rx_idx + 1) == PKTBUFSRX) - status |= RXBD_WRAP; - out_be16(&rxbd[rx_idx].status, status); - - rx_idx = (rx_idx + 1) % PKTBUFSRX; - } - - if (in_be32(®s->ievent) & IEVENT_BSY) { - out_be32(®s->ievent, IEVENT_BSY); - out_be32(®s->rstat, RSTAT_CLEAR_RHALT); - } - - return -1; - -} - -/* Stop the interface */ -static void tsec_halt(struct eth_device *dev) -{ - struct tsec_private *priv = (struct tsec_private *)dev->priv; - struct tsec __iomem *regs = priv->regs; - - clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); - setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); - - while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) - != (IEVENT_GRSC | IEVENT_GTSC)) - ; - - clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN); - - /* Shut down the PHY, as needed */ - phy_shutdown(priv->phydev); -} - -/* Initializes data structures and registers for the controller, - * and brings the interface up. Returns the link status, meaning +/* + * Initializes data structures and registers for the controller, + * and brings the interface up. Returns the link status, meaning * that it returns success if the link is up, failure otherwise. - * This allows u-boot to find the first active controller. + * This allows U-Boot to find the first active controller. */ +#ifndef CONFIG_DM_ETH static int tsec_init(struct eth_device *dev, bd_t * bd) +#else +static int tsec_init(struct udevice *dev) +#endif { struct tsec_private *priv = (struct tsec_private *)dev->priv; +#ifdef CONFIG_DM_ETH + struct eth_pdata *pdata = dev_get_platdata(dev); +#endif struct tsec __iomem *regs = priv->regs; u32 tempval; int ret; @@ -489,17 +554,27 @@ static int tsec_init(struct eth_device *dev, bd_t * bd) /* Init ECNTRL */ out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS); - /* Copy the station address into the address registers. + /* + * Copy the station address into the address registers. * For a station address of 0x12345678ABCD in transmission * order (BE), MACnADDR1 is set to 0xCDAB7856 and * MACnADDR2 is set to 0x34120000. */ +#ifndef CONFIG_DM_ETH tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) | (dev->enetaddr[3] << 8) | dev->enetaddr[2]; +#else + tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) | + (pdata->enetaddr[3] << 8) | pdata->enetaddr[2]; +#endif out_be32(®s->macstnaddr1, tempval); +#ifndef CONFIG_DM_ETH tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16); +#else + tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16); +#endif out_be32(®s->macstnaddr2, tempval); @@ -507,7 +582,7 @@ static int tsec_init(struct eth_device *dev, bd_t * bd) init_registers(regs); /* Ready the device for tx/rx */ - startup_tsec(dev); + startup_tsec(priv); /* Start up the PHY */ ret = phy_startup(priv->phydev); @@ -551,8 +626,8 @@ static phy_interface_t tsec_get_interface(struct tsec_private *priv) * be set by the platform code. */ if ((interface == PHY_INTERFACE_MODE_RGMII_ID) || - (interface == PHY_INTERFACE_MODE_RGMII_TXID) || - (interface == PHY_INTERFACE_MODE_RGMII_RXID)) + (interface == PHY_INTERFACE_MODE_RGMII_TXID) || + (interface == PHY_INTERFACE_MODE_RGMII_RXID)) return interface; return PHY_INTERFACE_MODE_RGMII; @@ -565,14 +640,13 @@ static phy_interface_t tsec_get_interface(struct tsec_private *priv) return PHY_INTERFACE_MODE_MII; } - -/* Discover which PHY is attached to the device, and configure it +/* + * Discover which PHY is attached to the device, and configure it * properly. If the PHY is not recognized, then return 0 * (failure). Otherwise, return 1 */ -static int init_phy(struct eth_device *dev) +static int init_phy(struct tsec_private *priv) { - struct tsec_private *priv = (struct tsec_private *)dev->priv; struct phy_device *phydev; struct tsec __iomem *regs = priv->regs; u32 supported = (SUPPORTED_10baseT_Half | @@ -584,14 +658,15 @@ static int init_phy(struct eth_device *dev) supported |= SUPPORTED_1000baseT_Full; /* Assign a Physical address to the TBI */ - out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); + out_be32(®s->tbipa, priv->tbiaddr); priv->interface = tsec_get_interface(priv); if (priv->interface == PHY_INTERFACE_MODE_SGMII) tsec_configure_serdes(priv); - phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); + phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev, + priv->interface); if (!phydev) return 0; @@ -605,7 +680,9 @@ static int init_phy(struct eth_device *dev) return 1; } -/* Initialize device structure. Returns success if PHY +#ifndef CONFIG_DM_ETH +/* + * Initialize device structure. Returns success if PHY * initialization succeeded (i.e. if it recognizes the PHY) */ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) @@ -630,11 +707,13 @@ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) priv->phyregs_sgmii = tsec_info->miiregs_sgmii; priv->phyaddr = tsec_info->phyaddr; + priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE; priv->flags = tsec_info->flags; strcpy(dev->name, tsec_info->devname); priv->interface = tsec_info->interface; priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname); + priv->dev = dev; dev->iobase = 0; dev->priv = priv; dev->init = tsec_init; @@ -645,7 +724,7 @@ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) dev->mcast = tsec_mcast_addr; #endif - /* Tell u-boot to get the addr from the env */ + /* Tell U-Boot to get the addr from the env */ for (i = 0; i < 6; i++) dev->enetaddr[i] = 0; @@ -657,7 +736,7 @@ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); /* Try to initialize PHY here, and return */ - return init_phy(dev); + return init_phy(priv); } /* @@ -690,3 +769,118 @@ int tsec_standard_init(bd_t *bis) return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); } +#else /* CONFIG_DM_ETH */ +int tsec_probe(struct udevice *dev) +{ + struct tsec_private *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + struct fsl_pq_mdio_info mdio_info; + int offset = 0; + int reg; + const char *phy_mode; + int ret; + + pdata->iobase = (phys_addr_t)dev_get_addr(dev); + priv->regs = (struct tsec *)pdata->iobase; + + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, + "phy-handle"); + if (offset > 0) { + reg = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0); + priv->phyaddr = reg; + } else { + debug("phy-handle does not exist under tsec %s\n", dev->name); + return -ENOENT; + } + + offset = fdt_parent_offset(gd->fdt_blob, offset); + if (offset > 0) { + reg = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0); + priv->phyregs_sgmii = (struct tsec_mii_mng *)(reg + 0x520); + } else { + debug("No parent node for PHY?\n"); + return -ENOENT; + } + + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, + "tbi-handle"); + if (offset > 0) { + reg = fdtdec_get_int(gd->fdt_blob, offset, "reg", + CONFIG_SYS_TBIPA_VALUE); + priv->tbiaddr = reg; + } else { + priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE; + } + + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, + "phy-connection-type", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("Invalid PHY interface '%s'\n", phy_mode); + return -EINVAL; + } + priv->interface = pdata->phy_interface; + + /* Initialize flags */ + priv->flags = TSEC_GIGABIT; + if (priv->interface == PHY_INTERFACE_MODE_SGMII) + priv->flags |= TSEC_SGMII; + + mdio_info.regs = priv->phyregs_sgmii; + mdio_info.name = (char *)dev->name; + ret = fsl_pq_mdio_init(NULL, &mdio_info); + if (ret) + return ret; + + /* Reset the MAC */ + setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); + udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ + clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); + + priv->dev = dev; + priv->bus = miiphy_get_dev_by_name(dev->name); + + /* Try to initialize PHY here, and return */ + return !init_phy(priv); +} + +int tsec_remove(struct udevice *dev) +{ + struct tsec_private *priv = dev->priv; + + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); + + return 0; +} + +static const struct eth_ops tsec_ops = { + .start = tsec_init, + .send = tsec_send, + .recv = tsec_recv, + .free_pkt = tsec_free_pkt, + .stop = tsec_halt, +#ifdef CONFIG_MCAST_TFTP + .mcast = tsec_mcast_addr, +#endif +}; + +static const struct udevice_id tsec_ids[] = { + { .compatible = "fsl,tsec" }, + { } +}; + +U_BOOT_DRIVER(eth_tsec) = { + .name = "tsec", + .id = UCLASS_ETH, + .of_match = tsec_ids, + .probe = tsec_probe, + .remove = tsec_remove, + .ops = &tsec_ops, + .priv_auto_alloc_size = sizeof(struct tsec_private), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; +#endif /* CONFIG_DM_ETH */ diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 7595db1acb..44afe14051 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -469,6 +469,47 @@ static void vsc9953_vlan_ingr_fltr_learn_drop(int enable) clrbits_le32(&l2ana_reg->ana.adv_learn, VSC9953_VLAN_CHK); } +enum aggr_code_mode { + AGGR_CODE_RAND = 0, + AGGR_CODE_ALL, /* S/D MAC, IPv4 S/D IP, IPv6 Flow Label, S/D PORT */ +}; + +/* Set aggregation code generation mode */ +static int vsc9953_aggr_code_set(enum aggr_code_mode ac) +{ + int rc; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + switch (ac) { + case AGGR_CODE_RAND: + clrsetbits_le32(&l2ana_reg->common.aggr_cfg, + VSC9953_AC_DMAC_ENA | VSC9953_AC_SMAC_ENA | + VSC9953_AC_IP6_LBL_ENA | + VSC9953_AC_IP6_TCPUDP_ENA | + VSC9953_AC_IP4_SIPDIP_ENA | + VSC9953_AC_IP4_TCPUDP_ENA, VSC9953_AC_RND_ENA); + rc = 0; + break; + case AGGR_CODE_ALL: + clrsetbits_le32(&l2ana_reg->common.aggr_cfg, VSC9953_AC_RND_ENA, + VSC9953_AC_DMAC_ENA | VSC9953_AC_SMAC_ENA | + VSC9953_AC_IP6_LBL_ENA | + VSC9953_AC_IP6_TCPUDP_ENA | + VSC9953_AC_IP4_SIPDIP_ENA | + VSC9953_AC_IP4_TCPUDP_ENA); + rc = 0; + break; + default: + /* unknown mode for aggregation code */ + rc = -EINVAL; + } + + return rc; +} + /* Egress untag modes of a VSC9953 port */ enum egress_untag_mode { EGRESS_UNTAG_ALL = 0, @@ -593,6 +634,25 @@ static void vsc9953_port_all_vlan_egress_untagged_set( vsc9953_port_vlan_egr_untag_set(i, mode); } +static int vsc9953_autoage_time_set(int age_period) +{ + u32 autoage; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + if (age_period < 0 || age_period > VSC9953_AUTOAGE_PERIOD_MASK) + return -EINVAL; + + autoage = bitfield_replace_by_mask(in_le32(&l2ana_reg->ana.auto_age), + VSC9953_AUTOAGE_PERIOD_MASK, + age_period); + out_le32(&l2ana_reg->ana.auto_age, autoage); + + return 0; +} + #ifdef CONFIG_CMD_ETHSW /* Enable/disable status of a VSC9953 port */ @@ -1474,6 +1534,224 @@ static int vsc9953_port_ingress_filtering_get(int port_no) return !!(val & (1 << port_no)); } +/* Get the aggregation group of a port */ +static int vsc9953_port_aggr_grp_get(int port_no, int *aggr_grp) +{ + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + if (!VSC9953_PORT_CHECK(port_no)) + return -EINVAL; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + val = in_le32(&l2ana_reg->port[port_no].port_cfg); + *aggr_grp = bitfield_extract_by_mask(val, + VSC9953_PORT_CFG_PORTID_MASK); + + return 0; +} + +static void vsc9953_aggr_grp_members_get(int aggr_grp, + u8 aggr_membr[VSC9953_MAX_PORTS]) +{ + int port_no; + int aggr_membr_grp; + + for (port_no = 0; port_no < VSC9953_MAX_PORTS; port_no++) { + aggr_membr[port_no] = 0; + + if (vsc9953_port_aggr_grp_get(port_no, &aggr_membr_grp)) + continue; + + if (aggr_grp == aggr_membr_grp) + aggr_membr[port_no] = 1; + } +} + +static void vsc9953_update_dest_members_masks(int port_no, u32 membr_bitfld_old, + u32 membr_bitfld_new) +{ + int i; + u32 pgid; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* + * NOTE: Only the unicast destination masks are updated, since + * we do not support for now Layer-2 multicast entries + */ + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (i == port_no) { + clrsetbits_le32(&l2ana_reg->port_id_tbl.port_grp_id[i], + VSC9953_PGID_PORT_MASK, + membr_bitfld_new); + continue; + } + + pgid = in_le32(&l2ana_reg->port_id_tbl.port_grp_id[i]); + if ((u32)(1 << i) & membr_bitfld_old & VSC9953_PGID_PORT_MASK) + pgid &= ~((u32)(1 << port_no)); + if ((u32)(1 << i) & membr_bitfld_new & VSC9953_PGID_PORT_MASK) + pgid |= ((u32)(1 << port_no)); + + out_le32(&l2ana_reg->port_id_tbl.port_grp_id[i], pgid); + } +} + +static void vsc9953_update_source_members_masks(int port_no, + u32 membr_bitfld_old, + u32 membr_bitfld_new) +{ + int i; + int index; + u32 pgid; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + for (i = 0; i < VSC9953_MAX_PORTS + 1; i++) { + index = PGID_SRC_START + i; + pgid = in_le32(&l2ana_reg->port_id_tbl.port_grp_id[index]); + if (i == port_no) { + pgid = (pgid | VSC9953_PGID_PORT_MASK) & + ~membr_bitfld_new; + out_le32(&l2ana_reg->port_id_tbl.port_grp_id[index], + pgid); + continue; + } + + if ((u32)(1 << i) & membr_bitfld_old & VSC9953_PGID_PORT_MASK) + pgid |= (u32)(1 << port_no); + + if ((u32)(1 << i) & membr_bitfld_new & VSC9953_PGID_PORT_MASK) + pgid &= ~(u32)(1 << port_no); + out_le32(&l2ana_reg->port_id_tbl.port_grp_id[index], pgid); + } +} + +static u32 vsc9953_aggr_mask_get_next(u32 aggr_mask, u32 member_bitfield) +{ + if (!member_bitfield) + return 0; + + if (!(aggr_mask & VSC9953_PGID_PORT_MASK)) + aggr_mask = 1; + else + aggr_mask <<= 1; + + while (!(aggr_mask & member_bitfield)) { + aggr_mask <<= 1; + if (!(aggr_mask & VSC9953_PGID_PORT_MASK)) + aggr_mask = 1; + } + + return aggr_mask; +} + +static void vsc9953_update_aggr_members_masks(int port_no, u32 membr_bitfld_old, + u32 membr_bitfld_new) +{ + int i; + u32 pgid; + u32 aggr_mask_old = 0; + u32 aggr_mask_new = 0; + struct vsc9953_analyzer *l2ana_reg; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + /* Update all the PGID aggregation masks */ + for (i = PGID_AGGR_START; i < PGID_SRC_START; i++) { + pgid = in_le32(&l2ana_reg->port_id_tbl.port_grp_id[i]); + + aggr_mask_old = vsc9953_aggr_mask_get_next(aggr_mask_old, + membr_bitfld_old); + pgid = (pgid & ~membr_bitfld_old) | aggr_mask_old; + + aggr_mask_new = vsc9953_aggr_mask_get_next(aggr_mask_new, + membr_bitfld_new); + pgid = (pgid & ~membr_bitfld_new) | aggr_mask_new; + + out_le32(&l2ana_reg->port_id_tbl.port_grp_id[i], pgid); + } +} + +static u32 vsc9953_aggr_membr_bitfield_get(u8 member[VSC9953_MAX_PORTS]) +{ + int i; + u32 member_bitfield = 0; + + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (member[i]) + member_bitfield |= 1 << i; + } + member_bitfield &= VSC9953_PGID_PORT_MASK; + + return member_bitfield; +} + +static void vsc9953_update_members_masks(int port_no, + u8 member_old[VSC9953_MAX_PORTS], + u8 member_new[VSC9953_MAX_PORTS]) +{ + u32 membr_bitfld_old = vsc9953_aggr_membr_bitfield_get(member_old); + u32 membr_bitfld_new = vsc9953_aggr_membr_bitfield_get(member_new); + + vsc9953_update_dest_members_masks(port_no, membr_bitfld_old, + membr_bitfld_new); + vsc9953_update_source_members_masks(port_no, membr_bitfld_old, + membr_bitfld_new); + vsc9953_update_aggr_members_masks(port_no, membr_bitfld_old, + membr_bitfld_new); +} + +/* Set the aggregation group of a port */ +static int vsc9953_port_aggr_grp_set(int port_no, int aggr_grp) +{ + u8 aggr_membr_old[VSC9953_MAX_PORTS]; + u8 aggr_membr_new[VSC9953_MAX_PORTS]; + int rc; + int aggr_grp_old; + u32 val; + struct vsc9953_analyzer *l2ana_reg; + + if (!VSC9953_PORT_CHECK(port_no) || !VSC9953_PORT_CHECK(aggr_grp)) + return -EINVAL; + + l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + + VSC9953_ANA_OFFSET); + + rc = vsc9953_port_aggr_grp_get(port_no, &aggr_grp_old); + if (rc) + return rc; + + /* get all the members of the old aggregation group */ + vsc9953_aggr_grp_members_get(aggr_grp_old, aggr_membr_old); + + /* get all the members of the same aggregation group */ + vsc9953_aggr_grp_members_get(aggr_grp, aggr_membr_new); + + /* add current port as member to the new aggregation group */ + aggr_membr_old[port_no] = 0; + aggr_membr_new[port_no] = 1; + + /* update masks */ + vsc9953_update_members_masks(port_no, aggr_membr_old, aggr_membr_new); + + /* Change logical port number */ + val = in_le32(&l2ana_reg->port[port_no].port_cfg); + val = bitfield_replace_by_mask(val, + VSC9953_PORT_CFG_PORTID_MASK, aggr_grp); + out_le32(&l2ana_reg->port[port_no].port_cfg, val); + + return 0; +} + static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) { int i; @@ -2064,6 +2342,72 @@ static int vsc9953_ingr_fltr_set_key_func(struct ethsw_command_def *parsed_cmd) return CMD_RET_SUCCESS; } +static int vsc9953_port_aggr_show_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + int aggr_grp; + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + + if (vsc9953_port_aggr_grp_get(parsed_cmd->port, &aggr_grp)) + return CMD_RET_FAILURE; + printf("%7s %10s\n", "Port", "Aggr grp"); + printf("%7d %10d\n", parsed_cmd->port, aggr_grp); + } else { + printf("%7s %10s\n", "Port", "Aggr grp"); + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (vsc9953_port_aggr_grp_get(i, &aggr_grp)) + continue; + printf("%7d %10d\n", i, aggr_grp); + } + } + + return CMD_RET_SUCCESS; +} + +static int vsc9953_port_aggr_set_key_func(struct ethsw_command_def *parsed_cmd) +{ + int i; + + /* Aggregation group number should be set in parsed_cmd->aggr_grp */ + if (parsed_cmd->aggr_grp == ETHSW_CMD_AGGR_GRP_NONE) { + printf("Please set an aggregation group value\n"); + return CMD_RET_FAILURE; + } + + if (!VSC9953_PORT_CHECK(parsed_cmd->aggr_grp)) { + printf("Invalid aggregation group number: %d\n", + parsed_cmd->aggr_grp); + return CMD_RET_FAILURE; + } + + if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { + if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { + printf("Invalid port number: %d\n", parsed_cmd->port); + return CMD_RET_FAILURE; + } + if (vsc9953_port_aggr_grp_set(parsed_cmd->port, + parsed_cmd->aggr_grp)) { + printf("Port %d: failed to set aggr group %d\n", + parsed_cmd->port, parsed_cmd->aggr_grp); + } + } else { + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + if (vsc9953_port_aggr_grp_set(i, + parsed_cmd->aggr_grp)) { + printf("Port %d: failed to set aggr group %d\n", + i, parsed_cmd->aggr_grp); + } + } + } + + return CMD_RET_SUCCESS; +} + static struct ethsw_command_func vsc9953_cmd_func = { .ethsw_name = "L2 Switch VSC9953", .port_enable = &vsc9953_port_status_key_func, @@ -2088,7 +2432,9 @@ static struct ethsw_command_func vsc9953_cmd_func = { .vlan_learn_show = &vsc9953_vlan_learn_show_key_func, .vlan_learn_set = &vsc9953_vlan_learn_set_key_func, .port_ingr_filt_show = &vsc9953_ingr_fltr_show_key_func, - .port_ingr_filt_set = &vsc9953_ingr_fltr_set_key_func + .port_ingr_filt_set = &vsc9953_ingr_fltr_set_key_func, + .port_aggr_show = &vsc9953_port_aggr_show_key_func, + .port_aggr_set = &vsc9953_port_aggr_set_key_func, }; #endif /* CONFIG_CMD_ETHSW */ @@ -2107,6 +2453,10 @@ void vsc9953_default_configuration(void) { int i; + if (vsc9953_autoage_time_set(VSC9953_DEFAULT_AGE_TIME)) + debug("VSC9953: failed to set AGE time to %d\n", + VSC9953_DEFAULT_AGE_TIME); + for (i = 0; i < VSC9953_MAX_VLAN; i++) vsc9953_vlan_table_membership_all_set(i, 0); vsc9953_port_all_vlan_aware_set(1); @@ -2115,6 +2465,8 @@ void vsc9953_default_configuration(void) vsc9953_vlan_table_membership_all_set(1, 1); vsc9953_vlan_ingr_fltr_learn_drop(1); vsc9953_port_all_vlan_egress_untagged_set(EGRESS_UNTAG_PVID_AND_ZERO); + if (vsc9953_aggr_code_set(AGGR_CODE_ALL)) + debug("VSC9953: failed to set default aggregation code mode\n"); } void vsc9953_init(bd_t *bis) diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index df053feee8..81274ee13b 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -8,15 +8,14 @@ #include <config.h> #include <common.h> +#include <dm.h> #include <net.h> #include <malloc.h> #include <asm/io.h> #include <phy.h> #include <miiphy.h> -#if !defined(CONFIG_PHYLIB) -# error AXI_ETHERNET requires PHYLIB -#endif +DECLARE_GLOBAL_DATA_PTR; /* Link setup */ #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ @@ -86,7 +85,8 @@ struct axidma_priv { struct axidma_reg *dmatx; struct axidma_reg *dmarx; int phyaddr; - + struct axi_regs *iobase; + phy_interface_t interface; struct phy_device *phydev; struct mii_dev *bus; }; @@ -147,9 +147,8 @@ struct axi_regs { */ #define PHY_DETECT_MASK 0x1808 -static inline int mdio_wait(struct eth_device *dev) +static inline int mdio_wait(struct axi_regs *regs) { - struct axi_regs *regs = (struct axi_regs *)dev->iobase; u32 timeout = 200; /* Wait till MDIO interface is ready to accept a new transaction. */ @@ -165,13 +164,13 @@ static inline int mdio_wait(struct eth_device *dev) return 0; } -static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum, - u16 *val) +static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum, + u16 *val) { - struct axi_regs *regs = (struct axi_regs *)dev->iobase; + struct axi_regs *regs = priv->iobase; u32 mdioctrlreg = 0; - if (mdio_wait(dev)) + if (mdio_wait(regs)) return 1; mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & @@ -183,7 +182,7 @@ static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum, out_be32(®s->mdio_mcr, mdioctrlreg); - if (mdio_wait(dev)) + if (mdio_wait(regs)) return 1; /* Read data */ @@ -191,13 +190,13 @@ static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum, return 0; } -static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum, - u32 data) +static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum, + u32 data) { - struct axi_regs *regs = (struct axi_regs *)dev->iobase; + struct axi_regs *regs = priv->iobase; u32 mdioctrlreg = 0; - if (mdio_wait(dev)) + if (mdio_wait(regs)) return 1; mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) & @@ -212,19 +211,18 @@ static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum, out_be32(®s->mdio_mcr, mdioctrlreg); - if (mdio_wait(dev)) + if (mdio_wait(regs)) return 1; return 0; } -/* Setting axi emac and phy to proper setting */ -static int setup_phy(struct eth_device *dev) +static int axiemac_phy_init(struct udevice *dev) { u16 phyreg; - u32 i, speed, emmc_reg, ret; - struct axidma_priv *priv = dev->priv; - struct axi_regs *regs = (struct axi_regs *)dev->iobase; + u32 i, ret; + struct axidma_priv *priv = dev_get_priv(dev); + struct axi_regs *regs = priv->iobase; struct phy_device *phydev; u32 supported = SUPPORTED_10baseT_Half | @@ -234,16 +232,19 @@ static int setup_phy(struct eth_device *dev) SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full; + /* Set default MDIO divisor */ + out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK); + if (priv->phyaddr == -1) { /* Detect the PHY address */ for (i = 31; i >= 0; i--) { - ret = phyread(dev, i, PHY_DETECT_REG, &phyreg); + ret = phyread(priv, i, PHY_DETECT_REG, &phyreg); if (!ret && (phyreg != 0xFFFF) && ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { /* Found a valid PHY address */ priv->phyaddr = i; debug("axiemac: Found valid phy address, %x\n", - phyreg); + i); break; } } @@ -256,6 +257,18 @@ static int setup_phy(struct eth_device *dev) phydev->advertising = phydev->supported; priv->phydev = phydev; phy_config(phydev); + + return 0; +} + +/* Setting axi emac and phy to proper setting */ +static int setup_phy(struct udevice *dev) +{ + u32 speed, emmc_reg; + struct axidma_priv *priv = dev_get_priv(dev); + struct axi_regs *regs = priv->iobase; + struct phy_device *phydev = priv->phydev; + if (phy_startup(phydev)) { printf("axiemac: could not initialize PHY %s\n", phydev->dev->name); @@ -299,9 +312,9 @@ static int setup_phy(struct eth_device *dev) } /* STOP DMA transfers */ -static void axiemac_halt(struct eth_device *dev) +static void axiemac_stop(struct udevice *dev) { - struct axidma_priv *priv = dev->priv; + struct axidma_priv *priv = dev_get_priv(dev); u32 temp; /* Stop the hardware */ @@ -316,9 +329,9 @@ static void axiemac_halt(struct eth_device *dev) debug("axiemac: Halted\n"); } -static int axi_ethernet_init(struct eth_device *dev) +static int axi_ethernet_init(struct axidma_priv *priv) { - struct axi_regs *regs = (struct axi_regs *)dev->iobase; + struct axi_regs *regs = priv->iobase; u32 timeout = 200; /* @@ -359,25 +372,26 @@ static int axi_ethernet_init(struct eth_device *dev) return 0; } -static int axiemac_setup_mac(struct eth_device *dev) +static int axiemac_write_hwaddr(struct udevice *dev) { - struct axi_regs *regs = (struct axi_regs *)dev->iobase; + struct eth_pdata *pdata = dev_get_platdata(dev); + struct axidma_priv *priv = dev_get_priv(dev); + struct axi_regs *regs = priv->iobase; /* Set the MAC address */ - int val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) | - (dev->enetaddr[1] << 8) | (dev->enetaddr[0])); + int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) | + (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0])); out_be32(®s->uaw0, val); - val = (dev->enetaddr[5] << 8) | dev->enetaddr[4] ; + val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4]; val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK; out_be32(®s->uaw1, val); return 0; } /* Reset DMA engine */ -static void axi_dma_init(struct eth_device *dev) +static void axi_dma_init(struct axidma_priv *priv) { - struct axidma_priv *priv = dev->priv; u32 timeout = 500; /* Reset the engine so the hardware starts from a known state */ @@ -388,9 +402,9 @@ static void axi_dma_init(struct eth_device *dev) while (timeout--) { /* Check transmit/receive channel */ /* Reset is done when the reset bit is low */ - if (!(in_be32(&priv->dmatx->control) | + if (!((in_be32(&priv->dmatx->control) | in_be32(&priv->dmarx->control)) - & XAXIDMA_CR_RESET_MASK) { + & XAXIDMA_CR_RESET_MASK)) { break; } } @@ -398,10 +412,10 @@ static void axi_dma_init(struct eth_device *dev) printf("%s: Timeout\n", __func__); } -static int axiemac_init(struct eth_device *dev, bd_t * bis) +static int axiemac_start(struct udevice *dev) { - struct axidma_priv *priv = dev->priv; - struct axi_regs *regs = (struct axi_regs *)dev->iobase; + struct axidma_priv *priv = dev_get_priv(dev); + struct axi_regs *regs = priv->iobase; u32 temp; debug("axiemac: Init started\n"); @@ -411,10 +425,10 @@ static int axiemac_init(struct eth_device *dev, bd_t * bis) * reset, and since AXIDMA reset line is connected to AxiEthernet, this * would ensure a reset of AxiEthernet. */ - axi_dma_init(dev); + axi_dma_init(priv); /* Initialize AxiEthernet hardware. */ - if (axi_ethernet_init(dev)) + if (axi_ethernet_init(priv)) return -1; /* Disable all RX interrupts before RxBD space setup */ @@ -452,7 +466,7 @@ static int axiemac_init(struct eth_device *dev, bd_t * bis) /* PHY setup */ if (!setup_phy(dev)) { - axiemac_halt(dev); + axiemac_stop(dev); return -1; } @@ -460,9 +474,9 @@ static int axiemac_init(struct eth_device *dev, bd_t * bis) return 0; } -static int axiemac_send(struct eth_device *dev, void *ptr, int len) +static int axiemac_send(struct udevice *dev, void *ptr, int len) { - struct axidma_priv *priv = dev->priv; + struct axidma_priv *priv = dev_get_priv(dev); u32 timeout; if (len > PKTSIZE_ALIGN) @@ -498,8 +512,8 @@ static int axiemac_send(struct eth_device *dev, void *ptr, int len) /* Wait for transmission to complete */ debug("axiemac: Waiting for tx to be done\n"); timeout = 200; - while (timeout && (!in_be32(&priv->dmatx->status) & - (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) { + while (timeout && (!(in_be32(&priv->dmatx->status) & + (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) { timeout--; udelay(1); } @@ -512,10 +526,9 @@ static int axiemac_send(struct eth_device *dev, void *ptr, int len) return 0; } -static int isrxready(struct eth_device *dev) +static int isrxready(struct axidma_priv *priv) { u32 status; - struct axidma_priv *priv = dev->priv; /* Read pending interrupts */ status = in_be32(&priv->dmarx->status); @@ -533,15 +546,15 @@ static int isrxready(struct eth_device *dev) return 0; } -static int axiemac_recv(struct eth_device *dev) +static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp) { u32 length; - struct axidma_priv *priv = dev->priv; + struct axidma_priv *priv = dev_get_priv(dev); u32 temp; /* Wait for an incoming packet */ - if (!isrxready(dev)) - return 0; + if (!isrxready(priv)) + return -1; debug("axiemac: RX data ready\n"); @@ -554,9 +567,14 @@ static int axiemac_recv(struct eth_device *dev) #ifdef DEBUG print_buffer(&rxframe, &rxframe[0], 1, length, 16); #endif - /* Pass the received frame up for processing */ - if (length) - net_process_received_packet(rxframe, length); + + *packetp = rxframe; + return length; +} + +static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct axidma_priv *priv = dev_get_priv(dev); #ifdef DEBUG /* It is useful to clear buffer to be sure that it is consistent */ @@ -581,76 +599,128 @@ static int axiemac_recv(struct eth_device *dev) debug("axiemac: RX completed, framelength = %d\n", length); - return length; + return 0; } -static int axiemac_miiphy_read(const char *devname, uchar addr, - uchar reg, ushort *val) +static int axiemac_miiphy_read(struct mii_dev *bus, int addr, + int devad, int reg) { - struct eth_device *dev = eth_get_dev(); - u32 ret; + int ret; + u16 value; - ret = phyread(dev, addr, reg, val); - debug("axiemac: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val); - return ret; + ret = phyread(bus->priv, addr, reg, &value); + debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, + value, ret); + return value; } -static int axiemac_miiphy_write(const char *devname, uchar addr, - uchar reg, ushort val) +static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value) { - struct eth_device *dev = eth_get_dev(); - - debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val); - return phywrite(dev, addr, reg, val); + debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value); + return phywrite(bus->priv, addr, reg, value); } -static int axiemac_bus_reset(struct mii_dev *bus) +static int axi_emac_probe(struct udevice *dev) { - debug("axiemac: Bus reset\n"); + struct axidma_priv *priv = dev_get_priv(dev); + int ret; + + priv->bus = mdio_alloc(); + priv->bus->read = axiemac_miiphy_read; + priv->bus->write = axiemac_miiphy_write; + priv->bus->priv = priv; + strcpy(priv->bus->name, "axi_emac"); + + ret = mdio_register(priv->bus); + if (ret) + return ret; + + axiemac_phy_init(dev); + return 0; } -int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, - unsigned long dma_addr) +static int axi_emac_remove(struct udevice *dev) { - struct eth_device *dev; - struct axidma_priv *priv; + struct axidma_priv *priv = dev_get_priv(dev); - dev = calloc(1, sizeof(struct eth_device)); - if (dev == NULL) - return -1; + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); - dev->priv = calloc(1, sizeof(struct axidma_priv)); - if (dev->priv == NULL) { - free(dev); - return -1; - } - priv = dev->priv; + return 0; +} - sprintf(dev->name, "aximac.%lx", base_addr); +static const struct eth_ops axi_emac_ops = { + .start = axiemac_start, + .send = axiemac_send, + .recv = axiemac_recv, + .free_pkt = axiemac_free_pkt, + .stop = axiemac_stop, + .write_hwaddr = axiemac_write_hwaddr, +}; - dev->iobase = base_addr; - priv->dmatx = (struct axidma_reg *)dma_addr; +static int axi_emac_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct axidma_priv *priv = dev_get_priv(dev); + int offset = 0; + const char *phy_mode; + + pdata->iobase = (phys_addr_t)dev_get_addr(dev); + priv->iobase = (struct axi_regs *)pdata->iobase; + + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, + "axistream-connected"); + if (offset <= 0) { + printf("%s: axistream is not found\n", __func__); + return -EINVAL; + } + priv->dmatx = (struct axidma_reg *)fdtdec_get_int(gd->fdt_blob, + offset, "reg", 0); + if (!priv->dmatx) { + printf("%s: axi_dma register space not found\n", __func__); + return -EINVAL; + } /* RX channel offset is 0x30 */ - priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30); - dev->init = axiemac_init; - dev->halt = axiemac_halt; - dev->send = axiemac_send; - dev->recv = axiemac_recv; - dev->write_hwaddr = axiemac_setup_mac; - -#ifdef CONFIG_PHY_ADDR - priv->phyaddr = CONFIG_PHY_ADDR; -#else + priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30); + priv->phyaddr = -1; -#endif - eth_register(dev); + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, + "phy-handle"); + if (offset > 0) + priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); + + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + priv->interface = pdata->phy_interface; + + printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, + priv->phyaddr, phy_string_for_interface(priv->interface)); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) - miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write); - priv->bus = miiphy_get_dev_by_name(dev->name); - priv->bus->reset = axiemac_bus_reset; -#endif - return 1; + return 0; } + +static const struct udevice_id axi_emac_ids[] = { + { .compatible = "xlnx,axi-ethernet-1.00.a" }, + { } +}; + +U_BOOT_DRIVER(axi_emac) = { + .name = "axi_emac", + .id = UCLASS_ETH, + .of_match = axi_emac_ids, + .ofdata_to_platdata = axi_emac_ofdata_to_platdata, + .probe = axi_emac_probe, + .remove = axi_emac_remove, + .ops = &axi_emac_ops, + .priv_auto_alloc_size = sizeof(struct axidma_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 564205df83..5862bf0a7e 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -10,27 +10,25 @@ #include <common.h> #include <net.h> #include <config.h> +#include <dm.h> +#include <console.h> #include <malloc.h> #include <asm/io.h> +#include <phy.h> +#include <miiphy.h> #include <fdtdec.h> +#include <asm-generic/errno.h> +#include <linux/kernel.h> -#undef DEBUG +DECLARE_GLOBAL_DATA_PTR; #define ENET_ADDR_LENGTH 6 - -/* EmacLite constants */ -#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */ -#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ -#define XEL_TSR_OFFSET 0x07FC /* Tx status */ -#define XEL_RSR_OFFSET 0x17FC /* Rx status */ -#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ +#define ETH_FCS_LEN 4 /* Octets in the FCS */ /* Xmit complete */ #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL /* Xmit interrupt enable bit */ #define XEL_TSR_XMIT_IE_MASK 0x00000008UL -/* Buffer is active, SW bit only */ -#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL /* Program the MAC address */ #define XEL_TSR_PROGRAM_MASK 0x00000002UL /* define for programming the MAC address into the EMAC Lite */ @@ -46,14 +44,56 @@ /* Recv interrupt enable bit */ #define XEL_RSR_RECV_IE_MASK 0x00000008UL +/* MDIO Address Register Bit Masks */ +#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ +#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ +#define XEL_MDIOADDR_PHYADR_SHIFT 5 +#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ + +/* MDIO Write Data Register Bit Masks */ +#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ + +/* MDIO Read Data Register Bit Masks */ +#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ + +/* MDIO Control Register Bit Masks */ +#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ +#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ + +struct emaclite_regs { + u32 tx_ping; /* 0x0 - TX Ping buffer */ + u32 reserved1[504]; + u32 mdioaddr; /* 0x7e4 - MDIO Address Register */ + u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */ + u32 mdiord;/* 0x7ec - MDIO Read Data Register */ + u32 mdioctrl; /* 0x7f0 - MDIO Control Register */ + u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */ + u32 global_interrupt; /* 0x7f8 - Global interrupt enable */ + u32 tx_ping_tsr; /* 0x7fc - Tx status */ + u32 tx_pong; /* 0x800 - TX Pong buffer */ + u32 reserved2[508]; + u32 tx_pong_tplr; /* 0xff4 - Tx packet length */ + u32 reserved3; /* 0xff8 */ + u32 tx_pong_tsr; /* 0xffc - Tx status */ + u32 rx_ping; /* 0x1000 - Receive Buffer */ + u32 reserved4[510]; + u32 rx_ping_rsr; /* 0x17fc - Rx status */ + u32 rx_pong; /* 0x1800 - Receive Buffer */ + u32 reserved5[510]; + u32 rx_pong_rsr; /* 0x1ffc - Rx status */ +}; + struct xemaclite { - u32 nexttxbuffertouse; /* Next TX buffer to write to */ - u32 nextrxbuffertouse; /* Next RX buffer to read from */ + bool use_rx_pong_buffer_next; /* Next RX buffer to read from */ u32 txpp; /* TX ping pong buffer */ u32 rxpp; /* RX ping pong buffer */ + int phyaddr; + struct emaclite_regs *regs; + struct phy_device *phydev; + struct mii_dev *bus; }; -static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ +static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */ static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount) { @@ -81,7 +121,7 @@ static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount) *to8ptr++ = *from8ptr++; } -static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount) +static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount) { u32 i; u32 alignbuffer; @@ -107,42 +147,206 @@ static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount) *to32ptr++ = alignbuffer; } -static void emaclite_halt(struct eth_device *dev) +static int wait_for_bit(const char *func, u32 *reg, const u32 mask, + bool set, unsigned int timeout) +{ + u32 val; + unsigned long start = get_timer(0); + + while (1) { + val = readl(reg); + + if (!set) + val = ~val; + + if ((val & mask) == mask) + return 0; + + if (get_timer(start) > timeout) + break; + + if (ctrlc()) { + puts("Abort\n"); + return -EINTR; + } + + udelay(1); + } + + debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", + func, reg, mask, set); + + return -ETIMEDOUT; +} + +static int mdio_wait(struct emaclite_regs *regs) { - debug("eth_halt\n"); + return wait_for_bit(__func__, ®s->mdioctrl, + XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000); } -static int emaclite_init(struct eth_device *dev, bd_t *bis) +static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, + u16 *data) { - struct xemaclite *emaclite = dev->priv; + struct emaclite_regs *regs = emaclite->regs; + + if (mdio_wait(regs)) + return 1; + + u32 ctrl_reg = in_be32(®s->mdioctrl); + out_be32(®s->mdioaddr, XEL_MDIOADDR_OP_MASK | + ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); + out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); + + if (mdio_wait(regs)) + return 1; + + /* Read data */ + *data = in_be32(®s->mdiord); + return 0; +} + +static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, + u16 data) +{ + struct emaclite_regs *regs = emaclite->regs; + + if (mdio_wait(regs)) + return 1; + + /* + * Write the PHY address, register number and clear the OP bit in the + * MDIO Address register and then write the value into the MDIO Write + * Data register. Finally, set the Status bit in the MDIO Control + * register to start a MDIO write transaction. + */ + u32 ctrl_reg = in_be32(®s->mdioctrl); + out_be32(®s->mdioaddr, ~XEL_MDIOADDR_OP_MASK & + ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); + out_be32(®s->mdiowr, data); + out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); + + if (mdio_wait(regs)) + return 1; + + return 0; +} + +static void emaclite_stop(struct udevice *dev) +{ + debug("eth_stop\n"); +} + +/* Use MII register 1 (MII status register) to detect PHY */ +#define PHY_DETECT_REG 1 + +/* Mask used to verify certain PHY features (or register contents) + * in the register above: + * 0x1000: 10Mbps full duplex support + * 0x0800: 10Mbps half duplex support + * 0x0008: Auto-negotiation support + */ +#define PHY_DETECT_MASK 0x1808 + +static int setup_phy(struct udevice *dev) +{ + int i; + u16 phyreg; + struct xemaclite *emaclite = dev_get_priv(dev); + struct phy_device *phydev; + + u32 supported = SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full; + + if (emaclite->phyaddr != -1) { + phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg); + if ((phyreg != 0xFFFF) && + ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { + /* Found a valid PHY address */ + debug("Default phy address %d is valid\n", + emaclite->phyaddr); + } else { + debug("PHY address is not setup correctly %d\n", + emaclite->phyaddr); + emaclite->phyaddr = -1; + } + } + + if (emaclite->phyaddr == -1) { + /* detect the PHY address */ + for (i = 31; i >= 0; i--) { + phyread(emaclite, i, PHY_DETECT_REG, &phyreg); + if ((phyreg != 0xFFFF) && + ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { + /* Found a valid PHY address */ + emaclite->phyaddr = i; + debug("emaclite: Found valid phy address, %d\n", + i); + break; + } + } + } + + /* interface - look at tsec */ + phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev, + PHY_INTERFACE_MODE_MII); + /* + * Phy can support 1000baseT but device NOT that's why phydev->supported + * must be setup for 1000baseT. phydev->advertising setups what speeds + * will be used for autonegotiation where 1000baseT must be disabled. + */ + phydev->supported = supported | SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full; + phydev->advertising = supported; + emaclite->phydev = phydev; + phy_config(phydev); + phy_startup(phydev); + + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return 0; + } + + /* Do not setup anything */ + return 1; +} + +static int emaclite_start(struct udevice *dev) +{ + struct xemaclite *emaclite = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + struct emaclite_regs *regs = emaclite->regs; + debug("EmacLite Initialization Started\n"); /* * TX - TX_PING & TX_PONG initialization */ /* Restart PING TX */ - out_be32 (dev->iobase + XEL_TSR_OFFSET, 0); + out_be32(®s->tx_ping_tsr, 0); /* Copy MAC address */ - xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH); + xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping, + ENET_ADDR_LENGTH); /* Set the length */ - out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); + out_be32(®s->tx_ping_tplr, ENET_ADDR_LENGTH); /* Update the MAC address in the EMAC Lite */ - out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR); + out_be32(®s->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR); /* Wait for EMAC Lite to finish with the MAC address update */ - while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) & + while ((in_be32 (®s->tx_ping_tsr) & XEL_TSR_PROG_MAC_ADDR) != 0) ; if (emaclite->txpp) { /* The same operation with PONG TX */ - out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); - xemaclite_alignedwrite(dev->enetaddr, dev->iobase + - XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH); - out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); - out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, - XEL_TSR_PROG_MAC_ADDR); - while ((in_be32 (dev->iobase + XEL_TSR_OFFSET + - XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) + out_be32(®s->tx_pong_tsr, 0); + xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong, + ENET_ADDR_LENGTH); + out_be32(®s->tx_pong_tplr, ENET_ADDR_LENGTH); + out_be32(®s->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR); + while ((in_be32(®s->tx_pong_tsr) & + XEL_TSR_PROG_MAC_ADDR) != 0) ; } @@ -150,52 +354,48 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) * RX - RX_PING & RX_PONG initialization */ /* Write out the value to flush the RX buffer */ - out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK); + out_be32(®s->rx_ping_rsr, XEL_RSR_RECV_IE_MASK); if (emaclite->rxpp) - out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET, - XEL_RSR_RECV_IE_MASK); + out_be32(®s->rx_pong_rsr, XEL_RSR_RECV_IE_MASK); + + out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); + if (in_be32(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK) + if (!setup_phy(dev)) + return -1; debug("EmacLite Initialization complete\n"); return 0; } -static int xemaclite_txbufferavailable(struct eth_device *dev) +static int xemaclite_txbufferavailable(struct xemaclite *emaclite) { - u32 reg; - u32 txpingbusy; - u32 txpongbusy; - struct xemaclite *emaclite = dev->priv; + u32 tmp; + struct emaclite_regs *regs = emaclite->regs; /* * Read the other buffer register * and determine if the other buffer is available */ - reg = in_be32 (dev->iobase + - emaclite->nexttxbuffertouse + 0); - txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == - XEL_TSR_XMIT_BUSY_MASK); - - reg = in_be32 (dev->iobase + - (emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0); - txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == - XEL_TSR_XMIT_BUSY_MASK); + tmp = ~in_be32(®s->tx_ping_tsr); + if (emaclite->txpp) + tmp |= ~in_be32(®s->tx_pong_tsr); - return !(txpingbusy && txpongbusy); + return !(tmp & XEL_TSR_XMIT_BUSY_MASK); } -static int emaclite_send(struct eth_device *dev, void *ptr, int len) +static int emaclite_send(struct udevice *dev, void *ptr, int len) { u32 reg; - u32 baseaddress; - struct xemaclite *emaclite = dev->priv; + struct xemaclite *emaclite = dev_get_priv(dev); + struct emaclite_regs *regs = emaclite->regs; u32 maxtry = 1000; if (len > PKTSIZE) len = PKTSIZE; - while (!xemaclite_txbufferavailable(dev) && maxtry) { + while (xemaclite_txbufferavailable(emaclite) && maxtry) { udelay(10); maxtry--; } @@ -203,58 +403,40 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) if (!maxtry) { printf("Error: Timeout waiting for ethernet TX buffer\n"); /* Restart PING TX */ - out_be32 (dev->iobase + XEL_TSR_OFFSET, 0); + out_be32(®s->tx_ping_tsr, 0); if (emaclite->txpp) { - out_be32 (dev->iobase + XEL_TSR_OFFSET + - XEL_BUFFER_OFFSET, 0); + out_be32(®s->tx_pong_tsr, 0); } return -1; } - /* Determine the expected TX buffer address */ - baseaddress = (dev->iobase + emaclite->nexttxbuffertouse); - /* Determine if the expected buffer address is empty */ - reg = in_be32 (baseaddress + XEL_TSR_OFFSET); - if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) - && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) - & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { - - if (emaclite->txpp) - emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET; - - debug("Send packet from 0x%x\n", baseaddress); + reg = in_be32(®s->tx_ping_tsr); + if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { + debug("Send packet from tx_ping buffer\n"); /* Write the frame to the buffer */ - xemaclite_alignedwrite(ptr, baseaddress, len); - out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & - (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); - reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + xemaclite_alignedwrite(ptr, ®s->tx_ping, len); + out_be32(®s->tx_ping_tplr, len & + (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)); + reg = in_be32(®s->tx_ping_tsr); reg |= XEL_TSR_XMIT_BUSY_MASK; - if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) - reg |= XEL_TSR_XMIT_ACTIVE_MASK; - out_be32 (baseaddress + XEL_TSR_OFFSET, reg); + out_be32(®s->tx_ping_tsr, reg); return 0; } if (emaclite->txpp) { - /* Switch to second buffer */ - baseaddress ^= XEL_BUFFER_OFFSET; /* Determine if the expected buffer address is empty */ - reg = in_be32 (baseaddress + XEL_TSR_OFFSET); - if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) - && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) - & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { - debug("Send packet from 0x%x\n", baseaddress); + reg = in_be32(®s->tx_pong_tsr); + if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { + debug("Send packet from tx_pong buffer\n"); /* Write the frame to the buffer */ - xemaclite_alignedwrite(ptr, baseaddress, len); - out_be32 (baseaddress + XEL_TPLR_OFFSET, (len & - (XEL_TPLR_LENGTH_MASK_HI | - XEL_TPLR_LENGTH_MASK_LO))); - reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + xemaclite_alignedwrite(ptr, ®s->tx_pong, len); + out_be32(®s->tx_pong_tplr, len & + (XEL_TPLR_LENGTH_MASK_HI | + XEL_TPLR_LENGTH_MASK_LO)); + reg = in_be32(®s->tx_pong_tsr); reg |= XEL_TSR_XMIT_BUSY_MASK; - if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) - reg |= XEL_TSR_XMIT_ACTIVE_MASK; - out_be32 (baseaddress + XEL_TSR_OFFSET, reg); + out_be32(®s->tx_pong_tsr, reg); return 0; } } @@ -263,130 +445,188 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) return -1; } -static int emaclite_recv(struct eth_device *dev) +static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp) { - u32 length; - u32 reg; - u32 baseaddress; + u32 length, first_read, reg, attempt = 0; + void *addr, *ack; struct xemaclite *emaclite = dev->priv; + struct emaclite_regs *regs = emaclite->regs; + struct ethernet_hdr *eth; + struct ip_udp_hdr *ip; + +try_again: + if (!emaclite->use_rx_pong_buffer_next) { + reg = in_be32(®s->rx_ping_rsr); + debug("Testing data at rx_ping\n"); + if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { + debug("Data found in rx_ping buffer\n"); + addr = ®s->rx_ping; + ack = ®s->rx_ping_rsr; + } else { + debug("Data not found in rx_ping buffer\n"); + /* Pong buffer is not available - return immediately */ + if (!emaclite->rxpp) + return -1; - baseaddress = dev->iobase + emaclite->nextrxbuffertouse; - reg = in_be32 (baseaddress + XEL_RSR_OFFSET); - debug("Testing data at address 0x%x\n", baseaddress); - if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { - if (emaclite->rxpp) - emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET; + /* Try pong buffer if this is first attempt */ + if (attempt++) + return -1; + emaclite->use_rx_pong_buffer_next = + !emaclite->use_rx_pong_buffer_next; + goto try_again; + } } else { - - if (!emaclite->rxpp) { - debug("No data was available - address 0x%x\n", - baseaddress); - return 0; + reg = in_be32(®s->rx_pong_rsr); + debug("Testing data at rx_pong\n"); + if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { + debug("Data found in rx_pong buffer\n"); + addr = ®s->rx_pong; + ack = ®s->rx_pong_rsr; } else { - baseaddress ^= XEL_BUFFER_OFFSET; - reg = in_be32 (baseaddress + XEL_RSR_OFFSET); - if ((reg & XEL_RSR_RECV_DONE_MASK) != - XEL_RSR_RECV_DONE_MASK) { - debug("No data was available - address 0x%x\n", - baseaddress); - return 0; - } + debug("Data not found in rx_pong buffer\n"); + /* Try ping buffer if this is first attempt */ + if (attempt++) + return -1; + emaclite->use_rx_pong_buffer_next = + !emaclite->use_rx_pong_buffer_next; + goto try_again; } } - /* Get the length of the frame that arrived */ - switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) & - 0xFFFF0000 ) >> 16) { - case 0x806: - length = 42 + 20; /* FIXME size of ARP */ - debug("ARP Packet\n"); - break; - case 0x800: - length = 14 + 14 + - (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + - 0x10))) & 0xFFFF0000) >> 16); - /* FIXME size of IP packet */ - debug ("IP Packet\n"); - break; - default: - debug("Other Packet\n"); - length = PKTSIZE; - break; + + /* Read all bytes for ARP packet with 32bit alignment - 48bytes */ + first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4); + xemaclite_alignedread(addr, etherrxbuff, first_read); + + /* Detect real packet size */ + eth = (struct ethernet_hdr *)etherrxbuff; + switch (ntohs(eth->et_protlen)) { + case PROT_ARP: + length = first_read; + debug("ARP Packet %x\n", length); + break; + case PROT_IP: + ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE); + length = ntohs(ip->ip_len); + length += ETHER_HDR_SIZE + ETH_FCS_LEN; + debug("IP Packet %x\n", length); + break; + default: + debug("Other Packet\n"); + length = PKTSIZE; + break; } - xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET), - etherrxbuff, length); + /* Read the rest of the packet which is longer then first read */ + if (length != first_read) + xemaclite_alignedread(addr + first_read, + etherrxbuff + first_read, + length - first_read); /* Acknowledge the frame */ - reg = in_be32 (baseaddress + XEL_RSR_OFFSET); + reg = in_be32(ack); reg &= ~XEL_RSR_RECV_DONE_MASK; - out_be32 (baseaddress + XEL_RSR_OFFSET, reg); + out_be32(ack, reg); - debug("Packet receive from 0x%x, length %dB\n", baseaddress, length); - net_process_received_packet((uchar *)etherrxbuff, length); + debug("Packet receive from 0x%p, length %dB\n", addr, length); + *packetp = etherrxbuff; return length; - } -int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, - int txpp, int rxpp) +static int emaclite_miiphy_read(struct mii_dev *bus, int addr, + int devad, int reg) { - struct eth_device *dev; - struct xemaclite *emaclite; + u32 ret; + u16 val = 0; - dev = calloc(1, sizeof(*dev)); - if (dev == NULL) - return -1; + ret = phyread(bus->priv, addr, reg, &val); + debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret); + return val; +} - emaclite = calloc(1, sizeof(struct xemaclite)); - if (emaclite == NULL) { - free(dev); - return -1; - } +static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value) +{ + debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value); + return phywrite(bus->priv, addr, reg, value); +} + +static int emaclite_probe(struct udevice *dev) +{ + struct xemaclite *emaclite = dev_get_priv(dev); + int ret; - dev->priv = emaclite; + emaclite->bus = mdio_alloc(); + emaclite->bus->read = emaclite_miiphy_read; + emaclite->bus->write = emaclite_miiphy_write; + emaclite->bus->priv = emaclite; + strcpy(emaclite->bus->name, "emaclite"); - emaclite->txpp = txpp; - emaclite->rxpp = rxpp; + ret = mdio_register(emaclite->bus); + if (ret) + return ret; - sprintf(dev->name, "Xelite.%lx", base_addr); + return 0; +} - dev->iobase = base_addr; - dev->init = emaclite_init; - dev->halt = emaclite_halt; - dev->send = emaclite_send; - dev->recv = emaclite_recv; +static int emaclite_remove(struct udevice *dev) +{ + struct xemaclite *emaclite = dev_get_priv(dev); - eth_register(dev); + free(emaclite->phydev); + mdio_unregister(emaclite->bus); + mdio_free(emaclite->bus); - return 1; + return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) -int xilinx_emaclite_of_init(const void *blob) +static const struct eth_ops emaclite_ops = { + .start = emaclite_start, + .send = emaclite_send, + .recv = emaclite_recv, + .stop = emaclite_stop, +}; + +static int emaclite_ofdata_to_platdata(struct udevice *dev) { + struct eth_pdata *pdata = dev_get_platdata(dev); + struct xemaclite *emaclite = dev_get_priv(dev); int offset = 0; - u32 ret = 0; - u32 reg; - do { - offset = fdt_node_offset_by_compatible(blob, offset, - "xlnx,xps-ethernetlite-1.00.a"); - if (offset != -1) { - reg = fdtdec_get_addr(blob, offset, "reg"); - if (reg != FDT_ADDR_T_NONE) { - u32 rxpp = fdtdec_get_int(blob, offset, - "xlnx,rx-ping-pong", 0); - u32 txpp = fdtdec_get_int(blob, offset, - "xlnx,tx-ping-pong", 0); - ret |= xilinx_emaclite_initialize(NULL, reg, - txpp, rxpp); - } else { - debug("EMACLITE: Can't get base address\n"); - return -1; - } - } - } while (offset != -1); + pdata->iobase = (phys_addr_t)dev_get_addr(dev); + emaclite->regs = (struct emaclite_regs *)pdata->iobase; + + emaclite->phyaddr = -1; + + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, + "phy-handle"); + if (offset > 0) + emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, + "reg", -1); + + emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "xlnx,tx-ping-pong", 0); + emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "xlnx,rx-ping-pong", 0); - return ret; + printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs, + emaclite->phyaddr, emaclite->txpp, emaclite->rxpp); + + return 0; } -#endif + +static const struct udevice_id emaclite_ids[] = { + { .compatible = "xlnx,xps-ethernetlite-1.00.a" }, + { } +}; + +U_BOOT_DRIVER(emaclite) = { + .name = "emaclite", + .id = UCLASS_ETH, + .of_match = emaclite_ids, + .ofdata_to_platdata = emaclite_ofdata_to_platdata, + .probe = emaclite_probe, + .remove = emaclite_remove, + .ops = &emaclite_ops, + .priv_auto_alloc_size = sizeof(struct xemaclite), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/drivers/net/xilinx_ll_temac.c b/drivers/net/xilinx_ll_temac.c index 7cc86571e4..ca09546ab5 100644 --- a/drivers/net/xilinx_ll_temac.c +++ b/drivers/net/xilinx_ll_temac.c @@ -303,7 +303,8 @@ int xilinx_ll_temac_initialize(bd_t *bis, struct ll_temac_info *devinf) if (devinf->devname) { strncpy(dev->name, devinf->devname, sizeof(dev->name)); } else { - snprintf(dev->name, sizeof(dev->name), "lltemac.%lx", devinf->base_addr); + snprintf(dev->name, sizeof(dev->name), "ll_tem.%lx", + devinf->base_addr); devinf->devname = dev->name; } diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 97e30f3be0..b3821c31a9 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -57,7 +57,11 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ +#ifdef CONFIG_ARM64 +#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000100000 /* Div pclk by 64, max 160MHz */ +#else #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ +#endif #ifdef CONFIG_ARM64 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 61292d72bd..d01bfc12e4 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1241,3 +1241,18 @@ U_BOOT_DRIVER(pci_generic_drv) = { .id = UCLASS_PCI_GENERIC, .of_match = pci_generic_ids, }; + +void pci_init(void) +{ + struct udevice *bus; + + /* + * Enumerate all known controller devices. Enumeration has the side- + * effect of probing them, so PCIe devices will be enumerated too. + */ + for (uclass_first_device(UCLASS_PCI, &bus); + bus; + uclass_next_device(&bus)) { + ; + } +} diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index 5a7fefed5e..5dadf6fa62 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -465,7 +465,11 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id, return err; } - tegra_pcie_board_init(); + err = tegra_pcie_board_init(); + if (err < 0) { + error("tegra_pcie_board_init() failed: err=%d", err); + return err; + } pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE); if (pcie->phy) { diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 57e6142c50..5dd2dddb44 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -131,6 +131,16 @@ config PINCTRL_SANDBOX actually does nothing but print debug messages when pinctrl operations are invoked. +config PIC32_PINCTRL + bool "Microchip PIC32 pin-control and pin-mux driver" + depends on DM && MACH_PIC32 + default y + help + Supports individual pin selection and configuration for each remappable + peripheral available on Microchip PIC32 SoCs. This driver is controlled + by a device tree node which contains both GPIO defintion and pin control + functions. + endif source "drivers/pinctrl/uniphier/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 70d25dc981..b4f46500eb 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/ +obj-$(CONFIG_PIC32_PINCTRL) += pinctrl_pic32.o diff --git a/drivers/pinctrl/pinctrl_pic32.c b/drivers/pinctrl/pinctrl_pic32.c new file mode 100644 index 0000000000..5cf97ecec8 --- /dev/null +++ b/drivers/pinctrl/pinctrl_pic32.c @@ -0,0 +1,363 @@ +/* + * Pinctrl driver for Microchip PIC32 SoCs + * Copyright (c) 2015 Microchip Technology Inc. + * Written by Purna Chandra Mandal <purna.mandal@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <asm/io.h> +#include <dm/pinctrl.h> +#include <dm/root.h> +#include <mach/pic32.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* PIC32 has 10 peripheral ports with 16 pins each. + * Ports are marked PORTA-PORTK or PORT0-PORT9. + */ +enum { + PIC32_PORT_A = 0, + PIC32_PORT_B = 1, + PIC32_PORT_C = 2, + PIC32_PORT_D = 3, + PIC32_PORT_E = 4, + PIC32_PORT_F = 5, + PIC32_PORT_G = 6, + PIC32_PORT_H = 7, + PIC32_PORT_J = 8, /* no PORT_I */ + PIC32_PORT_K = 9, + PIC32_PINS_PER_PORT = 16, +}; + +#define PIN_CONFIG_PIC32_DIGITAL (PIN_CONFIG_END + 1) +#define PIN_CONFIG_PIC32_ANALOG (PIN_CONFIG_END + 2) + +/* pin configuration descriptor */ +struct pic32_pin_config { + u16 port; /* port number */ + u16 pin; /* pin number in the port */ + u32 config; /* one of PIN_CONFIG_* */ +}; +#define PIN_CONFIG(_prt, _pin, _cfg) \ + {.port = (_prt), .pin = (_pin), .config = (_cfg), } + +/* In PIC32 muxing is performed at pin-level through two + * different set of registers - one set for input functions, + * and other for output functions. + * Pin configuration is handled through port register. + */ +/* Port control registers */ +struct pic32_reg_port { + struct pic32_reg_atomic ansel; + struct pic32_reg_atomic tris; + struct pic32_reg_atomic port; + struct pic32_reg_atomic lat; + struct pic32_reg_atomic odc; + struct pic32_reg_atomic cnpu; + struct pic32_reg_atomic cnpd; + struct pic32_reg_atomic cncon; + struct pic32_reg_atomic unused[8]; +}; + +/* Input function mux registers */ +struct pic32_reg_in_mux { + u32 unused0; + u32 int1[4]; + u32 unused1; + u32 t2ck[8]; + u32 ic1[9]; + u32 unused2; + u32 ocfar; + u32 unused3; + u32 u1rx; + u32 u1cts; + u32 u2rx; + u32 u2cts; + u32 u3rx; + u32 u3cts; + u32 u4rx; + u32 u4cts; + u32 u5rx; + u32 u5cts; + u32 u6rx; + u32 u6cts; + u32 unused4; + u32 sdi1; + u32 ss1; + u32 unused5; + u32 sdi2; + u32 ss2; + u32 unused6; + u32 sdi3; + u32 ss3; + u32 unused7; + u32 sdi4; + u32 ss4; + u32 unused8; + u32 sdi5; + u32 ss5; + u32 unused9; + u32 sdi6; + u32 ss6; + u32 c1rx; + u32 c2rx; + u32 refclki1; + u32 refclki2; + u32 refclki3; + u32 refclki4; +}; + +/* output mux register offset */ +#define PPS_OUT(__port, __pin) \ + (((__port) * PIC32_PINS_PER_PORT + (__pin)) << 2) + + +struct pic32_pinctrl_priv { + struct pic32_reg_in_mux *mux_in; /* mux input function */ + struct pic32_reg_port *pinconf; /* pin configuration*/ + void __iomem *mux_out; /* mux output function */ +}; + +enum { + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_ETH, + PERIPH_ID_USB, + PERIPH_ID_SDHCI, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SQI, +}; + +static int pic32_pinconfig_one(struct pic32_pinctrl_priv *priv, + u32 port_nr, u32 pin, u32 param) +{ + struct pic32_reg_port *port; + + port = &priv->pinconf[port_nr]; + switch (param) { + case PIN_CONFIG_PIC32_DIGITAL: + writel(BIT(pin), &port->ansel.clr); + break; + case PIN_CONFIG_PIC32_ANALOG: + writel(BIT(pin), &port->ansel.set); + break; + case PIN_CONFIG_INPUT_ENABLE: + writel(BIT(pin), &port->tris.set); + break; + case PIN_CONFIG_OUTPUT: + writel(BIT(pin), &port->tris.clr); + break; + case PIN_CONFIG_BIAS_PULL_UP: + writel(BIT(pin), &port->cnpu.set); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + writel(BIT(pin), &port->cnpd.set); + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + writel(BIT(pin), &port->odc.set); + break; + default: + break; + } + + return 0; +} + +static int pic32_pinconfig_set(struct pic32_pinctrl_priv *priv, + const struct pic32_pin_config *list, int count) +{ + int i; + + for (i = 0 ; i < count; i++) + pic32_pinconfig_one(priv, list[i].port, + list[i].pin, list[i].config); + + return 0; +} + +static void pic32_eth_pin_config(struct udevice *dev) +{ + struct pic32_pinctrl_priv *priv = dev_get_priv(dev); + const struct pic32_pin_config configs[] = { + /* EMDC - D11 */ + PIN_CONFIG(PIC32_PORT_D, 11, PIN_CONFIG_PIC32_DIGITAL), + PIN_CONFIG(PIC32_PORT_D, 11, PIN_CONFIG_OUTPUT), + /* ETXEN */ + PIN_CONFIG(PIC32_PORT_D, 6, PIN_CONFIG_PIC32_DIGITAL), + PIN_CONFIG(PIC32_PORT_D, 6, PIN_CONFIG_OUTPUT), + /* ECRSDV */ + PIN_CONFIG(PIC32_PORT_H, 13, PIN_CONFIG_PIC32_DIGITAL), + PIN_CONFIG(PIC32_PORT_H, 13, PIN_CONFIG_INPUT_ENABLE), + /* ERXD0 */ + PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_PIC32_DIGITAL), + PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_INPUT_ENABLE), + PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_BIAS_PULL_DOWN), + /* ERXD1 */ + PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_PIC32_DIGITAL), + PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_INPUT_ENABLE), + PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_BIAS_PULL_DOWN), + /* EREFCLK */ + PIN_CONFIG(PIC32_PORT_J, 11, PIN_CONFIG_PIC32_DIGITAL), + PIN_CONFIG(PIC32_PORT_J, 11, PIN_CONFIG_INPUT_ENABLE), + /* ETXD1 */ + PIN_CONFIG(PIC32_PORT_J, 9, PIN_CONFIG_PIC32_DIGITAL), + PIN_CONFIG(PIC32_PORT_J, 9, PIN_CONFIG_OUTPUT), + /* ETXD0 */ + PIN_CONFIG(PIC32_PORT_J, 8, PIN_CONFIG_PIC32_DIGITAL), + PIN_CONFIG(PIC32_PORT_J, 8, PIN_CONFIG_OUTPUT), + /* EMDIO */ + PIN_CONFIG(PIC32_PORT_J, 1, PIN_CONFIG_PIC32_DIGITAL), + PIN_CONFIG(PIC32_PORT_J, 1, PIN_CONFIG_INPUT_ENABLE), + /* ERXERR */ + PIN_CONFIG(PIC32_PORT_F, 3, PIN_CONFIG_PIC32_DIGITAL), + PIN_CONFIG(PIC32_PORT_F, 3, PIN_CONFIG_INPUT_ENABLE), + }; + + pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs)); +} + +static int pic32_pinctrl_request(struct udevice *dev, int func, int flags) +{ + struct pic32_pinctrl_priv *priv = dev_get_priv(dev); + + switch (func) { + case PERIPH_ID_UART2: + /* PPS for U2 RX/TX */ + writel(0x02, priv->mux_out + PPS_OUT(PIC32_PORT_G, 9)); + writel(0x05, &priv->mux_in->u2rx); /* B0 */ + /* set digital mode */ + pic32_pinconfig_one(priv, PIC32_PORT_G, 9, + PIN_CONFIG_PIC32_DIGITAL); + pic32_pinconfig_one(priv, PIC32_PORT_B, 0, + PIN_CONFIG_PIC32_DIGITAL); + break; + case PERIPH_ID_ETH: + pic32_eth_pin_config(dev); + break; + default: + debug("%s: unknown-unhandled case\n", __func__); + break; + } + + return 0; +} + +static int pic32_pinctrl_get_periph_id(struct udevice *dev, + struct udevice *periph) +{ + int ret; + u32 cell[2]; + + ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset, + "interrupts", cell, ARRAY_SIZE(cell)); + if (ret < 0) + return -EINVAL; + + /* interrupt number */ + switch (cell[0]) { + case 112 ... 114: + return PERIPH_ID_UART1; + case 145 ... 147: + return PERIPH_ID_UART2; + case 109 ... 111: + return PERIPH_ID_SPI1; + case 142 ... 144: + return PERIPH_ID_SPI2; + case 115 ... 117: + return PERIPH_ID_I2C1; + case 148 ... 150: + return PERIPH_ID_I2C2; + case 132 ... 133: + return PERIPH_ID_USB; + case 169: + return PERIPH_ID_SQI; + case 191: + return PERIPH_ID_SDHCI; + case 153: + return PERIPH_ID_ETH; + default: + break; + } + + return -ENOENT; +} + +static int pic32_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + int func; + + debug("%s: periph %s\n", __func__, periph->name); + func = pic32_pinctrl_get_periph_id(dev, periph); + if (func < 0) + return func; + return pic32_pinctrl_request(dev, func, 0); +} + +static struct pinctrl_ops pic32_pinctrl_ops = { + .set_state_simple = pic32_pinctrl_set_state_simple, + .request = pic32_pinctrl_request, + .get_periph_id = pic32_pinctrl_get_periph_id, +}; + +static int pic32_pinctrl_probe(struct udevice *dev) +{ + struct pic32_pinctrl_priv *priv = dev_get_priv(dev); + struct fdt_resource res; + void *fdt = (void *)gd->fdt_blob; + int node = dev->of_offset; + int ret; + + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", + "ppsin", &res); + if (ret < 0) { + printf("pinctrl: resource \"ppsin\" not found\n"); + return ret; + } + priv->mux_in = ioremap(res.start, fdt_resource_size(&res)); + + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", + "ppsout", &res); + if (ret < 0) { + printf("pinctrl: resource \"ppsout\" not found\n"); + return ret; + } + priv->mux_out = ioremap(res.start, fdt_resource_size(&res)); + + ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", + "port", &res); + if (ret < 0) { + printf("pinctrl: resource \"port\" not found\n"); + return ret; + } + priv->pinconf = ioremap(res.start, fdt_resource_size(&res)); + + return 0; +} + +static int pic32_pinctrl_bind(struct udevice *dev) +{ + /* scan child GPIO banks */ + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); +} + +static const struct udevice_id pic32_pinctrl_ids[] = { + { .compatible = "microchip,pic32mzda-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_pic32) = { + .name = "pinctrl_pic32", + .id = UCLASS_PINCTRL, + .of_match = pic32_pinctrl_ids, + .ops = &pic32_pinctrl_ops, + .probe = pic32_pinctrl_probe, + .bind = pic32_pinctrl_bind, + .priv_auto_alloc_size = sizeof(struct pic32_pinctrl_priv), +}; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 83068cfd50..fac317610e 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -112,6 +112,13 @@ config DEBUG_UART_S5P will need to provide parameters to make this work. The driver will be available until the real driver-model serial is running. +config DEBUG_UART_UARTLITE + bool "Xilinx Uartlite" + help + Select this to enable a debug UART using the serial_uartlite driver. + You will need to provide parameters to make this work. The driver will + be available until the real driver-model serial is running. + config DEBUG_UART_ZYNQ bool "Xilinx Zynq" help @@ -143,6 +150,14 @@ config DEBUG_UART_PL011 work. The driver will be available until the real driver model serial is running. +config DEBUG_UART_PIC32 + bool "Microchip PIC32" + depends on PIC32_SERIAL + help + Select this to enable a debug UART using the serial_pic32 driver. You + will need to provide parameters to make this work. The driver will + be available until the real driver model serial is running. + endchoice config DEBUG_UART_BASE @@ -234,6 +249,13 @@ config FSL_LPUART Select this to enable a Low Power UART for Freescale VF610 and QorIQ Layerscape devices. +config PIC32_SERIAL + bool "Support for Microchip PIC32 on-chip UART" + depends on DM_SERIAL && MACH_PIC32 + default y + help + Support for the UART found on Microchip PIC32 SoC's. + config SYS_NS16550 bool "NS16550 UART or compatible" help @@ -271,4 +293,11 @@ config UNIPHIER_SERIAL If you have a UniPhier based board and want to use the on-chip serial ports, say Y to this option. If unsure, say N. +config XILINX_UARTLITE + bool "Xilinx Uarlite support" + depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || 4xx) + help + If you have a Xilinx based board and want to use the uartlite + serial ports, say Y to this option. If unsure, say N. + endmenu diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index dd871478ea..57cd38bf6e 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o +obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c new file mode 100644 index 0000000000..af9fbbf655 --- /dev/null +++ b/drivers/serial/serial_pic32.c @@ -0,0 +1,198 @@ +/* + * (c) 2015 Paul Thacker <paul.thacker@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <serial.h> +#include <wait_bit.h> +#include <mach/pic32.h> +#include <dt-bindings/clock/microchip,clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* UART Control Registers */ +#define U_MOD 0x00 +#define U_MODCLR (U_MOD + _CLR_OFFSET) +#define U_MODSET (U_MOD + _SET_OFFSET) +#define U_STA 0x10 +#define U_STACLR (U_STA + _CLR_OFFSET) +#define U_STASET (U_STA + _SET_OFFSET) +#define U_TXR 0x20 +#define U_RXR 0x30 +#define U_BRG 0x40 + +/* U_MOD bits */ +#define UART_ENABLE BIT(15) + +/* U_STA bits */ +#define UART_RX_ENABLE BIT(12) +#define UART_TX_BRK BIT(11) +#define UART_TX_ENABLE BIT(10) +#define UART_TX_FULL BIT(9) +#define UART_TX_EMPTY BIT(8) +#define UART_RX_OVER BIT(1) +#define UART_RX_DATA_AVAIL BIT(0) + +struct pic32_uart_priv { + void __iomem *base; + ulong uartclk; +}; + +/* + * Initialize the serial port with the given baudrate. + * The settings are always 8 data bits, no parity, 1 stop bit, no start bits. + */ +static int pic32_serial_init(void __iomem *base, ulong clk, u32 baudrate) +{ + u32 div = DIV_ROUND_CLOSEST(clk, baudrate * 16); + + /* wait for TX FIFO to empty */ + wait_for_bit(__func__, base + U_STA, UART_TX_EMPTY, + true, CONFIG_SYS_HZ, false); + + /* send break */ + writel(UART_TX_BRK, base + U_STASET); + + /* disable and clear mode */ + writel(0, base + U_MOD); + writel(0, base + U_STA); + + /* set baud rate generator */ + writel(div - 1, base + U_BRG); + + /* enable the UART for TX and RX */ + writel(UART_TX_ENABLE | UART_RX_ENABLE, base + U_STASET); + + /* enable the UART */ + writel(UART_ENABLE, base + U_MODSET); + return 0; +} + +/* Check whether any char pending in RX fifo */ +static int pic32_uart_pending_input(void __iomem *base) +{ + /* check if rx buffer overrun error has occurred */ + if (readl(base + U_STA) & UART_RX_OVER) { + readl(base + U_RXR); + + /* clear overrun error to keep receiving */ + writel(UART_RX_OVER, base + U_STACLR); + } + + /* In PIC32 there is no way to know number of outstanding + * chars in rx-fifo. Only it can be known whether there is any. + */ + return readl(base + U_STA) & UART_RX_DATA_AVAIL; +} + +static int pic32_uart_pending(struct udevice *dev, bool input) +{ + struct pic32_uart_priv *priv = dev_get_priv(dev); + + if (input) + return pic32_uart_pending_input(priv->base); + + return !(readl(priv->base + U_STA) & UART_TX_EMPTY); +} + +static int pic32_uart_setbrg(struct udevice *dev, int baudrate) +{ + struct pic32_uart_priv *priv = dev_get_priv(dev); + + return pic32_serial_init(priv->base, priv->uartclk, baudrate); +} + +static int pic32_uart_putc(struct udevice *dev, const char ch) +{ + struct pic32_uart_priv *priv = dev_get_priv(dev); + + /* Check if Tx FIFO is full */ + if (readl(priv->base + U_STA) & UART_TX_FULL) + return -EAGAIN; + + /* pump the char to tx buffer */ + writel(ch, priv->base + U_TXR); + + return 0; +} + +static int pic32_uart_getc(struct udevice *dev) +{ + struct pic32_uart_priv *priv = dev_get_priv(dev); + + /* return error if RX fifo is empty */ + if (!pic32_uart_pending_input(priv->base)) + return -EAGAIN; + + /* read the character from rx buffer */ + return readl(priv->base + U_RXR) & 0xff; +} + +static int pic32_uart_probe(struct udevice *dev) +{ + struct pic32_uart_priv *priv = dev_get_priv(dev); + struct udevice *clkdev; + fdt_addr_t addr; + fdt_size_t size; + int ret; + + /* get address */ + addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = ioremap(addr, size); + + /* get clock rate */ + ret = clk_get_by_index(dev, 0, &clkdev); + if (ret < 0) + return ret; + priv->uartclk = clk_get_periph_rate(clkdev, ret); + + /* initialize serial */ + return pic32_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE); +} + +static const struct dm_serial_ops pic32_uart_ops = { + .putc = pic32_uart_putc, + .pending = pic32_uart_pending, + .getc = pic32_uart_getc, + .setbrg = pic32_uart_setbrg, +}; + +static const struct udevice_id pic32_uart_ids[] = { + { .compatible = "microchip,pic32mzda-uart" }, + {} +}; + +U_BOOT_DRIVER(pic32_serial) = { + .name = "pic32-uart", + .id = UCLASS_SERIAL, + .of_match = pic32_uart_ids, + .probe = pic32_uart_probe, + .ops = &pic32_uart_ops, + .flags = DM_FLAG_PRE_RELOC, + .priv_auto_alloc_size = sizeof(struct pic32_uart_priv), +}; + +#ifdef CONFIG_DEBUG_UART_PIC32 +#include <debug_uart.h> + +static inline void _debug_uart_init(void) +{ + void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; + + pic32_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); +} + +static inline void _debug_uart_putc(int ch) +{ + writel(ch, CONFIG_DEBUG_UART_BASE + U_TXR); +} + +DEBUG_UART_FUNCS +#endif diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index 988438e754..a2e9303925 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2008-2011 Michal Simek <monstr@monstr.eu> + * (C) Copyright 2008 - 2015 Michal Simek <monstr@monstr.eu> * Clean driver and add xilinx constant from header file * * (C) Copyright 2004 Atmark Techno, Inc. @@ -10,13 +10,17 @@ #include <config.h> #include <common.h> +#include <dm.h> #include <asm/io.h> #include <linux/compiler.h> #include <serial.h> -#define SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */ -#define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */ -#define SR_RX_FIFO_FULL 0x02 /* receive FIFO full */ +DECLARE_GLOBAL_DATA_PTR; + +#define SR_TX_FIFO_FULL BIT(3) /* transmit FIFO full */ +#define SR_TX_FIFO_EMPTY BIT(2) /* transmit FIFO empty */ +#define SR_RX_FIFO_VALID_DATA BIT(0) /* data in receive FIFO */ +#define SR_RX_FIFO_FULL BIT(1) /* receive FIFO full */ #define ULITE_CONTROL_RST_TX 0x01 #define ULITE_CONTROL_RST_RX 0x02 @@ -28,135 +32,111 @@ struct uartlite { unsigned int control; }; -static struct uartlite *userial_ports[4] = { -#ifdef XILINX_UARTLITE_BASEADDR - [0] = (struct uartlite *)XILINX_UARTLITE_BASEADDR, -#endif -#ifdef XILINX_UARTLITE_BASEADDR1 - [1] = (struct uartlite *)XILINX_UARTLITE_BASEADDR1, -#endif -#ifdef XILINX_UARTLITE_BASEADDR2 - [2] = (struct uartlite *)XILINX_UARTLITE_BASEADDR2, -#endif -#ifdef XILINX_UARTLITE_BASEADDR3 - [3] = (struct uartlite *)XILINX_UARTLITE_BASEADDR3 -#endif +struct uartlite_platdata { + struct uartlite *regs; }; -static void uartlite_serial_putc(const char c, const int port) +static int uartlite_serial_putc(struct udevice *dev, const char ch) { - struct uartlite *regs = userial_ports[port]; + struct uartlite_platdata *plat = dev_get_platdata(dev); + struct uartlite *regs = plat->regs; - if (c == '\n') - uartlite_serial_putc('\r', port); + if (in_be32(®s->status) & SR_TX_FIFO_FULL) + return -EAGAIN; - while (in_be32(®s->status) & SR_TX_FIFO_FULL) - ; - out_be32(®s->tx_fifo, c & 0xff); -} + out_be32(®s->tx_fifo, ch & 0xff); -static void uartlite_serial_puts(const char *s, const int port) -{ - while (*s) - uartlite_serial_putc(*s++, port); + return 0; } -static int uartlite_serial_getc(const int port) +static int uartlite_serial_getc(struct udevice *dev) { - struct uartlite *regs = userial_ports[port]; + struct uartlite_platdata *plat = dev_get_platdata(dev); + struct uartlite *regs = plat->regs; + + if (!(in_be32(®s->status) & SR_RX_FIFO_VALID_DATA)) + return -EAGAIN; - while (!(in_be32(®s->status) & SR_RX_FIFO_VALID_DATA)) - ; return in_be32(®s->rx_fifo) & 0xff; } -static int uartlite_serial_tstc(const int port) +static int uartlite_serial_pending(struct udevice *dev, bool input) { - struct uartlite *regs = userial_ports[port]; + struct uartlite_platdata *plat = dev_get_platdata(dev); + struct uartlite *regs = plat->regs; + + if (input) + return in_be32(®s->status) & SR_RX_FIFO_VALID_DATA; - return in_be32(®s->status) & SR_RX_FIFO_VALID_DATA; + return !(in_be32(®s->status) & SR_TX_FIFO_EMPTY); } -static int uartlite_serial_init(const int port) +static int uartlite_serial_probe(struct udevice *dev) { - struct uartlite *regs = userial_ports[port]; + struct uartlite_platdata *plat = dev_get_platdata(dev); + struct uartlite *regs = plat->regs; - if (regs) { - out_be32(®s->control, 0); - out_be32(®s->control, - ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); - in_be32(®s->control); - return 0; - } + out_be32(®s->control, 0); + out_be32(®s->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); + in_be32(®s->control); - return -1; + return 0; } -/* Multi serial device functions */ -#define DECLARE_ESERIAL_FUNCTIONS(port) \ - static int userial##port##_init(void) \ - { return uartlite_serial_init(port); } \ - static void userial##port##_setbrg(void) {} \ - static int userial##port##_getc(void) \ - { return uartlite_serial_getc(port); } \ - static int userial##port##_tstc(void) \ - { return uartlite_serial_tstc(port); } \ - static void userial##port##_putc(const char c) \ - { uartlite_serial_putc(c, port); } \ - static void userial##port##_puts(const char *s) \ - { uartlite_serial_puts(s, port); } - -/* Serial device descriptor */ -#define INIT_ESERIAL_STRUCTURE(port, __name) { \ - .name = __name, \ - .start = userial##port##_init, \ - .stop = NULL, \ - .setbrg = userial##port##_setbrg, \ - .getc = userial##port##_getc, \ - .tstc = userial##port##_tstc, \ - .putc = userial##port##_putc, \ - .puts = userial##port##_puts, \ +static int uartlite_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct uartlite_platdata *plat = dev_get_platdata(dev); + + plat->regs = (struct uartlite *)dev_get_addr(dev); + + return 0; } -DECLARE_ESERIAL_FUNCTIONS(0); -struct serial_device uartlite_serial0_device = - INIT_ESERIAL_STRUCTURE(0, "ttyUL0"); -DECLARE_ESERIAL_FUNCTIONS(1); -struct serial_device uartlite_serial1_device = - INIT_ESERIAL_STRUCTURE(1, "ttyUL1"); -DECLARE_ESERIAL_FUNCTIONS(2); -struct serial_device uartlite_serial2_device = - INIT_ESERIAL_STRUCTURE(2, "ttyUL2"); -DECLARE_ESERIAL_FUNCTIONS(3); -struct serial_device uartlite_serial3_device = - INIT_ESERIAL_STRUCTURE(3, "ttyUL3"); - -__weak struct serial_device *default_serial_console(void) +static const struct dm_serial_ops uartlite_serial_ops = { + .putc = uartlite_serial_putc, + .pending = uartlite_serial_pending, + .getc = uartlite_serial_getc, +}; + +static const struct udevice_id uartlite_serial_ids[] = { + { .compatible = "xlnx,opb-uartlite-1.00.b", }, + { .compatible = "xlnx,xps-uartlite-1.00.a" }, + { } +}; + +U_BOOT_DRIVER(serial_uartlite) = { + .name = "serial_uartlite", + .id = UCLASS_SERIAL, + .of_match = uartlite_serial_ids, + .ofdata_to_platdata = uartlite_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct uartlite_platdata), + .probe = uartlite_serial_probe, + .ops = &uartlite_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#ifdef CONFIG_DEBUG_UART_UARTLITE + +#include <debug_uart.h> + +static inline void _debug_uart_init(void) { - if (userial_ports[0]) - return &uartlite_serial0_device; - if (userial_ports[1]) - return &uartlite_serial1_device; - if (userial_ports[2]) - return &uartlite_serial2_device; - if (userial_ports[3]) - return &uartlite_serial3_device; - - return NULL; + struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE; + + out_be32(®s->control, 0); + out_be32(®s->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); + in_be32(®s->control); } -void uartlite_serial_initialize(void) +static inline void _debug_uart_putc(int ch) { -#ifdef XILINX_UARTLITE_BASEADDR - serial_register(&uartlite_serial0_device); -#endif /* XILINX_UARTLITE_BASEADDR */ -#ifdef XILINX_UARTLITE_BASEADDR1 - serial_register(&uartlite_serial1_device); -#endif /* XILINX_UARTLITE_BASEADDR1 */ -#ifdef XILINX_UARTLITE_BASEADDR2 - serial_register(&uartlite_serial2_device); -#endif /* XILINX_UARTLITE_BASEADDR2 */ -#ifdef XILINX_UARTLITE_BASEADDR3 - serial_register(&uartlite_serial3_device); -#endif /* XILINX_UARTLITE_BASEADDR3 */ + struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE; + + while (in_be32(®s->status) & SR_TX_FIFO_FULL) + ; + + out_be32(®s->tx_fifo, ch & 0xff); } + +DEBUG_UART_FUNCS +#endif diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 3430482f8d..e79d997cba 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -156,13 +156,8 @@ static int zynq_serial_pending(struct udevice *dev, bool input) static int zynq_serial_ofdata_to_platdata(struct udevice *dev) { struct zynq_uart_priv *priv = dev_get_priv(dev); - fdt_addr_t addr; - addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - - priv->regs = (struct uart_zynq *)addr; + priv->regs = (struct uart_zynq *)dev_get_addr(dev); return 0; } @@ -177,6 +172,7 @@ static const struct dm_serial_ops zynq_serial_ops = { static const struct udevice_id zynq_serial_ids[] = { { .compatible = "xlnx,xuartps" }, { .compatible = "cdns,uart-r1p8" }, + { .compatible = "cdns,uart-r1p12" }, { } }; diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 542b6cfe35..cb8d929d07 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -477,8 +477,8 @@ static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len) static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) { struct fsl_qspi_regs *regs = priv->regs; - u32 mcr_reg, rbsr_reg, data; - int i, size; + u32 mcr_reg, rbsr_reg, data, size; + int i; mcr_reg = qspi_read32(priv->flags, ®s->mcr); qspi_write32(priv->flags, ®s->mcr, @@ -494,15 +494,15 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) ; i = 0; - size = len; - while ((RX_BUFFER_SIZE >= size) && (size > 0)) { + while ((RX_BUFFER_SIZE >= len) && (len > 0)) { rbsr_reg = qspi_read32(priv->flags, ®s->rbsr); if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) { data = qspi_read32(priv->flags, ®s->rbdr[i]); data = qspi_endian_xchg(data); - memcpy(rxbuf, &data, 4); + size = (len < 4) ? len : 4; + memcpy(rxbuf, &data, size); + len -= size; rxbuf++; - size -= 4; i++; } } @@ -639,7 +639,7 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) qspi_write32(priv->flags, ®s->mcr, mcr_reg); } -static void qspi_op_rdsr(struct fsl_qspi_priv *priv, u32 *rxbuf) +static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) { struct fsl_qspi_regs *regs = priv->regs; u32 mcr_reg, reg, data; @@ -662,7 +662,7 @@ static void qspi_op_rdsr(struct fsl_qspi_priv *priv, u32 *rxbuf) if (reg & QSPI_RBSR_RDBFL_MASK) { data = qspi_read32(priv->flags, ®s->rbdr[0]); data = qspi_endian_xchg(data); - memcpy(rxbuf, &data, 4); + memcpy(rxbuf, &data, len); qspi_write32(priv->flags, ®s->mcr, qspi_read32(priv->flags, ®s->mcr) | QSPI_MCR_CLR_RXF_MASK); @@ -751,7 +751,7 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, } else if (priv->cur_seqid == QSPI_CMD_RDID) qspi_op_rdid(priv, din, bytes); else if (priv->cur_seqid == QSPI_CMD_RDSR) - qspi_op_rdsr(priv, din); + qspi_op_rdsr(priv, din, bytes); #ifdef CONFIG_SPI_FLASH_BAR else if ((priv->cur_seqid == QSPI_CMD_BRRD) || (priv->cur_seqid == QSPI_CMD_RDEAR)) { @@ -936,7 +936,7 @@ static int fsl_qspi_probe(struct udevice *bus) dm_spi_bus->max_hz = plat->speed_hz; - priv->regs = (struct fsl_qspi_regs *)plat->reg_base; + priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base; priv->flags = plat->flags; priv->speed_hz = plat->speed_hz; diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig index 31b35f75c9..9a7b7f535f 100644 --- a/drivers/tpm/Kconfig +++ b/drivers/tpm/Kconfig @@ -50,7 +50,7 @@ config TPM_TIS_LPC bool "Enable support for Infineon SLB9635/45 TPMs on LPC" depends on TPM && X86 help - This driver supports Infineon TPM devices connected on the I2C bus. + This driver supports Infineon TPM devices connected on the LPC bus. The usual tpm operations and the 'tpm' command can be used to talk to the device using the standard TPM Interface Specification (TIS) protocol @@ -64,4 +64,22 @@ config TPM_AUTH_SESSIONS TPM_LoadKey2 and TPM_GetPubKey are provided. Both features are available using the 'tpm' command, too. +config TPM_ST33ZP24_I2C + bool "STMicroelectronics ST33ZP24 I2C TPM" + depends on TPM && DM_I2C + ---help--- + This driver supports STMicroelectronics TPM devices connected on the I2C bus. + The usual tpm operations and the 'tpm' command can be used to talk + to the device using the standard TPM Interface Specification (TIS) + protocol + +config TPM_ST33ZP24_SPI + bool "STMicroelectronics ST33ZP24 SPI TPM" + depends on TPM && DM_SPI + ---help--- + This driver supports STMicroelectronics TPM devices connected on the SPI bus. + The usual tpm operations and the 'tpm' command can be used to talk + to the device using the standard TPM Interface Specification (TIS) + protocol + endmenu diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile index 1d49e952ae..c42a93f267 100644 --- a/drivers/tpm/Makefile +++ b/drivers/tpm/Makefile @@ -9,3 +9,5 @@ obj-$(CONFIG_TPM_ATMEL_TWI) += tpm_atmel_twi.o obj-$(CONFIG_TPM_TIS_INFINEON) += tpm_tis_infineon.o obj-$(CONFIG_TPM_TIS_LPC) += tpm_tis_lpc.o obj-$(CONFIG_TPM_TIS_SANDBOX) += tpm_tis_sandbox.o +obj-$(CONFIG_TPM_ST33ZP24_I2C) += tpm_tis_st33zp24_i2c.o +obj-$(CONFIG_TPM_ST33ZP24_SPI) += tpm_tis_st33zp24_spi.o diff --git a/drivers/tpm/tpm_tis_infineon.h b/drivers/tpm/tpm_tis.h index 3b510d101e..25b152b321 100644 --- a/drivers/tpm/tpm_tis_infineon.h +++ b/drivers/tpm/tpm_tis.h @@ -37,18 +37,12 @@ enum tpm_timeout { #define TPM_RSP_SIZE_BYTE 2 #define TPM_RSP_RC_BYTE 6 -enum i2c_chip_type { - SLB9635, - SLB9645, - UNKNOWN, -}; - struct tpm_chip { int is_open; int locality; u32 vend_dev; unsigned long timeout_a, timeout_b, timeout_c, timeout_d; /* msec */ - enum i2c_chip_type chip_type; + ulong chip_type; }; struct tpm_input_header { @@ -134,13 +128,4 @@ enum tis_status { TPM_STS_DATA_EXPECT = 0x08, }; -/* expected value for DIDVID register */ -#define TPM_TIS_I2C_DID_VID_9635 0x000b15d1L -#define TPM_TIS_I2C_DID_VID_9645 0x001a15d1L - -#define TPM_ACCESS(l) (0x0000 | ((l) << 4)) -#define TPM_STS(l) (0x0001 | ((l) << 4)) -#define TPM_DATA_FIFO(l) (0x0005 | ((l) << 4)) -#define TPM_DID_VID(l) (0x0006 | ((l) << 4)) - #endif diff --git a/drivers/tpm/tpm_tis_infineon.c b/drivers/tpm/tpm_tis_infineon.c index f57c32837b..a4b6741676 100644 --- a/drivers/tpm/tpm_tis_infineon.c +++ b/drivers/tpm/tpm_tis_infineon.c @@ -30,17 +30,32 @@ #include <linux/types.h> #include <linux/unaligned/be_byteshift.h> -#include "tpm_tis_infineon.h" +#include "tpm_tis.h" #include "tpm_internal.h" DECLARE_GLOBAL_DATA_PTR; +enum i2c_chip_type { + SLB9635, + SLB9645, + UNKNOWN, +}; + +/* expected value for DIDVID register */ +#define TPM_TIS_I2C_DID_VID_9635 0x000b15d1L +#define TPM_TIS_I2C_DID_VID_9645 0x001a15d1L + static const char * const chip_name[] = { [SLB9635] = "slb9635tt", [SLB9645] = "slb9645tt", [UNKNOWN] = "unknown/fallback to slb9635", }; +#define TPM_ACCESS(l) (0x0000 | ((l) << 4)) +#define TPM_STS(l) (0x0001 | ((l) << 4)) +#define TPM_DATA_FIFO(l) (0x0005 | ((l) << 4)) +#define TPM_DID_VID(l) (0x0006 | ((l) << 4)) + /* * tpm_tis_i2c_read() - read from TPM register * @addr: register address to read from diff --git a/drivers/tpm/tpm_tis_st33zp24_i2c.c b/drivers/tpm/tpm_tis_st33zp24_i2c.c new file mode 100644 index 0000000000..9e4829fea2 --- /dev/null +++ b/drivers/tpm/tpm_tis_st33zp24_i2c.c @@ -0,0 +1,543 @@ +/* + * STMicroelectronics TPM ST33ZP24 I2C UBOOT driver + * + * Copyright (C) 2016 STMicroelectronics + * + * Description: Device driver for ST33ZP24 I2C TPM TCG. + * + * This device driver implements the TPM interface as defined in + * the TCG TPM Interface Spec version 1.21, revision 1.0 and the + * STMicroelectronics Protocol Stack Specification version 1.2.0. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <i2c.h> +#include <tpm.h> +#include <errno.h> +#include <linux/types.h> +#include <asm/unaligned.h> + +#include "tpm_tis.h" +#include "tpm_internal.h" + +#define TPM_ACCESS 0x0 +#define TPM_STS 0x18 +#define TPM_DATA_FIFO 0x24 + +#define LOCALITY0 0 + +#define TPM_DUMMY_BYTE 0xAA +#define TPM_ST33ZP24_I2C_SLAVE_ADDR 0x13 + +#define TPM_WRITE_DIRECTION 0x80 + +/* + * st33zp24_i2c_write8_reg + * Send byte to the TIS register according to the ST33ZP24 I2C protocol. + * @param: tpm_register, the tpm tis register where the data should be written + * @param: tpm_data, the tpm_data to write inside the tpm_register + * @param: tpm_size, The length of the data + * @return: Number of byte written successfully else an error code. + */ +static int st33zp24_i2c_write8_reg(struct udevice *dev, u8 tpm_register, + const u8 *tpm_data, size_t tpm_size) +{ + struct tpm_chip_priv *chip_priv = dev_get_uclass_priv(dev); + + chip_priv->buf[0] = tpm_register; + memcpy(chip_priv->buf + 1, tpm_data, tpm_size); + + return dm_i2c_write(dev, 0, chip_priv->buf, tpm_size + 1); +} + +/* +* st33zp24_i2c_read8_reg +* Recv byte from the TIS register according to the ST33ZP24 I2C protocol. +* @param: tpm_register, the tpm tis register where the data should be read +* @param: tpm_data, the TPM response +* @param: tpm_size, tpm TPM response size to read. +* @return: Number of byte read successfully else an error code. +*/ +static int st33zp24_i2c_read8_reg(struct udevice *dev, u8 tpm_register, + u8 *tpm_data, size_t tpm_size) +{ + int status; + u8 data; + + data = TPM_DUMMY_BYTE; + status = st33zp24_i2c_write8_reg(dev, tpm_register, &data, 1); + if (status < 0) + return status; + + return dm_i2c_read(dev, 0, tpm_data, tpm_size); +} + +/* + * st33zp24_i2c_write + * Send byte to the TIS register according to the ST33ZP24 I2C protocol. + * @param: phy_id, the phy description + * @param: tpm_register, the tpm tis register where the data should be written + * @param: tpm_data, the tpm_data to write inside the tpm_register + * @param: tpm_size, the length of the data + * @return: number of byte written successfully: should be one if success. + */ +static int st33zp24_i2c_write(struct udevice *dev, u8 tpm_register, + const u8 *tpm_data, size_t tpm_size) +{ + return st33zp24_i2c_write8_reg(dev, tpm_register | TPM_WRITE_DIRECTION, + tpm_data, tpm_size); +} + +/* + * st33zp24_i2c_read + * Recv byte from the TIS register according to the ST33ZP24 I2C protocol. + * @param: phy_id, the phy description + * @param: tpm_register, the tpm tis register where the data should be read + * @param: tpm_data, the TPM response + * @param: tpm_size, tpm TPM response size to read. + * @return: number of byte read successfully: should be one if success. + */ +static int st33zp24_i2c_read(struct udevice *dev, u8 tpm_register, + u8 *tpm_data, size_t tpm_size) +{ + return st33zp24_i2c_read8_reg(dev, tpm_register, tpm_data, tpm_size); +} + +/* + * st33zp24_i2c_release_locality release the active locality + * @param: chip, the tpm chip description. + */ +static void st33zp24_i2c_release_locality(struct udevice *dev) +{ + u8 data = TPM_ACCESS_ACTIVE_LOCALITY; + + st33zp24_i2c_write(dev, TPM_ACCESS, &data, 1); +} + +/* + * st33zp24_i2c_check_locality if the locality is active + * @param: chip, the tpm chip description + * @return: the active locality or -EACCES. + */ +static int st33zp24_i2c_check_locality(struct udevice *dev) +{ + struct tpm_chip *chip = dev_get_priv(dev); + u8 data; + u8 status; + + status = st33zp24_i2c_read(dev, TPM_ACCESS, &data, 1); + if (!status && (data & + (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) == + (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) + return chip->locality; + + return -EACCES; +} + +/* + * st33zp24_i2c_request_locality request the TPM locality + * @param: chip, the chip description + * @return: the active locality or negative value. + */ +static int st33zp24_i2c_request_locality(struct udevice *dev) +{ + struct tpm_chip *chip = dev_get_priv(dev); + unsigned long start, stop; + long ret; + u8 data; + + if (st33zp24_i2c_check_locality(dev) == chip->locality) + return chip->locality; + + data = TPM_ACCESS_REQUEST_USE; + ret = st33zp24_i2c_write(dev, TPM_ACCESS, &data, 1); + if (ret < 0) + return ret; + + /* wait for locality activated */ + start = get_timer(0); + stop = chip->timeout_a; + do { + if (st33zp24_i2c_check_locality(dev) >= 0) + return chip->locality; + udelay(TPM_TIMEOUT_MS * 1000); + } while (get_timer(start) < stop); + + return -EACCES; +} + +/* + * st33zp24_i2c_status return the TPM_STS register + * @param: chip, the tpm chip description + * @return: the TPM_STS register value. + */ +static u8 st33zp24_i2c_status(struct udevice *dev) +{ + u8 data; + + st33zp24_i2c_read(dev, TPM_STS, &data, 1); + + return data; +} + +/* + * st33zp24_i2c_get_burstcount return the burstcount address 0x19 0x1A + * @param: chip, the chip description + * return: the burstcount or -TPM_DRIVER_ERR in case of error. + */ +static int st33zp24_i2c_get_burstcount(struct udevice *dev) +{ + struct tpm_chip *chip = dev_get_priv(dev); + unsigned long start, stop; + int burstcnt, status; + u8 tpm_reg, temp; + + /* wait for burstcount */ + start = get_timer(0); + stop = chip->timeout_d; + do { + tpm_reg = TPM_STS + 1; + status = st33zp24_i2c_read(dev, tpm_reg, &temp, 1); + if (status < 0) + return -EBUSY; + + tpm_reg = TPM_STS + 2; + burstcnt = temp; + status = st33zp24_i2c_read(dev, tpm_reg, &temp, 1); + if (status < 0) + return -EBUSY; + + burstcnt |= temp << 8; + if (burstcnt) + return burstcnt; + udelay(TIS_SHORT_TIMEOUT_MS * 1000); + } while (get_timer(start) < stop); + + return -EBUSY; +} + +/* + * st33zp24_i2c_cancel, cancel the current command execution or + * set STS to COMMAND READY. + * @param: chip, tpm_chip description. + */ +static void st33zp24_i2c_cancel(struct udevice *dev) +{ + u8 data; + + data = TPM_STS_COMMAND_READY; + st33zp24_i2c_write(dev, TPM_STS, &data, 1); +} + +/* + * st33zp24_i2c_wait_for_stat wait for a TPM_STS value + * @param: chip, the tpm chip description + * @param: mask, the value mask to wait + * @param: timeout, the timeout + * @param: status, + * @return: the tpm status, 0 if success, -ETIME if timeout is reached. + */ +static int st33zp24_i2c_wait_for_stat(struct udevice *dev, u8 mask, + unsigned long timeout, int *status) +{ + unsigned long start, stop; + + /* Check current status */ + *status = st33zp24_i2c_status(dev); + if ((*status & mask) == mask) + return 0; + + start = get_timer(0); + stop = timeout; + do { + udelay(TPM_TIMEOUT_MS * 1000); + *status = st33zp24_i2c_status(dev); + if ((*status & mask) == mask) + return 0; + } while (get_timer(start) < stop); + + return -ETIME; +} + +/* + * st33zp24_i2c_recv_data receive data + * @param: chip, the tpm chip description + * @param: buf, the buffer where the data are received + * @param: count, the number of data to receive + * @return: the number of bytes read from TPM FIFO. + */ +static int st33zp24_i2c_recv_data(struct udevice *dev, u8 *buf, size_t count) +{ + struct tpm_chip *chip = dev_get_priv(dev); + int size = 0, burstcnt, len, ret, status; + + while (size < count && + st33zp24_i2c_wait_for_stat(dev, TPM_STS_DATA_AVAIL | TPM_STS_VALID, + chip->timeout_c, &status) == 0) { + burstcnt = st33zp24_i2c_get_burstcount(dev); + if (burstcnt < 0) + return burstcnt; + len = min_t(int, burstcnt, count - size); + ret = st33zp24_i2c_read(dev, TPM_DATA_FIFO, buf + size, len); + if (ret < 0) + return ret; + + size += len; + } + + return size; +} + +/* + * st33zp24_i2c_recv received TPM response through TPM phy. + * @param: chip, tpm_chip description. + * @param: buf, the buffer to store data. + * @param: count, the number of bytes that can received (sizeof buf). + * @return: Returns zero in case of success else -EIO. + */ +static int st33zp24_i2c_recv(struct udevice *dev, u8 *buf, size_t count) +{ + struct tpm_chip *chip = dev_get_priv(dev); + int size, expected; + + if (!chip) + return -ENODEV; + + if (count < TPM_HEADER_SIZE) { + size = -EIO; + goto out; + } + + size = st33zp24_i2c_recv_data(dev, buf, TPM_HEADER_SIZE); + if (size < TPM_HEADER_SIZE) { + debug("TPM error, unable to read header\n"); + goto out; + } + + expected = get_unaligned_be32(buf + 2); + if (expected > count) { + size = -EIO; + goto out; + } + + size += st33zp24_i2c_recv_data(dev, &buf[TPM_HEADER_SIZE], + expected - TPM_HEADER_SIZE); + if (size < expected) { + debug("TPM error, unable to read remaining bytes of result\n"); + size = -EIO; + goto out; + } + +out: + st33zp24_i2c_cancel(dev); + st33zp24_i2c_release_locality(dev); + + return size; +} + +/* + * st33zp24_i2c_send send TPM commands through TPM phy. + * @param: chip, tpm_chip description. + * @param: buf, the buffer to send. + * @param: len, the number of bytes to send. + * @return: Returns zero in case of success else the negative error code. + */ +static int st33zp24_i2c_send(struct udevice *dev, const u8 *buf, size_t len) +{ + struct tpm_chip *chip = dev_get_priv(dev); + u32 i, size; + int burstcnt, ret, status; + u8 data, tpm_stat; + + if (!chip) + return -ENODEV; + if (len < TPM_HEADER_SIZE) + return -EIO; + + ret = st33zp24_i2c_request_locality(dev); + if (ret < 0) + return ret; + + tpm_stat = st33zp24_i2c_status(dev); + if ((tpm_stat & TPM_STS_COMMAND_READY) == 0) { + st33zp24_i2c_cancel(dev); + if (st33zp24_i2c_wait_for_stat(dev, TPM_STS_COMMAND_READY, + chip->timeout_b, &status) < 0) { + ret = -ETIME; + goto out_err; + } + } + + for (i = 0; i < len - 1;) { + burstcnt = st33zp24_i2c_get_burstcount(dev); + if (burstcnt < 0) + return burstcnt; + + size = min_t(int, len - i - 1, burstcnt); + ret = st33zp24_i2c_write(dev, TPM_DATA_FIFO, buf + i, size); + if (ret < 0) + goto out_err; + + i += size; + } + + tpm_stat = st33zp24_i2c_status(dev); + if ((tpm_stat & TPM_STS_DATA_EXPECT) == 0) { + ret = -EIO; + goto out_err; + } + + ret = st33zp24_i2c_write(dev, TPM_DATA_FIFO, buf + len - 1, 1); + if (ret < 0) + goto out_err; + + tpm_stat = st33zp24_i2c_status(dev); + if ((tpm_stat & TPM_STS_DATA_EXPECT) != 0) { + ret = -EIO; + goto out_err; + } + + data = TPM_STS_GO; + ret = st33zp24_i2c_write(dev, TPM_STS, &data, 1); + if (ret < 0) + goto out_err; + + return len; + +out_err: + st33zp24_i2c_cancel(dev); + st33zp24_i2c_release_locality(dev); + + return ret; +} + +static int st33zp24_i2c_cleanup(struct udevice *dev) +{ + st33zp24_i2c_cancel(dev); + /* + * The TPM needs some time to clean up here, + * so we sleep rather than keeping the bus busy + */ + mdelay(2); + st33zp24_i2c_release_locality(dev); + + return 0; +} + +static int st33zp24_i2c_init(struct udevice *dev) +{ + struct tpm_chip *chip = dev_get_priv(dev); + + chip->is_open = 1; + + /* Default timeouts - these could move to the device tree */ + chip->timeout_a = TIS_SHORT_TIMEOUT_MS; + chip->timeout_b = TIS_LONG_TIMEOUT_MS; + chip->timeout_c = TIS_SHORT_TIMEOUT_MS; + chip->timeout_d = TIS_SHORT_TIMEOUT_MS; + + chip->locality = LOCALITY0; + + /* + * A timeout query to TPM can be placed here. + * Standard timeout values are used so far + */ + + return 0; +} + +static int st33zp24_i2c_open(struct udevice *dev) +{ + struct tpm_chip *chip = dev_get_priv(dev); + int rc; + + debug("%s: start\n", __func__); + if (chip->is_open) + return -EBUSY; + + rc = st33zp24_i2c_init(dev); + if (rc < 0) + chip->is_open = 0; + + return rc; +} + +static int st33zp24_i2c_close(struct udevice *dev) +{ + struct tpm_chip *chip = dev_get_priv(dev); + + if (chip->is_open) { + st33zp24_i2c_release_locality(dev); + chip->is_open = 0; + chip->vend_dev = 0; + } + + return 0; +} + +static int st33zp24_i2c_get_desc(struct udevice *dev, char *buf, int size) +{ + struct tpm_chip *chip = dev_get_priv(dev); + + if (size < 50) + return -ENOSPC; + + return snprintf(buf, size, "1.2 TPM (%s, chip type %s device-id 0x%x)", + chip->is_open ? "open" : "closed", + dev->name, + chip->vend_dev >> 16); +} + +static const struct tpm_ops st33zp24_i2c_tpm_ops = { + .open = st33zp24_i2c_open, + .close = st33zp24_i2c_close, + .recv = st33zp24_i2c_recv, + .send = st33zp24_i2c_send, + .cleanup = st33zp24_i2c_cleanup, + .get_desc = st33zp24_i2c_get_desc, +}; + +static int st33zp24_i2c_probe(struct udevice *dev) +{ + struct tpm_chip *chip = dev_get_priv(dev); + + /* Default timeouts */ + chip->timeout_a = TIS_SHORT_TIMEOUT_MS; + chip->timeout_b = TIS_LONG_TIMEOUT_MS; + chip->timeout_c = TIS_SHORT_TIMEOUT_MS; + chip->timeout_d = TIS_SHORT_TIMEOUT_MS; + + chip->locality = LOCALITY0; + + i2c_set_chip_offset_len(dev, 0); + + debug("ST33ZP24 I2C TPM from STMicroelectronics found\n"); + + return 0; +} + +static int st33zp24_i2c_remove(struct udevice *dev) +{ + st33zp24_i2c_release_locality(dev); + + return 0; +} + +static const struct udevice_id st33zp24_i2c_ids[] = { + { .compatible = "st,st33zp24-i2c" }, + { } +}; + +U_BOOT_DRIVER(st33zp24_i2c) = { + .name = "st33zp24-i2c", + .id = UCLASS_TPM, + .of_match = of_match_ptr(st33zp24_i2c_ids), + .probe = st33zp24_i2c_probe, + .remove = st33zp24_i2c_remove, + .ops = &st33zp24_i2c_tpm_ops, + .priv_auto_alloc_size = sizeof(struct tpm_chip), +}; diff --git a/drivers/tpm/tpm_tis_st33zp24_spi.c b/drivers/tpm/tpm_tis_st33zp24_spi.c new file mode 100644 index 0000000000..417bbf1c69 --- /dev/null +++ b/drivers/tpm/tpm_tis_st33zp24_spi.c @@ -0,0 +1,672 @@ +/* + * STMicroelectronics TPM ST33ZP24 SPI UBOOT driver + * + * Copyright (C) 2016 STMicroelectronics + * + * Description: Device driver for ST33ZP24 SPI TPM TCG. + * + * This device driver implements the TPM interface as defined in + * the TCG TPM Interface Spec version 1.21, revision 1.0 and the + * STMicroelectronics Protocol Stack Specification version 1.2.0. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <spi.h> +#include <tpm.h> +#include <errno.h> +#include <linux/types.h> +#include <asm/unaligned.h> +#include <linux/compat.h> + +#include "tpm_tis.h" +#include "tpm_internal.h" + +#define TPM_ACCESS 0x0 +#define TPM_STS 0x18 +#define TPM_DATA_FIFO 0x24 + +#define LOCALITY0 0 + +#define TPM_DATA_FIFO 0x24 +#define TPM_INTF_CAPABILITY 0x14 + +#define TPM_DUMMY_BYTE 0x00 +#define TPM_WRITE_DIRECTION 0x80 + +#define MAX_SPI_LATENCY 15 +#define LOCALITY0 0 + +#define ST33ZP24_OK 0x5A +#define ST33ZP24_UNDEFINED_ERR 0x80 +#define ST33ZP24_BADLOCALITY 0x81 +#define ST33ZP24_TISREGISTER_UKNOWN 0x82 +#define ST33ZP24_LOCALITY_NOT_ACTIVATED 0x83 +#define ST33ZP24_HASH_END_BEFORE_HASH_START 0x84 +#define ST33ZP24_BAD_COMMAND_ORDER 0x85 +#define ST33ZP24_INCORECT_RECEIVED_LENGTH 0x86 +#define ST33ZP24_TPM_FIFO_OVERFLOW 0x89 +#define ST33ZP24_UNEXPECTED_READ_FIFO 0x8A +#define ST33ZP24_UNEXPECTED_WRITE_FIFO 0x8B +#define ST33ZP24_CMDRDY_SET_WHEN_PROCESSING_HASH_END 0x90 +#define ST33ZP24_DUMMY_BYTES 0x00 + +/* + * TPM command can be up to 2048 byte, A TPM response can be up to + * 1024 byte. + * Between command and response, there are latency byte (up to 15 + * usually on st33zp24 2 are enough). + * + * Overall when sending a command and expecting an answer we need if + * worst case: + * 2048 (for the TPM command) + 1024 (for the TPM answer). We need + * some latency byte before the answer is available (max 15). + * We have 2048 + 1024 + 15. + */ +#define ST33ZP24_SPI_BUFFER_SIZE (TPM_BUFSIZE + (TPM_BUFSIZE / 2) +\ + MAX_SPI_LATENCY) + +struct st33zp24_spi_phy { + int latency; + + u8 tx_buf[ST33ZP24_SPI_BUFFER_SIZE]; + u8 rx_buf[ST33ZP24_SPI_BUFFER_SIZE]; +}; + +static int st33zp24_spi_status_to_errno(u8 code) +{ + switch (code) { + case ST33ZP24_OK: + return 0; + case ST33ZP24_UNDEFINED_ERR: + case ST33ZP24_BADLOCALITY: + case ST33ZP24_TISREGISTER_UKNOWN: + case ST33ZP24_LOCALITY_NOT_ACTIVATED: + case ST33ZP24_HASH_END_BEFORE_HASH_START: + case ST33ZP24_BAD_COMMAND_ORDER: + case ST33ZP24_UNEXPECTED_READ_FIFO: + case ST33ZP24_UNEXPECTED_WRITE_FIFO: + case ST33ZP24_CMDRDY_SET_WHEN_PROCESSING_HASH_END: + return -EPROTO; + case ST33ZP24_INCORECT_RECEIVED_LENGTH: + case ST33ZP24_TPM_FIFO_OVERFLOW: + return -EMSGSIZE; + case ST33ZP24_DUMMY_BYTES: + return -ENOSYS; + } + return code; +} + +/* + * st33zp24_spi_send + * Send byte to TPM register according to the ST33ZP24 SPI protocol. + * @param: tpm, the chip description + * @param: tpm_register, the tpm tis register where the data should be written + * @param: tpm_data, the tpm_data to write inside the tpm_register + * @param: tpm_size, The length of the data + * @return: should be zero if success else a negative error code. + */ +static int st33zp24_spi_write(struct udevice *dev, u8 tpm_register, + const u8 *tpm_data, size_t tpm_size) +{ + int total_length = 0, ret; + struct spi_slave *slave = dev_get_parent_priv(dev); + struct st33zp24_spi_phy *phy = dev_get_platdata(dev); + + u8 *tx_buf = (u8 *)phy->tx_buf; + u8 *rx_buf = phy->rx_buf; + + tx_buf[total_length++] = TPM_WRITE_DIRECTION | LOCALITY0; + tx_buf[total_length++] = tpm_register; + + if (tpm_size > 0 && tpm_register == TPM_DATA_FIFO) { + tx_buf[total_length++] = tpm_size >> 8; + tx_buf[total_length++] = tpm_size; + } + memcpy(tx_buf + total_length, tpm_data, tpm_size); + total_length += tpm_size; + + memset(tx_buf + total_length, TPM_DUMMY_BYTE, phy->latency); + + total_length += phy->latency; + + ret = spi_claim_bus(slave); + if (ret < 0) + return ret; + + ret = spi_xfer(slave, total_length * 8, tx_buf, rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END); + if (ret < 0) + return ret; + + spi_release_bus(slave); + + if (ret == 0) + ret = rx_buf[total_length - 1]; + + return st33zp24_spi_status_to_errno(ret); +} + +/* + * spi_st33zp24_spi_read8_reg + * Recv byte from the TIS register according to the ST33ZP24 SPI protocol. + * @param: tpm, the chip description + * @param: tpm_loc, the locality to read register from + * @param: tpm_register, the tpm tis register where the data should be read + * @param: tpm_data, the TPM response + * @param: tpm_size, tpm TPM response size to read. + * @return: should be zero if success else a negative error code. + */ +static u8 st33zp24_spi_read8_reg(struct udevice *dev, u8 tpm_register, + u8 *tpm_data, size_t tpm_size) +{ + int total_length = 0, ret; + struct spi_slave *slave = dev_get_parent_priv(dev); + struct st33zp24_spi_phy *phy = dev_get_platdata(dev); + + u8 *tx_buf = (u8 *)phy->tx_buf; + u8 *rx_buf = phy->rx_buf; + + /* Pre-Header */ + tx_buf[total_length++] = LOCALITY0; + tx_buf[total_length++] = tpm_register; + + memset(&tx_buf[total_length], TPM_DUMMY_BYTE, + phy->latency + tpm_size); + total_length += phy->latency + tpm_size; + + ret = spi_claim_bus(slave); + if (ret < 0) + return 0; + + ret = spi_xfer(slave, total_length * 8, tx_buf, rx_buf, + SPI_XFER_BEGIN | SPI_XFER_END); + if (ret < 0) + return 0; + + spi_release_bus(slave); + + if (tpm_size > 0 && ret == 0) { + ret = rx_buf[total_length - tpm_size - 1]; + memcpy(tpm_data, rx_buf + total_length - tpm_size, tpm_size); + } + return ret; +} + +/* + * st33zp24_spi_recv + * Recv byte from the TIS register according to the ST33ZP24 SPI protocol. + * @param: phy_id, the phy description + * @param: tpm_register, the tpm tis register where the data should be read + * @param: tpm_data, the TPM response + * @param: tpm_size, tpm TPM response size to read. + * @return: number of byte read successfully: should be one if success. + */ +static int st33zp24_spi_read(struct udevice *dev, u8 tpm_register, + u8 *tpm_data, size_t tpm_size) +{ + int ret; + + ret = st33zp24_spi_read8_reg(dev, tpm_register, tpm_data, tpm_size); + if (!st33zp24_spi_status_to_errno(ret)) + return tpm_size; + + return ret; +} + +static int st33zp24_spi_evaluate_latency(struct udevice *dev) +{ + int latency = 1, status = 0; + u8 data = 0; + struct st33zp24_spi_phy *phy = dev_get_platdata(dev); + + while (!status && latency < MAX_SPI_LATENCY) { + phy->latency = latency; + status = st33zp24_spi_read8_reg(dev, TPM_INTF_CAPABILITY, + &data, 1); + latency++; + } + if (status < 0) + return status; + if (latency == MAX_SPI_LATENCY) + return -ENODEV; + + return latency - 1; +} + +/* + * st33zp24_spi_release_locality release the active locality + * @param: chip, the tpm chip description. + */ +static void st33zp24_spi_release_locality(struct udevice *dev) +{ + u8 data = TPM_ACCESS_ACTIVE_LOCALITY; + + st33zp24_spi_write(dev, TPM_ACCESS, &data, 1); +} + +/* + * st33zp24_spi_check_locality if the locality is active + * @param: chip, the tpm chip description + * @return: the active locality or -EACCES. + */ +static int st33zp24_spi_check_locality(struct udevice *dev) +{ + u8 data; + u8 status; + struct tpm_chip *chip = dev_get_priv(dev); + + status = st33zp24_spi_read(dev, TPM_ACCESS, &data, 1); + if (status && (data & + (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) == + (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) + return chip->locality; + + return -EACCES; +} + +/* + * st33zp24_spi_request_locality request the TPM locality + * @param: chip, the chip description + * @return: the active locality or negative value. + */ +static int st33zp24_spi_request_locality(struct udevice *dev) +{ + unsigned long start, stop; + long ret; + u8 data; + struct tpm_chip *chip = dev_get_priv(dev); + + if (st33zp24_spi_check_locality(dev) == chip->locality) + return chip->locality; + + data = TPM_ACCESS_REQUEST_USE; + ret = st33zp24_spi_write(dev, TPM_ACCESS, &data, 1); + if (ret < 0) + return ret; + + /* wait for locality activated */ + start = get_timer(0); + stop = chip->timeout_a; + do { + if (st33zp24_spi_check_locality(dev) >= 0) + return chip->locality; + udelay(TPM_TIMEOUT_MS * 1000); + } while (get_timer(start) < stop); + + return -EACCES; +} + +/* + * st33zp24_spi_status return the TPM_STS register + * @param: chip, the tpm chip description + * @return: the TPM_STS register value. + */ +static u8 st33zp24_spi_status(struct udevice *dev) +{ + u8 data; + + st33zp24_spi_read(dev, TPM_STS, &data, 1); + return data; +} + +/* + * st33zp24_spi_get_burstcount return the burstcount address 0x19 0x1A + * @param: chip, the chip description + * return: the burstcount or -TPM_DRIVER_ERR in case of error. + */ +static int st33zp24_spi_get_burstcount(struct udevice *dev) +{ + struct tpm_chip *chip = dev_get_priv(dev); + unsigned long start, stop; + int burstcnt, status; + u8 tpm_reg, temp; + + /* wait for burstcount */ + start = get_timer(0); + stop = chip->timeout_d; + do { + tpm_reg = TPM_STS + 1; + status = st33zp24_spi_read(dev, tpm_reg, &temp, 1); + if (status < 0) + return -EBUSY; + + tpm_reg = TPM_STS + 2; + burstcnt = temp; + status = st33zp24_spi_read(dev, tpm_reg, &temp, 1); + if (status < 0) + return -EBUSY; + + burstcnt |= temp << 8; + if (burstcnt) + return burstcnt; + udelay(TIS_SHORT_TIMEOUT_MS * 1000); + } while (get_timer(start) < stop); + + return -EBUSY; +} + +/* + * st33zp24_spi_cancel, cancel the current command execution or + * set STS to COMMAND READY. + * @param: chip, tpm_chip description. + */ +static void st33zp24_spi_cancel(struct udevice *dev) +{ + u8 data; + + data = TPM_STS_COMMAND_READY; + st33zp24_spi_write(dev, TPM_STS, &data, 1); +} + +/* + * st33zp24_spi_wait_for_stat wait for a TPM_STS value + * @param: chip, the tpm chip description + * @param: mask, the value mask to wait + * @param: timeout, the timeout + * @param: status, + * @return: the tpm status, 0 if success, -ETIME if timeout is reached. + */ +static int st33zp24_spi_wait_for_stat(struct udevice *dev, u8 mask, + unsigned long timeout, int *status) +{ + unsigned long start, stop; + + /* Check current status */ + *status = st33zp24_spi_status(dev); + if ((*status & mask) == mask) + return 0; + + start = get_timer(0); + stop = timeout; + do { + udelay(TPM_TIMEOUT_MS * 1000); + *status = st33zp24_spi_status(dev); + if ((*status & mask) == mask) + return 0; + } while (get_timer(start) < stop); + + return -ETIME; +} + +/* + * st33zp24_spi_recv_data receive data + * @param: chip, the tpm chip description + * @param: buf, the buffer where the data are received + * @param: count, the number of data to receive + * @return: the number of bytes read from TPM FIFO. + */ +static int st33zp24_spi_recv_data(struct udevice *dev, u8 *buf, size_t count) +{ + struct tpm_chip *chip = dev_get_priv(dev); + int size = 0, burstcnt, len, ret, status; + + while (size < count && + st33zp24_spi_wait_for_stat(dev, TPM_STS_DATA_AVAIL | TPM_STS_VALID, + chip->timeout_c, &status) == 0) { + burstcnt = st33zp24_spi_get_burstcount(dev); + if (burstcnt < 0) + return burstcnt; + len = min_t(int, burstcnt, count - size); + ret = st33zp24_spi_read(dev, TPM_DATA_FIFO, buf + size, len); + if (ret < 0) + return ret; + + size += len; + } + return size; +} + +/* + * st33zp24_spi_recv received TPM response through TPM phy. + * @param: chip, tpm_chip description. + * @param: buf, the buffer to store data. + * @param: count, the number of bytes that can received (sizeof buf). + * @return: Returns zero in case of success else -EIO. + */ +static int st33zp24_spi_recv(struct udevice *dev, u8 *buf, size_t count) +{ + struct tpm_chip *chip = dev_get_priv(dev); + int size, expected; + + if (!chip) + return -ENODEV; + + if (count < TPM_HEADER_SIZE) { + size = -EIO; + goto out; + } + + size = st33zp24_spi_recv_data(dev, buf, TPM_HEADER_SIZE); + if (size < TPM_HEADER_SIZE) { + debug("TPM error, unable to read header\n"); + goto out; + } + + expected = get_unaligned_be32(buf + 2); + if (expected > count) { + size = -EIO; + goto out; + } + + size += st33zp24_spi_recv_data(dev, &buf[TPM_HEADER_SIZE], + expected - TPM_HEADER_SIZE); + if (size < expected) { + debug("TPM error, unable to read remaining bytes of result\n"); + size = -EIO; + goto out; + } + +out: + st33zp24_spi_cancel(dev); + st33zp24_spi_release_locality(dev); + + return size; +} + +/* + * st33zp24_spi_send send TPM commands through TPM phy. + * @param: chip, tpm_chip description. + * @param: buf, the buffer to send. + * @param: len, the number of bytes to send. + * @return: Returns zero in case of success else the negative error code. + */ +static int st33zp24_spi_send(struct udevice *dev, const u8 *buf, size_t len) +{ + struct tpm_chip *chip = dev_get_priv(dev); + u32 i, size; + int burstcnt, ret, status; + u8 data, tpm_stat; + + if (!chip) + return -ENODEV; + if (len < TPM_HEADER_SIZE) + return -EIO; + + ret = st33zp24_spi_request_locality(dev); + if (ret < 0) + return ret; + + tpm_stat = st33zp24_spi_status(dev); + if ((tpm_stat & TPM_STS_COMMAND_READY) == 0) { + st33zp24_spi_cancel(dev); + if (st33zp24_spi_wait_for_stat(dev, TPM_STS_COMMAND_READY, + chip->timeout_b, &status) < 0) { + ret = -ETIME; + goto out_err; + } + } + + for (i = 0; i < len - 1;) { + burstcnt = st33zp24_spi_get_burstcount(dev); + if (burstcnt < 0) + return burstcnt; + + size = min_t(int, len - i - 1, burstcnt); + ret = st33zp24_spi_write(dev, TPM_DATA_FIFO, buf + i, size); + if (ret < 0) + goto out_err; + + i += size; + } + + tpm_stat = st33zp24_spi_status(dev); + if ((tpm_stat & TPM_STS_DATA_EXPECT) == 0) { + ret = -EIO; + goto out_err; + } + + ret = st33zp24_spi_write(dev, TPM_DATA_FIFO, buf + len - 1, 1); + if (ret < 0) + goto out_err; + + tpm_stat = st33zp24_spi_status(dev); + if ((tpm_stat & TPM_STS_DATA_EXPECT) != 0) { + ret = -EIO; + goto out_err; + } + + data = TPM_STS_GO; + ret = st33zp24_spi_write(dev, TPM_STS, &data, 1); + if (ret < 0) + goto out_err; + + return len; + +out_err: + st33zp24_spi_cancel(dev); + st33zp24_spi_release_locality(dev); + + return ret; +} + +static int st33zp24_spi_cleanup(struct udevice *dev) +{ + st33zp24_spi_cancel(dev); + /* + * The TPM needs some time to clean up here, + * so we sleep rather than keeping the bus busy + */ + mdelay(2); + st33zp24_spi_release_locality(dev); + + return 0; +} + +static int st33zp24_spi_init(struct udevice *dev) +{ + struct tpm_chip *chip = dev_get_priv(dev); + struct st33zp24_spi_phy *phy = dev_get_platdata(dev); + + chip->is_open = 1; + + /* Default timeouts - these could move to the device tree */ + chip->timeout_a = TIS_SHORT_TIMEOUT_MS; + chip->timeout_b = TIS_LONG_TIMEOUT_MS; + chip->timeout_c = TIS_SHORT_TIMEOUT_MS; + chip->timeout_d = TIS_SHORT_TIMEOUT_MS; + + chip->locality = LOCALITY0; + + phy->latency = st33zp24_spi_evaluate_latency(dev); + if (phy->latency <= 0) + return -ENODEV; + + /* + * A timeout query to TPM can be placed here. + * Standard timeout values are used so far + */ + + return 0; +} + +static int st33zp24_spi_open(struct udevice *dev) +{ + struct tpm_chip *chip = dev_get_priv(dev); + int rc; + + debug("%s: start\n", __func__); + if (chip->is_open) + return -EBUSY; + + rc = st33zp24_spi_init(dev); + if (rc < 0) + chip->is_open = 0; + + return rc; +} + +static int st33zp24_spi_close(struct udevice *dev) +{ + struct tpm_chip *chip = dev_get_priv(dev); + + if (chip->is_open) { + st33zp24_spi_release_locality(dev); + chip->is_open = 0; + chip->vend_dev = 0; + } + + return 0; +} + +static int st33zp24_spi_get_desc(struct udevice *dev, char *buf, int size) +{ + struct tpm_chip *chip = dev_get_priv(dev); + + if (size < 50) + return -ENOSPC; + + return snprintf(buf, size, "1.2 TPM (%s, chip type %s device-id 0x%x)", + chip->is_open ? "open" : "closed", + dev->name, + chip->vend_dev >> 16); +} + +const struct tpm_ops st33zp24_spi_tpm_ops = { + .open = st33zp24_spi_open, + .close = st33zp24_spi_close, + .recv = st33zp24_spi_recv, + .send = st33zp24_spi_send, + .cleanup = st33zp24_spi_cleanup, + .get_desc = st33zp24_spi_get_desc, +}; + +static int st33zp24_spi_probe(struct udevice *dev) +{ + struct tpm_chip_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->duration_ms[TPM_SHORT] = TIS_SHORT_TIMEOUT_MS; + uc_priv->duration_ms[TPM_MEDIUM] = TIS_LONG_TIMEOUT_MS; + uc_priv->duration_ms[TPM_LONG] = TIS_LONG_TIMEOUT_MS; + uc_priv->retry_time_ms = TPM_TIMEOUT_MS; + + debug("ST33ZP24 SPI TPM from STMicroelectronics found\n"); + + return 0; +} + +static int st33zp24_spi_remove(struct udevice *dev) +{ + st33zp24_spi_release_locality(dev); + + return 0; +} + +static const struct udevice_id st33zp24_spi_ids[] = { + { .compatible = "st,st33zp24-spi" }, + { } +}; + +U_BOOT_DRIVER(st33zp24_spi_spi) = { + .name = "st33zp24-spi", + .id = UCLASS_TPM, + .of_match = of_match_ptr(st33zp24_spi_ids), + .probe = st33zp24_spi_probe, + .remove = st33zp24_spi_remove, + .ops = &st33zp24_spi_tpm_ops, + .priv_auto_alloc_size = sizeof(struct tpm_chip), + .platdata_auto_alloc_size = sizeof(struct st33zp24_spi_phy), +}; diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index f54631cc17..fbc5d7cfe7 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -44,7 +44,17 @@ config VIDEO_BPP32 this option, such displays will not be supported and console output will be empty. -config VIDEO_ROTATION +config CONSOLE_NORMAL + bool "Support a simple text console" + depends on DM_VIDEO + default y if DM_VIDEO + help + Support drawing text on the frame buffer console so that it can be + used as a console. Rotation is not supported by this driver (see + CONFIG_CONSOLE_ROTATION for that). A built-in 8x16 font is used + for the display. + +config CONSOLE_ROTATION bool "Support rotated displays" depends on DM_VIDEO help @@ -57,6 +67,30 @@ config VIDEO_ROTATION struct video_priv: 0=unrotated, 1=90 degrees clockwise, 2=180 degrees, 3=270 degrees. +config CONSOLE_TRUETYPE + bool "Support a console that uses TrueType fonts" + depends on DM_VIDEO + help + TrueTrype fonts can provide outline-drawing capability rather than + needing to provide a bitmap for each font and size that is needed. + With this option you can adjust the text size and use a variety of + fonts. Note that this is noticeably slower than with normal console. + +config CONSOLE_TRUETYPE_SIZE + int "TrueType font size" + depends on CONSOLE_TRUETYPE + default 18 + help + This sets the font size for the console. The size is measured in + pixels and is the nominal height of a character. Note that fonts + are commonly measured in 'points', being 1/72 inch (about 3.52mm). + However that measurement depends on the size of your display and + there is no standard display density. At present there is not a + method to select the display's physical size, which would allow + U-Boot to calculate the correct font size. + +source "drivers/video/fonts/Kconfig" + config VIDEO_VESA bool "Enable VESA video driver support" default n diff --git a/drivers/video/Makefile b/drivers/video/Makefile index be908f6ed8..c55e6eda3b 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -9,12 +9,14 @@ ifdef CONFIG_DM obj-$(CONFIG_DISPLAY) += display-uclass.o obj-$(CONFIG_DM_VIDEO) += backlight-uclass.o obj-$(CONFIG_DM_VIDEO) += panel-uclass.o simple_panel.o -obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o console_normal.o +obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o obj-$(CONFIG_DM_VIDEO) += video_bmp.o ifdef CONFIG_DM_VIDEO obj-$(CONFIG_DM_PWM) += pwm_backlight.o endif -obj-$(CONFIG_VIDEO_ROTATION) += console_rotate.o +obj-$(CONFIG_CONSOLE_NORMAL) += console_normal.o +obj-$(CONFIG_CONSOLE_ROTATION) += console_rotate.o +obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/ endif obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c index d1031c8ed1..89a55dd11d 100644 --- a/drivers/video/console_normal.c +++ b/drivers/video/console_normal.c @@ -71,13 +71,18 @@ static int console_normal_move_rows(struct udevice *dev, uint rowdst, return 0; } -static int console_normal_putc_xy(struct udevice *dev, uint x, uint y, char ch) +static int console_normal_putc_xy(struct udevice *dev, uint x_frac, uint y, + char ch) { + struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid); int i, row; void *line = vid_priv->fb + y * vid_priv->line_length + - x * VNBYTES(vid_priv->bpix); + VID_TO_PIXEL(x_frac) * VNBYTES(vid_priv->bpix); + + if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) + return -EAGAIN; for (row = 0; row < VIDEO_FONT_HEIGHT; row++) { uchar bits = video_fontdata[ch * VIDEO_FONT_HEIGHT + row]; @@ -125,6 +130,20 @@ static int console_normal_putc_xy(struct udevice *dev, uint x, uint y, char ch) line += vid_priv->line_length; } + return VID_TO_POS(VIDEO_FONT_WIDTH); +} + +static int console_normal_probe(struct udevice *dev) +{ + struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); + struct udevice *vid_dev = dev->parent; + struct video_priv *vid_priv = dev_get_uclass_priv(vid_dev); + + vc_priv->x_charsize = VIDEO_FONT_WIDTH; + vc_priv->y_charsize = VIDEO_FONT_HEIGHT; + vc_priv->cols = vid_priv->xsize / VIDEO_FONT_WIDTH; + vc_priv->rows = vid_priv->ysize / VIDEO_FONT_HEIGHT; + return 0; } @@ -138,4 +157,5 @@ U_BOOT_DRIVER(vidconsole_normal) = { .name = "vidconsole0", .id = UCLASS_VIDEO_CONSOLE, .ops = &console_normal_ops, + .probe = console_normal_probe, }; diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c index ebb31d8cd0..227141d687 100644 --- a/drivers/video/console_rotate.c +++ b/drivers/video/console_rotate.c @@ -82,17 +82,22 @@ static int console_move_rows_1(struct udevice *dev, uint rowdst, uint rowsrc, return 0; } -static int console_putc_xy_1(struct udevice *dev, uint x, uint y, char ch) +static int console_putc_xy_1(struct udevice *dev, uint x_frac, uint y, char ch) { + struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid); int pbytes = VNBYTES(vid_priv->bpix); int i, col; int mask = 0x80; - void *line = vid_priv->fb + (x + 1) * vid_priv->line_length - - (y + 1) * pbytes; + void *line; uchar *pfont = video_fontdata + ch * VIDEO_FONT_HEIGHT; + line = vid_priv->fb + (VID_TO_PIXEL(x_frac) + 1) * + vid_priv->line_length - (y + 1) * pbytes; + if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) + return -EAGAIN; + for (col = 0; col < VIDEO_FONT_HEIGHT; col++) { switch (vid_priv->bpix) { #ifdef CONFIG_VIDEO_BPP8 @@ -135,7 +140,7 @@ static int console_putc_xy_1(struct udevice *dev, uint x, uint y, char ch) mask >>= 1; } - return 0; + return VID_TO_POS(VIDEO_FONT_WIDTH); } @@ -201,17 +206,21 @@ static int console_move_rows_2(struct udevice *dev, uint rowdst, uint rowsrc, return 0; } -static int console_putc_xy_2(struct udevice *dev, uint x, uint y, char ch) +static int console_putc_xy_2(struct udevice *dev, uint x_frac, uint y, char ch) { + struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid); int i, row; void *line; + if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) + return -EAGAIN; + line = vid_priv->fb + (vid_priv->ysize - y - 1) * - vid_priv->line_length + - (vid_priv->xsize - x - VIDEO_FONT_WIDTH - 1) * - VNBYTES(vid_priv->bpix); + vid_priv->line_length + + (vid_priv->xsize - VID_TO_PIXEL(x_frac) - + VIDEO_FONT_WIDTH - 1) * VNBYTES(vid_priv->bpix); for (row = 0; row < VIDEO_FONT_HEIGHT; row++) { uchar bits = video_fontdata[ch * VIDEO_FONT_HEIGHT + row]; @@ -259,7 +268,7 @@ static int console_putc_xy_2(struct udevice *dev, uint x, uint y, char ch) line -= vid_priv->line_length; } - return 0; + return VID_TO_POS(VIDEO_FONT_WIDTH); } static int console_set_row_3(struct udevice *dev, uint row, int clr) @@ -329,17 +338,22 @@ static int console_move_rows_3(struct udevice *dev, uint rowdst, uint rowsrc, return 0; } -static int console_putc_xy_3(struct udevice *dev, uint x, uint y, char ch) +static int console_putc_xy_3(struct udevice *dev, uint x_frac, uint y, char ch) { + struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); struct udevice *vid = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid); int pbytes = VNBYTES(vid_priv->bpix); int i, col; int mask = 0x80; - void *line = vid_priv->fb + (vid_priv->ysize - x - 1) * + void *line = vid_priv->fb + + (vid_priv->ysize - VID_TO_PIXEL(x_frac) - 1) * vid_priv->line_length + y * pbytes; uchar *pfont = video_fontdata + ch * VIDEO_FONT_HEIGHT; + if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac) + return -EAGAIN; + for (col = 0; col < VIDEO_FONT_HEIGHT; col++) { switch (vid_priv->bpix) { #ifdef CONFIG_VIDEO_BPP8 @@ -382,17 +396,35 @@ static int console_putc_xy_3(struct udevice *dev, uint x, uint y, char ch) mask >>= 1; } - return 0; + return VID_TO_POS(VIDEO_FONT_WIDTH); } +static int console_probe_2(struct udevice *dev) +{ + struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); + struct udevice *vid_dev = dev->parent; + struct video_priv *vid_priv = dev_get_uclass_priv(vid_dev); + + vc_priv->x_charsize = VIDEO_FONT_WIDTH; + vc_priv->y_charsize = VIDEO_FONT_HEIGHT; + vc_priv->cols = vid_priv->xsize / VIDEO_FONT_WIDTH; + vc_priv->rows = vid_priv->ysize / VIDEO_FONT_HEIGHT; + + return 0; +} + static int console_probe_1_3(struct udevice *dev) { - struct vidconsole_priv *priv = dev_get_uclass_priv(dev); - struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); + struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); + struct udevice *vid_dev = dev->parent; + struct video_priv *vid_priv = dev_get_uclass_priv(vid_dev); - priv->cols = vid_priv->ysize / VIDEO_FONT_WIDTH; - priv->rows = vid_priv->xsize / VIDEO_FONT_HEIGHT; + vc_priv->x_charsize = VIDEO_FONT_WIDTH; + vc_priv->y_charsize = VIDEO_FONT_HEIGHT; + vc_priv->cols = vid_priv->ysize / VIDEO_FONT_WIDTH; + vc_priv->rows = vid_priv->xsize / VIDEO_FONT_HEIGHT; + vc_priv->xsize_frac = VID_TO_POS(vid_priv->ysize); return 0; } @@ -426,6 +458,7 @@ U_BOOT_DRIVER(vidconsole_2) = { .name = "vidconsole2", .id = UCLASS_VIDEO_CONSOLE, .ops = &console_ops_2, + .probe = console_probe_2, }; U_BOOT_DRIVER(vidconsole_3) = { diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c new file mode 100644 index 0000000000..c249f047f5 --- /dev/null +++ b/drivers/video/console_truetype.c @@ -0,0 +1,550 @@ +/* + * Copyright (c) 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <video.h> +#include <video_console.h> + +/* Functions needed by stb_truetype.h */ +static int tt_floor(double val) +{ + if (val < 0) + return (int)(val - 0.999); + + return (int)val; +} + +static int tt_ceil(double val) +{ + if (val < 0) + return (int)val; + + return (int)(val + 0.999); +} + +static double frac(double val) +{ + return val - tt_floor(val); +} + +static double tt_fabs(double x) +{ + return x < 0 ? -x : x; +} + + /* + * Simple square root algorithm. This is from: + * http://stackoverflow.com/questions/1623375/writing-your-own-square-root-function + * Written by Chihung Yu + * Creative Commons license + * http://creativecommons.org/licenses/by-sa/3.0/legalcode + * It has been modified to compile correctly, and for U-Boot style. + */ +static double tt_sqrt(double value) +{ + double lo = 1.0; + double hi = value; + + while (hi - lo > 0.00001) { + double mid = lo + (hi - lo) / 2; + + if (mid * mid - value > 0.00001) + hi = mid; + else + lo = mid; + } + + return lo; +} + +#define STBTT_ifloor tt_floor +#define STBTT_iceil tt_ceil +#define STBTT_fabs tt_fabs +#define STBTT_sqrt tt_sqrt +#define STBTT_malloc(size, u) ((void)(u), malloc(size)) +#define STBTT_free(size, u) ((void)(u), free(size)) +#define STBTT_assert(x) +#define STBTT_strlen(x) strlen(x) +#define STBTT_memcpy memcpy +#define STBTT_memset memset + +#define STB_TRUETYPE_IMPLEMENTATION +#include "stb_truetype.h" + +/** + * struct pos_info - Records a cursor position + * + * @xpos_frac: Fractional X position in pixels (multiplied by VID_FRAC_DIV) + * @ypos: Y position (pixels from the top) + */ +struct pos_info { + int xpos_frac; + int ypos; +}; + +/* + * Allow one for each character on the command line plus one for each newline. + * This is just an estimate, but it should not be exceeded. + */ +#define POS_HISTORY_SIZE (CONFIG_SYS_CBSIZE * 11 / 10) + +/** + * struct console_tt_priv - Private data for this driver + * + * @font_size: Vertical font size in pixels + * @font_data: Pointer to TrueType font file contents + * @font: TrueType font information for the current font + * @pos: List of cursor positions for each character written. This is + * used to handle backspace. We clear the frame buffer between + * the last position and the current position, thus erasing the + * last character. We record enough characters to go back to the + * start of the current command line. + * @pos_ptr: Current position in the position history + * @baseline: Pixel offset of the font's baseline from the cursor position. + * This is the 'ascent' of the font, scaled to pixel coordinates. + * It measures the distance from the baseline to the top of the + * font. + * @scale: Scale of the font. This is calculated from the pixel height + * of the font. It is used by the STB library to generate images + * of the correct size. + */ +struct console_tt_priv { + int font_size; + u8 *font_data; + stbtt_fontinfo font; + struct pos_info pos[POS_HISTORY_SIZE]; + int pos_ptr; + int baseline; + double scale; +}; + +static int console_truetype_set_row(struct udevice *dev, uint row, int clr) +{ + struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); + struct console_tt_priv *priv = dev_get_priv(dev); + void *line; + int pixels = priv->font_size * vid_priv->line_length; + int i; + + line = vid_priv->fb + row * priv->font_size * vid_priv->line_length; + switch (vid_priv->bpix) { +#ifdef CONFIG_VIDEO_BPP8 + case VIDEO_BPP8: { + uint8_t *dst = line; + + for (i = 0; i < pixels; i++) + *dst++ = clr; + break; + } +#endif +#ifdef CONFIG_VIDEO_BPP16 + case VIDEO_BPP16: { + uint16_t *dst = line; + + for (i = 0; i < pixels; i++) + *dst++ = clr; + break; + } +#endif +#ifdef CONFIG_VIDEO_BPP32 + case VIDEO_BPP32: { + uint32_t *dst = line; + + for (i = 0; i < pixels; i++) + *dst++ = clr; + break; + } +#endif + default: + return -ENOSYS; + } + + return 0; +} + +static int console_truetype_move_rows(struct udevice *dev, uint rowdst, + uint rowsrc, uint count) +{ + struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); + struct console_tt_priv *priv = dev_get_priv(dev); + void *dst; + void *src; + int i, diff; + + dst = vid_priv->fb + rowdst * priv->font_size * vid_priv->line_length; + src = vid_priv->fb + rowsrc * priv->font_size * vid_priv->line_length; + memmove(dst, src, priv->font_size * vid_priv->line_length * count); + + /* Scroll up our position history */ + diff = (rowsrc - rowdst) * priv->font_size; + for (i = 0; i < priv->pos_ptr; i++) + priv->pos[i].ypos -= diff; + + return 0; +} + +static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y, + char ch) +{ + struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); + struct udevice *vid = dev->parent; + struct video_priv *vid_priv = dev_get_uclass_priv(vid); + struct console_tt_priv *priv = dev_get_priv(dev); + stbtt_fontinfo *font = &priv->font; + int width, height, xoff, yoff; + double xpos, x_shift; + int lsb; + int width_frac, linenum; + struct pos_info *pos; + u8 *bits, *data; + int advance; + void *line; + int row; + + /* First get some basic metrics about this character */ + stbtt_GetCodepointHMetrics(font, ch, &advance, &lsb); + + /* + * First out our current X position in fractional pixels. If we wrote + * a character previously, using kerning to fine-tune the position of + * this character */ + xpos = frac(VID_TO_PIXEL((double)x)); + if (vc_priv->last_ch) { + xpos += priv->scale * stbtt_GetCodepointKernAdvance(font, + vc_priv->last_ch, ch); + } + + /* + * Figure out where the cursor will move to after this character, and + * abort if we are out of space on this line. Also calculate the + * effective width of this character, which will be our return value: + * it dictates how much the cursor will move forward on the line. + */ + x_shift = xpos - (double)tt_floor(xpos); + xpos += advance * priv->scale; + width_frac = (int)VID_TO_POS(xpos); + if (x + width_frac >= vc_priv->xsize_frac) + return -EAGAIN; + + /* Write the current cursor position into history */ + if (priv->pos_ptr < POS_HISTORY_SIZE) { + pos = &priv->pos[priv->pos_ptr]; + pos->xpos_frac = vc_priv->xcur_frac; + pos->ypos = vc_priv->ycur; + priv->pos_ptr++; + } + + /* + * Figure out how much past the start of a pixel we are, and pass this + * information into the render, which will return a 8-bit-per-pixel + * image of the character. For empty characters, like ' ', data will + * return NULL; + */ + data = stbtt_GetCodepointBitmapSubpixel(font, priv->scale, priv->scale, + x_shift, 0, ch, &width, &height, + &xoff, &yoff); + if (!data) + return width_frac; + + /* Figure out where to write the character in the frame buffer */ + bits = data; + line = vid_priv->fb + y * vid_priv->line_length + + VID_TO_PIXEL(x) * VNBYTES(vid_priv->bpix); + linenum = priv->baseline + yoff; + if (linenum > 0) + line += linenum * vid_priv->line_length; + + /* + * Write a row at a time, converting the 8bpp image into the colour + * depth of the display. We only expect white-on-black or the reverse + * so the code only handles this simple case. + */ + for (row = 0; row < height; row++) { + switch (vid_priv->bpix) { +#ifdef CONFIG_VIDEO_BPP16 + case VIDEO_BPP16: { + uint16_t *dst = (uint16_t *)line + xoff; + int i; + + for (i = 0; i < width; i++) { + int val = *bits; + int out; + + if (vid_priv->colour_bg) + val = 255 - val; + out = val >> 3 | + (val >> 2) << 5 | + (val >> 3) << 11; + if (vid_priv->colour_fg) + *dst++ |= out; + else + *dst++ &= out; + bits++; + } + break; + } +#endif + default: + return -ENOSYS; + } + + line += vid_priv->line_length; + } + free(data); + + return width_frac; +} + +/** + * console_truetype_erase() - Erase a character + * + * This is used for backspace. We erase a square of the display within the + * given bounds. + * + * @dev: Device to update + * @xstart: X start position in pixels from the left + * @ystart: Y start position in pixels from the top + * @xend: X end position in pixels from the left + * @yend: Y end position in pixels from the top + * @clr: Value to write + * @return 0 if OK, -ENOSYS if the display depth is not supported + */ +static int console_truetype_erase(struct udevice *dev, int xstart, int ystart, + int xend, int yend, int clr) +{ + struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); + void *line; + int pixels = xend - xstart; + int row, i; + + line = vid_priv->fb + ystart * vid_priv->line_length; + line += xstart * VNBYTES(vid_priv->bpix); + for (row = ystart; row < yend; row++) { + switch (vid_priv->bpix) { +#ifdef CONFIG_VIDEO_BPP8 + case VIDEO_BPP8: { + uint8_t *dst = line; + + for (i = 0; i < pixels; i++) + *dst++ = clr; + break; + } +#endif +#ifdef CONFIG_VIDEO_BPP16 + case VIDEO_BPP16: { + uint16_t *dst = line; + + for (i = 0; i < pixels; i++) + *dst++ = clr; + break; + } +#endif +#ifdef CONFIG_VIDEO_BPP32 + case VIDEO_BPP32: { + uint32_t *dst = line; + + for (i = 0; i < pixels; i++) + *dst++ = clr; + break; + } +#endif + default: + return -ENOSYS; + } + line += vid_priv->line_length; + } + + return 0; +} + +/** + * console_truetype_backspace() - Handle a backspace operation + * + * This clears the previous character so that the console looks as if it had + * not been entered. + * + * @dev: Device to update + * @return 0 if OK, -ENOSYS if not supported + */ +static int console_truetype_backspace(struct udevice *dev) +{ + struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); + struct console_tt_priv *priv = dev_get_priv(dev); + struct udevice *vid_dev = dev->parent; + struct video_priv *vid_priv = dev_get_uclass_priv(vid_dev); + struct pos_info *pos; + int xend; + + /* + * This indicates a very strange error higher in the stack. The caller + * has sent out n character and n + 1 backspaces. + */ + if (!priv->pos_ptr) + return -ENOSYS; + + /* Pop the last cursor position off the stack */ + pos = &priv->pos[--priv->pos_ptr]; + + /* + * Figure out the end position for clearing. Normlly it is the current + * cursor position, but if we are clearing a character on the previous + * line, we clear from the end of the line. + */ + if (pos->ypos == vc_priv->ycur) + xend = VID_TO_PIXEL(vc_priv->xcur_frac); + else + xend = vid_priv->xsize; + + console_truetype_erase(dev, VID_TO_PIXEL(pos->xpos_frac), pos->ypos, + xend, pos->ypos + vc_priv->y_charsize, + vid_priv->colour_bg); + + /* Move the cursor back to where it was when we pushed this record */ + vc_priv->xcur_frac = pos->xpos_frac; + vc_priv->ycur = pos->ypos; + + return 0; +} + +static int console_truetype_entry_start(struct udevice *dev) +{ + struct console_tt_priv *priv = dev_get_priv(dev); + + /* A new input line has start, so clear our history */ + priv->pos_ptr = 0; + + return 0; +} + +/* + * Provides a list of fonts which can be obtained at run-time in U-Boot. These + * are compiled in by the Makefile. + * + * At present there is no mechanism to select a particular font - the first + * one found is the one that is used. But the build system and the code here + * supports multiple fonts, which may be useful for certain firmware screens. + */ +struct font_info { + char *name; + u8 *begin; + u8 *end; +}; + +#define FONT_DECL(_name) \ + extern u8 __ttf_ ## _name ## _begin[]; \ + extern u8 __ttf_ ## _name ## _end[]; + +#define FONT_ENTRY(_name) { \ + .name = #_name, \ + .begin = __ttf_ ## _name ## _begin, \ + .end = __ttf_ ## _name ## _end, \ + } + +FONT_DECL(nimbus_sans_l_regular); +FONT_DECL(ankacoder_c75_r); +FONT_DECL(rufscript010); +FONT_DECL(cantoraone_regular); + +static struct font_info font_table[] = { +#ifdef CONFIG_CONSOLE_TRUETYPE_NIMBUS + FONT_ENTRY(nimbus_sans_l_regular), +#endif +#ifdef CONFIG_CONSOLE_TRUETYPE_ANKACODER + FONT_ENTRY(ankacoder_c75_r), +#endif +#ifdef CONFIG_CONSOLE_TRUETYPE_RUFSCRIPT + FONT_ENTRY(rufscript010), +#endif +#ifdef CONFIG_CONSOLE_TRUETYPE_CANTORAONE + FONT_ENTRY(cantoraone_regular), +#endif + {} /* sentinel */ +}; + +#define FONT_BEGIN(name) __ttf_ ## name ## _begin +#define FONT_END(name) __ttf_ ## name ## _end +#define FONT_IS_VALID(name) (abs(FONT_END(name) - FONT_BEGIN) > 4) + +/** + * console_truetype_find_font() - Find a suitable font + * + * This searched for the first available font. + * + * @return pointer to the font, or NULL if none is found + */ +static u8 *console_truetype_find_font(void) +{ + struct font_info *tab; + + for (tab = font_table; tab->begin; tab++) { + if (abs(tab->begin - tab->end) > 4) { + debug("%s: Font '%s', at %p, size %lx\n", __func__, + tab->name, tab->begin, + (ulong)(tab->end - tab->begin)); + return tab->begin; + } + } + + return NULL; +} + +static int console_truetype_probe(struct udevice *dev) +{ + struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev); + struct console_tt_priv *priv = dev_get_priv(dev); + struct udevice *vid_dev = dev->parent; + struct video_priv *vid_priv = dev_get_uclass_priv(vid_dev); + stbtt_fontinfo *font = &priv->font; + int ascent; + + debug("%s: start\n", __func__); + if (vid_priv->font_size) + priv->font_size = vid_priv->font_size; + else + priv->font_size = CONFIG_CONSOLE_TRUETYPE_SIZE; + priv->font_data = console_truetype_find_font(); + if (!priv->font_data) { + debug("%s: Could not find any fonts\n", __func__); + return -EBFONT; + } + + vc_priv->x_charsize = priv->font_size; + vc_priv->y_charsize = priv->font_size; + vc_priv->xstart_frac = VID_TO_POS(2); + vc_priv->cols = vid_priv->xsize / priv->font_size; + vc_priv->rows = vid_priv->ysize / priv->font_size; + vc_priv->tab_width_frac = VID_TO_POS(priv->font_size) * 8 / 2; + + if (!stbtt_InitFont(font, priv->font_data, 0)) { + debug("%s: Font init failed\n", __func__); + return -EPERM; + } + + /* Pre-calculate some things we will need regularly */ + priv->scale = stbtt_ScaleForPixelHeight(font, priv->font_size); + stbtt_GetFontVMetrics(font, &ascent, 0, 0); + priv->baseline = (int)(ascent * priv->scale); + debug("%s: ready\n", __func__); + + return 0; +} + +struct vidconsole_ops console_truetype_ops = { + .putc_xy = console_truetype_putc_xy, + .move_rows = console_truetype_move_rows, + .set_row = console_truetype_set_row, + .backspace = console_truetype_backspace, + .entry_start = console_truetype_entry_start, +}; + +U_BOOT_DRIVER(vidconsole_truetype) = { + .name = "vidconsole_tt", + .id = UCLASS_VIDEO_CONSOLE, + .ops = &console_truetype_ops, + .probe = console_truetype_probe, + .priv_auto_alloc_size = sizeof(struct console_tt_priv), +}; diff --git a/drivers/video/fonts/Kconfig b/drivers/video/fonts/Kconfig new file mode 100644 index 0000000000..3f1398db50 --- /dev/null +++ b/drivers/video/fonts/Kconfig @@ -0,0 +1,51 @@ +# +# Video fonts +# + +menu "TrueType Fonts" + +config CONSOLE_TRUETYPE_NIMBUS + bool "Nimbus Sans Regular" + depends on CONSOLE_TRUETYPE + help + Nimbus Sans L is a version of Nimbus Sans using Adobe font sources. + It was designed in 1987. A subset of Nimbus Sans L were released + under the GPL. Although the characters are not exactly the same, + Nimbus Sans L has metrics almost identical to Helvetica and Arial. + (From Wikipedia, the free encyclopedia) + From: https://fontlibrary.org/en/font/nimbus-sans-l + License: GNU GPL v3 + http://www.gnu.org/copyleft/gpl.html + +config CONSOLE_TRUETYPE_ANKACODER + bool "Anka Coder Narrow" + depends on CONSOLE_TRUETYPE + help + The Anka/Coder family is a monospaced, courier-width font for source + code and terminals, in two styles and weights. Anka/Coder Narrow was + developed for printing source code. + https://code.google.com/p/anka-coder-fonts/ + From: https://fontlibrary.org/en/font/anka-coder-narrow + License: SIL Open Font Licence + http://scripts.sil.org/cms/scripts/page.php?site_id=nrsi&id=OFL + +config CONSOLE_TRUETYPE_RUFSCRIPT + bool "Ruf Script" + depends on CONSOLE_TRUETYPE + help + A laid-back handwritten font. + Font: https://fontlibrary.org/en/font/rufscript + License: GPL with font exception + http://www.gnu.org/copyleft/gpl.html + +config CONSOLE_TRUETYPE_CANTORAONE + bool "Cantoraone" + depends on CONSOLE_TRUETYPE + help + Cantora is a friendly semi formal, semi condensed, semi sans-serif + with a hint of handwriting. Perfect for headlines. + From https://fontlibrary.org/en/font/cantora + License: SIL Open Font Licence + http://scripts.sil.org/cms/scripts/page.php?site_id=nrsi&id=OFL + +endmenu diff --git a/drivers/video/fonts/Makefile b/drivers/video/fonts/Makefile new file mode 100644 index 0000000000..46137f4f7e --- /dev/null +++ b/drivers/video/fonts/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_CONSOLE_TRUETYPE_NIMBUS) += nimbus_sans_l_regular.o +obj-$(CONFIG_CONSOLE_TRUETYPE_ANKACODER) += ankacoder_c75_r.o +obj-$(CONFIG_CONSOLE_TRUETYPE_RUFSCRIPT) += rufscript010.o +obj-$(CONFIG_CONSOLE_TRUETYPE_CANTORAONE) += cantoraone_regular.o diff --git a/drivers/video/fonts/ankacoder_c75_r.ttf b/drivers/video/fonts/ankacoder_c75_r.ttf Binary files differnew file mode 100644 index 0000000000..3b73dcf00e --- /dev/null +++ b/drivers/video/fonts/ankacoder_c75_r.ttf diff --git a/drivers/video/fonts/cantoraone_regular.ttf b/drivers/video/fonts/cantoraone_regular.ttf Binary files differnew file mode 100644 index 0000000000..57446a27a0 --- /dev/null +++ b/drivers/video/fonts/cantoraone_regular.ttf diff --git a/drivers/video/fonts/nimbus_sans_l_regular.ttf b/drivers/video/fonts/nimbus_sans_l_regular.ttf Binary files differnew file mode 100644 index 0000000000..3bd694d8ee --- /dev/null +++ b/drivers/video/fonts/nimbus_sans_l_regular.ttf diff --git a/drivers/video/fonts/rufscript010.ttf b/drivers/video/fonts/rufscript010.ttf Binary files differnew file mode 100644 index 0000000000..887a4496f3 --- /dev/null +++ b/drivers/video/fonts/rufscript010.ttf diff --git a/drivers/video/sandbox_sdl.c b/drivers/video/sandbox_sdl.c index 21448a1411..dc5a220d51 100644 --- a/drivers/video/sandbox_sdl.c +++ b/drivers/video/sandbox_sdl.c @@ -35,6 +35,8 @@ static int sandbox_sdl_probe(struct udevice *dev) uc_priv->ysize = plat->yres; uc_priv->bpix = plat->bpix; uc_priv->rot = plat->rot; + uc_priv->vidconsole_drv_name = plat->vidconsole_drv_name; + uc_priv->font_size = plat->font_size; return 0; } diff --git a/drivers/video/stb_truetype.h b/drivers/video/stb_truetype.h new file mode 100644 index 0000000000..91d8e6f905 --- /dev/null +++ b/drivers/video/stb_truetype.h @@ -0,0 +1,3240 @@ +// stb_truetype.h - v1.08 - public domain +// authored from 2009-2015 by Sean Barrett / RAD Game Tools +// +// This library processes TrueType files: +// parse files +// extract glyph metrics +// extract glyph shapes +// render glyphs to one-channel bitmaps with antialiasing (box filter) +// +// Todo: +// non-MS cmaps +// crashproof on bad data +// hinting? (no longer patented) +// cleartype-style AA? +// optimize: use simple memory allocator for intermediates +// optimize: build edge-list directly from curves +// optimize: rasterize directly from curves? +// +// ADDITIONAL CONTRIBUTORS +// +// Mikko Mononen: compound shape support, more cmap formats +// Tor Andersson: kerning, subpixel rendering +// +// Bug/warning reports/fixes: +// "Zer" on mollyrocket (with fix) +// Cass Everitt +// stoiko (Haemimont Games) +// Brian Hook +// Walter van Niftrik +// David Gow +// David Given +// Ivan-Assen Ivanov +// Anthony Pesch +// Johan Duparc +// Hou Qiming +// Fabian "ryg" Giesen +// Martins Mozeiko +// Cap Petschulat +// Omar Cornut +// github:aloucks +// Peter LaValle +// Sergey Popov +// Giumo X. Clanjor +// Higor Euripedes +// +// Misc other: +// Ryan Gordon +// +// VERSION HISTORY +// +// 1.08 (2015-09-13) document stbtt_Rasterize(); fixes for vertical & horizontal edges +// 1.07 (2015-08-01) allow PackFontRanges to accept arrays of sparse codepoints; +// variant PackFontRanges to pack and render in separate phases; +// fix stbtt_GetFontOFfsetForIndex (never worked for non-0 input?); +// fixed an assert() bug in the new rasterizer +// replace assert() with STBTT_assert() in new rasterizer +// 1.06 (2015-07-14) performance improvements (~35% faster on x86 and x64 on test machine) +// also more precise AA rasterizer, except if shapes overlap +// remove need for STBTT_sort +// 1.05 (2015-04-15) fix misplaced definitions for STBTT_STATIC +// 1.04 (2015-04-15) typo in example +// 1.03 (2015-04-12) STBTT_STATIC, fix memory leak in new packing, various fixes +// +// Full history can be found at the end of this file. +// +// LICENSE +// +// This software is in the public domain. Where that dedication is not +// recognized, you are granted a perpetual, irrevocable license to copy, +// distribute, and modify this file as you see fit. +// +// USAGE +// +// Include this file in whatever places neeed to refer to it. In ONE C/C++ +// file, write: +// #define STB_TRUETYPE_IMPLEMENTATION +// before the #include of this file. This expands out the actual +// implementation into that C/C++ file. +// +// To make the implementation private to the file that generates the implementation, +// #define STBTT_STATIC +// +// Simple 3D API (don't ship this, but it's fine for tools and quick start) +// stbtt_BakeFontBitmap() -- bake a font to a bitmap for use as texture +// stbtt_GetBakedQuad() -- compute quad to draw for a given char +// +// Improved 3D API (more shippable): +// #include "stb_rect_pack.h" -- optional, but you really want it +// stbtt_PackBegin() +// stbtt_PackSetOversample() -- for improved quality on small fonts +// stbtt_PackFontRanges() -- pack and renders +// stbtt_PackEnd() +// stbtt_GetPackedQuad() +// +// "Load" a font file from a memory buffer (you have to keep the buffer loaded) +// stbtt_InitFont() +// stbtt_GetFontOffsetForIndex() -- use for TTC font collections +// +// Render a unicode codepoint to a bitmap +// stbtt_GetCodepointBitmap() -- allocates and returns a bitmap +// stbtt_MakeCodepointBitmap() -- renders into bitmap you provide +// stbtt_GetCodepointBitmapBox() -- how big the bitmap must be +// +// Character advance/positioning +// stbtt_GetCodepointHMetrics() +// stbtt_GetFontVMetrics() +// stbtt_GetCodepointKernAdvance() +// +// Starting with version 1.06, the rasterizer was replaced with a new, +// faster and generally-more-precise rasterizer. The new rasterizer more +// accurately measures pixel coverage for anti-aliasing, except in the case +// where multiple shapes overlap, in which case it overestimates the AA pixel +// coverage. Thus, anti-aliasing of intersecting shapes may look wrong. If +// this turns out to be a problem, you can re-enable the old rasterizer with +// #define STBTT_RASTERIZER_VERSION 1 +// which will incur about a 15% speed hit. +// +// ADDITIONAL DOCUMENTATION +// +// Immediately after this block comment are a series of sample programs. +// +// After the sample programs is the "header file" section. This section +// includes documentation for each API function. +// +// Some important concepts to understand to use this library: +// +// Codepoint +// Characters are defined by unicode codepoints, e.g. 65 is +// uppercase A, 231 is lowercase c with a cedilla, 0x7e30 is +// the hiragana for "ma". +// +// Glyph +// A visual character shape (every codepoint is rendered as +// some glyph) +// +// Glyph index +// A font-specific integer ID representing a glyph +// +// Baseline +// Glyph shapes are defined relative to a baseline, which is the +// bottom of uppercase characters. Characters extend both above +// and below the baseline. +// +// Current Point +// As you draw text to the screen, you keep track of a "current point" +// which is the origin of each character. The current point's vertical +// position is the baseline. Even "baked fonts" use this model. +// +// Vertical Font Metrics +// The vertical qualities of the font, used to vertically position +// and space the characters. See docs for stbtt_GetFontVMetrics. +// +// Font Size in Pixels or Points +// The preferred interface for specifying font sizes in stb_truetype +// is to specify how tall the font's vertical extent should be in pixels. +// If that sounds good enough, skip the next paragraph. +// +// Most font APIs instead use "points", which are a common typographic +// measurement for describing font size, defined as 72 points per inch. +// stb_truetype provides a point API for compatibility. However, true +// "per inch" conventions don't make much sense on computer displays +// since they different monitors have different number of pixels per +// inch. For example, Windows traditionally uses a convention that +// there are 96 pixels per inch, thus making 'inch' measurements have +// nothing to do with inches, and thus effectively defining a point to +// be 1.333 pixels. Additionally, the TrueType font data provides +// an explicit scale factor to scale a given font's glyphs to points, +// but the author has observed that this scale factor is often wrong +// for non-commercial fonts, thus making fonts scaled in points +// according to the TrueType spec incoherently sized in practice. +// +// ADVANCED USAGE +// +// Quality: +// +// - Use the functions with Subpixel at the end to allow your characters +// to have subpixel positioning. Since the font is anti-aliased, not +// hinted, this is very import for quality. (This is not possible with +// baked fonts.) +// +// - Kerning is now supported, and if you're supporting subpixel rendering +// then kerning is worth using to give your text a polished look. +// +// Performance: +// +// - Convert Unicode codepoints to glyph indexes and operate on the glyphs; +// if you don't do this, stb_truetype is forced to do the conversion on +// every call. +// +// - There are a lot of memory allocations. We should modify it to take +// a temp buffer and allocate from the temp buffer (without freeing), +// should help performance a lot. +// +// NOTES +// +// The system uses the raw data found in the .ttf file without changing it +// and without building auxiliary data structures. This is a bit inefficient +// on little-endian systems (the data is big-endian), but assuming you're +// caching the bitmaps or glyph shapes this shouldn't be a big deal. +// +// It appears to be very hard to programmatically determine what font a +// given file is in a general way. I provide an API for this, but I don't +// recommend it. +// +// +// SOURCE STATISTICS (based on v0.6c, 2050 LOC) +// +// Documentation & header file 520 LOC \___ 660 LOC documentation +// Sample code 140 LOC / +// Truetype parsing 620 LOC ---- 620 LOC TrueType +// Software rasterization 240 LOC \ . +// Curve tesselation 120 LOC \__ 550 LOC Bitmap creation +// Bitmap management 100 LOC / +// Baked bitmap interface 70 LOC / +// Font name matching & access 150 LOC ---- 150 +// C runtime library abstraction 60 LOC ---- 60 +// +// +// PERFORMANCE MEASUREMENTS FOR 1.06: +// +// 32-bit 64-bit +// Previous release: 8.83 s 7.68 s +// Pool allocations: 7.72 s 6.34 s +// Inline sort : 6.54 s 5.65 s +// New rasterizer : 5.63 s 5.00 s + +////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////// +//// +//// SAMPLE PROGRAMS +//// +// +// Incomplete text-in-3d-api example, which draws quads properly aligned to be lossless +// +#if 0 +#define STB_TRUETYPE_IMPLEMENTATION // force following include to generate implementation +#include "stb_truetype.h" + +unsigned char ttf_buffer[1<<20]; +unsigned char temp_bitmap[512*512]; + +stbtt_bakedchar cdata[96]; // ASCII 32..126 is 95 glyphs +GLuint ftex; + +void my_stbtt_initfont(void) +{ + fread(ttf_buffer, 1, 1<<20, fopen("c:/windows/fonts/times.ttf", "rb")); + stbtt_BakeFontBitmap(ttf_buffer,0, 32.0, temp_bitmap,512,512, 32,96, cdata); // no guarantee this fits! + // can free ttf_buffer at this point + glGenTextures(1, &ftex); + glBindTexture(GL_TEXTURE_2D, ftex); + glTexImage2D(GL_TEXTURE_2D, 0, GL_ALPHA, 512,512, 0, GL_ALPHA, GL_UNSIGNED_BYTE, temp_bitmap); + // can free temp_bitmap at this point + glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_LINEAR); +} + +void my_stbtt_print(float x, float y, char *text) +{ + // assume orthographic projection with units = screen pixels, origin at top left + glEnable(GL_TEXTURE_2D); + glBindTexture(GL_TEXTURE_2D, ftex); + glBegin(GL_QUADS); + while (*text) { + if (*text >= 32 && *text < 128) { + stbtt_aligned_quad q; + stbtt_GetBakedQuad(cdata, 512,512, *text-32, &x,&y,&q,1);//1=opengl & d3d10+,0=d3d9 + glTexCoord2f(q.s0,q.t1); glVertex2f(q.x0,q.y0); + glTexCoord2f(q.s1,q.t1); glVertex2f(q.x1,q.y0); + glTexCoord2f(q.s1,q.t0); glVertex2f(q.x1,q.y1); + glTexCoord2f(q.s0,q.t0); glVertex2f(q.x0,q.y1); + } + ++text; + } + glEnd(); +} +#endif +// +// +////////////////////////////////////////////////////////////////////////////// +// +// Complete program (this compiles): get a single bitmap, print as ASCII art +// +#if 0 +#include <stdio.h> +#define STB_TRUETYPE_IMPLEMENTATION // force following include to generate implementation +#include "stb_truetype.h" + +char ttf_buffer[1<<25]; + +int main(int argc, char **argv) +{ + stbtt_fontinfo font; + unsigned char *bitmap; + int w,h,i,j,c = (argc > 1 ? atoi(argv[1]) : 'a'), s = (argc > 2 ? atoi(argv[2]) : 20); + + fread(ttf_buffer, 1, 1<<25, fopen(argc > 3 ? argv[3] : "c:/windows/fonts/arialbd.ttf", "rb")); + + stbtt_InitFont(&font, ttf_buffer, stbtt_GetFontOffsetForIndex(ttf_buffer,0)); + bitmap = stbtt_GetCodepointBitmap(&font, 0,stbtt_ScaleForPixelHeight(&font, s), c, &w, &h, 0,0); + + for (j=0; j < h; ++j) { + for (i=0; i < w; ++i) + putchar(" .:ioVM@"[bitmap[j*w+i]>>5]); + putchar('\n'); + } + return 0; +} +#endif +// +// Output: +// +// .ii. +// @@@@@@. +// V@Mio@@o +// :i. V@V +// :oM@@M +// :@@@MM@M +// @@o o@M +// :@@. M@M +// @@@o@@@@ +// :M@@V:@@. +// +////////////////////////////////////////////////////////////////////////////// +// +// Complete program: print "Hello World!" banner, with bugs +// +#if 0 +char buffer[24<<20]; +unsigned char screen[20][79]; + +int main(int arg, char **argv) +{ + stbtt_fontinfo font; + int i,j,ascent,baseline,ch=0; + float scale, xpos=2; // leave a little padding in case the character extends left + char *text = "Heljo World!"; // intentionally misspelled to show 'lj' brokenness + + fread(buffer, 1, 1000000, fopen("c:/windows/fonts/arialbd.ttf", "rb")); + stbtt_InitFont(&font, buffer, 0); + + scale = stbtt_ScaleForPixelHeight(&font, 15); + stbtt_GetFontVMetrics(&font, &ascent,0,0); + baseline = (int) (ascent*scale); + + while (text[ch]) { + int advance,lsb,x0,y0,x1,y1; + float x_shift = xpos - (float) floor(xpos); + stbtt_GetCodepointHMetrics(&font, text[ch], &advance, &lsb); + stbtt_GetCodepointBitmapBoxSubpixel(&font, text[ch], scale,scale,x_shift,0, &x0,&y0,&x1,&y1); + stbtt_MakeCodepointBitmapSubpixel(&font, &screen[baseline + y0][(int) xpos + x0], x1-x0,y1-y0, 79, scale,scale,x_shift,0, text[ch]); + // note that this stomps the old data, so where character boxes overlap (e.g. 'lj') it's wrong + // because this API is really for baking character bitmaps into textures. if you want to render + // a sequence of characters, you really need to render each bitmap to a temp buffer, then + // "alpha blend" that into the working buffer + xpos += (advance * scale); + if (text[ch+1]) + xpos += scale*stbtt_GetCodepointKernAdvance(&font, text[ch],text[ch+1]); + ++ch; + } + + for (j=0; j < 20; ++j) { + for (i=0; i < 78; ++i) + putchar(" .:ioVM@"[screen[j][i]>>5]); + putchar('\n'); + } + + return 0; +} +#endif + + +////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////// +//// +//// INTEGRATION WITH YOUR CODEBASE +//// +//// The following sections allow you to supply alternate definitions +//// of C library functions used by stb_truetype. + +#ifdef STB_TRUETYPE_IMPLEMENTATION + // #define your own (u)stbtt_int8/16/32 before including to override this + #ifndef stbtt_uint8 + typedef unsigned char stbtt_uint8; + typedef signed char stbtt_int8; + typedef unsigned short stbtt_uint16; + typedef signed short stbtt_int16; + typedef unsigned int stbtt_uint32; + typedef signed int stbtt_int32; + #endif + + typedef char stbtt__check_size32[sizeof(stbtt_int32)==4 ? 1 : -1]; + typedef char stbtt__check_size16[sizeof(stbtt_int16)==2 ? 1 : -1]; + + // #define your own STBTT_ifloor/STBTT_iceil() to avoid math.h + #ifndef STBTT_ifloor + #include <math.h> + #define STBTT_ifloor(x) ((int) floor(x)) + #define STBTT_iceil(x) ((int) ceil(x)) + #endif + + #ifndef STBTT_sqrt + #include <math.h> + #define STBTT_sqrt(x) sqrt(x) + #endif + + #ifndef STBTT_fabs + #include <math.h> + #define STBTT_fabs(x) fabs(x) + #endif + + // #define your own functions "STBTT_malloc" / "STBTT_free" to avoid malloc.h + #ifndef STBTT_malloc + #include <stdlib.h> + #define STBTT_malloc(x,u) ((void)(u),malloc(x)) + #define STBTT_free(x,u) ((void)(u),free(x)) + #endif + + #ifndef STBTT_assert + #include <assert.h> + #define STBTT_assert(x) assert(x) + #endif + + #ifndef STBTT_strlen + #include <string.h> + #define STBTT_strlen(x) strlen(x) + #endif + + #ifndef STBTT_memcpy + #include <memory.h> + #define STBTT_memcpy memcpy + #define STBTT_memset memset + #endif +#endif + +/////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// +//// +//// INTERFACE +//// +//// + +#ifndef __STB_INCLUDE_STB_TRUETYPE_H__ +#define __STB_INCLUDE_STB_TRUETYPE_H__ + +#ifdef STBTT_STATIC +#define STBTT_DEF static +#else +#define STBTT_DEF extern +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +////////////////////////////////////////////////////////////////////////////// +// +// TEXTURE BAKING API +// +// If you use this API, you only have to call two functions ever. +// + +typedef struct +{ + unsigned short x0,y0,x1,y1; // coordinates of bbox in bitmap + float xoff,yoff,xadvance; +} stbtt_bakedchar; + +STBTT_DEF int stbtt_BakeFontBitmap(const unsigned char *data, int offset, // font location (use offset=0 for plain .ttf) + float pixel_height, // height of font in pixels + unsigned char *pixels, int pw, int ph, // bitmap to be filled in + int first_char, int num_chars, // characters to bake + stbtt_bakedchar *chardata); // you allocate this, it's num_chars long +// if return is positive, the first unused row of the bitmap +// if return is negative, returns the negative of the number of characters that fit +// if return is 0, no characters fit and no rows were used +// This uses a very crappy packing. + +typedef struct +{ + float x0,y0,s0,t0; // top-left + float x1,y1,s1,t1; // bottom-right +} stbtt_aligned_quad; + +STBTT_DEF void stbtt_GetBakedQuad(stbtt_bakedchar *chardata, int pw, int ph, // same data as above + int char_index, // character to display + float *xpos, float *ypos, // pointers to current position in screen pixel space + stbtt_aligned_quad *q, // output: quad to draw + int opengl_fillrule); // true if opengl fill rule; false if DX9 or earlier +// Call GetBakedQuad with char_index = 'character - first_char', and it +// creates the quad you need to draw and advances the current position. +// +// The coordinate system used assumes y increases downwards. +// +// Characters will extend both above and below the current position; +// see discussion of "BASELINE" above. +// +// It's inefficient; you might want to c&p it and optimize it. + + + +////////////////////////////////////////////////////////////////////////////// +// +// NEW TEXTURE BAKING API +// +// This provides options for packing multiple fonts into one atlas, not +// perfectly but better than nothing. + +typedef struct +{ + unsigned short x0,y0,x1,y1; // coordinates of bbox in bitmap + float xoff,yoff,xadvance; + float xoff2,yoff2; +} stbtt_packedchar; + +typedef struct stbtt_pack_context stbtt_pack_context; +typedef struct stbtt_fontinfo stbtt_fontinfo; +#ifndef STB_RECT_PACK_VERSION +typedef struct stbrp_rect stbrp_rect; +#endif + +STBTT_DEF int stbtt_PackBegin(stbtt_pack_context *spc, unsigned char *pixels, int width, int height, int stride_in_bytes, int padding, void *alloc_context); +// Initializes a packing context stored in the passed-in stbtt_pack_context. +// Future calls using this context will pack characters into the bitmap passed +// in here: a 1-channel bitmap that is weight x height. stride_in_bytes is +// the distance from one row to the next (or 0 to mean they are packed tightly +// together). "padding" is the amount of padding to leave between each +// character (normally you want '1' for bitmaps you'll use as textures with +// bilinear filtering). +// +// Returns 0 on failure, 1 on success. + +STBTT_DEF void stbtt_PackEnd (stbtt_pack_context *spc); +// Cleans up the packing context and frees all memory. + +#define STBTT_POINT_SIZE(x) (-(x)) + +STBTT_DEF int stbtt_PackFontRange(stbtt_pack_context *spc, unsigned char *fontdata, int font_index, float font_size, + int first_unicode_char_in_range, int num_chars_in_range, stbtt_packedchar *chardata_for_range); +// Creates character bitmaps from the font_index'th font found in fontdata (use +// font_index=0 if you don't know what that is). It creates num_chars_in_range +// bitmaps for characters with unicode values starting at first_unicode_char_in_range +// and increasing. Data for how to render them is stored in chardata_for_range; +// pass these to stbtt_GetPackedQuad to get back renderable quads. +// +// font_size is the full height of the character from ascender to descender, +// as computed by stbtt_ScaleForPixelHeight. To use a point size as computed +// by stbtt_ScaleForMappingEmToPixels, wrap the point size in STBTT_POINT_SIZE() +// and pass that result as 'font_size': +// ..., 20 , ... // font max minus min y is 20 pixels tall +// ..., STBTT_POINT_SIZE(20), ... // 'M' is 20 pixels tall + +typedef struct +{ + float font_size; + int first_unicode_codepoint_in_range; // if non-zero, then the chars are continuous, and this is the first codepoint + int *array_of_unicode_codepoints; // if non-zero, then this is an array of unicode codepoints + int num_chars; + stbtt_packedchar *chardata_for_range; // output + unsigned char h_oversample, v_oversample; // don't set these, they're used internally +} stbtt_pack_range; + +STBTT_DEF int stbtt_PackFontRanges(stbtt_pack_context *spc, unsigned char *fontdata, int font_index, stbtt_pack_range *ranges, int num_ranges); +// Creates character bitmaps from multiple ranges of characters stored in +// ranges. This will usually create a better-packed bitmap than multiple +// calls to stbtt_PackFontRange. Note that you can call this multiple +// times within a single PackBegin/PackEnd. + +STBTT_DEF void stbtt_PackSetOversampling(stbtt_pack_context *spc, unsigned int h_oversample, unsigned int v_oversample); +// Oversampling a font increases the quality by allowing higher-quality subpixel +// positioning, and is especially valuable at smaller text sizes. +// +// This function sets the amount of oversampling for all following calls to +// stbtt_PackFontRange(s) or stbtt_PackFontRangesGatherRects for a given +// pack context. The default (no oversampling) is achieved by h_oversample=1 +// and v_oversample=1. The total number of pixels required is +// h_oversample*v_oversample larger than the default; for example, 2x2 +// oversampling requires 4x the storage of 1x1. For best results, render +// oversampled textures with bilinear filtering. Look at the readme in +// stb/tests/oversample for information about oversampled fonts +// +// To use with PackFontRangesGather etc., you must set it before calls +// call to PackFontRangesGatherRects. + +STBTT_DEF void stbtt_GetPackedQuad(stbtt_packedchar *chardata, int pw, int ph, // same data as above + int char_index, // character to display + float *xpos, float *ypos, // pointers to current position in screen pixel space + stbtt_aligned_quad *q, // output: quad to draw + int align_to_integer); + +STBTT_DEF int stbtt_PackFontRangesGatherRects(stbtt_pack_context *spc, stbtt_fontinfo *info, stbtt_pack_range *ranges, int num_ranges, stbrp_rect *rects); +STBTT_DEF void stbtt_PackFontRangesPackRects(stbtt_pack_context *spc, stbrp_rect *rects, int num_rects); +STBTT_DEF int stbtt_PackFontRangesRenderIntoRects(stbtt_pack_context *spc, stbtt_fontinfo *info, stbtt_pack_range *ranges, int num_ranges, stbrp_rect *rects); +// Calling these functions in sequence is roughly equivalent to calling +// stbtt_PackFontRanges(). If you more control over the packing of multiple +// fonts, or if you want to pack custom data into a font texture, take a look +// at the source to of stbtt_PackFontRanges() and create a custom version +// using these functions, e.g. call GatherRects multiple times, +// building up a single array of rects, then call PackRects once, +// then call RenderIntoRects repeatedly. This may result in a +// better packing than calling PackFontRanges multiple times +// (or it may not). + +// this is an opaque structure that you shouldn't mess with which holds +// all the context needed from PackBegin to PackEnd. +struct stbtt_pack_context { + void *user_allocator_context; + void *pack_info; + int width; + int height; + int stride_in_bytes; + int padding; + unsigned int h_oversample, v_oversample; + unsigned char *pixels; + void *nodes; +}; + +////////////////////////////////////////////////////////////////////////////// +// +// FONT LOADING +// +// + +STBTT_DEF int stbtt_GetFontOffsetForIndex(const unsigned char *data, int index); +// Each .ttf/.ttc file may have more than one font. Each font has a sequential +// index number starting from 0. Call this function to get the font offset for +// a given index; it returns -1 if the index is out of range. A regular .ttf +// file will only define one font and it always be at offset 0, so it will +// return '0' for index 0, and -1 for all other indices. You can just skip +// this step if you know it's that kind of font. + + +// The following structure is defined publically so you can declare one on +// the stack or as a global or etc, but you should treat it as opaque. +typedef struct stbtt_fontinfo +{ + void * userdata; + unsigned char * data; // pointer to .ttf file + int fontstart; // offset of start of font + + int numGlyphs; // number of glyphs, needed for range checking + + int loca,head,glyf,hhea,hmtx,kern; // table locations as offset from start of .ttf + int index_map; // a cmap mapping for our chosen character encoding + int indexToLocFormat; // format needed to map from glyph index to glyph +} stbtt_fontinfo; + +STBTT_DEF int stbtt_InitFont(stbtt_fontinfo *info, const unsigned char *data, int offset); +// Given an offset into the file that defines a font, this function builds +// the necessary cached info for the rest of the system. You must allocate +// the stbtt_fontinfo yourself, and stbtt_InitFont will fill it out. You don't +// need to do anything special to free it, because the contents are pure +// value data with no additional data structures. Returns 0 on failure. + + +////////////////////////////////////////////////////////////////////////////// +// +// CHARACTER TO GLYPH-INDEX CONVERSIOn + +STBTT_DEF int stbtt_FindGlyphIndex(const stbtt_fontinfo *info, int unicode_codepoint); +// If you're going to perform multiple operations on the same character +// and you want a speed-up, call this function with the character you're +// going to process, then use glyph-based functions instead of the +// codepoint-based functions. + + +////////////////////////////////////////////////////////////////////////////// +// +// CHARACTER PROPERTIES +// + +STBTT_DEF float stbtt_ScaleForPixelHeight(const stbtt_fontinfo *info, float pixels); +// computes a scale factor to produce a font whose "height" is 'pixels' tall. +// Height is measured as the distance from the highest ascender to the lowest +// descender; in other words, it's equivalent to calling stbtt_GetFontVMetrics +// and computing: +// scale = pixels / (ascent - descent) +// so if you prefer to measure height by the ascent only, use a similar calculation. + +STBTT_DEF float stbtt_ScaleForMappingEmToPixels(const stbtt_fontinfo *info, float pixels); +// computes a scale factor to produce a font whose EM size is mapped to +// 'pixels' tall. This is probably what traditional APIs compute, but +// I'm not positive. + +STBTT_DEF void stbtt_GetFontVMetrics(const stbtt_fontinfo *info, int *ascent, int *descent, int *lineGap); +// ascent is the coordinate above the baseline the font extends; descent +// is the coordinate below the baseline the font extends (i.e. it is typically negative) +// lineGap is the spacing between one row's descent and the next row's ascent... +// so you should advance the vertical position by "*ascent - *descent + *lineGap" +// these are expressed in unscaled coordinates, so you must multiply by +// the scale factor for a given size + +STBTT_DEF void stbtt_GetFontBoundingBox(const stbtt_fontinfo *info, int *x0, int *y0, int *x1, int *y1); +// the bounding box around all possible characters + +STBTT_DEF void stbtt_GetCodepointHMetrics(const stbtt_fontinfo *info, int codepoint, int *advanceWidth, int *leftSideBearing); +// leftSideBearing is the offset from the current horizontal position to the left edge of the character +// advanceWidth is the offset from the current horizontal position to the next horizontal position +// these are expressed in unscaled coordinates + +STBTT_DEF int stbtt_GetCodepointKernAdvance(const stbtt_fontinfo *info, int ch1, int ch2); +// an additional amount to add to the 'advance' value between ch1 and ch2 + +STBTT_DEF int stbtt_GetCodepointBox(const stbtt_fontinfo *info, int codepoint, int *x0, int *y0, int *x1, int *y1); +// Gets the bounding box of the visible part of the glyph, in unscaled coordinates + +STBTT_DEF void stbtt_GetGlyphHMetrics(const stbtt_fontinfo *info, int glyph_index, int *advanceWidth, int *leftSideBearing); +STBTT_DEF int stbtt_GetGlyphKernAdvance(const stbtt_fontinfo *info, int glyph1, int glyph2); +STBTT_DEF int stbtt_GetGlyphBox(const stbtt_fontinfo *info, int glyph_index, int *x0, int *y0, int *x1, int *y1); +// as above, but takes one or more glyph indices for greater efficiency + + +////////////////////////////////////////////////////////////////////////////// +// +// GLYPH SHAPES (you probably don't need these, but they have to go before +// the bitmaps for C declaration-order reasons) +// + +#ifndef STBTT_vmove // you can predefine these to use different values (but why?) + enum { + STBTT_vmove=1, + STBTT_vline, + STBTT_vcurve + }; +#endif + +#ifndef stbtt_vertex // you can predefine this to use different values + // (we share this with other code at RAD) + #define stbtt_vertex_type short // can't use stbtt_int16 because that's not visible in the header file + typedef struct + { + stbtt_vertex_type x,y,cx,cy; + unsigned char type,padding; + } stbtt_vertex; +#endif + +STBTT_DEF int stbtt_IsGlyphEmpty(const stbtt_fontinfo *info, int glyph_index); +// returns non-zero if nothing is drawn for this glyph + +STBTT_DEF int stbtt_GetCodepointShape(const stbtt_fontinfo *info, int unicode_codepoint, stbtt_vertex **vertices); +STBTT_DEF int stbtt_GetGlyphShape(const stbtt_fontinfo *info, int glyph_index, stbtt_vertex **vertices); +// returns # of vertices and fills *vertices with the pointer to them +// these are expressed in "unscaled" coordinates +// +// The shape is a series of countours. Each one starts with +// a STBTT_moveto, then consists of a series of mixed +// STBTT_lineto and STBTT_curveto segments. A lineto +// draws a line from previous endpoint to its x,y; a curveto +// draws a quadratic bezier from previous endpoint to +// its x,y, using cx,cy as the bezier control point. + +STBTT_DEF void stbtt_FreeShape(const stbtt_fontinfo *info, stbtt_vertex *vertices); +// frees the data allocated above + +////////////////////////////////////////////////////////////////////////////// +// +// BITMAP RENDERING +// + +STBTT_DEF void stbtt_FreeBitmap(unsigned char *bitmap, void *userdata); +// frees the bitmap allocated below + +STBTT_DEF unsigned char *stbtt_GetCodepointBitmap(const stbtt_fontinfo *info, float scale_x, float scale_y, int codepoint, int *width, int *height, int *xoff, int *yoff); +// allocates a large-enough single-channel 8bpp bitmap and renders the +// specified character/glyph at the specified scale into it, with +// antialiasing. 0 is no coverage (transparent), 255 is fully covered (opaque). +// *width & *height are filled out with the width & height of the bitmap, +// which is stored left-to-right, top-to-bottom. +// +// xoff/yoff are the offset it pixel space from the glyph origin to the top-left of the bitmap + +STBTT_DEF unsigned char *stbtt_GetCodepointBitmapSubpixel(const stbtt_fontinfo *info, float scale_x, float scale_y, float shift_x, float shift_y, int codepoint, int *width, int *height, int *xoff, int *yoff); +// the same as stbtt_GetCodepoitnBitmap, but you can specify a subpixel +// shift for the character + +STBTT_DEF void stbtt_MakeCodepointBitmap(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, int codepoint); +// the same as stbtt_GetCodepointBitmap, but you pass in storage for the bitmap +// in the form of 'output', with row spacing of 'out_stride' bytes. the bitmap +// is clipped to out_w/out_h bytes. Call stbtt_GetCodepointBitmapBox to get the +// width and height and positioning info for it first. + +STBTT_DEF void stbtt_MakeCodepointBitmapSubpixel(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int codepoint); +// same as stbtt_MakeCodepointBitmap, but you can specify a subpixel +// shift for the character + +STBTT_DEF void stbtt_GetCodepointBitmapBox(const stbtt_fontinfo *font, int codepoint, float scale_x, float scale_y, int *ix0, int *iy0, int *ix1, int *iy1); +// get the bbox of the bitmap centered around the glyph origin; so the +// bitmap width is ix1-ix0, height is iy1-iy0, and location to place +// the bitmap top left is (leftSideBearing*scale,iy0). +// (Note that the bitmap uses y-increases-down, but the shape uses +// y-increases-up, so CodepointBitmapBox and CodepointBox are inverted.) + +STBTT_DEF void stbtt_GetCodepointBitmapBoxSubpixel(const stbtt_fontinfo *font, int codepoint, float scale_x, float scale_y, float shift_x, float shift_y, int *ix0, int *iy0, int *ix1, int *iy1); +// same as stbtt_GetCodepointBitmapBox, but you can specify a subpixel +// shift for the character + +// the following functions are equivalent to the above functions, but operate +// on glyph indices instead of Unicode codepoints (for efficiency) +STBTT_DEF unsigned char *stbtt_GetGlyphBitmap(const stbtt_fontinfo *info, float scale_x, float scale_y, int glyph, int *width, int *height, int *xoff, int *yoff); +STBTT_DEF unsigned char *stbtt_GetGlyphBitmapSubpixel(const stbtt_fontinfo *info, float scale_x, float scale_y, float shift_x, float shift_y, int glyph, int *width, int *height, int *xoff, int *yoff); +STBTT_DEF void stbtt_MakeGlyphBitmap(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, int glyph); +STBTT_DEF void stbtt_MakeGlyphBitmapSubpixel(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int glyph); +STBTT_DEF void stbtt_GetGlyphBitmapBox(const stbtt_fontinfo *font, int glyph, float scale_x, float scale_y, int *ix0, int *iy0, int *ix1, int *iy1); +STBTT_DEF void stbtt_GetGlyphBitmapBoxSubpixel(const stbtt_fontinfo *font, int glyph, float scale_x, float scale_y,float shift_x, float shift_y, int *ix0, int *iy0, int *ix1, int *iy1); + + +// @TODO: don't expose this structure +typedef struct +{ + int w,h,stride; + unsigned char *pixels; +} stbtt__bitmap; + +// rasterize a shape with quadratic beziers into a bitmap +STBTT_DEF void stbtt_Rasterize(stbtt__bitmap *result, // 1-channel bitmap to draw into + float flatness_in_pixels, // allowable error of curve in pixels + stbtt_vertex *vertices, // array of vertices defining shape + int num_verts, // number of vertices in above array + float scale_x, float scale_y, // scale applied to input vertices + float shift_x, float shift_y, // translation applied to input vertices + int x_off, int y_off, // another translation applied to input + int invert, // if non-zero, vertically flip shape + void *userdata); // context for to STBTT_MALLOC + +////////////////////////////////////////////////////////////////////////////// +// +// Finding the right font... +// +// You should really just solve this offline, keep your own tables +// of what font is what, and don't try to get it out of the .ttf file. +// That's because getting it out of the .ttf file is really hard, because +// the names in the file can appear in many possible encodings, in many +// possible languages, and e.g. if you need a case-insensitive comparison, +// the details of that depend on the encoding & language in a complex way +// (actually underspecified in truetype, but also gigantic). +// +// But you can use the provided functions in two possible ways: +// stbtt_FindMatchingFont() will use *case-sensitive* comparisons on +// unicode-encoded names to try to find the font you want; +// you can run this before calling stbtt_InitFont() +// +// stbtt_GetFontNameString() lets you get any of the various strings +// from the file yourself and do your own comparisons on them. +// You have to have called stbtt_InitFont() first. + + +STBTT_DEF int stbtt_FindMatchingFont(const unsigned char *fontdata, const char *name, int flags); +// returns the offset (not index) of the font that matches, or -1 if none +// if you use STBTT_MACSTYLE_DONTCARE, use a font name like "Arial Bold". +// if you use any other flag, use a font name like "Arial"; this checks +// the 'macStyle' header field; i don't know if fonts set this consistently +#define STBTT_MACSTYLE_DONTCARE 0 +#define STBTT_MACSTYLE_BOLD 1 +#define STBTT_MACSTYLE_ITALIC 2 +#define STBTT_MACSTYLE_UNDERSCORE 4 +#define STBTT_MACSTYLE_NONE 8 // <= not same as 0, this makes us check the bitfield is 0 + +STBTT_DEF int stbtt_CompareUTF8toUTF16_bigendian(const char *s1, int len1, const char *s2, int len2); +// returns 1/0 whether the first string interpreted as utf8 is identical to +// the second string interpreted as big-endian utf16... useful for strings from next func + +STBTT_DEF const char *stbtt_GetFontNameString(const stbtt_fontinfo *font, int *length, int platformID, int encodingID, int languageID, int nameID); +// returns the string (which may be big-endian double byte, e.g. for unicode) +// and puts the length in bytes in *length. +// +// some of the values for the IDs are below; for more see the truetype spec: +// http://developer.apple.com/textfonts/TTRefMan/RM06/Chap6name.html +// http://www.microsoft.com/typography/otspec/name.htm + +enum { // platformID + STBTT_PLATFORM_ID_UNICODE =0, + STBTT_PLATFORM_ID_MAC =1, + STBTT_PLATFORM_ID_ISO =2, + STBTT_PLATFORM_ID_MICROSOFT =3 +}; + +enum { // encodingID for STBTT_PLATFORM_ID_UNICODE + STBTT_UNICODE_EID_UNICODE_1_0 =0, + STBTT_UNICODE_EID_UNICODE_1_1 =1, + STBTT_UNICODE_EID_ISO_10646 =2, + STBTT_UNICODE_EID_UNICODE_2_0_BMP=3, + STBTT_UNICODE_EID_UNICODE_2_0_FULL=4 +}; + +enum { // encodingID for STBTT_PLATFORM_ID_MICROSOFT + STBTT_MS_EID_SYMBOL =0, + STBTT_MS_EID_UNICODE_BMP =1, + STBTT_MS_EID_SHIFTJIS =2, + STBTT_MS_EID_UNICODE_FULL =10 +}; + +enum { // encodingID for STBTT_PLATFORM_ID_MAC; same as Script Manager codes + STBTT_MAC_EID_ROMAN =0, STBTT_MAC_EID_ARABIC =4, + STBTT_MAC_EID_JAPANESE =1, STBTT_MAC_EID_HEBREW =5, + STBTT_MAC_EID_CHINESE_TRAD =2, STBTT_MAC_EID_GREEK =6, + STBTT_MAC_EID_KOREAN =3, STBTT_MAC_EID_RUSSIAN =7 +}; + +enum { // languageID for STBTT_PLATFORM_ID_MICROSOFT; same as LCID... + // problematic because there are e.g. 16 english LCIDs and 16 arabic LCIDs + STBTT_MS_LANG_ENGLISH =0x0409, STBTT_MS_LANG_ITALIAN =0x0410, + STBTT_MS_LANG_CHINESE =0x0804, STBTT_MS_LANG_JAPANESE =0x0411, + STBTT_MS_LANG_DUTCH =0x0413, STBTT_MS_LANG_KOREAN =0x0412, + STBTT_MS_LANG_FRENCH =0x040c, STBTT_MS_LANG_RUSSIAN =0x0419, + STBTT_MS_LANG_GERMAN =0x0407, STBTT_MS_LANG_SPANISH =0x0409, + STBTT_MS_LANG_HEBREW =0x040d, STBTT_MS_LANG_SWEDISH =0x041D +}; + +enum { // languageID for STBTT_PLATFORM_ID_MAC + STBTT_MAC_LANG_ENGLISH =0 , STBTT_MAC_LANG_JAPANESE =11, + STBTT_MAC_LANG_ARABIC =12, STBTT_MAC_LANG_KOREAN =23, + STBTT_MAC_LANG_DUTCH =4 , STBTT_MAC_LANG_RUSSIAN =32, + STBTT_MAC_LANG_FRENCH =1 , STBTT_MAC_LANG_SPANISH =6 , + STBTT_MAC_LANG_GERMAN =2 , STBTT_MAC_LANG_SWEDISH =5 , + STBTT_MAC_LANG_HEBREW =10, STBTT_MAC_LANG_CHINESE_SIMPLIFIED =33, + STBTT_MAC_LANG_ITALIAN =3 , STBTT_MAC_LANG_CHINESE_TRAD =19 +}; + +#ifdef __cplusplus +} +#endif + +#endif // __STB_INCLUDE_STB_TRUETYPE_H__ + +/////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// +//// +//// IMPLEMENTATION +//// +//// + +#ifdef STB_TRUETYPE_IMPLEMENTATION + +#ifndef STBTT_MAX_OVERSAMPLE +#define STBTT_MAX_OVERSAMPLE 8 +#endif + +#if STBTT_MAX_OVERSAMPLE > 255 +#error "STBTT_MAX_OVERSAMPLE cannot be > 255" +#endif + +typedef int stbtt__test_oversample_pow2[(STBTT_MAX_OVERSAMPLE & (STBTT_MAX_OVERSAMPLE-1)) == 0 ? 1 : -1]; + +#ifndef STBTT_RASTERIZER_VERSION +#define STBTT_RASTERIZER_VERSION 2 +#endif + +////////////////////////////////////////////////////////////////////////// +// +// accessors to parse data from file +// + +// on platforms that don't allow misaligned reads, if we want to allow +// truetype fonts that aren't padded to alignment, define ALLOW_UNALIGNED_TRUETYPE + +#define ttBYTE(p) (* (stbtt_uint8 *) (p)) +#define ttCHAR(p) (* (stbtt_int8 *) (p)) +#define ttFixed(p) ttLONG(p) + +#if defined(STB_TRUETYPE_BIGENDIAN) && !defined(ALLOW_UNALIGNED_TRUETYPE) + + #define ttUSHORT(p) (* (stbtt_uint16 *) (p)) + #define ttSHORT(p) (* (stbtt_int16 *) (p)) + #define ttULONG(p) (* (stbtt_uint32 *) (p)) + #define ttLONG(p) (* (stbtt_int32 *) (p)) + +#else + + static stbtt_uint16 ttUSHORT(const stbtt_uint8 *p) { return p[0]*256 + p[1]; } + static stbtt_int16 ttSHORT(const stbtt_uint8 *p) { return p[0]*256 + p[1]; } + static stbtt_uint32 ttULONG(const stbtt_uint8 *p) { return (p[0]<<24) + (p[1]<<16) + (p[2]<<8) + p[3]; } + static stbtt_int32 ttLONG(const stbtt_uint8 *p) { return (p[0]<<24) + (p[1]<<16) + (p[2]<<8) + p[3]; } + +#endif + +#define stbtt_tag4(p,c0,c1,c2,c3) ((p)[0] == (c0) && (p)[1] == (c1) && (p)[2] == (c2) && (p)[3] == (c3)) +#define stbtt_tag(p,str) stbtt_tag4(p,str[0],str[1],str[2],str[3]) + +static int stbtt__isfont(const stbtt_uint8 *font) +{ + // check the version number + if (stbtt_tag4(font, '1',0,0,0)) return 1; // TrueType 1 + if (stbtt_tag(font, "typ1")) return 1; // TrueType with type 1 font -- we don't support this! + if (stbtt_tag(font, "OTTO")) return 1; // OpenType with CFF + if (stbtt_tag4(font, 0,1,0,0)) return 1; // OpenType 1.0 + return 0; +} + +// @OPTIMIZE: binary search +static stbtt_uint32 stbtt__find_table(stbtt_uint8 *data, stbtt_uint32 fontstart, const char *tag) +{ + stbtt_int32 num_tables = ttUSHORT(data+fontstart+4); + stbtt_uint32 tabledir = fontstart + 12; + stbtt_int32 i; + for (i=0; i < num_tables; ++i) { + stbtt_uint32 loc = tabledir + 16*i; + if (stbtt_tag(data+loc+0, tag)) + return ttULONG(data+loc+8); + } + return 0; +} + +STBTT_DEF int stbtt_GetFontOffsetForIndex(const unsigned char *font_collection, int index) +{ + // if it's just a font, there's only one valid index + if (stbtt__isfont(font_collection)) + return index == 0 ? 0 : -1; + + // check if it's a TTC + if (stbtt_tag(font_collection, "ttcf")) { + // version 1? + if (ttULONG(font_collection+4) == 0x00010000 || ttULONG(font_collection+4) == 0x00020000) { + stbtt_int32 n = ttLONG(font_collection+8); + if (index >= n) + return -1; + return ttULONG(font_collection+12+index*4); + } + } + return -1; +} + +STBTT_DEF int stbtt_InitFont(stbtt_fontinfo *info, const unsigned char *data2, int fontstart) +{ + stbtt_uint8 *data = (stbtt_uint8 *) data2; + stbtt_uint32 cmap, t; + stbtt_int32 i,numTables; + + info->data = data; + info->fontstart = fontstart; + + cmap = stbtt__find_table(data, fontstart, "cmap"); // required + info->loca = stbtt__find_table(data, fontstart, "loca"); // required + info->head = stbtt__find_table(data, fontstart, "head"); // required + info->glyf = stbtt__find_table(data, fontstart, "glyf"); // required + info->hhea = stbtt__find_table(data, fontstart, "hhea"); // required + info->hmtx = stbtt__find_table(data, fontstart, "hmtx"); // required + info->kern = stbtt__find_table(data, fontstart, "kern"); // not required + if (!cmap || !info->loca || !info->head || !info->glyf || !info->hhea || !info->hmtx) + return 0; + + t = stbtt__find_table(data, fontstart, "maxp"); + if (t) + info->numGlyphs = ttUSHORT(data+t+4); + else + info->numGlyphs = 0xffff; + + // find a cmap encoding table we understand *now* to avoid searching + // later. (todo: could make this installable) + // the same regardless of glyph. + numTables = ttUSHORT(data + cmap + 2); + info->index_map = 0; + for (i=0; i < numTables; ++i) { + stbtt_uint32 encoding_record = cmap + 4 + 8 * i; + // find an encoding we understand: + switch(ttUSHORT(data+encoding_record)) { + case STBTT_PLATFORM_ID_MICROSOFT: + switch (ttUSHORT(data+encoding_record+2)) { + case STBTT_MS_EID_UNICODE_BMP: + case STBTT_MS_EID_UNICODE_FULL: + // MS/Unicode + info->index_map = cmap + ttULONG(data+encoding_record+4); + break; + } + break; + case STBTT_PLATFORM_ID_UNICODE: + // Mac/iOS has these + // all the encodingIDs are unicode, so we don't bother to check it + info->index_map = cmap + ttULONG(data+encoding_record+4); + break; + } + } + if (info->index_map == 0) + return 0; + + info->indexToLocFormat = ttUSHORT(data+info->head + 50); + return 1; +} + +STBTT_DEF int stbtt_FindGlyphIndex(const stbtt_fontinfo *info, int unicode_codepoint) +{ + stbtt_uint8 *data = info->data; + stbtt_uint32 index_map = info->index_map; + + stbtt_uint16 format = ttUSHORT(data + index_map + 0); + if (format == 0) { // apple byte encoding + stbtt_int32 bytes = ttUSHORT(data + index_map + 2); + if (unicode_codepoint < bytes-6) + return ttBYTE(data + index_map + 6 + unicode_codepoint); + return 0; + } else if (format == 6) { + stbtt_uint32 first = ttUSHORT(data + index_map + 6); + stbtt_uint32 count = ttUSHORT(data + index_map + 8); + if ((stbtt_uint32) unicode_codepoint >= first && (stbtt_uint32) unicode_codepoint < first+count) + return ttUSHORT(data + index_map + 10 + (unicode_codepoint - first)*2); + return 0; + } else if (format == 2) { + STBTT_assert(0); // @TODO: high-byte mapping for japanese/chinese/korean + return 0; + } else if (format == 4) { // standard mapping for windows fonts: binary search collection of ranges + stbtt_uint16 segcount = ttUSHORT(data+index_map+6) >> 1; + stbtt_uint16 searchRange = ttUSHORT(data+index_map+8) >> 1; + stbtt_uint16 entrySelector = ttUSHORT(data+index_map+10); + stbtt_uint16 rangeShift = ttUSHORT(data+index_map+12) >> 1; + + // do a binary search of the segments + stbtt_uint32 endCount = index_map + 14; + stbtt_uint32 search = endCount; + + if (unicode_codepoint > 0xffff) + return 0; + + // they lie from endCount .. endCount + segCount + // but searchRange is the nearest power of two, so... + if (unicode_codepoint >= ttUSHORT(data + search + rangeShift*2)) + search += rangeShift*2; + + // now decrement to bias correctly to find smallest + search -= 2; + while (entrySelector) { + stbtt_uint16 end; + searchRange >>= 1; + end = ttUSHORT(data + search + searchRange*2); + if (unicode_codepoint > end) + search += searchRange*2; + --entrySelector; + } + search += 2; + + { + stbtt_uint16 offset, start; + stbtt_uint16 item = (stbtt_uint16) ((search - endCount) >> 1); + + STBTT_assert(unicode_codepoint <= ttUSHORT(data + endCount + 2*item)); + start = ttUSHORT(data + index_map + 14 + segcount*2 + 2 + 2*item); + if (unicode_codepoint < start) + return 0; + + offset = ttUSHORT(data + index_map + 14 + segcount*6 + 2 + 2*item); + if (offset == 0) + return (stbtt_uint16) (unicode_codepoint + ttSHORT(data + index_map + 14 + segcount*4 + 2 + 2*item)); + + return ttUSHORT(data + offset + (unicode_codepoint-start)*2 + index_map + 14 + segcount*6 + 2 + 2*item); + } + } else if (format == 12 || format == 13) { + stbtt_uint32 ngroups = ttULONG(data+index_map+12); + stbtt_int32 low,high; + low = 0; high = (stbtt_int32)ngroups; + // Binary search the right group. + while (low < high) { + stbtt_int32 mid = low + ((high-low) >> 1); // rounds down, so low <= mid < high + stbtt_uint32 start_char = ttULONG(data+index_map+16+mid*12); + stbtt_uint32 end_char = ttULONG(data+index_map+16+mid*12+4); + if ((stbtt_uint32) unicode_codepoint < start_char) + high = mid; + else if ((stbtt_uint32) unicode_codepoint > end_char) + low = mid+1; + else { + stbtt_uint32 start_glyph = ttULONG(data+index_map+16+mid*12+8); + if (format == 12) + return start_glyph + unicode_codepoint-start_char; + else // format == 13 + return start_glyph; + } + } + return 0; // not found + } + // @TODO + STBTT_assert(0); + return 0; +} + +STBTT_DEF int stbtt_GetCodepointShape(const stbtt_fontinfo *info, int unicode_codepoint, stbtt_vertex **vertices) +{ + return stbtt_GetGlyphShape(info, stbtt_FindGlyphIndex(info, unicode_codepoint), vertices); +} + +static void stbtt_setvertex(stbtt_vertex *v, stbtt_uint8 type, stbtt_int32 x, stbtt_int32 y, stbtt_int32 cx, stbtt_int32 cy) +{ + v->type = type; + v->x = (stbtt_int16) x; + v->y = (stbtt_int16) y; + v->cx = (stbtt_int16) cx; + v->cy = (stbtt_int16) cy; +} + +static int stbtt__GetGlyfOffset(const stbtt_fontinfo *info, int glyph_index) +{ + int g1,g2; + + if (glyph_index >= info->numGlyphs) return -1; // glyph index out of range + if (info->indexToLocFormat >= 2) return -1; // unknown index->glyph map format + + if (info->indexToLocFormat == 0) { + g1 = info->glyf + ttUSHORT(info->data + info->loca + glyph_index * 2) * 2; + g2 = info->glyf + ttUSHORT(info->data + info->loca + glyph_index * 2 + 2) * 2; + } else { + g1 = info->glyf + ttULONG (info->data + info->loca + glyph_index * 4); + g2 = info->glyf + ttULONG (info->data + info->loca + glyph_index * 4 + 4); + } + + return g1==g2 ? -1 : g1; // if length is 0, return -1 +} + +STBTT_DEF int stbtt_GetGlyphBox(const stbtt_fontinfo *info, int glyph_index, int *x0, int *y0, int *x1, int *y1) +{ + int g = stbtt__GetGlyfOffset(info, glyph_index); + if (g < 0) return 0; + + if (x0) *x0 = ttSHORT(info->data + g + 2); + if (y0) *y0 = ttSHORT(info->data + g + 4); + if (x1) *x1 = ttSHORT(info->data + g + 6); + if (y1) *y1 = ttSHORT(info->data + g + 8); + return 1; +} + +STBTT_DEF int stbtt_GetCodepointBox(const stbtt_fontinfo *info, int codepoint, int *x0, int *y0, int *x1, int *y1) +{ + return stbtt_GetGlyphBox(info, stbtt_FindGlyphIndex(info,codepoint), x0,y0,x1,y1); +} + +STBTT_DEF int stbtt_IsGlyphEmpty(const stbtt_fontinfo *info, int glyph_index) +{ + stbtt_int16 numberOfContours; + int g = stbtt__GetGlyfOffset(info, glyph_index); + if (g < 0) return 1; + numberOfContours = ttSHORT(info->data + g); + return numberOfContours == 0; +} + +static int stbtt__close_shape(stbtt_vertex *vertices, int num_vertices, int was_off, int start_off, + stbtt_int32 sx, stbtt_int32 sy, stbtt_int32 scx, stbtt_int32 scy, stbtt_int32 cx, stbtt_int32 cy) +{ + if (start_off) { + if (was_off) + stbtt_setvertex(&vertices[num_vertices++], STBTT_vcurve, (cx+scx)>>1, (cy+scy)>>1, cx,cy); + stbtt_setvertex(&vertices[num_vertices++], STBTT_vcurve, sx,sy,scx,scy); + } else { + if (was_off) + stbtt_setvertex(&vertices[num_vertices++], STBTT_vcurve,sx,sy,cx,cy); + else + stbtt_setvertex(&vertices[num_vertices++], STBTT_vline,sx,sy,0,0); + } + return num_vertices; +} + +STBTT_DEF int stbtt_GetGlyphShape(const stbtt_fontinfo *info, int glyph_index, stbtt_vertex **pvertices) +{ + stbtt_int16 numberOfContours; + stbtt_uint8 *endPtsOfContours; + stbtt_uint8 *data = info->data; + stbtt_vertex *vertices=0; + int num_vertices=0; + int g = stbtt__GetGlyfOffset(info, glyph_index); + + *pvertices = NULL; + + if (g < 0) return 0; + + numberOfContours = ttSHORT(data + g); + + if (numberOfContours > 0) { + stbtt_uint8 flags=0,flagcount; + stbtt_int32 ins, i,j=0,m,n, next_move, was_off=0, off, start_off=0; + stbtt_int32 x,y,cx,cy,sx,sy, scx,scy; + stbtt_uint8 *points; + endPtsOfContours = (data + g + 10); + ins = ttUSHORT(data + g + 10 + numberOfContours * 2); + points = data + g + 10 + numberOfContours * 2 + 2 + ins; + + n = 1+ttUSHORT(endPtsOfContours + numberOfContours*2-2); + + m = n + 2*numberOfContours; // a loose bound on how many vertices we might need + vertices = (stbtt_vertex *) STBTT_malloc(m * sizeof(vertices[0]), info->userdata); + if (vertices == 0) + return 0; + + next_move = 0; + flagcount=0; + + // in first pass, we load uninterpreted data into the allocated array + // above, shifted to the end of the array so we won't overwrite it when + // we create our final data starting from the front + + off = m - n; // starting offset for uninterpreted data, regardless of how m ends up being calculated + + // first load flags + + for (i=0; i < n; ++i) { + if (flagcount == 0) { + flags = *points++; + if (flags & 8) + flagcount = *points++; + } else + --flagcount; + vertices[off+i].type = flags; + } + + // now load x coordinates + x=0; + for (i=0; i < n; ++i) { + flags = vertices[off+i].type; + if (flags & 2) { + stbtt_int16 dx = *points++; + x += (flags & 16) ? dx : -dx; // ??? + } else { + if (!(flags & 16)) { + x = x + (stbtt_int16) (points[0]*256 + points[1]); + points += 2; + } + } + vertices[off+i].x = (stbtt_int16) x; + } + + // now load y coordinates + y=0; + for (i=0; i < n; ++i) { + flags = vertices[off+i].type; + if (flags & 4) { + stbtt_int16 dy = *points++; + y += (flags & 32) ? dy : -dy; // ??? + } else { + if (!(flags & 32)) { + y = y + (stbtt_int16) (points[0]*256 + points[1]); + points += 2; + } + } + vertices[off+i].y = (stbtt_int16) y; + } + + // now convert them to our format + num_vertices=0; + sx = sy = cx = cy = scx = scy = 0; + for (i=0; i < n; ++i) { + flags = vertices[off+i].type; + x = (stbtt_int16) vertices[off+i].x; + y = (stbtt_int16) vertices[off+i].y; + + if (next_move == i) { + if (i != 0) + num_vertices = stbtt__close_shape(vertices, num_vertices, was_off, start_off, sx,sy,scx,scy,cx,cy); + + // now start the new one + start_off = !(flags & 1); + if (start_off) { + // if we start off with an off-curve point, then when we need to find a point on the curve + // where we can start, and we need to save some state for when we wraparound. + scx = x; + scy = y; + if (!(vertices[off+i+1].type & 1)) { + // next point is also a curve point, so interpolate an on-point curve + sx = (x + (stbtt_int32) vertices[off+i+1].x) >> 1; + sy = (y + (stbtt_int32) vertices[off+i+1].y) >> 1; + } else { + // otherwise just use the next point as our start point + sx = (stbtt_int32) vertices[off+i+1].x; + sy = (stbtt_int32) vertices[off+i+1].y; + ++i; // we're using point i+1 as the starting point, so skip it + } + } else { + sx = x; + sy = y; + } + stbtt_setvertex(&vertices[num_vertices++], STBTT_vmove,sx,sy,0,0); + was_off = 0; + next_move = 1 + ttUSHORT(endPtsOfContours+j*2); + ++j; + } else { + if (!(flags & 1)) { // if it's a curve + if (was_off) // two off-curve control points in a row means interpolate an on-curve midpoint + stbtt_setvertex(&vertices[num_vertices++], STBTT_vcurve, (cx+x)>>1, (cy+y)>>1, cx, cy); + cx = x; + cy = y; + was_off = 1; + } else { + if (was_off) + stbtt_setvertex(&vertices[num_vertices++], STBTT_vcurve, x,y, cx, cy); + else + stbtt_setvertex(&vertices[num_vertices++], STBTT_vline, x,y,0,0); + was_off = 0; + } + } + } + num_vertices = stbtt__close_shape(vertices, num_vertices, was_off, start_off, sx,sy,scx,scy,cx,cy); + } else if (numberOfContours == -1) { + // Compound shapes. + int more = 1; + stbtt_uint8 *comp = data + g + 10; + num_vertices = 0; + vertices = 0; + while (more) { + stbtt_uint16 flags, gidx; + int comp_num_verts = 0, i; + stbtt_vertex *comp_verts = 0, *tmp = 0; + float mtx[6] = {1,0,0,1,0,0}, m, n; + + flags = ttSHORT(comp); comp+=2; + gidx = ttSHORT(comp); comp+=2; + + if (flags & 2) { // XY values + if (flags & 1) { // shorts + mtx[4] = ttSHORT(comp); comp+=2; + mtx[5] = ttSHORT(comp); comp+=2; + } else { + mtx[4] = ttCHAR(comp); comp+=1; + mtx[5] = ttCHAR(comp); comp+=1; + } + } + else { + // @TODO handle matching point + STBTT_assert(0); + } + if (flags & (1<<3)) { // WE_HAVE_A_SCALE + mtx[0] = mtx[3] = ttSHORT(comp)/16384.0f; comp+=2; + mtx[1] = mtx[2] = 0; + } else if (flags & (1<<6)) { // WE_HAVE_AN_X_AND_YSCALE + mtx[0] = ttSHORT(comp)/16384.0f; comp+=2; + mtx[1] = mtx[2] = 0; + mtx[3] = ttSHORT(comp)/16384.0f; comp+=2; + } else if (flags & (1<<7)) { // WE_HAVE_A_TWO_BY_TWO + mtx[0] = ttSHORT(comp)/16384.0f; comp+=2; + mtx[1] = ttSHORT(comp)/16384.0f; comp+=2; + mtx[2] = ttSHORT(comp)/16384.0f; comp+=2; + mtx[3] = ttSHORT(comp)/16384.0f; comp+=2; + } + + // Find transformation scales. + m = (float) STBTT_sqrt(mtx[0]*mtx[0] + mtx[1]*mtx[1]); + n = (float) STBTT_sqrt(mtx[2]*mtx[2] + mtx[3]*mtx[3]); + + // Get indexed glyph. + comp_num_verts = stbtt_GetGlyphShape(info, gidx, &comp_verts); + if (comp_num_verts > 0) { + // Transform vertices. + for (i = 0; i < comp_num_verts; ++i) { + stbtt_vertex* v = &comp_verts[i]; + stbtt_vertex_type x,y; + x=v->x; y=v->y; + v->x = (stbtt_vertex_type)(m * (mtx[0]*x + mtx[2]*y + mtx[4])); + v->y = (stbtt_vertex_type)(n * (mtx[1]*x + mtx[3]*y + mtx[5])); + x=v->cx; y=v->cy; + v->cx = (stbtt_vertex_type)(m * (mtx[0]*x + mtx[2]*y + mtx[4])); + v->cy = (stbtt_vertex_type)(n * (mtx[1]*x + mtx[3]*y + mtx[5])); + } + // Append vertices. + tmp = (stbtt_vertex*)STBTT_malloc((num_vertices+comp_num_verts)*sizeof(stbtt_vertex), info->userdata); + if (!tmp) { + if (vertices) STBTT_free(vertices, info->userdata); + if (comp_verts) STBTT_free(comp_verts, info->userdata); + return 0; + } + if (num_vertices > 0) STBTT_memcpy(tmp, vertices, num_vertices*sizeof(stbtt_vertex)); + STBTT_memcpy(tmp+num_vertices, comp_verts, comp_num_verts*sizeof(stbtt_vertex)); + if (vertices) STBTT_free(vertices, info->userdata); + vertices = tmp; + STBTT_free(comp_verts, info->userdata); + num_vertices += comp_num_verts; + } + // More components ? + more = flags & (1<<5); + } + } else if (numberOfContours < 0) { + // @TODO other compound variations? + STBTT_assert(0); + } else { + // numberOfCounters == 0, do nothing + } + + *pvertices = vertices; + return num_vertices; +} + +STBTT_DEF void stbtt_GetGlyphHMetrics(const stbtt_fontinfo *info, int glyph_index, int *advanceWidth, int *leftSideBearing) +{ + stbtt_uint16 numOfLongHorMetrics = ttUSHORT(info->data+info->hhea + 34); + if (glyph_index < numOfLongHorMetrics) { + if (advanceWidth) *advanceWidth = ttSHORT(info->data + info->hmtx + 4*glyph_index); + if (leftSideBearing) *leftSideBearing = ttSHORT(info->data + info->hmtx + 4*glyph_index + 2); + } else { + if (advanceWidth) *advanceWidth = ttSHORT(info->data + info->hmtx + 4*(numOfLongHorMetrics-1)); + if (leftSideBearing) *leftSideBearing = ttSHORT(info->data + info->hmtx + 4*numOfLongHorMetrics + 2*(glyph_index - numOfLongHorMetrics)); + } +} + +STBTT_DEF int stbtt_GetGlyphKernAdvance(const stbtt_fontinfo *info, int glyph1, int glyph2) +{ + stbtt_uint8 *data = info->data + info->kern; + stbtt_uint32 needle, straw; + int l, r, m; + + // we only look at the first table. it must be 'horizontal' and format 0. + if (!info->kern) + return 0; + if (ttUSHORT(data+2) < 1) // number of tables, need at least 1 + return 0; + if (ttUSHORT(data+8) != 1) // horizontal flag must be set in format + return 0; + + l = 0; + r = ttUSHORT(data+10) - 1; + needle = glyph1 << 16 | glyph2; + while (l <= r) { + m = (l + r) >> 1; + straw = ttULONG(data+18+(m*6)); // note: unaligned read + if (needle < straw) + r = m - 1; + else if (needle > straw) + l = m + 1; + else + return ttSHORT(data+22+(m*6)); + } + return 0; +} + +STBTT_DEF int stbtt_GetCodepointKernAdvance(const stbtt_fontinfo *info, int ch1, int ch2) +{ + if (!info->kern) // if no kerning table, don't waste time looking up both codepoint->glyphs + return 0; + return stbtt_GetGlyphKernAdvance(info, stbtt_FindGlyphIndex(info,ch1), stbtt_FindGlyphIndex(info,ch2)); +} + +STBTT_DEF void stbtt_GetCodepointHMetrics(const stbtt_fontinfo *info, int codepoint, int *advanceWidth, int *leftSideBearing) +{ + stbtt_GetGlyphHMetrics(info, stbtt_FindGlyphIndex(info,codepoint), advanceWidth, leftSideBearing); +} + +STBTT_DEF void stbtt_GetFontVMetrics(const stbtt_fontinfo *info, int *ascent, int *descent, int *lineGap) +{ + if (ascent ) *ascent = ttSHORT(info->data+info->hhea + 4); + if (descent) *descent = ttSHORT(info->data+info->hhea + 6); + if (lineGap) *lineGap = ttSHORT(info->data+info->hhea + 8); +} + +STBTT_DEF void stbtt_GetFontBoundingBox(const stbtt_fontinfo *info, int *x0, int *y0, int *x1, int *y1) +{ + *x0 = ttSHORT(info->data + info->head + 36); + *y0 = ttSHORT(info->data + info->head + 38); + *x1 = ttSHORT(info->data + info->head + 40); + *y1 = ttSHORT(info->data + info->head + 42); +} + +STBTT_DEF float stbtt_ScaleForPixelHeight(const stbtt_fontinfo *info, float height) +{ + int fheight = ttSHORT(info->data + info->hhea + 4) - ttSHORT(info->data + info->hhea + 6); + return (float) height / fheight; +} + +STBTT_DEF float stbtt_ScaleForMappingEmToPixels(const stbtt_fontinfo *info, float pixels) +{ + int unitsPerEm = ttUSHORT(info->data + info->head + 18); + return pixels / unitsPerEm; +} + +STBTT_DEF void stbtt_FreeShape(const stbtt_fontinfo *info, stbtt_vertex *v) +{ + STBTT_free(v, info->userdata); +} + +////////////////////////////////////////////////////////////////////////////// +// +// antialiasing software rasterizer +// + +STBTT_DEF void stbtt_GetGlyphBitmapBoxSubpixel(const stbtt_fontinfo *font, int glyph, float scale_x, float scale_y,float shift_x, float shift_y, int *ix0, int *iy0, int *ix1, int *iy1) +{ + int x0,y0,x1,y1; + if (!stbtt_GetGlyphBox(font, glyph, &x0,&y0,&x1,&y1)) { + // e.g. space character + if (ix0) *ix0 = 0; + if (iy0) *iy0 = 0; + if (ix1) *ix1 = 0; + if (iy1) *iy1 = 0; + } else { + // move to integral bboxes (treating pixels as little squares, what pixels get touched)? + if (ix0) *ix0 = STBTT_ifloor( x0 * scale_x + shift_x); + if (iy0) *iy0 = STBTT_ifloor(-y1 * scale_y + shift_y); + if (ix1) *ix1 = STBTT_iceil ( x1 * scale_x + shift_x); + if (iy1) *iy1 = STBTT_iceil (-y0 * scale_y + shift_y); + } +} + +STBTT_DEF void stbtt_GetGlyphBitmapBox(const stbtt_fontinfo *font, int glyph, float scale_x, float scale_y, int *ix0, int *iy0, int *ix1, int *iy1) +{ + stbtt_GetGlyphBitmapBoxSubpixel(font, glyph, scale_x, scale_y,0.0f,0.0f, ix0, iy0, ix1, iy1); +} + +STBTT_DEF void stbtt_GetCodepointBitmapBoxSubpixel(const stbtt_fontinfo *font, int codepoint, float scale_x, float scale_y, float shift_x, float shift_y, int *ix0, int *iy0, int *ix1, int *iy1) +{ + stbtt_GetGlyphBitmapBoxSubpixel(font, stbtt_FindGlyphIndex(font,codepoint), scale_x, scale_y,shift_x,shift_y, ix0,iy0,ix1,iy1); +} + +STBTT_DEF void stbtt_GetCodepointBitmapBox(const stbtt_fontinfo *font, int codepoint, float scale_x, float scale_y, int *ix0, int *iy0, int *ix1, int *iy1) +{ + stbtt_GetCodepointBitmapBoxSubpixel(font, codepoint, scale_x, scale_y,0.0f,0.0f, ix0,iy0,ix1,iy1); +} + +////////////////////////////////////////////////////////////////////////////// +// +// Rasterizer + +typedef struct stbtt__hheap_chunk +{ + struct stbtt__hheap_chunk *next; +} stbtt__hheap_chunk; + +typedef struct stbtt__hheap +{ + struct stbtt__hheap_chunk *head; + void *first_free; + int num_remaining_in_head_chunk; +} stbtt__hheap; + +static void *stbtt__hheap_alloc(stbtt__hheap *hh, size_t size, void *userdata) +{ + if (hh->first_free) { + void *p = hh->first_free; + hh->first_free = * (void **) p; + return p; + } else { + if (hh->num_remaining_in_head_chunk == 0) { + int count = (size < 32 ? 2000 : size < 128 ? 800 : 100); + stbtt__hheap_chunk *c = (stbtt__hheap_chunk *) STBTT_malloc(sizeof(stbtt__hheap_chunk) + size * count, userdata); + if (c == NULL) + return NULL; + c->next = hh->head; + hh->head = c; + hh->num_remaining_in_head_chunk = count; + } + --hh->num_remaining_in_head_chunk; + return (char *) (hh->head) + size * hh->num_remaining_in_head_chunk; + } +} + +static void stbtt__hheap_free(stbtt__hheap *hh, void *p) +{ + *(void **) p = hh->first_free; + hh->first_free = p; +} + +static void stbtt__hheap_cleanup(stbtt__hheap *hh, void *userdata) +{ + stbtt__hheap_chunk *c = hh->head; + while (c) { + stbtt__hheap_chunk *n = c->next; + STBTT_free(c, userdata); + c = n; + } +} + +typedef struct stbtt__edge { + float x0,y0, x1,y1; + int invert; +} stbtt__edge; + + +typedef struct stbtt__active_edge +{ + struct stbtt__active_edge *next; + #if STBTT_RASTERIZER_VERSION==1 + int x,dx; + float ey; + int direction; + #elif STBTT_RASTERIZER_VERSION==2 + float fx,fdx,fdy; + float direction; + float sy; + float ey; + #else + #error "Unrecognized value of STBTT_RASTERIZER_VERSION" + #endif +} stbtt__active_edge; + +#if STBTT_RASTERIZER_VERSION == 1 +#define STBTT_FIXSHIFT 10 +#define STBTT_FIX (1 << STBTT_FIXSHIFT) +#define STBTT_FIXMASK (STBTT_FIX-1) + +static stbtt__active_edge *stbtt__new_active(stbtt__hheap *hh, stbtt__edge *e, int off_x, float start_point, void *userdata) +{ + stbtt__active_edge *z = (stbtt__active_edge *) stbtt__hheap_alloc(hh, sizeof(*z), userdata); + float dxdy = (e->x1 - e->x0) / (e->y1 - e->y0); + if (!z) return z; + + // round dx down to avoid overshooting + if (dxdy < 0) + z->dx = -STBTT_ifloor(STBTT_FIX * -dxdy); + else + z->dx = STBTT_ifloor(STBTT_FIX * dxdy); + + z->x = STBTT_ifloor(STBTT_FIX * e->x0 + z->dx * (start_point - e->y0)); // use z->dx so when we offset later it's by the same amount + z->x -= off_x * STBTT_FIX; + + z->ey = e->y1; + z->next = 0; + z->direction = e->invert ? 1 : -1; + return z; +} +#elif STBTT_RASTERIZER_VERSION == 2 +static stbtt__active_edge *stbtt__new_active(stbtt__hheap *hh, stbtt__edge *e, int off_x, float start_point, void *userdata) +{ + stbtt__active_edge *z = (stbtt__active_edge *) stbtt__hheap_alloc(hh, sizeof(*z), userdata); + float dxdy = (e->x1 - e->x0) / (e->y1 - e->y0); + //STBTT_assert(e->y0 <= start_point); + if (!z) return z; + z->fdx = dxdy; + z->fdy = dxdy != 0.0f ? (1.0f/dxdy) : 0.0f; + z->fx = e->x0 + dxdy * (start_point - e->y0); + z->fx -= off_x; + z->direction = e->invert ? 1.0f : -1.0f; + z->sy = e->y0; + z->ey = e->y1; + z->next = 0; + return z; +} +#else +#error "Unrecognized value of STBTT_RASTERIZER_VERSION" +#endif + +#if STBTT_RASTERIZER_VERSION == 1 +// note: this routine clips fills that extend off the edges... ideally this +// wouldn't happen, but it could happen if the truetype glyph bounding boxes +// are wrong, or if the user supplies a too-small bitmap +static void stbtt__fill_active_edges(unsigned char *scanline, int len, stbtt__active_edge *e, int max_weight) +{ + // non-zero winding fill + int x0=0, w=0; + + while (e) { + if (w == 0) { + // if we're currently at zero, we need to record the edge start point + x0 = e->x; w += e->direction; + } else { + int x1 = e->x; w += e->direction; + // if we went to zero, we need to draw + if (w == 0) { + int i = x0 >> STBTT_FIXSHIFT; + int j = x1 >> STBTT_FIXSHIFT; + + if (i < len && j >= 0) { + if (i == j) { + // x0,x1 are the same pixel, so compute combined coverage + scanline[i] = scanline[i] + (stbtt_uint8) ((x1 - x0) * max_weight >> STBTT_FIXSHIFT); + } else { + if (i >= 0) // add antialiasing for x0 + scanline[i] = scanline[i] + (stbtt_uint8) (((STBTT_FIX - (x0 & STBTT_FIXMASK)) * max_weight) >> STBTT_FIXSHIFT); + else + i = -1; // clip + + if (j < len) // add antialiasing for x1 + scanline[j] = scanline[j] + (stbtt_uint8) (((x1 & STBTT_FIXMASK) * max_weight) >> STBTT_FIXSHIFT); + else + j = len; // clip + + for (++i; i < j; ++i) // fill pixels between x0 and x1 + scanline[i] = scanline[i] + (stbtt_uint8) max_weight; + } + } + } + } + + e = e->next; + } +} + +static void stbtt__rasterize_sorted_edges(stbtt__bitmap *result, stbtt__edge *e, int n, int vsubsample, int off_x, int off_y, void *userdata) +{ + stbtt__hheap hh = { 0, 0, 0 }; + stbtt__active_edge *active = NULL; + int y,j=0; + int max_weight = (255 / vsubsample); // weight per vertical scanline + int s; // vertical subsample index + unsigned char scanline_data[512], *scanline; + + if (result->w > 512) + scanline = (unsigned char *) STBTT_malloc(result->w, userdata); + else + scanline = scanline_data; + + y = off_y * vsubsample; + e[n].y0 = (off_y + result->h) * (float) vsubsample + 1; + + while (j < result->h) { + STBTT_memset(scanline, 0, result->w); + for (s=0; s < vsubsample; ++s) { + // find center of pixel for this scanline + float scan_y = y + 0.5f; + stbtt__active_edge **step = &active; + + // update all active edges; + // remove all active edges that terminate before the center of this scanline + while (*step) { + stbtt__active_edge * z = *step; + if (z->ey <= scan_y) { + *step = z->next; // delete from list + STBTT_assert(z->direction); + z->direction = 0; + stbtt__hheap_free(&hh, z); + } else { + z->x += z->dx; // advance to position for current scanline + step = &((*step)->next); // advance through list + } + } + + // resort the list if needed + for(;;) { + int changed=0; + step = &active; + while (*step && (*step)->next) { + if ((*step)->x > (*step)->next->x) { + stbtt__active_edge *t = *step; + stbtt__active_edge *q = t->next; + + t->next = q->next; + q->next = t; + *step = q; + changed = 1; + } + step = &(*step)->next; + } + if (!changed) break; + } + + // insert all edges that start before the center of this scanline -- omit ones that also end on this scanline + while (e->y0 <= scan_y) { + if (e->y1 > scan_y) { + stbtt__active_edge *z = stbtt__new_active(&hh, e, off_x, scan_y, userdata); + // find insertion point + if (active == NULL) + active = z; + else if (z->x < active->x) { + // insert at front + z->next = active; + active = z; + } else { + // find thing to insert AFTER + stbtt__active_edge *p = active; + while (p->next && p->next->x < z->x) + p = p->next; + // at this point, p->next->x is NOT < z->x + z->next = p->next; + p->next = z; + } + } + ++e; + } + + // now process all active edges in XOR fashion + if (active) + stbtt__fill_active_edges(scanline, result->w, active, max_weight); + + ++y; + } + STBTT_memcpy(result->pixels + j * result->stride, scanline, result->w); + ++j; + } + + stbtt__hheap_cleanup(&hh, userdata); + + if (scanline != scanline_data) + STBTT_free(scanline, userdata); +} + +#elif STBTT_RASTERIZER_VERSION == 2 + +// the edge passed in here does not cross the vertical line at x or the vertical line at x+1 +// (i.e. it has already been clipped to those) +static void stbtt__handle_clipped_edge(float *scanline, int x, stbtt__active_edge *e, float x0, float y0, float x1, float y1) +{ + if (y0 == y1) return; + STBTT_assert(y0 < y1); + STBTT_assert(e->sy <= e->ey); + if (y0 > e->ey) return; + if (y1 < e->sy) return; + if (y0 < e->sy) { + x0 += (x1-x0) * (e->sy - y0) / (y1-y0); + y0 = e->sy; + } + if (y1 > e->ey) { + x1 += (x1-x0) * (e->ey - y1) / (y1-y0); + y1 = e->ey; + } + + if (x0 == x) + STBTT_assert(x1 <= x+1); + else if (x0 == x+1) + STBTT_assert(x1 >= x); + else if (x0 <= x) + STBTT_assert(x1 <= x); + else if (x0 >= x+1) + STBTT_assert(x1 >= x+1); + else + STBTT_assert(x1 >= x && x1 <= x+1); + + if (x0 <= x && x1 <= x) + scanline[x] += e->direction * (y1-y0); + else if (x0 >= x+1 && x1 >= x+1) + ; + else { + STBTT_assert(x0 >= x && x0 <= x+1 && x1 >= x && x1 <= x+1); + scanline[x] += e->direction * (y1-y0) * (1-((x0-x)+(x1-x))/2); // coverage = 1 - average x position + } +} + +static void stbtt__fill_active_edges_new(float *scanline, float *scanline_fill, int len, stbtt__active_edge *e, float y_top) +{ + float y_bottom = y_top+1; + + while (e) { + // brute force every pixel + + // compute intersection points with top & bottom + STBTT_assert(e->ey >= y_top); + + if (e->fdx == 0) { + float x0 = e->fx; + if (x0 < len) { + if (x0 >= 0) { + stbtt__handle_clipped_edge(scanline,(int) x0,e, x0,y_top, x0,y_bottom); + stbtt__handle_clipped_edge(scanline_fill-1,(int) x0+1,e, x0,y_top, x0,y_bottom); + } else { + stbtt__handle_clipped_edge(scanline_fill-1,0,e, x0,y_top, x0,y_bottom); + } + } + } else { + float x0 = e->fx; + float dx = e->fdx; + float xb = x0 + dx; + float x_top, x_bottom; + float sy0,sy1; + float dy = e->fdy; + STBTT_assert(e->sy <= y_bottom && e->ey >= y_top); + + // compute endpoints of line segment clipped to this scanline (if the + // line segment starts on this scanline. x0 is the intersection of the + // line with y_top, but that may be off the line segment. + if (e->sy > y_top) { + x_top = x0 + dx * (e->sy - y_top); + sy0 = e->sy; + } else { + x_top = x0; + sy0 = y_top; + } + if (e->ey < y_bottom) { + x_bottom = x0 + dx * (e->ey - y_top); + sy1 = e->ey; + } else { + x_bottom = xb; + sy1 = y_bottom; + } + + if (x_top >= 0 && x_bottom >= 0 && x_top < len && x_bottom < len) { + // from here on, we don't have to range check x values + + if ((int) x_top == (int) x_bottom) { + float height; + // simple case, only spans one pixel + int x = (int) x_top; + height = sy1 - sy0; + STBTT_assert(x >= 0 && x < len); + scanline[x] += e->direction * (1-((x_top - x) + (x_bottom-x))/2) * height; + scanline_fill[x] += e->direction * height; // everything right of this pixel is filled + } else { + int x,x1,x2; + float y_crossing, step, sign, area; + // covers 2+ pixels + if (x_top > x_bottom) { + // flip scanline vertically; signed area is the same + float t; + sy0 = y_bottom - (sy0 - y_top); + sy1 = y_bottom - (sy1 - y_top); + t = sy0, sy0 = sy1, sy1 = t; + t = x_bottom, x_bottom = x_top, x_top = t; + dx = -dx; + dy = -dy; + t = x0, x0 = xb, xb = t; + } + + x1 = (int) x_top; + x2 = (int) x_bottom; + // compute intersection with y axis at x1+1 + y_crossing = (x1+1 - x0) * dy + y_top; + + sign = e->direction; + // area of the rectangle covered from y0..y_crossing + area = sign * (y_crossing-sy0); + // area of the triangle (x_top,y0), (x+1,y0), (x+1,y_crossing) + scanline[x1] += area * (1-((x_top - x1)+(x1+1-x1))/2); + + step = sign * dy; + for (x = x1+1; x < x2; ++x) { + scanline[x] += area + step/2; + area += step; + } + y_crossing += dy * (x2 - (x1+1)); + + STBTT_assert(fabs(area) <= 1.01f); + + scanline[x2] += area + sign * (1-((x2-x2)+(x_bottom-x2))/2) * (sy1-y_crossing); + + scanline_fill[x2] += sign * (sy1-sy0); + } + } else { + // if edge goes outside of box we're drawing, we require + // clipping logic. since this does not match the intended use + // of this library, we use a different, very slow brute + // force implementation + int x; + for (x=0; x < len; ++x) { + // cases: + // + // there can be up to two intersections with the pixel. any intersection + // with left or right edges can be handled by splitting into two (or three) + // regions. intersections with top & bottom do not necessitate case-wise logic. + // + // the old way of doing this found the intersections with the left & right edges, + // then used some simple logic to produce up to three segments in sorted order + // from top-to-bottom. however, this had a problem: if an x edge was epsilon + // across the x border, then the corresponding y position might not be distinct + // from the other y segment, and it might ignored as an empty segment. to avoid + // that, we need to explicitly produce segments based on x positions. + + // rename variables to clear pairs + float y0 = y_top; + float x1 = (float) (x); + float x2 = (float) (x+1); + float x3 = xb; + float y3 = y_bottom; + float y1,y2; + + // x = e->x + e->dx * (y-y_top) + // (y-y_top) = (x - e->x) / e->dx + // y = (x - e->x) / e->dx + y_top + y1 = (x - x0) / dx + y_top; + y2 = (x+1 - x0) / dx + y_top; + + if (x0 < x1 && x3 > x2) { // three segments descending down-right + stbtt__handle_clipped_edge(scanline,x,e, x0,y0, x1,y1); + stbtt__handle_clipped_edge(scanline,x,e, x1,y1, x2,y2); + stbtt__handle_clipped_edge(scanline,x,e, x2,y2, x3,y3); + } else if (x3 < x1 && x0 > x2) { // three segments descending down-left + stbtt__handle_clipped_edge(scanline,x,e, x0,y0, x2,y2); + stbtt__handle_clipped_edge(scanline,x,e, x2,y2, x1,y1); + stbtt__handle_clipped_edge(scanline,x,e, x1,y1, x3,y3); + } else if (x0 < x1 && x3 > x1) { // two segments across x, down-right + stbtt__handle_clipped_edge(scanline,x,e, x0,y0, x1,y1); + stbtt__handle_clipped_edge(scanline,x,e, x1,y1, x3,y3); + } else if (x3 < x1 && x0 > x1) { // two segments across x, down-left + stbtt__handle_clipped_edge(scanline,x,e, x0,y0, x1,y1); + stbtt__handle_clipped_edge(scanline,x,e, x1,y1, x3,y3); + } else if (x0 < x2 && x3 > x2) { // two segments across x+1, down-right + stbtt__handle_clipped_edge(scanline,x,e, x0,y0, x2,y2); + stbtt__handle_clipped_edge(scanline,x,e, x2,y2, x3,y3); + } else if (x3 < x2 && x0 > x2) { // two segments across x+1, down-left + stbtt__handle_clipped_edge(scanline,x,e, x0,y0, x2,y2); + stbtt__handle_clipped_edge(scanline,x,e, x2,y2, x3,y3); + } else { // one segment + stbtt__handle_clipped_edge(scanline,x,e, x0,y0, x3,y3); + } + } + } + } + e = e->next; + } +} + +// directly AA rasterize edges w/o supersampling +static void stbtt__rasterize_sorted_edges(stbtt__bitmap *result, stbtt__edge *e, int n, int vsubsample, int off_x, int off_y, void *userdata) +{ + stbtt__hheap hh = { 0, 0, 0 }; + stbtt__active_edge *active = NULL; + int y,j=0, i; + float scanline_data[129], *scanline, *scanline2; + + if (result->w > 64) + scanline = (float *) STBTT_malloc((result->w*2+1) * sizeof(float), userdata); + else + scanline = scanline_data; + + scanline2 = scanline + result->w; + + y = off_y; + e[n].y0 = (float) (off_y + result->h) + 1; + + while (j < result->h) { + // find center of pixel for this scanline + float scan_y_top = y + 0.0f; + float scan_y_bottom = y + 1.0f; + stbtt__active_edge **step = &active; + + STBTT_memset(scanline , 0, result->w*sizeof(scanline[0])); + STBTT_memset(scanline2, 0, (result->w+1)*sizeof(scanline[0])); + + // update all active edges; + // remove all active edges that terminate before the top of this scanline + while (*step) { + stbtt__active_edge * z = *step; + if (z->ey <= scan_y_top) { + *step = z->next; // delete from list + STBTT_assert(z->direction); + z->direction = 0; + stbtt__hheap_free(&hh, z); + } else { + step = &((*step)->next); // advance through list + } + } + + // insert all edges that start before the bottom of this scanline + while (e->y0 <= scan_y_bottom) { + if (e->y0 != e->y1) { + stbtt__active_edge *z = stbtt__new_active(&hh, e, off_x, scan_y_top, userdata); + STBTT_assert(z->ey >= scan_y_top); + // insert at front + z->next = active; + active = z; + } + ++e; + } + + // now process all active edges + if (active) + stbtt__fill_active_edges_new(scanline, scanline2+1, result->w, active, scan_y_top); + + { + float sum = 0; + for (i=0; i < result->w; ++i) { + float k; + int m; + sum += scanline2[i]; + k = scanline[i] + sum; + k = (float) STBTT_fabs(k)*255 + 0.5f; + m = (int) k; + if (m > 255) m = 255; + result->pixels[j*result->stride + i] = (unsigned char) m; + } + } + // advance all the edges + step = &active; + while (*step) { + stbtt__active_edge *z = *step; + z->fx += z->fdx; // advance to position for current scanline + step = &((*step)->next); // advance through list + } + + ++y; + ++j; + } + + stbtt__hheap_cleanup(&hh, userdata); + + if (scanline != scanline_data) + STBTT_free(scanline, userdata); +} +#else +#error "Unrecognized value of STBTT_RASTERIZER_VERSION" +#endif + +#define STBTT__COMPARE(a,b) ((a)->y0 < (b)->y0) + +static void stbtt__sort_edges_ins_sort(stbtt__edge *p, int n) +{ + int i,j; + for (i=1; i < n; ++i) { + stbtt__edge t = p[i], *a = &t; + j = i; + while (j > 0) { + stbtt__edge *b = &p[j-1]; + int c = STBTT__COMPARE(a,b); + if (!c) break; + p[j] = p[j-1]; + --j; + } + if (i != j) + p[j] = t; + } +} + +static void stbtt__sort_edges_quicksort(stbtt__edge *p, int n) +{ + /* threshhold for transitioning to insertion sort */ + while (n > 12) { + stbtt__edge t; + int c01,c12,c,m,i,j; + + /* compute median of three */ + m = n >> 1; + c01 = STBTT__COMPARE(&p[0],&p[m]); + c12 = STBTT__COMPARE(&p[m],&p[n-1]); + /* if 0 >= mid >= end, or 0 < mid < end, then use mid */ + if (c01 != c12) { + /* otherwise, we'll need to swap something else to middle */ + int z; + c = STBTT__COMPARE(&p[0],&p[n-1]); + /* 0>mid && mid<n: 0>n => n; 0<n => 0 */ + /* 0<mid && mid>n: 0>n => 0; 0<n => n */ + z = (c == c12) ? 0 : n-1; + t = p[z]; + p[z] = p[m]; + p[m] = t; + } + /* now p[m] is the median-of-three */ + /* swap it to the beginning so it won't move around */ + t = p[0]; + p[0] = p[m]; + p[m] = t; + + /* partition loop */ + i=1; + j=n-1; + for(;;) { + /* handling of equality is crucial here */ + /* for sentinels & efficiency with duplicates */ + for (;;++i) { + if (!STBTT__COMPARE(&p[i], &p[0])) break; + } + for (;;--j) { + if (!STBTT__COMPARE(&p[0], &p[j])) break; + } + /* make sure we haven't crossed */ + if (i >= j) break; + t = p[i]; + p[i] = p[j]; + p[j] = t; + + ++i; + --j; + } + /* recurse on smaller side, iterate on larger */ + if (j < (n-i)) { + stbtt__sort_edges_quicksort(p,j); + p = p+i; + n = n-i; + } else { + stbtt__sort_edges_quicksort(p+i, n-i); + n = j; + } + } +} + +static void stbtt__sort_edges(stbtt__edge *p, int n) +{ + stbtt__sort_edges_quicksort(p, n); + stbtt__sort_edges_ins_sort(p, n); +} + +typedef struct +{ + float x,y; +} stbtt__point; + +static void stbtt__rasterize(stbtt__bitmap *result, stbtt__point *pts, int *wcount, int windings, float scale_x, float scale_y, float shift_x, float shift_y, int off_x, int off_y, int invert, void *userdata) +{ + float y_scale_inv = invert ? -scale_y : scale_y; + stbtt__edge *e; + int n,i,j,k,m; +#if STBTT_RASTERIZER_VERSION == 1 + int vsubsample = result->h < 8 ? 15 : 5; +#elif STBTT_RASTERIZER_VERSION == 2 + int vsubsample = 1; +#else + #error "Unrecognized value of STBTT_RASTERIZER_VERSION" +#endif + // vsubsample should divide 255 evenly; otherwise we won't reach full opacity + + // now we have to blow out the windings into explicit edge lists + n = 0; + for (i=0; i < windings; ++i) + n += wcount[i]; + + e = (stbtt__edge *) STBTT_malloc(sizeof(*e) * (n+1), userdata); // add an extra one as a sentinel + if (e == 0) return; + n = 0; + + m=0; + for (i=0; i < windings; ++i) { + stbtt__point *p = pts + m; + m += wcount[i]; + j = wcount[i]-1; + for (k=0; k < wcount[i]; j=k++) { + int a=k,b=j; + // skip the edge if horizontal + if (p[j].y == p[k].y) + continue; + // add edge from j to k to the list + e[n].invert = 0; + if (invert ? p[j].y > p[k].y : p[j].y < p[k].y) { + e[n].invert = 1; + a=j,b=k; + } + e[n].x0 = p[a].x * scale_x + shift_x; + e[n].y0 = (p[a].y * y_scale_inv + shift_y) * vsubsample; + e[n].x1 = p[b].x * scale_x + shift_x; + e[n].y1 = (p[b].y * y_scale_inv + shift_y) * vsubsample; + ++n; + } + } + + // now sort the edges by their highest point (should snap to integer, and then by x) + //STBTT_sort(e, n, sizeof(e[0]), stbtt__edge_compare); + stbtt__sort_edges(e, n); + + // now, traverse the scanlines and find the intersections on each scanline, use xor winding rule + stbtt__rasterize_sorted_edges(result, e, n, vsubsample, off_x, off_y, userdata); + + STBTT_free(e, userdata); +} + +static void stbtt__add_point(stbtt__point *points, int n, float x, float y) +{ + if (!points) return; // during first pass, it's unallocated + points[n].x = x; + points[n].y = y; +} + +// tesselate until threshhold p is happy... @TODO warped to compensate for non-linear stretching +static int stbtt__tesselate_curve(stbtt__point *points, int *num_points, float x0, float y0, float x1, float y1, float x2, float y2, float objspace_flatness_squared, int n) +{ + // midpoint + float mx = (x0 + 2*x1 + x2)/4; + float my = (y0 + 2*y1 + y2)/4; + // versus directly drawn line + float dx = (x0+x2)/2 - mx; + float dy = (y0+y2)/2 - my; + if (n > 16) // 65536 segments on one curve better be enough! + return 1; + if (dx*dx+dy*dy > objspace_flatness_squared) { // half-pixel error allowed... need to be smaller if AA + stbtt__tesselate_curve(points, num_points, x0,y0, (x0+x1)/2.0f,(y0+y1)/2.0f, mx,my, objspace_flatness_squared,n+1); + stbtt__tesselate_curve(points, num_points, mx,my, (x1+x2)/2.0f,(y1+y2)/2.0f, x2,y2, objspace_flatness_squared,n+1); + } else { + stbtt__add_point(points, *num_points,x2,y2); + *num_points = *num_points+1; + } + return 1; +} + +// returns number of contours +static stbtt__point *stbtt_FlattenCurves(stbtt_vertex *vertices, int num_verts, float objspace_flatness, int **contour_lengths, int *num_contours, void *userdata) +{ + stbtt__point *points=0; + int num_points=0; + + float objspace_flatness_squared = objspace_flatness * objspace_flatness; + int i,n=0,start=0, pass; + + // count how many "moves" there are to get the contour count + for (i=0; i < num_verts; ++i) + if (vertices[i].type == STBTT_vmove) + ++n; + + *num_contours = n; + if (n == 0) return 0; + + *contour_lengths = (int *) STBTT_malloc(sizeof(**contour_lengths) * n, userdata); + + if (*contour_lengths == 0) { + *num_contours = 0; + return 0; + } + + // make two passes through the points so we don't need to realloc + for (pass=0; pass < 2; ++pass) { + float x=0,y=0; + if (pass == 1) { + points = (stbtt__point *) STBTT_malloc(num_points * sizeof(points[0]), userdata); + if (points == NULL) goto error; + } + num_points = 0; + n= -1; + for (i=0; i < num_verts; ++i) { + switch (vertices[i].type) { + case STBTT_vmove: + // start the next contour + if (n >= 0) + (*contour_lengths)[n] = num_points - start; + ++n; + start = num_points; + + x = vertices[i].x, y = vertices[i].y; + stbtt__add_point(points, num_points++, x,y); + break; + case STBTT_vline: + x = vertices[i].x, y = vertices[i].y; + stbtt__add_point(points, num_points++, x, y); + break; + case STBTT_vcurve: + stbtt__tesselate_curve(points, &num_points, x,y, + vertices[i].cx, vertices[i].cy, + vertices[i].x, vertices[i].y, + objspace_flatness_squared, 0); + x = vertices[i].x, y = vertices[i].y; + break; + } + } + (*contour_lengths)[n] = num_points - start; + } + + return points; +error: + STBTT_free(points, userdata); + STBTT_free(*contour_lengths, userdata); + *contour_lengths = 0; + *num_contours = 0; + return NULL; +} + +STBTT_DEF void stbtt_Rasterize(stbtt__bitmap *result, float flatness_in_pixels, stbtt_vertex *vertices, int num_verts, float scale_x, float scale_y, float shift_x, float shift_y, int x_off, int y_off, int invert, void *userdata) +{ + float scale = scale_x > scale_y ? scale_y : scale_x; + int winding_count, *winding_lengths; + stbtt__point *windings = stbtt_FlattenCurves(vertices, num_verts, flatness_in_pixels / scale, &winding_lengths, &winding_count, userdata); + if (windings) { + stbtt__rasterize(result, windings, winding_lengths, winding_count, scale_x, scale_y, shift_x, shift_y, x_off, y_off, invert, userdata); + STBTT_free(winding_lengths, userdata); + STBTT_free(windings, userdata); + } +} + +STBTT_DEF void stbtt_FreeBitmap(unsigned char *bitmap, void *userdata) +{ + STBTT_free(bitmap, userdata); +} + +STBTT_DEF unsigned char *stbtt_GetGlyphBitmapSubpixel(const stbtt_fontinfo *info, float scale_x, float scale_y, float shift_x, float shift_y, int glyph, int *width, int *height, int *xoff, int *yoff) +{ + int ix0,iy0,ix1,iy1; + stbtt__bitmap gbm; + stbtt_vertex *vertices; + int num_verts = stbtt_GetGlyphShape(info, glyph, &vertices); + + if (scale_x == 0) scale_x = scale_y; + if (scale_y == 0) { + if (scale_x == 0) return NULL; + scale_y = scale_x; + } + + stbtt_GetGlyphBitmapBoxSubpixel(info, glyph, scale_x, scale_y, shift_x, shift_y, &ix0,&iy0,&ix1,&iy1); + + // now we get the size + gbm.w = (ix1 - ix0); + gbm.h = (iy1 - iy0); + gbm.pixels = NULL; // in case we error + + if (width ) *width = gbm.w; + if (height) *height = gbm.h; + if (xoff ) *xoff = ix0; + if (yoff ) *yoff = iy0; + + if (gbm.w && gbm.h) { + gbm.pixels = (unsigned char *) STBTT_malloc(gbm.w * gbm.h, info->userdata); + if (gbm.pixels) { + gbm.stride = gbm.w; + + stbtt_Rasterize(&gbm, 0.35f, vertices, num_verts, scale_x, scale_y, shift_x, shift_y, ix0, iy0, 1, info->userdata); + } + } + STBTT_free(vertices, info->userdata); + return gbm.pixels; +} + +STBTT_DEF unsigned char *stbtt_GetGlyphBitmap(const stbtt_fontinfo *info, float scale_x, float scale_y, int glyph, int *width, int *height, int *xoff, int *yoff) +{ + return stbtt_GetGlyphBitmapSubpixel(info, scale_x, scale_y, 0.0f, 0.0f, glyph, width, height, xoff, yoff); +} + +STBTT_DEF void stbtt_MakeGlyphBitmapSubpixel(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int glyph) +{ + int ix0,iy0; + stbtt_vertex *vertices; + int num_verts = stbtt_GetGlyphShape(info, glyph, &vertices); + stbtt__bitmap gbm; + + stbtt_GetGlyphBitmapBoxSubpixel(info, glyph, scale_x, scale_y, shift_x, shift_y, &ix0,&iy0,0,0); + gbm.pixels = output; + gbm.w = out_w; + gbm.h = out_h; + gbm.stride = out_stride; + + if (gbm.w && gbm.h) + stbtt_Rasterize(&gbm, 0.35f, vertices, num_verts, scale_x, scale_y, shift_x, shift_y, ix0,iy0, 1, info->userdata); + + STBTT_free(vertices, info->userdata); +} + +STBTT_DEF void stbtt_MakeGlyphBitmap(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, int glyph) +{ + stbtt_MakeGlyphBitmapSubpixel(info, output, out_w, out_h, out_stride, scale_x, scale_y, 0.0f,0.0f, glyph); +} + +STBTT_DEF unsigned char *stbtt_GetCodepointBitmapSubpixel(const stbtt_fontinfo *info, float scale_x, float scale_y, float shift_x, float shift_y, int codepoint, int *width, int *height, int *xoff, int *yoff) +{ + return stbtt_GetGlyphBitmapSubpixel(info, scale_x, scale_y,shift_x,shift_y, stbtt_FindGlyphIndex(info,codepoint), width,height,xoff,yoff); +} + +STBTT_DEF void stbtt_MakeCodepointBitmapSubpixel(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, float shift_x, float shift_y, int codepoint) +{ + stbtt_MakeGlyphBitmapSubpixel(info, output, out_w, out_h, out_stride, scale_x, scale_y, shift_x, shift_y, stbtt_FindGlyphIndex(info,codepoint)); +} + +STBTT_DEF unsigned char *stbtt_GetCodepointBitmap(const stbtt_fontinfo *info, float scale_x, float scale_y, int codepoint, int *width, int *height, int *xoff, int *yoff) +{ + return stbtt_GetCodepointBitmapSubpixel(info, scale_x, scale_y, 0.0f,0.0f, codepoint, width,height,xoff,yoff); +} + +STBTT_DEF void stbtt_MakeCodepointBitmap(const stbtt_fontinfo *info, unsigned char *output, int out_w, int out_h, int out_stride, float scale_x, float scale_y, int codepoint) +{ + stbtt_MakeCodepointBitmapSubpixel(info, output, out_w, out_h, out_stride, scale_x, scale_y, 0.0f,0.0f, codepoint); +} + +////////////////////////////////////////////////////////////////////////////// +// +// bitmap baking +// +// This is SUPER-CRAPPY packing to keep source code small + +STBTT_DEF int stbtt_BakeFontBitmap(const unsigned char *data, int offset, // font location (use offset=0 for plain .ttf) + float pixel_height, // height of font in pixels + unsigned char *pixels, int pw, int ph, // bitmap to be filled in + int first_char, int num_chars, // characters to bake + stbtt_bakedchar *chardata) +{ + float scale; + int x,y,bottom_y, i; + stbtt_fontinfo f; + if (!stbtt_InitFont(&f, data, offset)) + return -1; + STBTT_memset(pixels, 0, pw*ph); // background of 0 around pixels + x=y=1; + bottom_y = 1; + + scale = stbtt_ScaleForPixelHeight(&f, pixel_height); + + for (i=0; i < num_chars; ++i) { + int advance, lsb, x0,y0,x1,y1,gw,gh; + int g = stbtt_FindGlyphIndex(&f, first_char + i); + stbtt_GetGlyphHMetrics(&f, g, &advance, &lsb); + stbtt_GetGlyphBitmapBox(&f, g, scale,scale, &x0,&y0,&x1,&y1); + gw = x1-x0; + gh = y1-y0; + if (x + gw + 1 >= pw) + y = bottom_y, x = 1; // advance to next row + if (y + gh + 1 >= ph) // check if it fits vertically AFTER potentially moving to next row + return -i; + STBTT_assert(x+gw < pw); + STBTT_assert(y+gh < ph); + stbtt_MakeGlyphBitmap(&f, pixels+x+y*pw, gw,gh,pw, scale,scale, g); + chardata[i].x0 = (stbtt_int16) x; + chardata[i].y0 = (stbtt_int16) y; + chardata[i].x1 = (stbtt_int16) (x + gw); + chardata[i].y1 = (stbtt_int16) (y + gh); + chardata[i].xadvance = scale * advance; + chardata[i].xoff = (float) x0; + chardata[i].yoff = (float) y0; + x = x + gw + 1; + if (y+gh+1 > bottom_y) + bottom_y = y+gh+1; + } + return bottom_y; +} + +STBTT_DEF void stbtt_GetBakedQuad(stbtt_bakedchar *chardata, int pw, int ph, int char_index, float *xpos, float *ypos, stbtt_aligned_quad *q, int opengl_fillrule) +{ + float d3d_bias = opengl_fillrule ? 0 : -0.5f; + float ipw = 1.0f / pw, iph = 1.0f / ph; + stbtt_bakedchar *b = chardata + char_index; + int round_x = STBTT_ifloor((*xpos + b->xoff) + 0.5f); + int round_y = STBTT_ifloor((*ypos + b->yoff) + 0.5f); + + q->x0 = round_x + d3d_bias; + q->y0 = round_y + d3d_bias; + q->x1 = round_x + b->x1 - b->x0 + d3d_bias; + q->y1 = round_y + b->y1 - b->y0 + d3d_bias; + + q->s0 = b->x0 * ipw; + q->t0 = b->y0 * iph; + q->s1 = b->x1 * ipw; + q->t1 = b->y1 * iph; + + *xpos += b->xadvance; +} + +////////////////////////////////////////////////////////////////////////////// +// +// rectangle packing replacement routines if you don't have stb_rect_pack.h +// + +#ifndef STB_RECT_PACK_VERSION +#ifdef _MSC_VER +#define STBTT__NOTUSED(v) (void)(v) +#else +#define STBTT__NOTUSED(v) (void)sizeof(v) +#endif + +typedef int stbrp_coord; + +//////////////////////////////////////////////////////////////////////////////////// +// // +// // +// COMPILER WARNING ?!?!? // +// // +// // +// if you get a compile warning due to these symbols being defined more than // +// once, move #include "stb_rect_pack.h" before #include "stb_truetype.h" // +// // +//////////////////////////////////////////////////////////////////////////////////// + +typedef struct +{ + int width,height; + int x,y,bottom_y; +} stbrp_context; + +typedef struct +{ + unsigned char x; +} stbrp_node; + +struct stbrp_rect +{ + stbrp_coord x,y; + int id,w,h,was_packed; +}; + +static void stbrp_init_target(stbrp_context *con, int pw, int ph, stbrp_node *nodes, int num_nodes) +{ + con->width = pw; + con->height = ph; + con->x = 0; + con->y = 0; + con->bottom_y = 0; + STBTT__NOTUSED(nodes); + STBTT__NOTUSED(num_nodes); +} + +static void stbrp_pack_rects(stbrp_context *con, stbrp_rect *rects, int num_rects) +{ + int i; + for (i=0; i < num_rects; ++i) { + if (con->x + rects[i].w > con->width) { + con->x = 0; + con->y = con->bottom_y; + } + if (con->y + rects[i].h > con->height) + break; + rects[i].x = con->x; + rects[i].y = con->y; + rects[i].was_packed = 1; + con->x += rects[i].w; + if (con->y + rects[i].h > con->bottom_y) + con->bottom_y = con->y + rects[i].h; + } + for ( ; i < num_rects; ++i) + rects[i].was_packed = 0; +} +#endif + +////////////////////////////////////////////////////////////////////////////// +// +// bitmap baking +// +// This is SUPER-AWESOME (tm Ryan Gordon) packing using stb_rect_pack.h. If +// stb_rect_pack.h isn't available, it uses the BakeFontBitmap strategy. + +STBTT_DEF int stbtt_PackBegin(stbtt_pack_context *spc, unsigned char *pixels, int pw, int ph, int stride_in_bytes, int padding, void *alloc_context) +{ + stbrp_context *context = (stbrp_context *) STBTT_malloc(sizeof(*context) ,alloc_context); + int num_nodes = pw - padding; + stbrp_node *nodes = (stbrp_node *) STBTT_malloc(sizeof(*nodes ) * num_nodes,alloc_context); + + if (context == NULL || nodes == NULL) { + if (context != NULL) STBTT_free(context, alloc_context); + if (nodes != NULL) STBTT_free(nodes , alloc_context); + return 0; + } + + spc->user_allocator_context = alloc_context; + spc->width = pw; + spc->height = ph; + spc->pixels = pixels; + spc->pack_info = context; + spc->nodes = nodes; + spc->padding = padding; + spc->stride_in_bytes = stride_in_bytes != 0 ? stride_in_bytes : pw; + spc->h_oversample = 1; + spc->v_oversample = 1; + + stbrp_init_target(context, pw-padding, ph-padding, nodes, num_nodes); + + if (pixels) + STBTT_memset(pixels, 0, pw*ph); // background of 0 around pixels + + return 1; +} + +STBTT_DEF void stbtt_PackEnd (stbtt_pack_context *spc) +{ + STBTT_free(spc->nodes , spc->user_allocator_context); + STBTT_free(spc->pack_info, spc->user_allocator_context); +} + +STBTT_DEF void stbtt_PackSetOversampling(stbtt_pack_context *spc, unsigned int h_oversample, unsigned int v_oversample) +{ + STBTT_assert(h_oversample <= STBTT_MAX_OVERSAMPLE); + STBTT_assert(v_oversample <= STBTT_MAX_OVERSAMPLE); + if (h_oversample <= STBTT_MAX_OVERSAMPLE) + spc->h_oversample = h_oversample; + if (v_oversample <= STBTT_MAX_OVERSAMPLE) + spc->v_oversample = v_oversample; +} + +#define STBTT__OVER_MASK (STBTT_MAX_OVERSAMPLE-1) + +static void stbtt__h_prefilter(unsigned char *pixels, int w, int h, int stride_in_bytes, unsigned int kernel_width) +{ + unsigned char buffer[STBTT_MAX_OVERSAMPLE]; + int safe_w = w - kernel_width; + int j; + for (j=0; j < h; ++j) { + int i; + unsigned int total; + STBTT_memset(buffer, 0, kernel_width); + + total = 0; + + // make kernel_width a constant in common cases so compiler can optimize out the divide + switch (kernel_width) { + case 2: + for (i=0; i <= safe_w; ++i) { + total += pixels[i] - buffer[i & STBTT__OVER_MASK]; + buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i]; + pixels[i] = (unsigned char) (total / 2); + } + break; + case 3: + for (i=0; i <= safe_w; ++i) { + total += pixels[i] - buffer[i & STBTT__OVER_MASK]; + buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i]; + pixels[i] = (unsigned char) (total / 3); + } + break; + case 4: + for (i=0; i <= safe_w; ++i) { + total += pixels[i] - buffer[i & STBTT__OVER_MASK]; + buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i]; + pixels[i] = (unsigned char) (total / 4); + } + break; + case 5: + for (i=0; i <= safe_w; ++i) { + total += pixels[i] - buffer[i & STBTT__OVER_MASK]; + buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i]; + pixels[i] = (unsigned char) (total / 5); + } + break; + default: + for (i=0; i <= safe_w; ++i) { + total += pixels[i] - buffer[i & STBTT__OVER_MASK]; + buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i]; + pixels[i] = (unsigned char) (total / kernel_width); + } + break; + } + + for (; i < w; ++i) { + STBTT_assert(pixels[i] == 0); + total -= buffer[i & STBTT__OVER_MASK]; + pixels[i] = (unsigned char) (total / kernel_width); + } + + pixels += stride_in_bytes; + } +} + +static void stbtt__v_prefilter(unsigned char *pixels, int w, int h, int stride_in_bytes, unsigned int kernel_width) +{ + unsigned char buffer[STBTT_MAX_OVERSAMPLE]; + int safe_h = h - kernel_width; + int j; + for (j=0; j < w; ++j) { + int i; + unsigned int total; + STBTT_memset(buffer, 0, kernel_width); + + total = 0; + + // make kernel_width a constant in common cases so compiler can optimize out the divide + switch (kernel_width) { + case 2: + for (i=0; i <= safe_h; ++i) { + total += pixels[i*stride_in_bytes] - buffer[i & STBTT__OVER_MASK]; + buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i*stride_in_bytes]; + pixels[i*stride_in_bytes] = (unsigned char) (total / 2); + } + break; + case 3: + for (i=0; i <= safe_h; ++i) { + total += pixels[i*stride_in_bytes] - buffer[i & STBTT__OVER_MASK]; + buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i*stride_in_bytes]; + pixels[i*stride_in_bytes] = (unsigned char) (total / 3); + } + break; + case 4: + for (i=0; i <= safe_h; ++i) { + total += pixels[i*stride_in_bytes] - buffer[i & STBTT__OVER_MASK]; + buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i*stride_in_bytes]; + pixels[i*stride_in_bytes] = (unsigned char) (total / 4); + } + break; + case 5: + for (i=0; i <= safe_h; ++i) { + total += pixels[i*stride_in_bytes] - buffer[i & STBTT__OVER_MASK]; + buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i*stride_in_bytes]; + pixels[i*stride_in_bytes] = (unsigned char) (total / 5); + } + break; + default: + for (i=0; i <= safe_h; ++i) { + total += pixels[i*stride_in_bytes] - buffer[i & STBTT__OVER_MASK]; + buffer[(i+kernel_width) & STBTT__OVER_MASK] = pixels[i*stride_in_bytes]; + pixels[i*stride_in_bytes] = (unsigned char) (total / kernel_width); + } + break; + } + + for (; i < h; ++i) { + STBTT_assert(pixels[i*stride_in_bytes] == 0); + total -= buffer[i & STBTT__OVER_MASK]; + pixels[i*stride_in_bytes] = (unsigned char) (total / kernel_width); + } + + pixels += 1; + } +} + +static float stbtt__oversample_shift(int oversample) +{ + if (!oversample) + return 0.0f; + + // The prefilter is a box filter of width "oversample", + // which shifts phase by (oversample - 1)/2 pixels in + // oversampled space. We want to shift in the opposite + // direction to counter this. + return (float)-(oversample - 1) / (2.0f * (float)oversample); +} + +// rects array must be big enough to accommodate all characters in the given ranges +STBTT_DEF int stbtt_PackFontRangesGatherRects(stbtt_pack_context *spc, stbtt_fontinfo *info, stbtt_pack_range *ranges, int num_ranges, stbrp_rect *rects) +{ + int i,j,k; + + k=0; + for (i=0; i < num_ranges; ++i) { + float fh = ranges[i].font_size; + float scale = fh > 0 ? stbtt_ScaleForPixelHeight(info, fh) : stbtt_ScaleForMappingEmToPixels(info, -fh); + ranges[i].h_oversample = (unsigned char) spc->h_oversample; + ranges[i].v_oversample = (unsigned char) spc->v_oversample; + for (j=0; j < ranges[i].num_chars; ++j) { + int x0,y0,x1,y1; + int codepoint = ranges[i].array_of_unicode_codepoints == NULL ? ranges[i].first_unicode_codepoint_in_range + j : ranges[i].array_of_unicode_codepoints[j]; + int glyph = stbtt_FindGlyphIndex(info, codepoint); + stbtt_GetGlyphBitmapBoxSubpixel(info,glyph, + scale * spc->h_oversample, + scale * spc->v_oversample, + 0,0, + &x0,&y0,&x1,&y1); + rects[k].w = (stbrp_coord) (x1-x0 + spc->padding + spc->h_oversample-1); + rects[k].h = (stbrp_coord) (y1-y0 + spc->padding + spc->v_oversample-1); + ++k; + } + } + + return k; +} + +// rects array must be big enough to accommodate all characters in the given ranges +STBTT_DEF int stbtt_PackFontRangesRenderIntoRects(stbtt_pack_context *spc, stbtt_fontinfo *info, stbtt_pack_range *ranges, int num_ranges, stbrp_rect *rects) +{ + int i,j,k, return_value = 1; + + // save current values + int old_h_over = spc->h_oversample; + int old_v_over = spc->v_oversample; + + k = 0; + for (i=0; i < num_ranges; ++i) { + float fh = ranges[i].font_size; + float scale = fh > 0 ? stbtt_ScaleForPixelHeight(info, fh) : stbtt_ScaleForMappingEmToPixels(info, -fh); + float recip_h,recip_v,sub_x,sub_y; + spc->h_oversample = ranges[i].h_oversample; + spc->v_oversample = ranges[i].v_oversample; + recip_h = 1.0f / spc->h_oversample; + recip_v = 1.0f / spc->v_oversample; + sub_x = stbtt__oversample_shift(spc->h_oversample); + sub_y = stbtt__oversample_shift(spc->v_oversample); + for (j=0; j < ranges[i].num_chars; ++j) { + stbrp_rect *r = &rects[k]; + if (r->was_packed) { + stbtt_packedchar *bc = &ranges[i].chardata_for_range[j]; + int advance, lsb, x0,y0,x1,y1; + int codepoint = ranges[i].array_of_unicode_codepoints == NULL ? ranges[i].first_unicode_codepoint_in_range + j : ranges[i].array_of_unicode_codepoints[j]; + int glyph = stbtt_FindGlyphIndex(info, codepoint); + stbrp_coord pad = (stbrp_coord) spc->padding; + + // pad on left and top + r->x += pad; + r->y += pad; + r->w -= pad; + r->h -= pad; + stbtt_GetGlyphHMetrics(info, glyph, &advance, &lsb); + stbtt_GetGlyphBitmapBox(info, glyph, + scale * spc->h_oversample, + scale * spc->v_oversample, + &x0,&y0,&x1,&y1); + stbtt_MakeGlyphBitmapSubpixel(info, + spc->pixels + r->x + r->y*spc->stride_in_bytes, + r->w - spc->h_oversample+1, + r->h - spc->v_oversample+1, + spc->stride_in_bytes, + scale * spc->h_oversample, + scale * spc->v_oversample, + 0,0, + glyph); + + if (spc->h_oversample > 1) + stbtt__h_prefilter(spc->pixels + r->x + r->y*spc->stride_in_bytes, + r->w, r->h, spc->stride_in_bytes, + spc->h_oversample); + + if (spc->v_oversample > 1) + stbtt__v_prefilter(spc->pixels + r->x + r->y*spc->stride_in_bytes, + r->w, r->h, spc->stride_in_bytes, + spc->v_oversample); + + bc->x0 = (stbtt_int16) r->x; + bc->y0 = (stbtt_int16) r->y; + bc->x1 = (stbtt_int16) (r->x + r->w); + bc->y1 = (stbtt_int16) (r->y + r->h); + bc->xadvance = scale * advance; + bc->xoff = (float) x0 * recip_h + sub_x; + bc->yoff = (float) y0 * recip_v + sub_y; + bc->xoff2 = (x0 + r->w) * recip_h + sub_x; + bc->yoff2 = (y0 + r->h) * recip_v + sub_y; + } else { + return_value = 0; // if any fail, report failure + } + + ++k; + } + } + + // restore original values + spc->h_oversample = old_h_over; + spc->v_oversample = old_v_over; + + return return_value; +} + +STBTT_DEF void stbtt_PackFontRangesPackRects(stbtt_pack_context *spc, stbrp_rect *rects, int num_rects) +{ + stbrp_pack_rects((stbrp_context *) spc->pack_info, rects, num_rects); +} + +STBTT_DEF int stbtt_PackFontRanges(stbtt_pack_context *spc, unsigned char *fontdata, int font_index, stbtt_pack_range *ranges, int num_ranges) +{ + stbtt_fontinfo info; + int i,j,n, return_value = 1; + //stbrp_context *context = (stbrp_context *) spc->pack_info; + stbrp_rect *rects; + + // flag all characters as NOT packed + for (i=0; i < num_ranges; ++i) + for (j=0; j < ranges[i].num_chars; ++j) + ranges[i].chardata_for_range[j].x0 = + ranges[i].chardata_for_range[j].y0 = + ranges[i].chardata_for_range[j].x1 = + ranges[i].chardata_for_range[j].y1 = 0; + + n = 0; + for (i=0; i < num_ranges; ++i) + n += ranges[i].num_chars; + + rects = (stbrp_rect *) STBTT_malloc(sizeof(*rects) * n, spc->user_allocator_context); + if (rects == NULL) + return 0; + + stbtt_InitFont(&info, fontdata, stbtt_GetFontOffsetForIndex(fontdata,font_index)); + + n = stbtt_PackFontRangesGatherRects(spc, &info, ranges, num_ranges, rects); + + stbtt_PackFontRangesPackRects(spc, rects, n); + + return_value = stbtt_PackFontRangesRenderIntoRects(spc, &info, ranges, num_ranges, rects); + + STBTT_free(rects, spc->user_allocator_context); + return return_value; +} + +STBTT_DEF int stbtt_PackFontRange(stbtt_pack_context *spc, unsigned char *fontdata, int font_index, float font_size, + int first_unicode_codepoint_in_range, int num_chars_in_range, stbtt_packedchar *chardata_for_range) +{ + stbtt_pack_range range; + range.first_unicode_codepoint_in_range = first_unicode_codepoint_in_range; + range.array_of_unicode_codepoints = NULL; + range.num_chars = num_chars_in_range; + range.chardata_for_range = chardata_for_range; + range.font_size = font_size; + return stbtt_PackFontRanges(spc, fontdata, font_index, &range, 1); +} + +STBTT_DEF void stbtt_GetPackedQuad(stbtt_packedchar *chardata, int pw, int ph, int char_index, float *xpos, float *ypos, stbtt_aligned_quad *q, int align_to_integer) +{ + float ipw = 1.0f / pw, iph = 1.0f / ph; + stbtt_packedchar *b = chardata + char_index; + + if (align_to_integer) { + float x = (float) STBTT_ifloor((*xpos + b->xoff) + 0.5f); + float y = (float) STBTT_ifloor((*ypos + b->yoff) + 0.5f); + q->x0 = x; + q->y0 = y; + q->x1 = x + b->xoff2 - b->xoff; + q->y1 = y + b->yoff2 - b->yoff; + } else { + q->x0 = *xpos + b->xoff; + q->y0 = *ypos + b->yoff; + q->x1 = *xpos + b->xoff2; + q->y1 = *ypos + b->yoff2; + } + + q->s0 = b->x0 * ipw; + q->t0 = b->y0 * iph; + q->s1 = b->x1 * ipw; + q->t1 = b->y1 * iph; + + *xpos += b->xadvance; +} + + +////////////////////////////////////////////////////////////////////////////// +// +// font name matching -- recommended not to use this +// + +// check if a utf8 string contains a prefix which is the utf16 string; if so return length of matching utf8 string +static stbtt_int32 stbtt__CompareUTF8toUTF16_bigendian_prefix(const stbtt_uint8 *s1, stbtt_int32 len1, const stbtt_uint8 *s2, stbtt_int32 len2) +{ + stbtt_int32 i=0; + + // convert utf16 to utf8 and compare the results while converting + while (len2) { + stbtt_uint16 ch = s2[0]*256 + s2[1]; + if (ch < 0x80) { + if (i >= len1) return -1; + if (s1[i++] != ch) return -1; + } else if (ch < 0x800) { + if (i+1 >= len1) return -1; + if (s1[i++] != 0xc0 + (ch >> 6)) return -1; + if (s1[i++] != 0x80 + (ch & 0x3f)) return -1; + } else if (ch >= 0xd800 && ch < 0xdc00) { + stbtt_uint32 c; + stbtt_uint16 ch2 = s2[2]*256 + s2[3]; + if (i+3 >= len1) return -1; + c = ((ch - 0xd800) << 10) + (ch2 - 0xdc00) + 0x10000; + if (s1[i++] != 0xf0 + (c >> 18)) return -1; + if (s1[i++] != 0x80 + ((c >> 12) & 0x3f)) return -1; + if (s1[i++] != 0x80 + ((c >> 6) & 0x3f)) return -1; + if (s1[i++] != 0x80 + ((c ) & 0x3f)) return -1; + s2 += 2; // plus another 2 below + len2 -= 2; + } else if (ch >= 0xdc00 && ch < 0xe000) { + return -1; + } else { + if (i+2 >= len1) return -1; + if (s1[i++] != 0xe0 + (ch >> 12)) return -1; + if (s1[i++] != 0x80 + ((ch >> 6) & 0x3f)) return -1; + if (s1[i++] != 0x80 + ((ch ) & 0x3f)) return -1; + } + s2 += 2; + len2 -= 2; + } + return i; +} + +STBTT_DEF int stbtt_CompareUTF8toUTF16_bigendian(const char *s1, int len1, const char *s2, int len2) +{ + return len1 == stbtt__CompareUTF8toUTF16_bigendian_prefix((const stbtt_uint8*) s1, len1, (const stbtt_uint8*) s2, len2); +} + +// returns results in whatever encoding you request... but note that 2-byte encodings +// will be BIG-ENDIAN... use stbtt_CompareUTF8toUTF16_bigendian() to compare +STBTT_DEF const char *stbtt_GetFontNameString(const stbtt_fontinfo *font, int *length, int platformID, int encodingID, int languageID, int nameID) +{ + stbtt_int32 i,count,stringOffset; + stbtt_uint8 *fc = font->data; + stbtt_uint32 offset = font->fontstart; + stbtt_uint32 nm = stbtt__find_table(fc, offset, "name"); + if (!nm) return NULL; + + count = ttUSHORT(fc+nm+2); + stringOffset = nm + ttUSHORT(fc+nm+4); + for (i=0; i < count; ++i) { + stbtt_uint32 loc = nm + 6 + 12 * i; + if (platformID == ttUSHORT(fc+loc+0) && encodingID == ttUSHORT(fc+loc+2) + && languageID == ttUSHORT(fc+loc+4) && nameID == ttUSHORT(fc+loc+6)) { + *length = ttUSHORT(fc+loc+8); + return (const char *) (fc+stringOffset+ttUSHORT(fc+loc+10)); + } + } + return NULL; +} + +static int stbtt__matchpair(stbtt_uint8 *fc, stbtt_uint32 nm, stbtt_uint8 *name, stbtt_int32 nlen, stbtt_int32 target_id, stbtt_int32 next_id) +{ + stbtt_int32 i; + stbtt_int32 count = ttUSHORT(fc+nm+2); + stbtt_int32 stringOffset = nm + ttUSHORT(fc+nm+4); + + for (i=0; i < count; ++i) { + stbtt_uint32 loc = nm + 6 + 12 * i; + stbtt_int32 id = ttUSHORT(fc+loc+6); + if (id == target_id) { + // find the encoding + stbtt_int32 platform = ttUSHORT(fc+loc+0), encoding = ttUSHORT(fc+loc+2), language = ttUSHORT(fc+loc+4); + + // is this a Unicode encoding? + if (platform == 0 || (platform == 3 && encoding == 1) || (platform == 3 && encoding == 10)) { + stbtt_int32 slen = ttUSHORT(fc+loc+8); + stbtt_int32 off = ttUSHORT(fc+loc+10); + + // check if there's a prefix match + stbtt_int32 matchlen = stbtt__CompareUTF8toUTF16_bigendian_prefix(name, nlen, fc+stringOffset+off,slen); + if (matchlen >= 0) { + // check for target_id+1 immediately following, with same encoding & language + if (i+1 < count && ttUSHORT(fc+loc+12+6) == next_id && ttUSHORT(fc+loc+12) == platform && ttUSHORT(fc+loc+12+2) == encoding && ttUSHORT(fc+loc+12+4) == language) { + slen = ttUSHORT(fc+loc+12+8); + off = ttUSHORT(fc+loc+12+10); + if (slen == 0) { + if (matchlen == nlen) + return 1; + } else if (matchlen < nlen && name[matchlen] == ' ') { + ++matchlen; + if (stbtt_CompareUTF8toUTF16_bigendian((char*) (name+matchlen), nlen-matchlen, (char*)(fc+stringOffset+off),slen)) + return 1; + } + } else { + // if nothing immediately following + if (matchlen == nlen) + return 1; + } + } + } + + // @TODO handle other encodings + } + } + return 0; +} + +static int stbtt__matches(stbtt_uint8 *fc, stbtt_uint32 offset, stbtt_uint8 *name, stbtt_int32 flags) +{ + stbtt_int32 nlen = (stbtt_int32) STBTT_strlen((char *) name); + stbtt_uint32 nm,hd; + if (!stbtt__isfont(fc+offset)) return 0; + + // check italics/bold/underline flags in macStyle... + if (flags) { + hd = stbtt__find_table(fc, offset, "head"); + if ((ttUSHORT(fc+hd+44) & 7) != (flags & 7)) return 0; + } + + nm = stbtt__find_table(fc, offset, "name"); + if (!nm) return 0; + + if (flags) { + // if we checked the macStyle flags, then just check the family and ignore the subfamily + if (stbtt__matchpair(fc, nm, name, nlen, 16, -1)) return 1; + if (stbtt__matchpair(fc, nm, name, nlen, 1, -1)) return 1; + if (stbtt__matchpair(fc, nm, name, nlen, 3, -1)) return 1; + } else { + if (stbtt__matchpair(fc, nm, name, nlen, 16, 17)) return 1; + if (stbtt__matchpair(fc, nm, name, nlen, 1, 2)) return 1; + if (stbtt__matchpair(fc, nm, name, nlen, 3, -1)) return 1; + } + + return 0; +} + +STBTT_DEF int stbtt_FindMatchingFont(const unsigned char *font_collection, const char *name_utf8, stbtt_int32 flags) +{ + stbtt_int32 i; + for (i=0;;++i) { + stbtt_int32 off = stbtt_GetFontOffsetForIndex(font_collection, i); + if (off < 0) return off; + if (stbtt__matches((stbtt_uint8 *) font_collection, off, (stbtt_uint8*) name_utf8, flags)) + return off; + } +} + +#endif // STB_TRUETYPE_IMPLEMENTATION + + +// FULL VERSION HISTORY +// +// 1.08 (2015-09-13) document stbtt_Rasterize(); fixes for vertical & horizontal edges +// 1.07 (2015-08-01) allow PackFontRanges to accept arrays of sparse codepoints; +// allow PackFontRanges to pack and render in separate phases; +// fix stbtt_GetFontOFfsetForIndex (never worked for non-0 input?); +// fixed an assert() bug in the new rasterizer +// replace assert() with STBTT_assert() in new rasterizer +// 1.06 (2015-07-14) performance improvements (~35% faster on x86 and x64 on test machine) +// also more precise AA rasterizer, except if shapes overlap +// remove need for STBTT_sort +// 1.05 (2015-04-15) fix misplaced definitions for STBTT_STATIC +// 1.04 (2015-04-15) typo in example +// 1.03 (2015-04-12) STBTT_STATIC, fix memory leak in new packing, various fixes +// 1.02 (2014-12-10) fix various warnings & compile issues w/ stb_rect_pack, C++ +// 1.01 (2014-12-08) fix subpixel position when oversampling to exactly match +// non-oversampled; STBTT_POINT_SIZE for packed case only +// 1.00 (2014-12-06) add new PackBegin etc. API, w/ support for oversampling +// 0.99 (2014-09-18) fix multiple bugs with subpixel rendering (ryg) +// 0.9 (2014-08-07) support certain mac/iOS fonts without an MS platformID +// 0.8b (2014-07-07) fix a warning +// 0.8 (2014-05-25) fix a few more warnings +// 0.7 (2013-09-25) bugfix: subpixel glyph bug fixed in 0.5 had come back +// 0.6c (2012-07-24) improve documentation +// 0.6b (2012-07-20) fix a few more warnings +// 0.6 (2012-07-17) fix warnings; added stbtt_ScaleForMappingEmToPixels, +// stbtt_GetFontBoundingBox, stbtt_IsGlyphEmpty +// 0.5 (2011-12-09) bugfixes: +// subpixel glyph renderer computed wrong bounding box +// first vertex of shape can be off-curve (FreeSans) +// 0.4b (2011-12-03) fixed an error in the font baking example +// 0.4 (2011-12-01) kerning, subpixel rendering (tor) +// bugfixes for: +// codepoint-to-glyph conversion using table fmt=12 +// codepoint-to-glyph conversion using table fmt=4 +// stbtt_GetBakedQuad with non-square texture (Zer) +// updated Hello World! sample to use kerning and subpixel +// fixed some warnings +// 0.3 (2009-06-24) cmap fmt=12, compound shapes (MM) +// userdata, malloc-from-userdata, non-zero fill (stb) +// 0.2 (2009-03-11) Fix unsigned/signed char warnings +// 0.1 (2009-03-09) First public release +// diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index 706a1894cc..f6326b6e07 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -47,19 +47,38 @@ int vidconsole_set_row(struct udevice *dev, uint row, int clr) return ops->set_row(dev, row, clr); } +static int vidconsole_entry_start(struct udevice *dev) +{ + struct vidconsole_ops *ops = vidconsole_get_ops(dev); + + if (!ops->entry_start) + return -ENOSYS; + return ops->entry_start(dev); +} + /* Move backwards one space */ -static void vidconsole_back(struct udevice *dev) +static int vidconsole_back(struct udevice *dev) { struct vidconsole_priv *priv = dev_get_uclass_priv(dev); + struct vidconsole_ops *ops = vidconsole_get_ops(dev); + int ret; - if (--priv->curr_col < 0) { - priv->curr_col = priv->cols - 1; - if (--priv->curr_row < 0) - priv->curr_row = 0; + if (ops->backspace) { + ret = ops->backspace(dev); + if (ret != -ENOSYS) + return ret; } - vidconsole_putc_xy(dev, priv->curr_col * VIDEO_FONT_WIDTH, - priv->curr_row * VIDEO_FONT_HEIGHT, ' '); + priv->xcur_frac -= VID_TO_POS(priv->x_charsize); + if (priv->xcur_frac < priv->xstart_frac) { + priv->xcur_frac = (priv->cols - 1) * + VID_TO_POS(priv->x_charsize); + priv->ycur -= priv->y_charsize; + if (priv->ycur < 0) + priv->ycur = 0; + } + + return 0; } /* Move to a newline, scrolling the display if necessary */ @@ -71,16 +90,19 @@ static void vidconsole_newline(struct udevice *dev) const int rows = CONFIG_CONSOLE_SCROLL_LINES; int i; - priv->curr_col = 0; + priv->xcur_frac = priv->xstart_frac; + priv->ycur += priv->y_charsize; /* Check if we need to scroll the terminal */ - if (++priv->curr_row >= priv->rows) { + if ((priv->ycur + priv->y_charsize) / priv->y_charsize > priv->rows) { vidconsole_move_rows(dev, 0, rows, priv->rows - rows); for (i = 0; i < rows; i++) vidconsole_set_row(dev, priv->rows - i - 1, vid_priv->colour_bg); - priv->curr_row -= rows; + priv->ycur -= rows * priv->y_charsize; } + priv->last_ch = 0; + video_sync(dev->parent); } @@ -90,21 +112,26 @@ int vidconsole_put_char(struct udevice *dev, char ch) int ret; switch (ch) { + case '\a': + /* beep */ + break; case '\r': - priv->curr_col = 0; + priv->xcur_frac = priv->xstart_frac; break; case '\n': vidconsole_newline(dev); + vidconsole_entry_start(dev); break; case '\t': /* Tab (8 chars alignment) */ - priv->curr_col += 8; - priv->curr_col &= ~7; + priv->xcur_frac = ((priv->xcur_frac / priv->tab_width_frac) + + 1) * priv->tab_width_frac; - if (priv->curr_col >= priv->cols) + if (priv->xcur_frac >= priv->xsize_frac) vidconsole_newline(dev); break; case '\b': vidconsole_back(dev); + priv->last_ch = 0; break; default: /* @@ -112,13 +139,17 @@ int vidconsole_put_char(struct udevice *dev, char ch) * colour depth. Check this and return an error to help with * diagnosis. */ - ret = vidconsole_putc_xy(dev, - priv->curr_col * VIDEO_FONT_WIDTH, - priv->curr_row * VIDEO_FONT_HEIGHT, - ch); - if (ret) + ret = vidconsole_putc_xy(dev, priv->xcur_frac, priv->ycur, ch); + if (ret == -EAGAIN) { + vidconsole_newline(dev); + ret = vidconsole_putc_xy(dev, priv->xcur_frac, + priv->ycur, ch); + } + if (ret < 0) return ret; - if (++priv->curr_col >= priv->cols) + priv->xcur_frac += ret; + priv->last_ch = ch; + if (priv->xcur_frac >= priv->xsize_frac) vidconsole_newline(dev); break; } @@ -148,8 +179,7 @@ static int vidconsole_pre_probe(struct udevice *dev) struct udevice *vid = dev->parent; struct video_priv *vid_priv = dev_get_uclass_priv(vid); - priv->rows = vid_priv->ysize / VIDEO_FONT_HEIGHT; - priv->cols = vid_priv->xsize / VIDEO_FONT_WIDTH; + priv->xsize_frac = VID_TO_POS(vid_priv->xsize); return 0; } @@ -161,12 +191,16 @@ static int vidconsole_post_probe(struct udevice *dev) struct stdio_dev *sdev = &priv->sdev; int ret; + if (!priv->tab_width_frac) + priv->tab_width_frac = VID_TO_POS(priv->x_charsize) * 8; + if (dev->seq) { snprintf(sdev->name, sizeof(sdev->name), "vidconsole%d", dev->seq); } else { strcpy(sdev->name, "vidconsole"); } + sdev->flags = DEV_FLAGS_OUTPUT; sdev->putc = vidconsole_putc; sdev->puts = vidconsole_puts; @@ -189,9 +223,11 @@ UCLASS_DRIVER(vidconsole) = { void vidconsole_position_cursor(struct udevice *dev, unsigned col, unsigned row) { struct vidconsole_priv *priv = dev_get_uclass_priv(dev); + struct udevice *vid_dev = dev->parent; + struct video_priv *vid_priv = dev_get_uclass_priv(vid_dev); - priv->curr_col = min_t(short, col, priv->cols - 1); - priv->curr_row = min_t(short, row, priv->rows - 1); + priv->xcur_frac = VID_TO_POS(min_t(short, col, vid_priv->xsize - 1)); + priv->ycur = min_t(short, row, vid_priv->ysize - 1); } static int do_video_setcursor(cmd_tbl_t *cmdtp, int flag, int argc, diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 24d537e6c4..b6dd0f5a58 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -180,6 +180,7 @@ static int video_post_probe(struct udevice *dev) struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); struct video_priv *priv = dev_get_uclass_priv(dev); char name[30], drv[15], *str; + const char *drv_name = drv; struct udevice *cons; int ret; @@ -197,20 +198,38 @@ static int video_post_probe(struct udevice *dev) video_clear(dev); /* - * Create a text console devices. For now we always do this, although + * Create a text console device. For now we always do this, although * it might be useful to support only bitmap drawing on the device - * for boards that don't need to display text. + * for boards that don't need to display text. We create a TrueType + * console if enabled, a rotated console if the video driver requests + * it, otherwise a normal console. + * + * The console can be override by setting vidconsole_drv_name before + * probing this video driver, or in the probe() method. + * + * TrueType does not support rotation at present so fall back to the + * rotated console in that case. */ - snprintf(name, sizeof(name), "%s.vidconsole", dev->name); + if (!priv->rot && IS_ENABLED(CONFIG_CONSOLE_TRUETYPE)) { + snprintf(name, sizeof(name), "%s.vidconsole_tt", dev->name); + strcpy(drv, "vidconsole_tt"); + } else { + snprintf(name, sizeof(name), "%s.vidconsole%d", dev->name, + priv->rot); + snprintf(drv, sizeof(drv), "vidconsole%d", priv->rot); + } + str = strdup(name); if (!str) return -ENOMEM; - snprintf(drv, sizeof(drv), "vidconsole%d", priv->rot); - ret = device_bind_driver(dev, drv, str, &cons); + if (priv->vidconsole_drv_name) + drv_name = priv->vidconsole_drv_name; + ret = device_bind_driver(dev, drv_name, str, &cons); if (ret) { debug("%s: Cannot bind console driver\n", __func__); return ret; } + ret = device_probe(cons); if (ret) { debug("%s: Cannot probe console driver\n", __func__); diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 66264ce3b4..37c6b438e2 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -139,16 +139,26 @@ BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_CMD_IDE #endif +#if defined(CONFIG_CMD_PCI_ENUM) || defined(CONFIG_DM_PCI) +#define BOOTENV_RUN_NET_PCI_ENUM "run boot_net_pci_enum; " +#define BOOTENV_SHARED_PCI \ + "boot_net_pci_enum=pci enum\0" +#else +#define BOOTENV_RUN_NET_PCI_ENUM +#define BOOTENV_SHARED_PCI +#endif + #ifdef CONFIG_CMD_USB -#define BOOTENV_RUN_USB_INIT "usb start; " +#define BOOTENV_RUN_NET_USB_START "run boot_net_usb_start; " #define BOOTENV_SHARED_USB \ + "boot_net_usb_start=usb start\0" \ "usb_boot=" \ - BOOTENV_RUN_USB_INIT \ + "usb start; " \ BOOTENV_SHARED_BLKDEV_BODY(usb) #define BOOTENV_DEV_USB BOOTENV_DEV_BLKDEV #define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV #else -#define BOOTENV_RUN_USB_INIT +#define BOOTENV_RUN_NET_USB_START #define BOOTENV_SHARED_USB #define BOOTENV_DEV_USB \ BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB @@ -159,7 +169,8 @@ #if defined(CONFIG_CMD_DHCP) #define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \ "bootcmd_dhcp=" \ - BOOTENV_RUN_USB_INIT \ + BOOTENV_RUN_NET_USB_START \ + BOOTENV_RUN_NET_PCI_ENUM \ "if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \ "source ${scriptaddr}; " \ "fi\0" @@ -175,7 +186,8 @@ #if defined(CONFIG_CMD_DHCP) && defined(CONFIG_CMD_PXE) #define BOOTENV_DEV_PXE(devtypeu, devtypel, instance) \ "bootcmd_pxe=" \ - BOOTENV_RUN_USB_INIT \ + BOOTENV_RUN_NET_USB_START \ + BOOTENV_RUN_NET_PCI_ENUM \ "dhcp; " \ "if pxe get; then " \ "pxe boot; " \ @@ -199,6 +211,7 @@ #define BOOTENV \ BOOTENV_SHARED_HOST \ BOOTENV_SHARED_MMC \ + BOOTENV_SHARED_PCI \ BOOTENV_SHARED_USB \ BOOTENV_SHARED_SATA \ BOOTENV_SHARED_SCSI \ diff --git a/include/config_fsl_secboot.h b/include/config_fsl_chain_trust.h index fc6788a7a6..45dda56bc3 100644 --- a/include/config_fsl_secboot.h +++ b/include/config_fsl_chain_trust.h @@ -4,15 +4,27 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_FSL_SECBOOT_H -#define __CONFIG_FSL_SECBOOT_H +#ifndef __CONFIG_FSL_CHAIN_TRUST_H +#define __CONFIG_FSL_CHAIN_TRUST_H +/* For secure boot, since ENVIRONMENT in flash/external memories is + * not verified, undef CONFIG_ENV_xxx and set default env + * (CONFIG_ENV_IS_NOWHERE) + */ #ifdef CONFIG_SECURE_BOOT -#ifndef CONFIG_CMD_ESBC_VALIDATE -#define CONFIG_CMD_ESBC_VALIDATE +#undef CONFIG_ENV_IS_IN_EEPROM +#undef CONFIG_ENV_IS_IN_NAND +#undef CONFIG_ENV_IS_IN_MMC +#undef CONFIG_ENV_IS_IN_SPI_FLASH +#undef CONFIG_ENV_IS_IN_FLASH + +#define CONFIG_ENV_IS_NOWHERE + #endif +#ifdef CONFIG_CHAIN_OF_TRUST + #ifndef CONFIG_EXTRA_ENV #define CONFIG_EXTRA_ENV "" #endif @@ -71,19 +83,8 @@ #endif /* CONFIG_RAMBOOT_NAND */ #endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ -#if defined(CONFIG_RAMBOOT_SPIFLASH) -#undef CONFIG_ENV_IS_IN_SPI_FLASH -#elif defined(CONFIG_RAMBOOT_NAND) -#undef CONFIG_ENV_IS_IN_NAND -#elif defined(CONFIG_RAMBOOT_SDCARD) -#undef CONFIG_ENV_IS_IN_MMC -#endif -#else /*CONFIG_SYS_RAMBOOT*/ -#undef CONFIG_ENV_IS_IN_FLASH #endif -#define CONFIG_ENV_IS_NOWHERE - #ifndef CONFIG_BS_COPY_ENV #define CONFIG_BS_COPY_ENV #endif @@ -92,25 +93,9 @@ #define CONFIG_BS_COPY_CMD #endif -#define CONFIG_SECBOOT_CMD CONFIG_BS_COPY_ENV \ +#define CONFIG_CHAIN_BOOT_CMD CONFIG_BS_COPY_ENV \ CONFIG_BS_COPY_CMD \ CONFIG_SECBOOT -/* - * We don't want boot delay for secure boot flow - * before autoboot starts - */ -#undef CONFIG_BOOTDELAY -#define CONFIG_BOOTDELAY 0 -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND CONFIG_SECBOOT_CMD - -/* - * CONFIG_ZERO_BOOTDELAY_CHECK should not be defined for - * secure boot flow as defining this would enable a user to - * reach uboot prompt by pressing some key before start of - * autoboot - */ -#undef CONFIG_ZERO_BOOTDELAY_CHECK #endif #endif diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 9fb5cee711..bcbae5099a 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -924,8 +924,4 @@ unsigned long get_board_ddr_clk(void); #include <asm/fsl_secure_boot.h> -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index d0e5a2565a..89907dce4b 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -722,8 +722,4 @@ combinations. this should be removed later #include <asm/fsl_secure_boot.h> -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f9776c0333..3c0faca134 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -952,8 +952,4 @@ extern unsigned long get_sdram_size(void); #include <asm/fsl_secure_boot.h> -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index b2e51b5b2f..f250e7f88e 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -756,8 +756,4 @@ unsigned long get_board_sys_clk(unsigned long dummy); #include <asm/fsl_secure_boot.h> -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 951cbc4f57..e5df784ece 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -39,6 +39,8 @@ #define CONFIG_BOARD_EARLY_INIT_F #endif +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg @@ -936,8 +938,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT -#include <asm/fsl_secure_boot.h> +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL #endif +#include <asm/fsl_secure_boot.h> + #endif /* __T1024QDS_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 4a0f5b2524..3cda3b1afd 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -33,6 +33,8 @@ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + /* support deep sleep */ #ifdef CONFIG_PPC_T1024 #define CONFIG_DEEP_SLEEP @@ -948,8 +950,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT -#include <asm/fsl_secure_boot.h> +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL #endif +#include <asm/fsl_secure_boot.h> + #endif /* __T1024RDB_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 9e151da16a..2e7892f94a 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -835,9 +835,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include <asm/fsl_secure_boot.h> -#define CONFIG_CMD_BLOB -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index da65f567ea..5fc34976d7 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -938,9 +938,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include <asm/fsl_secure_boot.h> -#define CONFIG_CMD_BLOB -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index a0cecc60cd..a56208c6a6 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -933,10 +933,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include <asm/fsl_secure_boot.h> -#define CONFIG_CMD_BLOB -#undef CONFIG_CMD_USB -#endif #endif /* __T208xQDS_H */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 312b0eb91f..b5290a1a16 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -889,10 +889,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include <asm/fsl_secure_boot.h> -#define CONFIG_CMD_BLOB -#undef CONFIG_CMD_USB -#endif #endif /* __T2080RDB_H */ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 1b94f6436c..91857d6997 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -644,8 +644,4 @@ unsigned long get_board_ddr_clk(void); #include <asm/fsl_secure_boot.h> -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 4a17f41eb3..c1a0a6ced9 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -847,13 +847,4 @@ unsigned long get_board_ddr_clk(void); #include <asm/fsl_secure_boot.h> -#ifdef CONFIG_SECURE_BOOT -/* Secure Boot target was not getting build for T4240 because of - * increased binary size. So the size is being reduced by removing USB - * which is anyways not used in Secure Environment. - */ -#undef CONFIG_CMD_USB -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 4ed8e00e05..3cc2874dcb 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -13,6 +13,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* * High Level Configuration Options */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 23457d6931..4547d7f4aa 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -13,6 +13,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* * High Level Configuration Options */ diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 9db4a4ff27..d692106315 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -12,6 +12,8 @@ #include <asm/hardware.h> +#define CONFIG_SYS_CACHELINE_SIZE 32 + #define CONFIG_SYS_TEXT_BASE 0x26f00000 /* ARM asynchronous clock */ diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h index 305864f8b8..1d4869bc5f 100644 --- a/include/configs/bcm_ep_board.h +++ b/include/configs/bcm_ep_board.h @@ -11,6 +11,7 @@ #define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_CACHELINE_SIZE 64 /* * Memory configuration diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 2dc745e59f..24ae14df30 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -17,6 +17,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* * High Level Configuration Options */ diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index 0aefec8a00..7a07de439c 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -10,6 +10,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* * High Level Configuration Options */ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 5aed3a5fcd..dd44462a9f 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -12,6 +12,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_CACHELINE_SIZE 32 + #include <asm/arch/imx-regs.h> #define CONFIG_VF610 diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index aef37dd670..a099eee047 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -765,8 +765,4 @@ #include <asm/fsl_secure_boot.h> -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/fx12mm.h b/include/configs/fx12mm.h deleted file mode 100644 index fa32a2e8cf..0000000000 --- a/include/configs/fx12mm.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2008 - * - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com - * - * Georg Schardt <schardt@team-ctech.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Configuration file for the Virtex4FX12 Minimodul by Avnet/Memec, - * see http://www.em.avnet.com - */ - -#ifndef __CONFIG_FX12_H -#define __CONFIG_FX12_H - -#include "../board/avnet/fx12mm/xparameters.h" - -/* cmd config */ -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD - -/* sdram */ -#define CONFIG_SYS_SDRAM_SIZE_MB 64 - -/* environment */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_SYS_ENV_OFFSET 0xA0000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET) -#define CONFIG_ENV_OVERWRITE 1 - -/*Misc*/ -#define CONFIG_PREBOOT "echo U-Boot is up and running;" - -/*Flash*/ -#define CONFIG_SYS_FLASH_SIZE (4*1024*1024) -#define CONFIG_SYS_MAX_FLASH_SECT 71 -#define MTDIDS_DEFAULT "nor0=fx12mm-flash" -#define MTDPARTS_DEFAULT "mtdparts=fx12mm-flash:-(user)" - -#include "configs/xilinx-ppc405.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 94b0f038f2..d5cbb33661 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -10,6 +10,8 @@ #undef DEBUG +#define CONFIG_SYS_CACHELINE_SIZE 32 + #define CONFIG_SH73A0 #define CONFIG_KZM_A9_GT #define CONFIG_RMOBILE_BOARD_STRING "KMC KZM-A9-GT" diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index e8b1ecaeb1..f6efc55059 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -659,12 +659,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MISC_INIT_R /* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM #define CONFIG_CMD_HASH #define CONFIG_SHA_HW_ACCEL +#endif -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB #include <asm/fsl_secure_boot.h> -#endif +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 317ba62d3d..ae58646d5e 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -517,12 +517,12 @@ #define CONFIG_MISC_INIT_R /* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM #define CONFIG_CMD_HASH #define CONFIG_SHA_HW_ACCEL +#endif -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB #include <asm/fsl_secure_boot.h> -#endif +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 677d28113c..6150bc1a74 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -121,6 +121,7 @@ #endif /* IFC */ +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_FSL_IFC /* * CONFIG_SYS_FLASH_BASE has the final address (core view) @@ -139,6 +140,7 @@ #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ #endif +#endif /* I2C */ #define CONFIG_CMD_I2C @@ -197,14 +199,39 @@ #define CONFIG_DOS_PARTITION #endif +/* DSPI */ +#define CONFIG_FSL_DSPI +#ifdef CONFIG_FSL_DSPI +#define CONFIG_CMD_SF +#define CONFIG_DM_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO /* cs0 */ +#define CONFIG_SPI_FLASH_SST /* cs1 */ +#define CONFIG_SPI_FLASH_EON /* cs2 */ +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_CS 0 +#endif +#endif + +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + /* FMan ucode */ #define CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 1000000 +#define CONFIG_ENV_SPI_MODE 0x03 +#else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR /* FMan fireware Pre-load address */ #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 +#endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif @@ -252,4 +279,10 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #endif /* __LS1043A_COMMON_H */ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 398f1c3f77..4ab8e13ba1 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -10,10 +10,16 @@ #include "ls1043a_common.h" #define CONFIG_DISPLAY_CPUINFO +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_DISPLAY_BOARDINFO_LATE +#else #define CONFIG_DISPLAY_BOARDINFO +#endif #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) #define CONFIG_SYS_TEXT_BASE 0x82000000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x40010000 #else #define CONFIG_SYS_TEXT_BASE 0x60100000 #endif @@ -33,7 +39,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 @@ -85,8 +91,18 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_SD_BOOT +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg +#else #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg #endif +#endif + +/* LPUART */ +#ifdef CONFIG_LPUART +#define CONFIG_LPUART_32B_REG +#endif /* SATA */ #define CONFIG_LIBATA @@ -108,6 +124,7 @@ unsigned long get_board_ddr_clk(void); /* * IFC Definitions */ +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ @@ -191,6 +208,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#endif #ifdef CONFIG_NAND_BOOT #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ @@ -198,6 +216,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) #endif +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS +#endif + /* * QIXIS Definitions */ @@ -212,7 +236,14 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_SHIFT 0 #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x44 +#define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_SD_QSPI 0xff +#define QIXIS_LBMAP_QSPI 0xff +#define QIXIS_RCW_SRC_NAND 0x106 +#define QIXIS_RCW_SRC_SD 0x040 +#define QIXIS_RCW_SRC_QSPI 0x045 +#define QIXIS_RST_CTL_RESET 0x41 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 @@ -338,6 +369,16 @@ unsigned long get_board_ddr_clk(void); #define VDD_MV_MIN 819 #define VDD_MV_MAX 1212 +/* QSPI device */ +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_FSL_QSPI +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SPI_FLASH_SPANSION +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 +#endif +#endif + /* * Miscellaneous configurable options */ @@ -388,6 +429,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) @@ -401,4 +447,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_MII #define CONFIG_CMDLINE_TAG +#include <asm/fsl_secure_boot.h> + #endif /* __LS1043AQDS_H__ */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 585114f3d5..506f50d895 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -222,16 +222,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -/* DSPI */ -#define CONFIG_FSL_DSPI -#ifdef CONFIG_FSL_DSPI -#define CONFIG_CMD_SF -#define CONFIG_DM_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SF_DEFAULT_BUS 1 -#define CONFIG_SF_DEFAULT_CS 0 -#endif - /* * Environment */ @@ -291,14 +281,6 @@ #define CONFIG_CMD_EXT2 #endif -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#define CONFIG_CMD_BLOB -/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ -#define CONFIG_ESBC_ADDR_64BIT -#endif - #include <asm/fsl_secure_boot.h> #endif /* __LS1043ARDB_H__ */ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 4ae7d11685..def0a6f3f0 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -15,9 +15,6 @@ #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 -/* Errata fixes */ -#define CONFIG_ARM_ERRATA_828024 -#define CONFIG_ARM_ERRATA_826974 #include <asm/arch/ls2080a_stream_id.h> #include <asm/arch/config.h> @@ -196,7 +193,7 @@ unsigned long long get_qixis_addr(void); */ #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER) #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024) -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) #define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) #endif diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index ba84248081..a402c06a3b 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -346,7 +346,7 @@ unsigned long get_board_ddr_clk(void); "initrd_high=0xffffffffffffffff\0" \ "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ - "kernel_size=0x28000000\0" + "kernel_size=0x2800000\0" #ifdef CONFIG_FSL_MC_ENET #define CONFIG_FSL_MEMAC diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index f93861d770..97a0d86b91 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -32,54 +32,20 @@ #endif /* uart */ -#ifdef XILINX_UARTLITE_BASEADDR -# define CONFIG_XILINX_UARTLITE -# define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR -# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE -# define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } -# define CONSOLE_ARG "console=console=ttyUL0,115200\0" -#elif XILINX_UART16550_BASEADDR -# define CONFIG_SYS_NS16550_SERIAL -# if defined(__MICROBLAZEEL__) -# define CONFIG_SYS_NS16550_REG_SIZE -4 -# else -# define CONFIG_SYS_NS16550_REG_SIZE 4 -# endif -# define CONFIG_CONS_INDEX 1 -# define CONFIG_SYS_NS16550_COM1 \ - ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000) -# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ # define CONFIG_BAUDRATE 115200 - /* The following table includes the supported baudrates */ # define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -# define CONSOLE_ARG "console=console=ttyS0,115200\0" -#else -# error Undefined uart -#endif /* setting reset address */ /*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ -/* ethernet */ -#undef CONFIG_SYS_ENET -#if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL) -# define CONFIG_XILINX_EMACLITE 1 -# define CONFIG_SYS_ENET -#endif -#if defined(XILINX_AXIEMAC_BASEADDR) -# define CONFIG_XILINX_AXIEMAC 1 -# define CONFIG_SYS_ENET -#endif - -#undef ET_DEBUG - /* gpio */ #ifdef XILINX_GPIO_BASEADDR # define CONFIG_XILINX_GPIO # define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR #endif +#define CONFIG_BOARD_LATE_INIT /* interrupt controller */ #ifdef XILINX_INTC_BASEADDR @@ -103,13 +69,6 @@ # endif #endif -#if !defined(CONFIG_OF_CONTROL) || \ - (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL)) -/* ddr sdram - main memory */ -# define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START -# define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE -#endif - #define CONFIG_SYS_MALLOC_LEN 0xC0000 /* Stack location before relocation */ @@ -198,16 +157,6 @@ #endif /* !SPIFLASH */ #endif /* !FLASH */ -/* system ace */ -#ifdef XILINX_SYSACE_BASEADDR -# define CONFIG_SYSTEMACE -/* #define DEBUG_SYSTEMACE */ -# define SYSTEMACE_CONFIG_FPGA -# define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR -# define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH -# define CONFIG_DOS_PARTITION -#endif - #if defined(XILINX_USE_ICACHE) # define CONFIG_ICACHE #else @@ -245,17 +194,6 @@ # undef CONFIG_CMD_CACHE #endif -#ifdef CONFIG_SYS_ENET -# define CONFIG_CMD_PING -# define CONFIG_CMD_DHCP -# define CONFIG_CMD_TFTPPUT -#endif - -#if defined(CONFIG_SYSTEMACE) -# define CONFIG_CMD_EXT2 -# define CONFIG_CMD_FAT -#endif - #if defined(FLASH) # define CONFIG_CMD_JFFS2 # define CONFIG_CMD_UBI @@ -315,7 +253,7 @@ #define CONFIG_SYS_MAXARGS 15 #define CONFIG_SYS_LONGHELP /* default load address */ -#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START +#define CONFIG_SYS_LOAD_ADDR 0 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ #define CONFIG_BOOTARGS "root=romfs" @@ -342,15 +280,10 @@ #define CONFIG_CMDLINE_EDITING -#define CONFIG_NETCONSOLE #define CONFIG_SYS_CONSOLE_IS_IN_ENV -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - /* Enable flat device tree support */ #define CONFIG_LMB 1 -#define CONFIG_FIT 1 #define CONFIG_OF_LIBFDT 1 #if defined(CONFIG_XILINX_AXIEMAC) @@ -358,20 +291,19 @@ # define CONFIG_CMD_MII 1 # define CONFIG_PHY_GIGE 1 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 -# define CONFIG_PHYLIB 1 # define CONFIG_PHY_ATHEROS 1 # define CONFIG_PHY_BROADCOM 1 # define CONFIG_PHY_DAVICOM 1 # define CONFIG_PHY_LXT 1 # define CONFIG_PHY_MARVELL 1 # define CONFIG_PHY_MICREL 1 +# define CONFIG_PHY_MICREL_KSZ9021 # define CONFIG_PHY_NATSEMI 1 # define CONFIG_PHY_REALTEK 1 # define CONFIG_PHY_VITESSE 1 #else # undef CONFIG_MII # undef CONFIG_CMD_MII -# undef CONFIG_PHYLIB #endif /* SPL part */ diff --git a/include/configs/ml507.h b/include/configs/ml507.h deleted file mode 100644 index 89a72904b3..0000000000 --- a/include/configs/ml507.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*CPU*/ -#define CONFIG_440 1 -#define CONFIG_XILINX_ML507 1 -#include "../board/xilinx/ml507/xparameters.h" - -/*Mem Map*/ -#define CONFIG_SYS_SDRAM_SIZE_MB 256 - -/*Env*/ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0x340000 -#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET) - -/*Misc*/ -#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" - -/*Flash*/ -#define CONFIG_SYS_FLASH_SIZE (32*1024*1024) -#define CONFIG_SYS_MAX_FLASH_SECT 259 -#define MTDIDS_DEFAULT "nor0=ml507-flash" -#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)" - -/*Generic Configs*/ -#include <configs/xilinx-ppc440.h> - -#endif /* __CONFIG_H */ diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index b11e43a0a9..5c4140526d 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -19,6 +19,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* * High Level Configuration Options */ diff --git a/include/configs/novena.h b/include/configs/novena.h index 5f0a2302de..d5f517c76d 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -110,11 +110,12 @@ #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_SPD_BUS_NUM 0 /* I2C EEPROM */ #ifdef CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_SPD_BUS_NUM 2 +#define CONFIG_SYS_I2C_EEPROM_BUS 2 #endif /* MMC Configs */ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 891bdb0ecf..2628dfa636 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -9,6 +9,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_CACHELINE_SIZE 32 + #include <asm/arch/imx-regs.h> #define CONFIG_VF610 diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h new file mode 100644 index 0000000000..3ea11946b8 --- /dev/null +++ b/include/configs/pic32mzdask.h @@ -0,0 +1,168 @@ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Microchip PIC32MZ[DA] Starter Kit. + */ + +#ifndef __PIC32MZDASK_CONFIG_H +#define __PIC32MZDASK_CONFIG_H + +/* System Configuration */ +#define CONFIG_SYS_TEXT_BASE 0x9d004000 /* .text */ +#define CONFIG_DISPLAY_BOARDINFO + +/*-------------------------------------------- + * CPU configuration + */ +/* CPU Timer rate */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 100000000 + +/* Cache Configuration */ +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT + +/*---------------------------------------------------------------------- + * Memory Layout + */ +#define CONFIG_SYS_SRAM_BASE 0x80000000 +#define CONFIG_SYS_SRAM_SIZE 0x00080000 /* 512K */ + +/* Initial RAM for temporary stack, global data */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_RAM_ADDR \ + (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) + +/* SDRAM Configuration (for final code, data, stack, heap) */ +#define CONFIG_SYS_SDRAM_BASE 0x88000000 +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_BOOTPARAMS_LEN (4 << 10) +#define CONFIG_STACKSIZE (4 << 10) /* regular stack */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (192 << 10) + +#define CONFIG_SYS_LOAD_ADDR 0x88500000 /* default load address */ +#define CONFIG_SYS_ENV_ADDR 0x88300000 +#define CONFIG_SYS_FDT_ADDR 0x89d00000 + +/* Memory Test */ +#define CONFIG_SYS_MEMTEST_START 0x88000000 +#define CONFIG_SYS_MEMTEST_END 0x88080000 + +/*---------------------------------------------------------------------- + * Commands + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMD_CLK + +/*------------------------------------------------- + * FLASH configuration + */ +#define CONFIG_SYS_NO_FLASH + +/*------------------------------------------------------------ + * Console Configuration + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Networking Configuration + */ +#define CONFIG_MII +#define CONFIG_PHY_SMSC +#define CONFIG_SYS_RX_ETH_BUFFER 8 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_ARP_TIMEOUT 500 /* millisec */ + +#define CONFIG_CMD_MII + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Handover flattened device tree (dtb file) to Linux kernel + */ +#define CONFIG_OF_LIBFDT 1 + +/*----------------------------------------------------------------------- + * SDHC Configuration + */ +#define CONFIG_SDHCI +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC + +/*----------------------------------------------------------------------- + * File System Configuration + */ +/* FAT FS */ +#define CONFIG_DOS_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_SUPPORT_VFAT +#define CONFIG_FS_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_PART +#define CONFIG_CMD_FAT + +/* EXT4 FS */ +#define CONFIG_FS_EXT4 +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE + +/* ------------------------------------------------- + * Environment + */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x4000 + +/* --------------------------------------------------------------------- + * Board boot configuration + */ +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_BOOTDELAY 5 + +#define MEM_LAYOUT_ENV_SETTINGS \ + "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ + "fdt_addr_r="__stringify(CONFIG_SYS_FDT_ADDR)"\0" \ + "scriptaddr="__stringify(CONFIG_SYS_ENV_ADDR)"\0" + +#define CONFIG_LEGACY_BOOTCMD_ENV \ + "legacy_bootcmd= " \ + "if load mmc 0 ${scriptaddr} uEnv.txt; then " \ + "env import -tr ${scriptaddr} ${filesize}; " \ + "if test -n \"${bootcmd_uenv}\" ; then " \ + "echo Running bootcmd_uenv ...; " \ + "run bootcmd_uenv; " \ + "fi; " \ + "fi; \0" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + CONFIG_LEGACY_BOOTCMD_ENV \ + BOOTENV + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "run distro_bootcmd || run legacy_bootcmd" + +#endif /* __PIC32MZDASK_CONFIG_H */ diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index f0a3a187d7..f750b5305d 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -9,6 +9,8 @@ #ifndef __RCAR_GEN2_COMMON_H #define __RCAR_GEN2_COMMON_H +#define CONFIG_SYS_CACHELINE_SIZE 64 + #include <asm/arch/rmobile.h> #define CONFIG_CMD_DFL diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index d22ea74136..368d0462fe 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_RK3036_COMMON_H #define __CONFIG_RK3036_COMMON_H +#define CONFIG_SYS_CACHELINE_SIZE 32 + #include <asm/arch/hardware.h> #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index ebf1ab09b3..427ac4bcff 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -7,6 +7,8 @@ #ifndef __CONFIG_RK3288_COMMON_H #define __CONFIG_RK3288_COMMON_H +#define CONFIG_SYS_CACHELINE_SIZE 64 + #include <asm/arch/hardware.h> #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 8f65d7ed7a..f92c23db51 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -17,6 +17,8 @@ #define CONFIG_S5PC110 1 /* which is in a S5PC110 */ #define CONFIG_MACH_GONI 1 /* working with Goni */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + #include <linux/sizes.h> #include <asm/arch/cpu.h> /* get chip and board defs */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index c36e444a6c..db79e54b5b 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -12,6 +12,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* * High Level Configuration Options * (easy to change) diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index e7b56754cf..f260a6402d 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -56,7 +56,7 @@ "netdev=eth0\0" \ "hostname=mcvevk\0" \ "kernel_addr_r=0x10000000\0" \ - "update_filename=u-boot-with-spl-dtb.sfp\0" \ + "update_filename=u-boot-with-spl.sfp\0" \ "update_sd_offset=0x800\0" \ "update_sd=" /* Update the SD firmware partition */ \ "if mmc rescan ; then " \ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index c1bd179005..d5aba70aaa 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -13,6 +13,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* * High Level Configuration Options */ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h new file mode 100644 index 0000000000..cd9d6b693b --- /dev/null +++ b/include/configs/theadorable.h @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_THEADORABLE_H +#define _CONFIG_THEADORABLE_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ +#define CONFIG_SYS_TEXT_BASE 0x00800000 +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* + * Commands configuration + */ +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_ENV +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_I2C +#define CONFIG_CMD_SATA +#define CONFIG_CMD_TIME + +/* + * The debugging version enables USB support via defconfig. + * This version should also enable all other non-production + * interfaces / features. + */ +#ifdef CONFIG_USB +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SPI +#define CONFIG_CMD_TFTPPUT +#endif + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 + +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ + +/* SPI NOR flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */ +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ +#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PREBOOT +#define CONFIG_FIT + +#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Keep device tree and initrd in lower memory so the kernel can access them */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +/* SATA support */ +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_SATA_MV +#define CONFIG_LIBATA +#define CONFIG_LBA48 +#define CONFIG_EFI_PARTITION +#define CONFIG_DOS_PARTITION + +/* Additional FS support/configuration */ +#define CONFIG_SUPPORT_VFAT + +/* PCIe support */ +#ifdef CONFIG_CMD_PCI +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI +#define CONFIG_PCI_MVEBU +#define CONFIG_PCI_PNP +#endif +#endif + +/* Enable LCD and reserve 512KB from top of memory*/ +#define CONFIG_SYS_MEM_TOP_HIDE 0x80000 + +#define CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_CMD_BMP + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * Memory layout while starting into the bin_hdr via the + * BootROM: + * + * 0x4000.4000 - 0x4003.4000 headers space (192KiB) + * 0x4000.4030 bin_hdr start address + * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) + * 0x4007.fffc BootROM stack top + * + * The address space between 0x4007.fffc and 0x400f.fff is not locked in + * L2 cache thus cannot be used. + */ + +/* SPL */ +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40004030 +#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT + +/* SPL related SPI defines */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000 +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS + +/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ +#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ + +#endif /* _CONFIG_THEADORABLE_H */ diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index e726040b70..3d0498df05 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -16,6 +16,8 @@ #ifndef __CONFIG_TI814X_EVM_H #define __CONFIG_TI814X_EVM_H +#define CONFIG_SYS_CACHELINE_SIZE 64 + #define CONFIG_TI81XX #define CONFIG_TI814X #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index ba652cabab..533fae7d82 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -10,6 +10,8 @@ #ifndef __CONFIG_TI816X_EVM_H #define __CONFIG_TI816X_EVM_H +#define CONFIG_SYS_CACHELINE_SIZE 64 + #define CONFIG_TI81XX #define CONFIG_TI816X #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 02fdcdca8f..6a4868c377 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -14,6 +14,11 @@ #ifndef __CONFIG_TI_OMAP3_COMMON_H__ #define __CONFIG_TI_OMAP3_COMMON_H__ +/* + * High Level Configuration Options + */ + +#define CONFIG_SYS_CACHELINE_SIZE 64 #include <asm/arch/cpu.h> #include <asm/arch/omap.h> diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index f5f53249e2..2ec2f015c1 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -16,6 +16,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* High Level Configuration Options */ #define CONFIG_SYS_THUMB_BUILD #define CONFIG_OMAP /* in a TI OMAP core */ diff --git a/include/configs/v5fx30teval.h b/include/configs/v5fx30teval.h deleted file mode 100644 index 298fa3e6d0..0000000000 --- a/include/configs/v5fx30teval.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*CPU*/ -#define CONFIG_440 1 -#define CONFIG_XILINX_ML507 1 -#include "../board/avnet/v5fx30teval/xparameters.h" - -/*Mem Map*/ -#define CONFIG_SYS_SDRAM_SIZE_MB 64 - -/*Env*/ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0x1A0000 -#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET) - -/*Misc*/ -#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" - -/*Flash*/ -#define CONFIG_SYS_FLASH_SIZE (16*1024*1024) -#define CONFIG_SYS_MAX_FLASH_SECT 131 -#define MTDIDS_DEFAULT "nor0=v5fx30t-flash" -#define MTDPARTS_DEFAULT "mtdparts=v5fx30t-flash:-(user)" - -/*Generic Configs*/ -#include <configs/xilinx-ppc440.h> - -#endif /* __CONFIG_H */ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index cec510c1f1..d78ca0bc5c 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -118,6 +118,8 @@ #define CONFIG_SYS_MEMTEST_START V2M_BASE #define CONFIG_SYS_MEMTEST_END 0x20000000 +#define CONFIG_SYS_CACHELINE_SIZE 64 + #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_SYS_L2CACHE_OFF 1 diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index dcfafaf631..d100f7349e 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -9,6 +9,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_CACHELINE_SIZE 32 + #include <asm/arch/imx-regs.h> #define CONFIG_VF610 diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 4182a3bf63..dc7b227d25 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -100,6 +100,7 @@ * Command line configuration. */ #define CONFIG_CMD_DATE +#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMD_IO #define CONFIG_CMD_IRQ diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h index eb400d0960..d01d88b33f 100644 --- a/include/configs/xilinx-ppc.h +++ b/include/configs/xilinx-ppc.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * (C) Copyright 2008 @@ -101,22 +101,10 @@ #define CONFIG_SYS_NO_FLASH #endif -/* serial communication */ -#ifdef XPAR_UARTLITE_0_BASEADDR -#define CONFIG_XILINX_UARTLITE -#define XILINX_UARTLITE_BASEADDR XPAR_UARTLITE_0_BASEADDR -#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE -#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } -#else -#ifdef XPAR_UARTNS550_0_BASEADDR -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 4 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 XPAR_UARTNS550_0_BASEADDR -#define CONFIG_SYS_NS16550_CLK XPAR_UARTNS550_0_CLOCK_FREQ_HZ +#define CONFIG_OF_LIBFDT 1 #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 115200 } -#endif -#endif +/* The following table includes the supported baudrates */ +# define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} #endif /* __CONFIG_H */ diff --git a/include/configs/xilinx-ppc405-generic.h b/include/configs/xilinx-ppc405-generic.h index 40fa0878a4..6182b0e7cf 100644 --- a/include/configs/xilinx-ppc405-generic.h +++ b/include/configs/xilinx-ppc405-generic.h @@ -1,7 +1,7 @@ /* * * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * (C) Copyright 2008 @@ -14,6 +14,9 @@ #include "../board/xilinx/ppc405-generic/xparameters.h" +#define CONFIG_405 1 +#define CONFIG_XILINX_405 1 + /* sdram */ #define CONFIG_SYS_SDRAM_SIZE_MB 256 @@ -26,16 +29,16 @@ #define CONFIG_ENV_OVERWRITE 1 /*Misc*/ -#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" +#define CONFIG_PREBOOT "echo U-Boot is up and running;" /*Flash*/ -#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR -#define CONFIG_SYS_FLASH_SIZE (32*1024*1024) -#define CONFIG_SYS_MAX_FLASH_SECT 71 +#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR +#define CONFIG_SYS_FLASH_SIZE (128*1024*1024) +#define CONFIG_SYS_MAX_FLASH_SECT 1024 #define CONFIG_SYS_FLASH_CFI 1 #define CONFIG_FLASH_CFI_DRIVER 1 -#define MTDIDS_DEFAULT "nor0=ppc405-flash" -#define MTDPARTS_DEFAULT "mtdpartsa=ppc405-flash:-(user)" +#define MTDIDS_DEFAULT "nor0=flash" +#define MTDPARTS_DEFAULT "mtdparts=flash:-(user)" -#include <configs/xilinx-ppc405.h> +#include <configs/xilinx-ppc.h> #endif /* __CONFIG_H */ diff --git a/include/configs/xilinx-ppc405.h b/include/configs/xilinx-ppc405.h deleted file mode 100644 index a0151fe8f4..0000000000 --- a/include/configs/xilinx-ppc405.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * - * (C) Copyright 2008 - * Georg Schardt <schardt@team-ctech.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* cpu parameter */ -#define CONFIG_405 1 -#define CONFIG_XILINX_405 1 - -#include <configs/xilinx-ppc.h> - -#endif diff --git a/include/configs/xilinx-ppc440-generic.h b/include/configs/xilinx-ppc440-generic.h index 95b8834078..f2505a6cd2 100644 --- a/include/configs/xilinx-ppc440-generic.h +++ b/include/configs/xilinx-ppc440-generic.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,31 +8,42 @@ #ifndef __CONFIG_H #define __CONFIG_H -/*CPU*/ +/* CPU */ #define CONFIG_440 1 +#define CONFIG_XILINX_440 1 #define CONFIG_XILINX_PPC440_GENERIC 1 #include "../board/xilinx/ppc440-generic/xparameters.h" -/*Mem Map*/ +/* Mem Map */ #define CONFIG_SYS_SDRAM_SIZE_MB 256 -/*Env*/ +/* Env */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0x340000 +#define CONFIG_ENV_OFFSET 0x340000 #define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET) -/*Misc*/ -#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" - -/*Flash*/ -#define CONFIG_SYS_FLASH_SIZE (32*1024*1024) -#define CONFIG_SYS_MAX_FLASH_SECT 259 -#define MTDIDS_DEFAULT "nor0=ml507-flash" -#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)" - -/*Generic Configs*/ -#include <configs/xilinx-ppc440.h> +/* Misc */ +#define CONFIG_PREBOOT "echo U-Boot is up and running;" + +/* Flash */ +#define CONFIG_SYS_FLASH_SIZE (128*1024*1024) +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define MTDIDS_DEFAULT "nor0=flash" +#define MTDPARTS_DEFAULT "mtdparts=flash:-(user)" + +/* Net */ +#ifdef XPAR_LLTEMAC_0_BASEADDR +#define CONFIG_XILINX_LL_TEMAC +#define CONFIG_MII +#define CONFIG_PHYLIB +#define CONFIG_PHY_MARVELL +#define CONFIG_NET_RANDOM_ETHADDR +#define CONFIG_LIB_RAND +#endif + +/* Generic Configs */ +#include <configs/xilinx-ppc.h> #endif /* __CONFIG_H */ diff --git a/include/configs/xilinx-ppc440.h b/include/configs/xilinx-ppc440.h deleted file mode 100644 index f45700878e..0000000000 --- a/include/configs/xilinx-ppc440.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef __CONFIG_GEN_H -#define __CONFIG_GEN_H - -/*CPU*/ -#define CONFIG_440 1 -#define CONFIG_XILINX_440 1 - -#include <configs/xilinx-ppc.h> - -#endif /* __CONFIG_H */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 03f74508ef..27ef74daf5 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -23,10 +23,8 @@ #define GICD_BASE 0xF9010000 #define GICC_BASE 0xF9020000 -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE @@ -37,7 +35,9 @@ /* Cache Definitions */ #define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_IDENT_STRING " Xilinx ZynqMP" +#if !defined(CONFIG_IDENT_STRING) +# define CONFIG_IDENT_STRING " Xilinx ZynqMP" +#endif #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) @@ -45,7 +45,9 @@ #define CONFIG_OF_LIBFDT /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ -#define COUNTER_FREQUENCY 4000000 +#if !defined(COUNTER_FREQUENCY) +# define COUNTER_FREQUENCY 100000000 +#endif /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x2000000) @@ -137,9 +139,9 @@ #define CONFIG_THOR_RESET_OFF #define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ - "set dfu_alt_info " \ - "Image ram 0x200000 0x1800000\\\\;" \ - "system.dtb ram 0x7000000 0x40000\0" \ + "setenv dfu_alt_info " \ + "Image ram $kernel_addr $kernel_size\\\\;" \ + "system.dtb ram $fdt_addr $fdt_size\0" \ "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" @@ -156,12 +158,14 @@ "kernel_addr=0x80000\0" \ "fdt_addr=0x7000000\0" \ "fdt_high=0x10000000\0" \ - "sdboot=mmcinfo && load mmc 0:0 $fdt_addr system.dtb && " \ - "load mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0" \ + "kernel_size=0x2000000\0" \ + "fdt_size=0x80000\0" \ + "sdbootdev=0\0"\ + "sdboot=mmc dev $sdbootdev && mmcinfo && load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \ + "load mmc $sdbootdev:$partid $kernel_addr Image && " \ + "booti $kernel_addr - $fdt_addr\0" \ DFU_ALT_INFO -#define CONFIG_BOOTARGS "setenv bootargs console=ttyPS0,${baudrate} " \ - "earlycon=cdns,mmio,0xff000000,${baudrate}n8" #define CONFIG_PREBOOT "run bootargs" #define CONFIG_BOOTCOMMAND "run $modeboot" #define CONFIG_BOOTDELAY 5 @@ -189,7 +193,10 @@ # define CONFIG_MII # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_PHY_MARVELL +# define CONFIG_PHY_NATSEMI # define CONFIG_PHY_TI +# define CONFIG_PHY_GIGE +# define PHY_ANEG_TIMEOUT 20000 #endif /* I2C */ diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index ec39211af3..9906c426f5 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -1,7 +1,5 @@ /* - * Configuration for Xilinx ZynqMP emulation - * platforms. See zynqmp-common.h for ZynqMP - * common configs + * Configuration for Xilinx ZynqMP emulation platforms * * (C) Copyright 2014 - 2015 Xilinx, Inc. * Michal Simek <michal.simek@xilinx.com> @@ -17,6 +15,7 @@ #define CONFIG_ZYNQ_SDHCI0 #define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 +#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9) #define CONFIG_ZYNQ_I2C0 #define CONFIG_SYS_I2C_ZYNQ #define CONFIG_ZYNQ_EEPROM @@ -24,6 +23,13 @@ #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ ZYNQMP_USB1_XHCI_BASEADDR} +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 + +#define COUNTER_FREQUENCY 4000000 + #include <configs/xilinx_zynqmp.h> #endif /* __CONFIG_ZYNQMP_EP_H */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 0ab60839b6..e8c3ef0c38 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -66,7 +66,6 @@ #ifdef CONFIG_ZYNQ_QSPI # define CONFIG_SF_DEFAULT_SPEED 30000000 # define CONFIG_SPI_FLASH_ISSI -# define CONFIG_SPI_FLASH_BAR # define CONFIG_CMD_SF #endif diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h index 9388870d0c..b348ad5231 100644 --- a/include/dm/device-internal.h +++ b/include/dm/device-internal.h @@ -66,19 +66,6 @@ int device_bind_by_name(struct udevice *parent, bool pre_reloc_only, int device_probe(struct udevice *dev); /** - * device_probe() - Probe a child device, activating it - * - * Activate a device so that it is ready for use. All its parents are probed - * first. The child is provided with parent data if parent_priv is not NULL. - * - * @dev: Pointer to device to probe - * @parent_priv: Pointer to parent data. If non-NULL then this is provided to - * the child. - * @return 0 if OK, -ve on error - */ -int device_probe_child(struct udevice *dev, void *parent_priv); - -/** * device_remove() - Remove a device, de-activating it * * De-activate a device so that it is no longer ready for use. All its diff --git a/include/dm/test.h b/include/dm/test.h index ca924d9237..cba504909a 100644 --- a/include/dm/test.h +++ b/include/dm/test.h @@ -161,6 +161,8 @@ struct sandbox_sdl_plat { int yres; int bpix; int rot; + const char *vidconsole_drv_name; + int font_size; }; /* Declare ping methods for the drivers */ diff --git a/include/dt-bindings/clock/microchip,clock.h b/include/dt-bindings/clock/microchip,clock.h new file mode 100644 index 0000000000..93c222d74f --- /dev/null +++ b/include/dt-bindings/clock/microchip,clock.h @@ -0,0 +1,29 @@ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __CLK_MICROCHIP_PIC32 +#define __CLK_MICROCHIP_PIC32 + +/* clock output indices */ +#define BASECLK 0 +#define PLLCLK 1 +#define MPLL 2 +#define SYSCLK 3 +#define PB1CLK 4 +#define PB2CLK 5 +#define PB3CLK 6 +#define PB4CLK 7 +#define PB5CLK 8 +#define PB6CLK 9 +#define PB7CLK 10 +#define REF1CLK 11 +#define REF2CLK 12 +#define REF3CLK 13 +#define REF4CLK 14 +#define REF5CLK 15 + +#endif /* __CLK_MICROCHIP_PIC32 */ diff --git a/include/ethsw.h b/include/ethsw.h index 2d3c12a39e..25f358d128 100644 --- a/include/ethsw.h +++ b/include/ethsw.h @@ -12,6 +12,7 @@ #define ETHSW_MAX_CMD_PARAMS 20 #define ETHSW_CMD_PORT_ALL -1 #define ETHSW_CMD_VLAN_ALL -1 +#define ETHSW_CMD_AGGR_GRP_NONE -1 /* IDs used to track keywords in a command */ enum ethsw_keyword_id { @@ -41,6 +42,7 @@ enum ethsw_keyword_id { ethsw_id_private, ethsw_id_ingress, ethsw_id_filtering, + ethsw_id_aggr, ethsw_id_count, /* keep last */ }; @@ -50,6 +52,7 @@ enum ethsw_keyword_opt_id { ethsw_id_pvid_no, ethsw_id_add_del_no, ethsw_id_add_del_mac, + ethsw_id_aggr_no, ethsw_id_count_all, /* keep last */ }; @@ -58,6 +61,7 @@ struct ethsw_command_def { int cmd_keywords_nr; int port; int vid; + int aggr_grp; uchar ethaddr[6]; int (*cmd_function)(struct ethsw_command_def *parsed_cmd); }; @@ -88,6 +92,8 @@ struct ethsw_command_func { int (*vlan_learn_set)(struct ethsw_command_def *parsed_cmd); int (*port_ingr_filt_show)(struct ethsw_command_def *parsed_cmd); int (*port_ingr_filt_set)(struct ethsw_command_def *parsed_cmd); + int (*port_aggr_show)(struct ethsw_command_def *parsed_cmd); + int (*port_aggr_set)(struct ethsw_command_def *parsed_cmd); }; int ethsw_define_functions(const struct ethsw_command_func *cmd_func); diff --git a/include/fpga.h b/include/fpga.h index e0d12981b2..d768fb1417 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -46,6 +46,7 @@ typedef struct { /* typedef fpga_desc */ typedef enum { BIT_FULL = 0, BIT_PARTIAL, + BIT_NONE = 0xFF, } bitstream_type; /* root function definitions */ diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h index 92c5437d89..b1ad46ee45 100644 --- a/include/fsl-mc/fsl_dpbp.h +++ b/include/fsl-mc/fsl_dpbp.h @@ -15,7 +15,7 @@ /* DPBP Version */ #define DPBP_VER_MAJOR 2 -#define DPBP_VER_MINOR 1 +#define DPBP_VER_MINOR 2 /* Command IDs */ #define DPBP_CMDID_CLOSE 0x800 diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h index 0bc0b449c2..d8c458fb4f 100644 --- a/include/fsl-mc/fsl_dpio.h +++ b/include/fsl-mc/fsl_dpio.h @@ -9,7 +9,7 @@ /* DPIO Version */ #define DPIO_VER_MAJOR 3 -#define DPIO_VER_MINOR 1 +#define DPIO_VER_MINOR 2 /* Command IDs */ #define DPIO_CMDID_CLOSE 0x800 @@ -45,6 +45,7 @@ do { \ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, attr->qbman_portal_ci_offset);\ MC_RSP_OP(cmd, 3, 0, 16, uint16_t, attr->version.major);\ MC_RSP_OP(cmd, 3, 16, 16, uint16_t, attr->version.minor);\ + MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->qbman_version);\ } while (0) /* Data Path I/O Portal API @@ -195,6 +196,7 @@ int dpio_reset(struct fsl_mc_io *mc_io, * @channel_mode: Notification channel mode * @num_priorities: Number of priorities for the notification channel (1-8); * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' + * @qbman_version: QBMAN version */ struct dpio_attr { int id; @@ -212,6 +214,7 @@ struct dpio_attr { uint16_t qbman_portal_id; enum dpio_channel_mode channel_mode; uint8_t num_priorities; + uint32_t qbman_version; }; /** diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h index 24f0b483aa..296f3aed24 100644 --- a/include/fsl-mc/fsl_dpmac.h +++ b/include/fsl-mc/fsl_dpmac.h @@ -12,7 +12,7 @@ /* DPMAC Version */ #define DPMAC_VER_MAJOR 3 -#define DPMAC_VER_MINOR 1 +#define DPMAC_VER_MINOR 2 /* Command IDs */ #define DPMAC_CMDID_CLOSE 0x800 diff --git a/include/fsl-mc/fsl_dpmng.h b/include/fsl-mc/fsl_dpmng.h index b0a87a9082..023b5bbdb4 100644 --- a/include/fsl-mc/fsl_dpmng.h +++ b/include/fsl-mc/fsl_dpmng.h @@ -14,7 +14,7 @@ struct fsl_mc_io; /** * Management Complex firmware version information */ -#define MC_VER_MAJOR 8 +#define MC_VER_MAJOR 9 #define MC_VER_MINOR 0 /** diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h index 140a009185..f396dc304f 100644 --- a/include/fsl-mc/fsl_dpni.h +++ b/include/fsl-mc/fsl_dpni.h @@ -7,8 +7,8 @@ #define _FSL_DPNI_H /* DPNI Version */ -#define DPNI_VER_MAJOR 5 -#define DPNI_VER_MINOR 1 +#define DPNI_VER_MAJOR 6 +#define DPNI_VER_MINOR 0 /* Command IDs */ #define DPNI_CMDID_OPEN 0x801 @@ -28,6 +28,7 @@ #define DPNI_CMDID_SET_TX_BUFFER_LAYOUT 0x204 #define DPNI_CMDID_SET_TX_CONF_BUFFER_LAYOUT 0x205 #define DPNI_CMDID_GET_TX_CONF_BUFFER_LAYOUT 0x206 +#define DPNI_CMDID_SET_ERRORS_BEHAVIOR 0x20B #define DPNI_CMDID_GET_QDID 0x210 #define DPNI_CMDID_GET_TX_DATA_OFFSET 0x212 @@ -45,11 +46,73 @@ #define DPNI_CMDID_GET_TX_FLOW 0x237 #define DPNI_CMDID_SET_RX_FLOW 0x238 #define DPNI_CMDID_GET_RX_FLOW 0x239 +#define DPNI_CMDID_SET_TX_CONF 0x257 +#define DPNI_CMDID_GET_TX_CONF 0x258 /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_OPEN(cmd, dpni_id) \ MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id) +#define DPNI_PREP_EXTENDED_CFG(ext, cfg) \ +do { \ + MC_PREP_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \ + MC_PREP_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \ + MC_PREP_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \ + MC_PREP_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \ + MC_PREP_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \ + MC_PREP_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \ + MC_PREP_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \ + MC_PREP_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \ + MC_PREP_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \ + MC_PREP_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \ + MC_PREP_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \ + MC_PREP_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \ + MC_PREP_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \ + MC_PREP_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \ + MC_PREP_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \ + MC_PREP_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \ + MC_PREP_OP(ext, 4, 0, 16, uint16_t, \ + cfg->ipr_cfg.max_open_frames_ipv4); \ + MC_PREP_OP(ext, 4, 16, 16, uint16_t, \ + cfg->ipr_cfg.max_open_frames_ipv6); \ + MC_PREP_OP(ext, 4, 32, 16, uint16_t, \ + cfg->ipr_cfg.max_reass_frm_size); \ + MC_PREP_OP(ext, 5, 0, 16, uint16_t, \ + cfg->ipr_cfg.min_frag_size_ipv4); \ + MC_PREP_OP(ext, 5, 16, 16, uint16_t, \ + cfg->ipr_cfg.min_frag_size_ipv6); \ +} while (0) + +#define DPNI_EXT_EXTENDED_CFG(ext, cfg) \ +do { \ + MC_EXT_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \ + MC_EXT_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \ + MC_EXT_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \ + MC_EXT_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \ + MC_EXT_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \ + MC_EXT_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \ + MC_EXT_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \ + MC_EXT_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \ + MC_EXT_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \ + MC_EXT_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \ + MC_EXT_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \ + MC_EXT_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \ + MC_EXT_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \ + MC_EXT_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \ + MC_EXT_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \ + MC_EXT_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \ + MC_EXT_OP(ext, 4, 0, 16, uint16_t, \ + cfg->ipr_cfg.max_open_frames_ipv4); \ + MC_EXT_OP(ext, 4, 16, 16, uint16_t, \ + cfg->ipr_cfg.max_open_frames_ipv6); \ + MC_EXT_OP(ext, 4, 32, 16, uint16_t, \ + cfg->ipr_cfg.max_reass_frm_size); \ + MC_EXT_OP(ext, 5, 0, 16, uint16_t, \ + cfg->ipr_cfg.min_frag_size_ipv4); \ + MC_EXT_OP(ext, 5, 16, 16, uint16_t, \ + cfg->ipr_cfg.min_frag_size_ipv6); \ +} while (0) + /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_CREATE(cmd, cfg) \ do { \ @@ -69,32 +132,23 @@ do { \ MC_CMD_OP(cmd, 2, 32, 8, uint8_t, cfg->adv.max_qos_key_size); \ MC_CMD_OP(cmd, 2, 48, 8, uint8_t, cfg->adv.max_dist_key_size); \ MC_CMD_OP(cmd, 2, 56, 8, enum net_prot, cfg->adv.start_hdr); \ - MC_CMD_OP(cmd, 3, 0, 8, uint8_t, cfg->adv.max_dist_per_tc[0]); \ - MC_CMD_OP(cmd, 3, 8, 8, uint8_t, cfg->adv.max_dist_per_tc[1]); \ - MC_CMD_OP(cmd, 3, 16, 8, uint8_t, cfg->adv.max_dist_per_tc[2]); \ - MC_CMD_OP(cmd, 3, 24, 8, uint8_t, cfg->adv.max_dist_per_tc[3]); \ - MC_CMD_OP(cmd, 3, 32, 8, uint8_t, cfg->adv.max_dist_per_tc[4]); \ - MC_CMD_OP(cmd, 3, 40, 8, uint8_t, cfg->adv.max_dist_per_tc[5]); \ - MC_CMD_OP(cmd, 3, 48, 8, uint8_t, cfg->adv.max_dist_per_tc[6]); \ - MC_CMD_OP(cmd, 3, 56, 8, uint8_t, cfg->adv.max_dist_per_tc[7]); \ - MC_CMD_OP(cmd, 4, 0, 16, uint16_t, \ - cfg->adv.ipr_cfg.max_reass_frm_size); \ - MC_CMD_OP(cmd, 4, 16, 16, uint16_t, \ - cfg->adv.ipr_cfg.min_frag_size_ipv4); \ - MC_CMD_OP(cmd, 4, 32, 16, uint16_t, \ - cfg->adv.ipr_cfg.min_frag_size_ipv6); \ MC_CMD_OP(cmd, 4, 48, 8, uint8_t, cfg->adv.max_policers); \ MC_CMD_OP(cmd, 4, 56, 8, uint8_t, cfg->adv.max_congestion_ctrl); \ - MC_CMD_OP(cmd, 5, 0, 16, uint16_t, \ - cfg->adv.ipr_cfg.max_open_frames_ipv4); \ - MC_CMD_OP(cmd, 5, 16, 16, uint16_t, \ - cfg->adv.ipr_cfg.max_open_frames_ipv6); \ + MC_CMD_OP(cmd, 5, 0, 64, uint64_t, cfg->adv.ext_cfg_iova); \ } while (0) /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_SET_POOLS(cmd, cfg) \ do { \ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_dpbp); \ + MC_CMD_OP(cmd, 0, 8, 1, int, cfg->pools[0].backup_pool); \ + MC_CMD_OP(cmd, 0, 9, 1, int, cfg->pools[1].backup_pool); \ + MC_CMD_OP(cmd, 0, 10, 1, int, cfg->pools[2].backup_pool); \ + MC_CMD_OP(cmd, 0, 11, 1, int, cfg->pools[3].backup_pool); \ + MC_CMD_OP(cmd, 0, 12, 1, int, cfg->pools[4].backup_pool); \ + MC_CMD_OP(cmd, 0, 13, 1, int, cfg->pools[5].backup_pool); \ + MC_CMD_OP(cmd, 0, 14, 1, int, cfg->pools[6].backup_pool); \ + MC_CMD_OP(cmd, 0, 15, 1, int, cfg->pools[7].backup_pool); \ MC_CMD_OP(cmd, 0, 32, 32, int, cfg->pools[0].dpbp_id); \ MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\ MC_CMD_OP(cmd, 1, 0, 32, int, cfg->pools[1].dpbp_id); \ @@ -114,6 +168,10 @@ do { \ } while (0) /* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_GET_ATTR(cmd, attr) \ + MC_CMD_OP(cmd, 6, 0, 64, uint64_t, attr->ext_cfg_iova) + +/* cmd, param, offset, width, type, arg_name */ #define DPNI_RSP_GET_ATTR(cmd, attr) \ do { \ MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\ @@ -127,31 +185,21 @@ do { \ MC_RSP_OP(cmd, 2, 24, 8, uint8_t, attr->max_qos_entries); \ MC_RSP_OP(cmd, 2, 32, 8, uint8_t, attr->max_qos_key_size); \ MC_RSP_OP(cmd, 2, 40, 8, uint8_t, attr->max_dist_key_size); \ - MC_RSP_OP(cmd, 3, 0, 8, uint8_t, attr->max_dist_per_tc[0]); \ - MC_RSP_OP(cmd, 3, 8, 8, uint8_t, attr->max_dist_per_tc[1]); \ - MC_RSP_OP(cmd, 3, 16, 8, uint8_t, attr->max_dist_per_tc[2]); \ - MC_RSP_OP(cmd, 3, 24, 8, uint8_t, attr->max_dist_per_tc[3]); \ - MC_RSP_OP(cmd, 3, 32, 8, uint8_t, attr->max_dist_per_tc[4]); \ - MC_RSP_OP(cmd, 3, 40, 8, uint8_t, attr->max_dist_per_tc[5]); \ - MC_RSP_OP(cmd, 3, 48, 8, uint8_t, attr->max_dist_per_tc[6]); \ - MC_RSP_OP(cmd, 3, 56, 8, uint8_t, attr->max_dist_per_tc[7]); \ - MC_RSP_OP(cmd, 4, 0, 16, uint16_t, \ - attr->ipr_cfg.max_reass_frm_size); \ - MC_RSP_OP(cmd, 4, 16, 16, uint16_t, \ - attr->ipr_cfg.min_frag_size_ipv4); \ - MC_RSP_OP(cmd, 4, 32, 16, uint16_t, \ - attr->ipr_cfg.min_frag_size_ipv6);\ - MC_RSP_OP(cmd, 4, 48, 8, uint8_t, attr->max_policers); \ - MC_RSP_OP(cmd, 4, 56, 8, uint8_t, attr->max_congestion_ctrl); \ - MC_RSP_OP(cmd, 5, 0, 16, uint16_t, \ - attr->ipr_cfg.max_open_frames_ipv4); \ - MC_RSP_OP(cmd, 5, 16, 16, uint16_t, \ - attr->ipr_cfg.max_open_frames_ipv6); \ + MC_RSP_OP(cmd, 4, 48, 8, uint8_t, attr->max_policers); \ + MC_RSP_OP(cmd, 4, 56, 8, uint8_t, attr->max_congestion_ctrl); \ MC_RSP_OP(cmd, 5, 32, 16, uint16_t, attr->version.major);\ MC_RSP_OP(cmd, 5, 48, 16, uint16_t, attr->version.minor);\ } while (0) /* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->errors); \ + MC_CMD_OP(cmd, 0, 32, 4, enum dpni_error_action, cfg->error_action); \ + MC_CMD_OP(cmd, 0, 36, 1, int, cfg->set_frame_annotation); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ #define DPNI_RSP_GET_RX_BUFFER_LAYOUT(cmd, layout) \ do { \ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, layout->private_data_size); \ @@ -313,23 +361,11 @@ do { \ /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_SET_TX_FLOW(cmd, flow_id, cfg) \ do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, \ - cfg->conf_err_cfg.queue_cfg.dest_cfg.dest_id);\ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, \ - cfg->conf_err_cfg.queue_cfg.dest_cfg.priority);\ - MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, \ - cfg->conf_err_cfg.queue_cfg.dest_cfg.dest_type);\ - MC_CMD_OP(cmd, 0, 42, 1, int, cfg->conf_err_cfg.errors_only);\ MC_CMD_OP(cmd, 0, 43, 1, int, cfg->l3_chksum_gen);\ MC_CMD_OP(cmd, 0, 44, 1, int, cfg->l4_chksum_gen);\ - MC_CMD_OP(cmd, 0, 45, 1, int, \ - cfg->conf_err_cfg.use_default_queue);\ + MC_CMD_OP(cmd, 0, 45, 1, int, cfg->use_common_tx_conf_queue);\ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id);\ - MC_CMD_OP(cmd, 1, 0, 64, uint64_t, \ - cfg->conf_err_cfg.queue_cfg.user_ctx);\ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\ - MC_CMD_OP(cmd, 2, 32, 32, uint32_t, \ - cfg->conf_err_cfg.queue_cfg.options);\ } while (0) /* cmd, param, offset, width, type, arg_name */ @@ -343,21 +379,9 @@ do { \ /* cmd, param, offset, width, type, arg_name */ #define DPNI_RSP_GET_TX_FLOW(cmd, attr) \ do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, \ - attr->conf_err_attr.queue_attr.dest_cfg.dest_id);\ - MC_RSP_OP(cmd, 0, 32, 8, uint8_t, \ - attr->conf_err_attr.queue_attr.dest_cfg.priority);\ - MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, \ - attr->conf_err_attr.queue_attr.dest_cfg.dest_type);\ - MC_RSP_OP(cmd, 0, 42, 1, int, attr->conf_err_attr.errors_only);\ MC_RSP_OP(cmd, 0, 43, 1, int, attr->l3_chksum_gen);\ MC_RSP_OP(cmd, 0, 44, 1, int, attr->l4_chksum_gen);\ - MC_RSP_OP(cmd, 0, 45, 1, int, \ - attr->conf_err_attr.use_default_queue);\ - MC_RSP_OP(cmd, 1, 0, 64, uint64_t, \ - attr->conf_err_attr.queue_attr.user_ctx);\ - MC_RSP_OP(cmd, 2, 32, 32, uint32_t, \ - attr->conf_err_attr.queue_attr.fqid);\ + MC_RSP_OP(cmd, 0, 45, 1, int, attr->use_common_tx_conf_queue);\ } while (0) /* cmd, param, offset, width, type, arg_name */ @@ -370,7 +394,7 @@ do { \ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \ MC_CMD_OP(cmd, 2, 16, 8, uint8_t, tc_id); \ - MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->options); \ + MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->options); \ MC_CMD_OP(cmd, 3, 0, 4, enum dpni_flc_type, cfg->flc_cfg.flc_type); \ MC_CMD_OP(cmd, 3, 4, 4, enum dpni_stash_size, \ cfg->flc_cfg.frame_data_size);\ @@ -378,6 +402,7 @@ do { \ cfg->flc_cfg.flow_context_size);\ MC_CMD_OP(cmd, 3, 32, 32, uint32_t, cfg->flc_cfg.options);\ MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->flc_cfg.flow_context);\ + MC_CMD_OP(cmd, 5, 0, 32, uint32_t, cfg->tail_drop_threshold); \ } while (0) /* cmd, param, offset, width, type, arg_name */ @@ -393,8 +418,9 @@ do { \ MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id); \ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\ MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, attr->dest_cfg.dest_type); \ - MC_CMD_OP(cmd, 0, 42, 1, int, attr->order_preservation_en);\ + MC_RSP_OP(cmd, 0, 42, 1, int, attr->order_preservation_en);\ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->user_ctx); \ + MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->tail_drop_threshold); \ MC_RSP_OP(cmd, 2, 32, 32, uint32_t, attr->fqid); \ MC_RSP_OP(cmd, 3, 0, 4, enum dpni_flc_type, attr->flc_cfg.flc_type); \ MC_RSP_OP(cmd, 3, 4, 4, enum dpni_stash_size, \ @@ -405,6 +431,58 @@ do { \ MC_RSP_OP(cmd, 4, 0, 64, uint64_t, attr->flc_cfg.flow_context);\ } while (0) +#define DPNI_CMD_SET_TX_CONF(cmd, flow_id, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->queue_cfg.dest_cfg.priority); \ + MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, \ + cfg->queue_cfg.dest_cfg.dest_type); \ + MC_CMD_OP(cmd, 0, 42, 1, int, cfg->errors_only); \ + MC_CMD_OP(cmd, 0, 46, 1, int, cfg->queue_cfg.order_preservation_en); \ + MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \ + MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->queue_cfg.user_ctx); \ + MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->queue_cfg.options); \ + MC_CMD_OP(cmd, 2, 32, 32, int, cfg->queue_cfg.dest_cfg.dest_id); \ + MC_CMD_OP(cmd, 3, 0, 32, uint32_t, \ + cfg->queue_cfg.tail_drop_threshold); \ + MC_CMD_OP(cmd, 4, 0, 4, enum dpni_flc_type, \ + cfg->queue_cfg.flc_cfg.flc_type); \ + MC_CMD_OP(cmd, 4, 4, 4, enum dpni_stash_size, \ + cfg->queue_cfg.flc_cfg.frame_data_size); \ + MC_CMD_OP(cmd, 4, 8, 4, enum dpni_stash_size, \ + cfg->queue_cfg.flc_cfg.flow_context_size); \ + MC_CMD_OP(cmd, 4, 32, 32, uint32_t, cfg->queue_cfg.flc_cfg.options); \ + MC_CMD_OP(cmd, 5, 0, 64, uint64_t, \ + cfg->queue_cfg.flc_cfg.flow_context); \ +} while (0) + +#define DPNI_CMD_GET_TX_CONF(cmd, flow_id) \ + MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id) + +#define DPNI_RSP_GET_TX_CONF(cmd, attr) \ +do { \ + MC_RSP_OP(cmd, 0, 32, 8, uint8_t, \ + attr->queue_attr.dest_cfg.priority); \ + MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, \ + attr->queue_attr.dest_cfg.dest_type); \ + MC_RSP_OP(cmd, 0, 42, 1, int, attr->errors_only); \ + MC_RSP_OP(cmd, 0, 46, 1, int, \ + attr->queue_attr.order_preservation_en); \ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->queue_attr.user_ctx); \ + MC_RSP_OP(cmd, 2, 32, 32, int, attr->queue_attr.dest_cfg.dest_id); \ + MC_RSP_OP(cmd, 3, 0, 32, uint32_t, \ + attr->queue_attr.tail_drop_threshold); \ + MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->queue_attr.fqid); \ + MC_RSP_OP(cmd, 4, 0, 4, enum dpni_flc_type, \ + attr->queue_attr.flc_cfg.flc_type); \ + MC_RSP_OP(cmd, 4, 4, 4, enum dpni_stash_size, \ + attr->queue_attr.flc_cfg.frame_data_size); \ + MC_RSP_OP(cmd, 4, 8, 4, enum dpni_stash_size, \ + attr->queue_attr.flc_cfg.flow_context_size); \ + MC_RSP_OP(cmd, 4, 32, 32, uint32_t, attr->queue_attr.flc_cfg.options); \ + MC_RSP_OP(cmd, 5, 0, 64, uint64_t, \ + attr->queue_attr.flc_cfg.flow_context); \ +} while (0) + enum net_prot { NET_PROT_NONE = 0, NET_PROT_PAYLOAD, @@ -479,6 +557,8 @@ struct fsl_mc_io; #define DPNI_ALL_TC_FLOWS (uint16_t)(-1) /* Generate new flow ID; see dpni_set_tx_flow() */ #define DPNI_NEW_FLOW_ID (uint16_t)(-1) +/* use for common tx-conf queue; see dpni_set_tx_conf_<x>() */ +#define DPNI_COMMON_TX_CONF (uint16_t)(-1) /** * dpni_open() - Open a control session for the specified object @@ -565,22 +645,56 @@ int dpni_close(struct fsl_mc_io *mc_io, #define DPNI_OPT_FS_MASK_SUPPORT 0x00040000 /** - * struct dpni_ipr_cfg - Structure representing IP reassembly configuration - * @max_reass_frm_size: Maximum size of the reassembled frame - * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments - * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments - * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly process - * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly process + * struct dpni_extended_cfg - Structure representing extended DPNI configuration + * @tc_cfg: TCs configuration + * @ipr_cfg: IP reassembly configuration */ -struct dpni_ipr_cfg { - uint16_t max_reass_frm_size; - uint16_t min_frag_size_ipv4; - uint16_t min_frag_size_ipv6; - uint16_t max_open_frames_ipv4; - uint16_t max_open_frames_ipv6; +struct dpni_extended_cfg { + /** + * struct tc_cfg - TC configuration + * @max_dist: Maximum distribution size for Rx traffic class; + * supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96, + * 112,128,192,224,256,384,448,512,768,896,1024; + * value '0' will be treated as '1'. + * other unsupported values will be round down to the nearest + * supported value. + * @max_fs_entries: Maximum FS entries for Rx traffic class; + * '0' means no support for this TC; + */ + struct { + uint16_t max_dist; + uint16_t max_fs_entries; + } tc_cfg[DPNI_MAX_TC]; + /** + * struct ipr_cfg - Structure representing IP reassembly configuration + * @max_reass_frm_size: Maximum size of the reassembled frame + * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments + * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments + * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly + * process + * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly + * process + */ + struct { + uint16_t max_reass_frm_size; + uint16_t min_frag_size_ipv4; + uint16_t min_frag_size_ipv6; + uint16_t max_open_frames_ipv4; + uint16_t max_open_frames_ipv6; + } ipr_cfg; }; /** + * dpni_prepare_extended_cfg() - function prepare extended parameters + * @cfg: extended structure + * @ext_cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA + * + * This function has to be called before dpni_create() + */ +int dpni_prepare_extended_cfg(const struct dpni_extended_cfg *cfg, + uint8_t *ext_cfg_buf); + +/** * struct dpni_cfg - Structure representing DPNI configuration * @mac_addr: Primary MAC address * @adv: Advanced parameters; default is all zeros; @@ -599,11 +713,6 @@ struct dpni_cfg { * '0' will be treated as '1' * @max_tcs: Maximum number of traffic classes (for both Tx and Rx); * '0' will e treated as '1' - * @max_dist_per_tc: Maximum distribution size per Rx traffic class; - * Must be set to the required value minus 1; - * i.e. 0->1, 1->2, ... ,255->256; - * Non-power-of-2 values are rounded up to the next - * power-of-2 value as hardware demands it * @max_unicast_filters: Maximum number of unicast filters; * '0' is treated as '16' * @max_multicast_filters: Maximum number of multicast filters; @@ -619,16 +728,17 @@ struct dpni_cfg { * should be between '0' and max_tcs * @max_congestion_ctrl: Maximum number of congestion control groups * (CGs); covers early drop and congestion notification - * requirements for traffic classes; - * should be between '0' and max_tcs - * @ipr_cfg: IP reassembly configuration + * requirements; + * should be between '0' and ('max_tcs' + 'max_senders') + * @ext_cfg_iova: I/O virtual address of 256 bytes DMA-able memory + * filled with the extended configuration by calling + * dpni_prepare_extended_cfg() */ struct { uint32_t options; enum net_prot start_hdr; uint8_t max_senders; uint8_t max_tcs; - uint8_t max_dist_per_tc[DPNI_MAX_TC]; uint8_t max_unicast_filters; uint8_t max_multicast_filters; uint8_t max_vlan_filters; @@ -637,7 +747,7 @@ struct dpni_cfg { uint8_t max_dist_key_size; uint8_t max_policers; uint8_t max_congestion_ctrl; - struct dpni_ipr_cfg ipr_cfg; + uint64_t ext_cfg_iova; } adv; }; @@ -765,8 +875,6 @@ int dpni_reset(struct fsl_mc_io *mc_io, * @max_senders: Maximum number of different senders; used as the number * of dedicated Tx flows; * @max_tcs: Maximum number of traffic classes (for both Tx and Rx) - * @max_dist_per_tc: Maximum distribution size per Rx traffic class; - * Set to the required value minus 1 * @max_unicast_filters: Maximum number of unicast filters * @max_multicast_filters: Maximum number of multicast filters * @max_vlan_filters: Maximum number of VLAN filters @@ -775,7 +883,8 @@ int dpni_reset(struct fsl_mc_io *mc_io, * @max_dist_key_size: Maximum key size for the distribution look-up * @max_policers: Maximum number of policers; * @max_congestion_ctrl: Maximum number of congestion control groups (CGs); - * @ipr_cfg: IP reassembly configuration + * @ext_cfg_iova: I/O virtual address of 256 bytes DMA-able memory; + * call dpni_extract_extended_cfg() to extract the extended configuration */ struct dpni_attr { int id; @@ -792,7 +901,6 @@ struct dpni_attr { uint32_t options; uint8_t max_senders; uint8_t max_tcs; - uint8_t max_dist_per_tc[DPNI_MAX_TC]; uint8_t max_unicast_filters; uint8_t max_multicast_filters; uint8_t max_vlan_filters; @@ -801,7 +909,7 @@ struct dpni_attr { uint8_t max_dist_key_size; uint8_t max_policers; uint8_t max_congestion_ctrl; - struct dpni_ipr_cfg ipr_cfg; + uint64_t ext_cfg_iova; }; /** @@ -809,7 +917,7 @@ struct dpni_attr { * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPNI object - * @attr: Returned object's attributes + * @attr: Object's attributes * * Return: '0' on Success; Error code otherwise. */ @@ -818,6 +926,87 @@ int dpni_get_attributes(struct fsl_mc_io *mc_io, uint16_t token, struct dpni_attr *attr); +/** + * dpni_extract_extended_cfg() - extract the extended parameters + * @cfg: extended structure + * @ext_cfg_buf: 256 bytes of DMA-able memory + * + * This function has to be called after dpni_get_attributes() + */ +int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg, + const uint8_t *ext_cfg_buf); + +/** + * DPNI errors + */ + +/** + * Extract out of frame header error + */ +#define DPNI_ERROR_EOFHE 0x00020000 +/** + * Frame length error + */ +#define DPNI_ERROR_FLE 0x00002000 +/** + * Frame physical error + */ +#define DPNI_ERROR_FPE 0x00001000 +/** + * Parsing header error + */ +#define DPNI_ERROR_PHE 0x00000020 +/** + * Parser L3 checksum error + */ +#define DPNI_ERROR_L3CE 0x00000004 +/** + * Parser L3 checksum error + */ +#define DPNI_ERROR_L4CE 0x00000001 + +/** + * enum dpni_error_action - Defines DPNI behavior for errors + * @DPNI_ERROR_ACTION_DISCARD: Discard the frame + * @DPNI_ERROR_ACTION_CONTINUE: Continue with the normal flow + * @DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE: Send the frame to the error queue + */ +enum dpni_error_action { + DPNI_ERROR_ACTION_DISCARD = 0, + DPNI_ERROR_ACTION_CONTINUE = 1, + DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE = 2 +}; + +/** + * struct dpni_error_cfg - Structure representing DPNI errors treatment + * @errors: Errors mask; use 'DPNI_ERROR__<X> + * @error_action: The desired action for the errors mask + * @set_frame_annotation: Set to '1' to mark the errors in frame annotation + * status (FAS); relevant only for the non-discard action + */ +struct dpni_error_cfg { + uint32_t errors; + enum dpni_error_action error_action; + int set_frame_annotation; +}; + +/** + * dpni_set_errors_behavior() - Set errors behavior + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @cfg: Errors configuration + * + * this function may be called numerous times with different + * error masks + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_error_cfg *cfg); + /* DPNI buffer layout modification options */ /* Select to modify the time-stamp setting */ @@ -1254,6 +1443,8 @@ struct dpni_flc_cfg { #define DPNI_QUEUE_OPT_FLC 0x00000004 /* Select to modify the queue's order preservation */ #define DPNI_QUEUE_OPT_ORDER_PRESERVATION 0x00000008 +/* Select to modify the queue's tail-drop threshold */ +#define DPNI_QUEUE_OPT_TAILDROP_THRESHOLD 0x00000010 /** * struct dpni_queue_cfg - Structure representing queue configuration @@ -1272,6 +1463,10 @@ struct dpni_flc_cfg { * @order_preservation_en: enable/disable order preservation; * valid only if 'DPNI_QUEUE_OPT_ORDER_PRESERVATION' is contained * in 'options' + * @tail_drop_threshold: set the queue's tail drop threshold in bytes; + * '0' value disable the threshold; maximum value is 0xE000000; + * valid only if 'DPNI_QUEUE_OPT_TAILDROP_THRESHOLD' is contained + * in 'options' */ struct dpni_queue_cfg { uint32_t options; @@ -1279,6 +1474,7 @@ struct dpni_queue_cfg { struct dpni_dest_cfg dest_cfg; struct dpni_flc_cfg flc_cfg; int order_preservation_en; + uint32_t tail_drop_threshold; }; /** @@ -1288,6 +1484,7 @@ struct dpni_queue_cfg { * @dest_cfg: Queue destination configuration * @flc_cfg: Flow context configuration * @order_preservation_en: enable/disable order preservation + * @tail_drop_threshold: queue's tail drop threshold in bytes; * @fqid: Virtual fqid value to be used for dequeue operations */ struct dpni_queue_attr { @@ -1295,6 +1492,7 @@ struct dpni_queue_attr { struct dpni_dest_cfg dest_cfg; struct dpni_flc_cfg flc_cfg; int order_preservation_en; + uint32_t tail_drop_threshold; uint32_t fqid; }; @@ -1302,10 +1500,6 @@ struct dpni_queue_attr { /* Select to modify the settings for dedicate Tx confirmation/error */ #define DPNI_TX_FLOW_OPT_TX_CONF_ERROR 0x00000001 -/*!< Select to modify the Tx confirmation and/or error setting */ -#define DPNI_TX_FLOW_OPT_ONLY_TX_ERROR 0x00000002 -/*!< Select to modify the queue configuration */ -#define DPNI_TX_FLOW_OPT_QUEUE 0x00000004 /*!< Select to modify the L3 checksum generation setting */ #define DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN 0x00000010 /*!< Select to modify the L4 checksum generation setting */ @@ -1314,41 +1508,22 @@ struct dpni_queue_attr { /** * struct dpni_tx_flow_cfg - Structure representing Tx flow configuration * @options: Flags representing the suggested modifications to the Tx flow; - * Use any combination 'DPNI_TX_FLOW_OPT_<X>' flags - * @conf_err_cfg: Tx confirmation and error configuration; these settings are - * ignored if 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' was set at - * DPNI creation + * Use any combination 'DPNI_TX_FLOW_OPT_<X>' flags + * @use_common_tx_conf_queue: Set to '1' to use the common (default) Tx + * confirmation and error queue; Set to '0' to use the private + * Tx confirmation and error queue; valid only if + * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' wasn't set at DPNI creation + * and 'DPNI_TX_FLOW_OPT_TX_CONF_ERROR' is contained in 'options' * @l3_chksum_gen: Set to '1' to enable L3 checksum generation; '0' to disable; - * valid only if 'DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN' is contained in - * 'options' + * valid only if 'DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN' is contained in 'options' * @l4_chksum_gen: Set to '1' to enable L4 checksum generation; '0' to disable; - * valid only if 'DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN' is contained in - * 'options' + * valid only if 'DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN' is contained in 'options' */ struct dpni_tx_flow_cfg { - uint32_t options; - /** - * struct cnf_err_cfg - Tx confirmation and error configuration - * @use_default_queue: Set to '1' to use the common (default) Tx - * confirmation and error queue; Set to '0' to use the - * private Tx confirmation and error queue; valid only if - * 'DPNI_TX_FLOW_OPT_TX_CONF_ERROR' is contained in - * 'options' - * @errors_only: Set to '1' to report back only error frames; - * Set to '0' to confirm transmission/error for all - * transmitted frames; - * valid only if 'DPNI_TX_FLOW_OPT_ONLY_TX_ERROR' is - * contained in 'options' and 'use_default_queue = 0'; - * @queue_cfg: Queue configuration; valid only if - * 'DPNI_TX_FLOW_OPT_QUEUE' is contained in 'options' - */ - struct { - int use_default_queue; - int errors_only; - struct dpni_queue_cfg queue_cfg; - } conf_err_cfg; - int l3_chksum_gen; - int l4_chksum_gen; + uint32_t options; + int use_common_tx_conf_queue; + int l3_chksum_gen; + int l4_chksum_gen; }; /** @@ -1357,10 +1532,9 @@ struct dpni_tx_flow_cfg { * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPNI object * @flow_id: Provides (or returns) the sender's flow ID; - * for each new sender set (*flow_id) to - * 'DPNI_NEW_FLOW_ID' to generate a new flow_id; - * this ID should be used as the QDBIN argument - * in enqueue operations + * for each new sender set (*flow_id) to 'DPNI_NEW_FLOW_ID' to generate + * a new flow_id; this ID should be used as the QDBIN argument + * in enqueue operations * @cfg: Tx flow configuration * * Return: '0' on Success; Error code otherwise. @@ -1373,28 +1547,15 @@ int dpni_set_tx_flow(struct fsl_mc_io *mc_io, /** * struct dpni_tx_flow_attr - Structure representing Tx flow attributes - * @conf_err_attr: Tx confirmation and error attributes + * @use_common_tx_conf_queue: '1' if using common (default) Tx confirmation and + * error queue; '0' if using private Tx confirmation and error queue * @l3_chksum_gen: '1' if L3 checksum generation is enabled; '0' if disabled * @l4_chksum_gen: '1' if L4 checksum generation is enabled; '0' if disabled */ struct dpni_tx_flow_attr { - /** - * struct conf_err_attr - Tx confirmation and error attributes - * @use_default_queue: '1' if using common (default) Tx confirmation and - * error queue; - * '0' if using private Tx confirmation and error - * queue - * @errors_only: '1' if only error frames are reported back; '0' if all - * transmitted frames are confirmed - * @queue_attr: Queue attributes - */ - struct { - int use_default_queue; - int errors_only; - struct dpni_queue_attr queue_attr; - } conf_err_attr; - int l3_chksum_gen; - int l4_chksum_gen; + int use_common_tx_conf_queue; + int l3_chksum_gen; + int l4_chksum_gen; }; /** @@ -1403,7 +1564,7 @@ struct dpni_tx_flow_attr { * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPNI object * @flow_id: The sender's flow ID, as returned by the - * dpni_set_tx_flow() function + * dpni_set_tx_flow() function * @attr: Returned Tx flow attributes * * Return: '0' on Success; Error code otherwise. @@ -1415,6 +1576,76 @@ int dpni_get_tx_flow(struct fsl_mc_io *mc_io, struct dpni_tx_flow_attr *attr); /** + * struct dpni_tx_conf_cfg - Structure representing Tx conf configuration + * @errors_only: Set to '1' to report back only error frames; + * Set to '0' to confirm transmission/error for all transmitted frames; + * @queue_cfg: Queue configuration + */ +struct dpni_tx_conf_cfg { + int errors_only; + struct dpni_queue_cfg queue_cfg; +}; + +/** + * dpni_set_tx_conf() - Set Tx confirmation and error queue configuration + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @flow_id: The sender's flow ID, as returned by the + * dpni_set_tx_flow() function; + * use 'DPNI_COMMON_TX_CONF' for common tx-conf + * @cfg: Queue configuration + * + * If either 'DPNI_OPT_TX_CONF_DISABLED' or + * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation, + * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF'; + * i.e. only serve the common tx-conf-err queue; + * if 'DPNI_OPT_TX_CONF_DISABLED' was selected, only error frames are reported + * back - successfully transmitted frames are not confirmed. Otherwise, all + * transmitted frames are sent for confirmation. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_tx_conf(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint16_t flow_id, + const struct dpni_tx_conf_cfg *cfg); + +/** + * struct dpni_tx_conf_attr - Structure representing Tx conf attributes + * @errors_only: '1' if only error frames are reported back; '0' if all + * transmitted frames are confirmed + * @queue_attr: Queue attributes + */ +struct dpni_tx_conf_attr { + int errors_only; + struct dpni_queue_attr queue_attr; +}; + +/** + * dpni_get_tx_conf() - Get Tx confirmation and error queue attributes + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @flow_id: The sender's flow ID, as returned by the + * dpni_set_tx_flow() function; + * use 'DPNI_COMMON_TX_CONF' for common tx-conf + * @attr: Returned tx-conf attributes + * + * If either 'DPNI_OPT_TX_CONF_DISABLED' or + * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation, + * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF'; + * i.e. only serve the common tx-conf-err queue; + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_tx_conf(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint16_t flow_id, + struct dpni_tx_conf_attr *attr); +/** * dpni_set_rx_flow() - Set Rx flow configuration * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h index a87179d6d5..535c789c95 100644 --- a/include/fsl-mc/fsl_dprc.h +++ b/include/fsl-mc/fsl_dprc.h @@ -11,7 +11,7 @@ /* DPRC Version */ #define DPRC_VER_MAJOR 5 -#define DPRC_VER_MINOR 0 +#define DPRC_VER_MINOR 1 /* Command IDs */ #define DPRC_CMDID_CLOSE 0x800 @@ -110,6 +110,74 @@ do { \ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\ MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\ MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\ + MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \ + MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\ + MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\ + MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\ + MC_RSP_OP(cmd, 3, 24, 8, char, obj_desc->type[3]);\ + MC_RSP_OP(cmd, 3, 32, 8, char, obj_desc->type[4]);\ + MC_RSP_OP(cmd, 3, 40, 8, char, obj_desc->type[5]);\ + MC_RSP_OP(cmd, 3, 48, 8, char, obj_desc->type[6]);\ + MC_RSP_OP(cmd, 3, 56, 8, char, obj_desc->type[7]);\ + MC_RSP_OP(cmd, 4, 0, 8, char, obj_desc->type[8]);\ + MC_RSP_OP(cmd, 4, 8, 8, char, obj_desc->type[9]);\ + MC_RSP_OP(cmd, 4, 16, 8, char, obj_desc->type[10]);\ + MC_RSP_OP(cmd, 4, 24, 8, char, obj_desc->type[11]);\ + MC_RSP_OP(cmd, 4, 32, 8, char, obj_desc->type[12]);\ + MC_RSP_OP(cmd, 4, 40, 8, char, obj_desc->type[13]);\ + MC_RSP_OP(cmd, 4, 48, 8, char, obj_desc->type[14]);\ + MC_RSP_OP(cmd, 4, 56, 8, char, obj_desc->type[15]);\ + MC_RSP_OP(cmd, 5, 0, 8, char, obj_desc->label[0]);\ + MC_RSP_OP(cmd, 5, 8, 8, char, obj_desc->label[1]);\ + MC_RSP_OP(cmd, 5, 16, 8, char, obj_desc->label[2]);\ + MC_RSP_OP(cmd, 5, 24, 8, char, obj_desc->label[3]);\ + MC_RSP_OP(cmd, 5, 32, 8, char, obj_desc->label[4]);\ + MC_RSP_OP(cmd, 5, 40, 8, char, obj_desc->label[5]);\ + MC_RSP_OP(cmd, 5, 48, 8, char, obj_desc->label[6]);\ + MC_RSP_OP(cmd, 5, 56, 8, char, obj_desc->label[7]);\ + MC_RSP_OP(cmd, 6, 0, 8, char, obj_desc->label[8]);\ + MC_RSP_OP(cmd, 6, 8, 8, char, obj_desc->label[9]);\ + MC_RSP_OP(cmd, 6, 16, 8, char, obj_desc->label[10]);\ + MC_RSP_OP(cmd, 6, 24, 8, char, obj_desc->label[11]);\ + MC_RSP_OP(cmd, 6, 32, 8, char, obj_desc->label[12]);\ + MC_RSP_OP(cmd, 6, 40, 8, char, obj_desc->label[13]);\ + MC_RSP_OP(cmd, 6, 48, 8, char, obj_desc->label[14]);\ + MC_RSP_OP(cmd, 6, 56, 8, char, obj_desc->label[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_GET_OBJ_DESC(cmd, obj_type, obj_id) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, obj_id);\ + MC_CMD_OP(cmd, 1, 0, 8, char, obj_type[0]);\ + MC_CMD_OP(cmd, 1, 8, 8, char, obj_type[1]);\ + MC_CMD_OP(cmd, 1, 16, 8, char, obj_type[2]);\ + MC_CMD_OP(cmd, 1, 24, 8, char, obj_type[3]);\ + MC_CMD_OP(cmd, 1, 32, 8, char, obj_type[4]);\ + MC_CMD_OP(cmd, 1, 40, 8, char, obj_type[5]);\ + MC_CMD_OP(cmd, 1, 48, 8, char, obj_type[6]);\ + MC_CMD_OP(cmd, 1, 56, 8, char, obj_type[7]);\ + MC_CMD_OP(cmd, 2, 0, 8, char, obj_type[8]);\ + MC_CMD_OP(cmd, 2, 8, 8, char, obj_type[9]);\ + MC_CMD_OP(cmd, 2, 16, 8, char, obj_type[10]);\ + MC_CMD_OP(cmd, 2, 24, 8, char, obj_type[11]);\ + MC_CMD_OP(cmd, 2, 32, 8, char, obj_type[12]);\ + MC_CMD_OP(cmd, 2, 40, 8, char, obj_type[13]);\ + MC_CMD_OP(cmd, 2, 48, 8, char, obj_type[14]);\ + MC_CMD_OP(cmd, 2, 56, 8, char, obj_type[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_OBJ_DESC(cmd, obj_desc) \ +do { \ + MC_RSP_OP(cmd, 0, 32, 32, int, obj_desc->id); \ + MC_RSP_OP(cmd, 1, 0, 16, uint16_t, obj_desc->vendor); \ + MC_RSP_OP(cmd, 1, 16, 8, uint8_t, obj_desc->irq_count); \ + MC_RSP_OP(cmd, 1, 24, 8, uint8_t, obj_desc->region_count); \ + MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\ + MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\ + MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\ + MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \ MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\ MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\ MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\ @@ -480,14 +548,13 @@ int dprc_close(struct fsl_mc_io *mc_io, */ #define DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED 0x00000008 -/* IOMMU bypass - indicates whether objects of this container are permitted - * to bypass the IOMMU. - */ -#define DPRC_CFG_OPT_IOMMU_BYPASS 0x00000010 -/* AIOP - Indicates that container belongs to AIOP. */ +/* AIOP - Indicates that container belongs to AIOP. */ #define DPRC_CFG_OPT_AIOP 0x00000020 +/* IRQ Config - Indicates that the container allowed to configure its IRQs.*/ +#define DPRC_CFG_OPT_IRQ_CFG_ALLOWED 0x00000040 + /** * struct dprc_cfg - Container configuration options * @icid: Container's ICID; if set to 'DPRC_GET_ICID_FROM_POOL', a free @@ -637,6 +704,14 @@ int dprc_get_obj_count(struct fsl_mc_io *mc_io, #define DPRC_OBJ_STATE_PLUGGED 0x00000002 /** + * Shareability flag - Object flag indicating no memory shareability. + * the object generates memory accesses that are non coherent with other + * masters; + * user is responsible for proper memory handling through IOMMU configuration. + */ +#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001 + +/** * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj() * @type: Type of object: NULL terminated string * @id: ID of logical object resource @@ -647,6 +722,7 @@ int dprc_get_obj_count(struct fsl_mc_io *mc_io, * @region_count: Number of mappable regions supported by the object * @state: Object state: combination of DPRC_OBJ_STATE_ states * @label: Object label + * @flags: Object's flags */ struct dprc_obj_desc { char type[16]; @@ -658,6 +734,7 @@ struct dprc_obj_desc { uint8_t region_count; uint32_t state; char label[16]; + uint16_t flags; }; /** @@ -859,7 +936,10 @@ int dprc_disconnect(struct fsl_mc_io *mc_io, * @token: Token of DPRC object * @endpoint1: Endpoint 1 configuration parameters * @endpoint2: Returned endpoint 2 configuration parameters -* @state: Returned link state: 1 - link is up, 0 - link is down +* @state: Returned link state: +* 1 - link is up; +* 0 - link is down; +* -1 - no connection (endpoint2 information is irrelevant) * * Return: '0' on Success; -ENAVAIL if connection does not exist. */ diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h index 7f87d4e302..f3d1498cc0 100644 --- a/include/fsl-mc/fsl_mc_cmd.h +++ b/include/fsl-mc/fsl_mc_cmd.h @@ -68,8 +68,11 @@ enum mc_cmd_status { #define MC_CMD_HDR_READ_TOKEN(_hdr) \ ((uint16_t)mc_dec((_hdr), MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S)) +#define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \ + ((_ext)[_param] |= cpu_to_le64(mc_enc((_offset), (_width), _arg))) + #define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \ - ((_ext)[_param] |= mc_enc((_offset), (_width), _arg)) + (_arg = (_type)mc_dec(cpu_to_le64(_ext[_param]), (_offset), (_width))) #define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg)) diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 9ea8b63779..3699c0408a 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -129,6 +129,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define SDRAM_CFG2_ODT_ONLY_READ 2 #define SDRAM_CFG2_ODT_ALWAYS 3 +#define SDRAM_INTERVAL_BSTOPRE 0x3FFF #define TIMING_CFG_2_CPO_MASK 0x0F800000 #if defined(CONFIG_SYS_FSL_DDR_VER) && \ diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h index 2137282df3..25678a9988 100644 --- a/include/fsl_mdio.h +++ b/include/fsl_mdio.h @@ -5,6 +5,7 @@ * * SPDX-License-Identifier: GPL-2.0+ */ + #ifndef __FSL_PHY_H__ #define __FSL_PHY_H__ @@ -27,9 +28,9 @@ int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc); #define PHY_EXT_PAGE_ACCESS 0x1f /* MII Management Configuration Register */ -#define MIIMCFG_RESET_MGMT 0x80000000 -#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007 -#define MIIMCFG_INIT_VALUE 0x00000003 +#define MIIMCFG_RESET_MGMT 0x80000000 +#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007 +#define MIIMCFG_INIT_VALUE 0x00000003 /* MII Management Command Register */ #define MIIMCOM_READ_CYCLE 0x00000001 diff --git a/include/fsl_validate.h b/include/fsl_validate.h index a62dc74e69..83efcf49ad 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -193,14 +193,18 @@ struct fsl_secboot_img_priv { */ struct fsl_secboot_sg_table sgtbl[MAX_SG_ENTRIES]; /* SG table */ - u32 ehdrloc; /* ESBC client location */ + uintptr_t ehdrloc; /* ESBC Header location */ + uintptr_t img_addr; /* ESBC Image Location */ + uint32_t img_size; /* ESBC Image Size */ }; -int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]); +int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, + uintptr_t img_loc); int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +int fsl_check_boot_mode_secure(void); +int fsl_setenv_chain_of_trust(void); #endif diff --git a/include/mmc.h b/include/mmc.h index 465daeb085..d652c1484e 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -479,6 +479,7 @@ void board_mmc_power_init(void); int board_mmc_init(bd_t *bis); int cpu_mmc_init(bd_t *bis); int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); +int mmc_get_env_dev(void); struct pci_device_id; diff --git a/include/net.h b/include/net.h index ac44d614ca..a739f45bbb 100644 --- a/include/net.h +++ b/include/net.h @@ -86,11 +86,13 @@ enum eth_state_t { * @iobase: The base address of the hardware registers * @enetaddr: The Ethernet MAC address that is loaded from EEPROM or env * @phy_interface: PHY interface to use - see PHY_INTERFACE_MODE_... + * @max_speed: Maximum speed of Ethernet connection supported by MAC */ struct eth_pdata { phys_addr_t iobase; unsigned char enetaddr[6]; int phy_interface; + int max_speed; }; enum eth_recv_flags { diff --git a/include/netdev.h b/include/netdev.h index de74b9a534..244f23f93c 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -80,11 +80,6 @@ int tsi108_eth_initialize(bd_t *bis); int uec_standard_init(bd_t *bis); int uli526x_initialize(bd_t *bis); int armada100_fec_register(unsigned long base_addr); -int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, - unsigned long dma_addr); -int xilinx_emaclite_of_init(const void *blob); -int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, - int txpp, int rxpp); int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags, unsigned long ctrl_addr); /* diff --git a/include/phy.h b/include/phy.h index 66cf61bdfb..09bbe483a4 100644 --- a/include/phy.h +++ b/include/phy.h @@ -17,18 +17,28 @@ #define PHY_MAX_ADDR 32 -#define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ - SUPPORTED_10baseT_Full | \ - SUPPORTED_100baseT_Half | \ - SUPPORTED_100baseT_Full | \ - SUPPORTED_Autoneg | \ +#define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */ + +#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \ SUPPORTED_TP | \ SUPPORTED_MII) -#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ - SUPPORTED_1000baseT_Half | \ +#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \ + SUPPORTED_10baseT_Full) + +#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \ + SUPPORTED_100baseT_Full) + +#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \ SUPPORTED_1000baseT_Full) +#define PHY_BASIC_FEATURES (PHY_10BT_FEATURES | \ + PHY_100BT_FEATURES | \ + PHY_DEFAULT_FEATURES) + +#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ + PHY_1000BT_FEATURES) + #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \ SUPPORTED_10000baseT_Full) @@ -226,6 +236,7 @@ int phy_startup(struct phy_device *phydev); int phy_config(struct phy_device *phydev); int phy_shutdown(struct phy_device *phydev); int phy_register(struct phy_driver *drv); +int phy_set_supported(struct phy_device *phydev, u32 max_speed); int genphy_config_aneg(struct phy_device *phydev); int genphy_restart_aneg(struct phy_device *phydev); int genphy_update_link(struct phy_device *phydev); diff --git a/include/tsec.h b/include/tsec.h index 1119d2cb60..fb27edf225 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -3,15 +3,12 @@ * * Driver for the Motorola Triple Speed Ethernet Controller * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * maintained by Xianghua Xiao (x.xiao@motorola.com) * author Andy Fleming * + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __TSEC_H @@ -21,6 +18,8 @@ #include <config.h> #include <phy.h> +#ifndef CONFIG_DM_ETH + #ifdef CONFIG_LS102XA #define TSEC_SIZE 0x40000 #define TSEC_MDIO_OFFSET 0x40000 @@ -67,11 +66,13 @@ x.mii_devname = DEFAULT_MII_NAME;\ } -#define MAC_ADDR_LEN 6 +#endif /* CONFIG_DM_ETH */ + +#define MAC_ADDR_LEN 6 /* #define TSEC_TIMEOUT 1000000 */ -#define TSEC_TIMEOUT 1000 -#define TOUT_LOOP 1000000 +#define TSEC_TIMEOUT 1000 +#define TOUT_LOOP 1000000 /* TBI register addresses */ #define TBI_CR 0x00 @@ -83,8 +84,8 @@ /* TBI MDIO register bit fields*/ #define TBICON_CLK_SELECT 0x0020 -#define TBIANA_ASYMMETRIC_PAUSE 0x0100 -#define TBIANA_SYMMETRIC_PAUSE 0x0080 +#define TBIANA_ASYMMETRIC_PAUSE 0x0100 +#define TBIANA_SYMMETRIC_PAUSE 0x0080 #define TBIANA_HALF_DUPLEX 0x0040 #define TBIANA_FULL_DUPLEX 0x0020 #define TBICR_PHY_RESET 0x8000 @@ -93,13 +94,12 @@ #define TBICR_FULL_DUPLEX 0x0100 #define TBICR_SPEED1_SET 0x0040 - /* MAC register bits */ #define MACCFG1_SOFT_RESET 0x80000000 #define MACCFG1_RESET_RX_MC 0x00080000 #define MACCFG1_RESET_TX_MC 0x00040000 #define MACCFG1_RESET_RX_FUN 0x00020000 -#define MACCFG1_RESET_TX_FUN 0x00010000 +#define MACCFG1_RESET_TX_FUN 0x00010000 #define MACCFG1_LOOPBACK 0x00000100 #define MACCFG1_RX_FLOW 0x00000020 #define MACCFG1_TX_FLOW 0x00000010 @@ -122,7 +122,7 @@ #define ECNTRL_SGMII_MODE 0x00000002 #ifndef CONFIG_SYS_TBIPA_VALUE - #define CONFIG_SYS_TBIPA_VALUE 0x1f +# define CONFIG_SYS_TBIPA_VALUE 0x1f #endif #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN @@ -137,7 +137,6 @@ #define TSTAT_CLEAR_THALT 0x80000000 #define RSTAT_CLEAR_RHALT 0x00800000 - #define IEVENT_INIT_CLEAR 0xffffffff #define IEVENT_BABR 0x80000000 #define IEVENT_RXC 0x40000000 @@ -164,11 +163,9 @@ #define IMASK_TXFEN 0x00100000 #define IMASK_RXFEN0 0x00000080 - /* Default Attribute fields */ -#define ATTR_INIT_SETTINGS 0x000000c0 -#define ATTRELI_INIT_SETTINGS 0x00000000 - +#define ATTR_INIT_SETTINGS 0x000000c0 +#define ATTRELI_INIT_SETTINGS 0x00000000 /* TxBD status field bits */ #define TXBD_READY 0x8000 @@ -181,7 +178,7 @@ #define TXBD_HUGEFRAME 0x0080 #define TXBD_LATECOLLISION 0x0080 #define TXBD_RETRYLIMIT 0x0040 -#define TXBD_RETRYCOUNTMASK 0x003c +#define TXBD_RETRYCOUNTMASK 0x003c #define TXBD_UNDERRUN 0x0002 #define TXBD_STATS 0x03ff @@ -204,15 +201,15 @@ #define RXBD_STATS 0x003f struct txbd8 { - uint16_t status; /* Status Fields */ - uint16_t length; /* Buffer length */ - uint32_t bufptr; /* Buffer Pointer */ + uint16_t status; /* Status Fields */ + uint16_t length; /* Buffer length */ + uint32_t bufptr; /* Buffer Pointer */ }; struct rxbd8 { - uint16_t status; /* Status Fields */ - uint16_t length; /* Buffer Length */ - uint32_t bufptr; /* Buffer Pointer */ + uint16_t status; /* Status Fields */ + uint16_t length; /* Buffer Length */ + uint32_t bufptr; /* Buffer Pointer */ }; struct tsec_rmon_mib { @@ -336,15 +333,15 @@ struct tsec { u32 rbdlen; /* RxBD Data Length */ u32 res310[4]; u32 res320; - u32 crbptr; /* Current Receive Buffer Pointer */ + u32 crbptr; /* Current Receive Buffer Pointer */ u32 res328[6]; - u32 mrblr; /* Maximum Receive Buffer Length */ + u32 mrblr; /* Maximum Receive Buffer Length */ u32 res344[16]; - u32 rbptr; /* RxBD Pointer */ + u32 rbptr; /* RxBD Pointer */ u32 res388[30]; /* (0x2_n400) */ u32 res400; - u32 rbase; /* RxBD Base Address */ + u32 rbase; /* RxBD Base Address */ u32 res408[62]; /* MAC Registers (0x2_n500) */ @@ -388,21 +385,33 @@ struct tsec { u32 resc00[256]; }; -#define TSEC_GIGABIT (1 << 0) +#define TSEC_GIGABIT (1 << 0) /* These flags currently only have meaning if we're using the eTSEC */ #define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */ #define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */ +#define TX_BUF_CNT 2 + struct tsec_private { + struct txbd8 __iomem txbd[TX_BUF_CNT]; + struct rxbd8 __iomem rxbd[PKTBUFSRX]; struct tsec __iomem *regs; struct tsec_mii_mng __iomem *phyregs_sgmii; struct phy_device *phydev; phy_interface_t interface; struct mii_dev *bus; uint phyaddr; + uint tbiaddr; char mii_devname[16]; u32 flags; + uint rx_idx; /* index of the current RX buffer */ + uint tx_idx; /* index of the current TX buffer */ +#ifndef CONFIG_DM_ETH + struct eth_device *dev; +#else + struct udevice *dev; +#endif }; struct tsec_info_struct { @@ -415,7 +424,9 @@ struct tsec_info_struct { u32 flags; }; +#ifndef CONFIG_DM_ETH int tsec_standard_init(bd_t *bis); int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num); +#endif #endif /* __TSEC_H */ diff --git a/include/video.h b/include/video.h index fa643ca5ab..c434bc71ae 100644 --- a/include/video.h +++ b/include/video.h @@ -49,8 +49,11 @@ enum video_log2_bpp { * * @xsize: Number of pixel columns (e.g. 1366) * @ysize: Number of pixels rows (e.g.. 768) - * @tor: Display rotation (0=none, 1=90 degrees clockwise, etc.) + * @rot: Display rotation (0=none, 1=90 degrees clockwise, etc.) * @bpix: Encoded bits per pixel + * @vidconsole_drv_name: Driver to use for the text console, NULL to + * select automatically + * @font_size: Font size in pixels (0 to use a default value) * @fb: Frame buffer * @fb_size: Frame buffer size * @line_length: Length of each frame buffer line, in bytes @@ -66,6 +69,8 @@ struct video_priv { ushort ysize; ushort rot; enum video_log2_bpp bpix; + const char *vidconsole_drv_name; + int font_size; /* * Things that are private to the uclass: don't use these in the diff --git a/include/video_console.h b/include/video_console.h index c0fc79273a..26047934da 100644 --- a/include/video_console.h +++ b/include/video_console.h @@ -7,21 +7,41 @@ #ifndef __video_console_h #define __video_console_h +#define VID_FRAC_DIV 256 + +#define VID_TO_PIXEL(x) ((x) / VID_FRAC_DIV) +#define VID_TO_POS(x) ((x) * VID_FRAC_DIV) + /** * struct vidconsole_priv - uclass-private data about a console device * + * Drivers must set up @rows, @cols, @x_charsize, @y_charsize in their probe() + * method. Drivers may set up @xstart_frac if desired. + * * @sdev: stdio device, acting as an output sink - * @curr_col: Current text column (0=left) - * @curr_row: Current row (0=top) + * @xcur_frac: Current X position, in fractional units (VID_TO_POS(x)) + * @curr_row: Current Y position in pixels (0=top) * @rows: Number of text rows * @cols: Number of text columns + * @x_charsize: Character width in pixels + * @y_charsize: Character height in pixels + * @tab_width_frac: Tab width in fractional units + * @xsize_frac: Width of the display in fractional units + * @xstart_frac: Left margin for the text console in fractional units + * @last_ch: Last character written to the text console on this line */ struct vidconsole_priv { struct stdio_dev sdev; - int curr_col; - int curr_row; + int xcur_frac; + int ycur; int rows; int cols; + int x_charsize; + int y_charsize; + int tab_width_frac; + int xsize_frac; + int xstart_frac; + int last_ch; }; /** @@ -36,12 +56,15 @@ struct vidconsole_ops { * putc_xy() - write a single character to a position * * @dev: Device to write to - * @x: Pixel X position (0=left-most pixel) + * @x_frac: Fractional pixel X position (0=left-most pixel) which + * is the X position multipled by VID_FRAC_DIV. * @y: Pixel Y position (0=top-most pixel) * @ch: Character to write - * @return 0 if OK, -ve on error + * @return number of fractional pixels that the cursor should move, + * if all is OK, -EAGAIN if we ran out of space on this line, other -ve + * on error */ - int (*putc_xy)(struct udevice *dev, uint x, uint y, char ch); + int (*putc_xy)(struct udevice *dev, uint x_frac, uint y, char ch); /** * move_rows() - Move text rows from one place to another @@ -66,6 +89,32 @@ struct vidconsole_ops { * @return 0 if OK, -ve on error */ int (*set_row)(struct udevice *dev, uint row, int clr); + + /** + * entry_start() - Indicate that text entry is starting afresh + * + * Consoles which use proportional fonts need to track the position of + * each character output so that backspace will return to the correct + * place. This method signals to the console driver that a new entry + * line is being start (e.g. the user pressed return to start a new + * command). The driver can use this signal to empty its list of + * positions. + */ + int (*entry_start)(struct udevice *dev); + + /** + * backspace() - Handle erasing the last character + * + * With proportional fonts the vidconsole uclass cannot itself erase + * the previous character. This optional method will be called when + * a backspace is needed. The driver should erase the previous + * character and update the cursor position (xcur_frac, ycur) to the + * start of the previous character. + * + * If not implement, default behaviour will work for fixed-width + * characters. + */ + int (*backspace)(struct udevice *dev); }; /* Get a pointer to the driver operations for a video console device */ @@ -75,10 +124,13 @@ struct vidconsole_ops { * vidconsole_putc_xy() - write a single character to a position * * @dev: Device to write to - * @x: Pixel X position (0=left-most pixel) + * @x_frac: Fractional pixel X position (0=left-most pixel) which + * is the X position multipled by VID_FRAC_DIV. * @y: Pixel Y position (0=top-most pixel) * @ch: Character to write - * @return 0 if OK, -ve on error + * @return number of fractional pixels that the cursor should move, + * if all is OK, -EAGAIN if we ran out of space on this line, other -ve + * on error */ int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, char ch); diff --git a/include/vsc9953.h b/include/vsc9953.h index cd5cfc76b0..a2d4554c3b 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -126,6 +126,7 @@ #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100 #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200 #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400 +#define VSC9953_PORT_CFG_PORTID_MASK 0x0000003c /* Macros for vsc9953_qsys_sys.switch_port_mode register */ #define VSC9953_PORT_ENA 0x00002000 @@ -136,6 +137,9 @@ /* Macros for vsc9953_ana_ana.adv_learn register */ #define VSC9953_VLAN_CHK 0x00000400 +/* Macros for vsc9953_ana_ana.auto_age register */ +#define VSC9953_AUTOAGE_PERIOD_MASK 0x001ffffe + /* Macros for vsc9953_rew_port.port_tag_cfg register */ #define VSC9953_TAG_CFG_MASK 0x00000180 #define VSC9953_TAG_CFG_NONE 0x00000000 @@ -153,6 +157,19 @@ /* Macros for vsc9953_ana_ana_tables.mach_data register */ #define VSC9953_MACHDATA_VID_MASK 0x1fff0000 +/* Macros for vsc9953_ana_common.aggr_cfg register */ +#define VSC9953_AC_RND_ENA 0x00000080 +#define VSC9953_AC_DMAC_ENA 0x00000040 +#define VSC9953_AC_SMAC_ENA 0x00000020 +#define VSC9953_AC_IP6_LBL_ENA 0x00000010 +#define VSC9953_AC_IP6_TCPUDP_ENA 0x00000008 +#define VSC9953_AC_IP4_SIPDIP_ENA 0x00000004 +#define VSC9953_AC_IP4_TCPUDP_ENA 0x00000002 +#define VSC9953_AC_MASK 0x000000fe + +/* Macros for vsc9953_ana_pgid.port_grp_id[] registers */ +#define VSC9953_PGID_PORT_MASK 0x000003ff + #define VSC9953_MAX_PORTS 10 #define VSC9953_PORT_CHECK(port) \ (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) @@ -164,6 +181,7 @@ #define VSC9953_MAX_VLAN 4096 #define VSC9953_VLAN_CHECK(vid) \ (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1) +#define VSC9953_DEFAULT_AGE_TIME 300 #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" @@ -235,6 +253,10 @@ struct vsc9953_ana_ana { u32 port_mode[12]; }; +#define PGID_DST_START 0 +#define PGID_AGGR_START 64 +#define PGID_SRC_START 80 + struct vsc9953_ana_pgid { u32 port_grp_id[91]; }; @@ -269,7 +291,7 @@ struct vsc9953_analyzer { struct vsc9953_ana_ana_tables ana_tables; u32 reserved2[14]; struct vsc9953_ana_ana ana; - u32 reserved3[22]; + u32 reserved3[21]; struct vsc9953_ana_pgid port_id_tbl; u32 reserved4[549]; struct vsc9953_ana_pfc pfc[10]; diff --git a/include/winbond_w83627.h b/include/winbond_w83627.h new file mode 100644 index 0000000000..ac3bec6f9f --- /dev/null +++ b/include/winbond_w83627.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _WINBOND_W83627_H_ +#define _WINBOND_W83627_H_ + +/* I/O address of Winbond Super IO chip */ +#define WINBOND_IO_PORT 0x2e + +/* Logical device number */ +#define W83627DHG_FDC 0 /* Floppy */ +#define W83627DHG_PP 1 /* Parallel port */ +#define W83627DHG_SP1 2 /* Com1 */ +#define W83627DHG_SP2 3 /* Com2 */ +#define W83627DHG_KBC 5 /* PS/2 keyboard & mouse */ +#define W83627DHG_SPI 6 /* Serial peripheral interface */ +#define W83627DHG_WDTO_PLED 8 /* WDTO#, PLED */ +#define W83627DHG_ACPI 10 /* ACPI */ +#define W83627DHG_HWM 11 /* Hardware monitor */ +#define W83627DHG_PECI_SST 12 /* PECI, SST */ + +/** + * Configure the base I/O port of the specified serial device and enable the + * serial device. + * + * @dev: high 8 bits = super I/O port, low 8 bits = logical device number + * @iobase: processor I/O port address to assign to this serial device + * @irq: processor IRQ number to assign to this serial device + */ +void winbond_enable_serial(uint dev, uint iobase, uint irq); + +#endif /* _WINBOND_W83627_H_ */ @@ -262,7 +262,7 @@ int tpm_init(void) struct udevice *dev; err = uclass_first_device(UCLASS_TPM, &dev); - if (err) + if (err || !dev) return err; return tpm_open(dev); } diff --git a/net/Makefile b/net/Makefile index e9cc8ada96..f03d608326 100644 --- a/net/Makefile +++ b/net/Makefile @@ -12,7 +12,12 @@ obj-$(CONFIG_CMD_NET) += arp.o obj-$(CONFIG_CMD_NET) += bootp.o obj-$(CONFIG_CMD_CDP) += cdp.o obj-$(CONFIG_CMD_DNS) += dns.o -obj-$(CONFIG_CMD_NET) += eth.o +ifdef CONFIG_DM_ETH +obj-$(CONFIG_CMD_NET) += eth-uclass.o +else +obj-$(CONFIG_CMD_NET) += eth_legacy.o +endif +obj-$(CONFIG_CMD_NET) += eth_common.o obj-$(CONFIG_CMD_LINK_LOCAL) += link_local.o obj-$(CONFIG_CMD_NET) += net.o obj-$(CONFIG_CMD_NFS) += nfs.o diff --git a/net/bootp.c b/net/bootp.c index 8aeddb08ea..f2978a23ce 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -949,6 +949,7 @@ static void dhcp_send_request_packet(struct bootp_hdr *bp_offer) net_write_ip(&bp->bp_giaddr, zero_ip); memcpy(bp->bp_chaddr, net_ethaddr, 6); + copy_filename(bp->bp_file, net_boot_file_name, sizeof(bp->bp_file)); /* * ID is the id of the OFFER packet @@ -995,6 +996,9 @@ static void dhcp_handler(uchar *pkt, unsigned dest, struct in_addr sip, debug("DHCPHandler: got DHCP packet: (src=%d, dst=%d, len=%d) state: " "%d\n", src, dest, len, dhcp_state); + if (net_read_ip(&bp->bp_yiaddr).s_addr == 0) + return; + switch (dhcp_state) { case SELECTING: /* diff --git a/net/eth.c b/net/eth-uclass.c index 45fe6e3c1c..a356a08826 100644 --- a/net/eth.c +++ b/net/eth-uclass.c @@ -7,113 +7,13 @@ */ #include <common.h> -#include <command.h> #include <dm.h> #include <environment.h> #include <net.h> -#include <miiphy.h> -#include <phy.h> -#include <asm/errno.h> #include <dm/device-internal.h> #include <dm/uclass-internal.h> +#include "eth_internal.h" -DECLARE_GLOBAL_DATA_PTR; - -void eth_parse_enetaddr(const char *addr, uchar *enetaddr) -{ - char *end; - int i; - - for (i = 0; i < 6; ++i) { - enetaddr[i] = addr ? simple_strtoul(addr, &end, 16) : 0; - if (addr) - addr = (*end) ? end + 1 : end; - } -} - -int eth_getenv_enetaddr(const char *name, uchar *enetaddr) -{ - eth_parse_enetaddr(getenv(name), enetaddr); - return is_valid_ethaddr(enetaddr); -} - -int eth_setenv_enetaddr(const char *name, const uchar *enetaddr) -{ - char buf[20]; - - sprintf(buf, "%pM", enetaddr); - - return setenv(name, buf); -} - -int eth_getenv_enetaddr_by_index(const char *base_name, int index, - uchar *enetaddr) -{ - char enetvar[32]; - sprintf(enetvar, index ? "%s%daddr" : "%saddr", base_name, index); - return eth_getenv_enetaddr(enetvar, enetaddr); -} - -static inline int eth_setenv_enetaddr_by_index(const char *base_name, int index, - uchar *enetaddr) -{ - char enetvar[32]; - sprintf(enetvar, index ? "%s%daddr" : "%saddr", base_name, index); - return eth_setenv_enetaddr(enetvar, enetaddr); -} - -static int eth_mac_skip(int index) -{ - char enetvar[15]; - char *skip_state; - - sprintf(enetvar, index ? "eth%dmacskip" : "ethmacskip", index); - skip_state = getenv(enetvar); - return skip_state != NULL; -} - -static void eth_current_changed(void); - -/* - * CPU and board-specific Ethernet initializations. Aliased function - * signals caller to move on - */ -static int __def_eth_init(bd_t *bis) -{ - return -1; -} -int cpu_eth_init(bd_t *bis) __attribute__((weak, alias("__def_eth_init"))); -int board_eth_init(bd_t *bis) __attribute__((weak, alias("__def_eth_init"))); - -static void eth_common_init(void) -{ - bootstage_mark(BOOTSTAGE_ID_NET_ETH_START); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) - miiphy_init(); -#endif - -#ifdef CONFIG_PHYLIB - phy_init(); -#endif - - /* - * If board-specific initialization exists, call it. - * If not, call a CPU-specific one - */ - if (board_eth_init != __def_eth_init) { - if (board_eth_init(gd->bd) < 0) - printf("Board Net Initialization Failed\n"); - } else if (cpu_eth_init != __def_eth_init) { - if (cpu_eth_init(gd->bd) < 0) - printf("CPU Net Initialization Failed\n"); - } else { -#ifndef CONFIG_DM_ETH - printf("Net Initialization Skipped\n"); -#endif - } -} - -#ifdef CONFIG_DM_ETH /** * struct eth_device_priv - private structure for each Ethernet device * @@ -144,7 +44,7 @@ static struct eth_uclass_priv *eth_get_uclass_priv(void) return uc->priv; } -static void eth_set_current_to_next(void) +void eth_set_current_to_next(void) { struct eth_uclass_priv *uc_priv; @@ -177,7 +77,7 @@ struct udevice *eth_get_dev(void) * In case it was not probed, we will attempt to do so. * dev may be NULL to unset the active device. */ -static void eth_set_dev(struct udevice *dev) +void eth_set_dev(struct udevice *dev) { if (dev && !device_active(dev)) { eth_errno = device_probe(dev); @@ -647,493 +547,3 @@ UCLASS_DRIVER(eth) = { .per_device_auto_alloc_size = sizeof(struct eth_device_priv), .flags = DM_UC_FLAG_SEQ_ALIAS, }; -#endif /* #ifdef CONFIG_DM_ETH */ - -#ifndef CONFIG_DM_ETH - -#ifdef CONFIG_API -static struct { - uchar data[PKTSIZE]; - int length; -} eth_rcv_bufs[PKTBUFSRX]; - -static unsigned int eth_rcv_current, eth_rcv_last; -#endif - -static struct eth_device *eth_devices; -struct eth_device *eth_current; - -static void eth_set_current_to_next(void) -{ - eth_current = eth_current->next; -} - -static void eth_set_dev(struct eth_device *dev) -{ - eth_current = dev; -} - -struct eth_device *eth_get_dev_by_name(const char *devname) -{ - struct eth_device *dev, *target_dev; - - BUG_ON(devname == NULL); - - if (!eth_devices) - return NULL; - - dev = eth_devices; - target_dev = NULL; - do { - if (strcmp(devname, dev->name) == 0) { - target_dev = dev; - break; - } - dev = dev->next; - } while (dev != eth_devices); - - return target_dev; -} - -struct eth_device *eth_get_dev_by_index(int index) -{ - struct eth_device *dev, *target_dev; - - if (!eth_devices) - return NULL; - - dev = eth_devices; - target_dev = NULL; - do { - if (dev->index == index) { - target_dev = dev; - break; - } - dev = dev->next; - } while (dev != eth_devices); - - return target_dev; -} - -int eth_get_dev_index(void) -{ - if (!eth_current) - return -1; - - return eth_current->index; -} - -static int on_ethaddr(const char *name, const char *value, enum env_op op, - int flags) -{ - int index; - struct eth_device *dev; - - if (!eth_devices) - return 0; - - /* look for an index after "eth" */ - index = simple_strtoul(name + 3, NULL, 10); - - dev = eth_devices; - do { - if (dev->index == index) { - switch (op) { - case env_op_create: - case env_op_overwrite: - eth_parse_enetaddr(value, dev->enetaddr); - break; - case env_op_delete: - memset(dev->enetaddr, 0, 6); - } - } - dev = dev->next; - } while (dev != eth_devices); - - return 0; -} -U_BOOT_ENV_CALLBACK(ethaddr, on_ethaddr); - -int eth_write_hwaddr(struct eth_device *dev, const char *base_name, - int eth_number) -{ - unsigned char env_enetaddr[6]; - int ret = 0; - - eth_getenv_enetaddr_by_index(base_name, eth_number, env_enetaddr); - - if (!is_zero_ethaddr(env_enetaddr)) { - if (!is_zero_ethaddr(dev->enetaddr) && - memcmp(dev->enetaddr, env_enetaddr, 6)) { - printf("\nWarning: %s MAC addresses don't match:\n", - dev->name); - printf("Address in SROM is %pM\n", - dev->enetaddr); - printf("Address in environment is %pM\n", - env_enetaddr); - } - - memcpy(dev->enetaddr, env_enetaddr, 6); - } else if (is_valid_ethaddr(dev->enetaddr)) { - eth_setenv_enetaddr_by_index(base_name, eth_number, - dev->enetaddr); - } else if (is_zero_ethaddr(dev->enetaddr)) { -#ifdef CONFIG_NET_RANDOM_ETHADDR - net_random_ethaddr(dev->enetaddr); - printf("\nWarning: %s (eth%d) using random MAC address - %pM\n", - dev->name, eth_number, dev->enetaddr); -#else - printf("\nError: %s address not set.\n", - dev->name); - return -EINVAL; -#endif - } - - if (dev->write_hwaddr && !eth_mac_skip(eth_number)) { - if (!is_valid_ethaddr(dev->enetaddr)) { - printf("\nError: %s address %pM illegal value\n", - dev->name, dev->enetaddr); - return -EINVAL; - } - - ret = dev->write_hwaddr(dev); - if (ret) - printf("\nWarning: %s failed to set MAC address\n", - dev->name); - } - - return ret; -} - -int eth_register(struct eth_device *dev) -{ - struct eth_device *d; - static int index; - - assert(strlen(dev->name) < sizeof(dev->name)); - - if (!eth_devices) { - eth_devices = dev; - eth_current = dev; - eth_current_changed(); - } else { - for (d = eth_devices; d->next != eth_devices; d = d->next) - ; - d->next = dev; - } - - dev->state = ETH_STATE_INIT; - dev->next = eth_devices; - dev->index = index++; - - return 0; -} - -int eth_unregister(struct eth_device *dev) -{ - struct eth_device *cur; - - /* No device */ - if (!eth_devices) - return -ENODEV; - - for (cur = eth_devices; cur->next != eth_devices && cur->next != dev; - cur = cur->next) - ; - - /* Device not found */ - if (cur->next != dev) - return -ENODEV; - - cur->next = dev->next; - - if (eth_devices == dev) - eth_devices = dev->next == eth_devices ? NULL : dev->next; - - if (eth_current == dev) { - eth_current = eth_devices; - eth_current_changed(); - } - - return 0; -} - -int eth_initialize(void) -{ - int num_devices = 0; - - eth_devices = NULL; - eth_current = NULL; - eth_common_init(); - - if (!eth_devices) { - puts("No ethernet found.\n"); - bootstage_error(BOOTSTAGE_ID_NET_ETH_START); - } else { - struct eth_device *dev = eth_devices; - char *ethprime = getenv("ethprime"); - - bootstage_mark(BOOTSTAGE_ID_NET_ETH_INIT); - do { - if (dev->index) - puts(", "); - - printf("%s", dev->name); - - if (ethprime && strcmp(dev->name, ethprime) == 0) { - eth_current = dev; - puts(" [PRIME]"); - } - - if (strchr(dev->name, ' ')) - puts("\nWarning: eth device name has a space!" - "\n"); - - eth_write_hwaddr(dev, "eth", dev->index); - - dev = dev->next; - num_devices++; - } while (dev != eth_devices); - - eth_current_changed(); - putc('\n'); - } - - return num_devices; -} - -#ifdef CONFIG_MCAST_TFTP -/* Multicast. - * mcast_addr: multicast ipaddr from which multicast Mac is made - * join: 1=join, 0=leave. - */ -int eth_mcast_join(struct in_addr mcast_ip, int join) -{ - u8 mcast_mac[6]; - if (!eth_current || !eth_current->mcast) - return -1; - mcast_mac[5] = htonl(mcast_ip.s_addr) & 0xff; - mcast_mac[4] = (htonl(mcast_ip.s_addr)>>8) & 0xff; - mcast_mac[3] = (htonl(mcast_ip.s_addr)>>16) & 0x7f; - mcast_mac[2] = 0x5e; - mcast_mac[1] = 0x0; - mcast_mac[0] = 0x1; - return eth_current->mcast(eth_current, mcast_mac, join); -} - -/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c - * and this is the ethernet-crc method needed for TSEC -- and perhaps - * some other adapter -- hash tables - */ -#define CRCPOLY_LE 0xedb88320 -u32 ether_crc(size_t len, unsigned char const *p) -{ - int i; - u32 crc; - crc = ~0; - while (len--) { - crc ^= *p++; - for (i = 0; i < 8; i++) - crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0); - } - /* an reverse the bits, cuz of way they arrive -- last-first */ - crc = (crc >> 16) | (crc << 16); - crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00); - crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0); - crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc); - crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa); - return crc; -} - -#endif - - -int eth_init(void) -{ - struct eth_device *old_current; - - if (!eth_current) { - puts("No ethernet found.\n"); - return -ENODEV; - } - - old_current = eth_current; - do { - debug("Trying %s\n", eth_current->name); - - if (eth_current->init(eth_current, gd->bd) >= 0) { - eth_current->state = ETH_STATE_ACTIVE; - - return 0; - } - debug("FAIL\n"); - - eth_try_another(0); - } while (old_current != eth_current); - - return -ETIMEDOUT; -} - -void eth_halt(void) -{ - if (!eth_current) - return; - - eth_current->halt(eth_current); - - eth_current->state = ETH_STATE_PASSIVE; -} - -int eth_is_active(struct eth_device *dev) -{ - return dev && dev->state == ETH_STATE_ACTIVE; -} - -int eth_send(void *packet, int length) -{ - if (!eth_current) - return -ENODEV; - - return eth_current->send(eth_current, packet, length); -} - -int eth_rx(void) -{ - if (!eth_current) - return -ENODEV; - - return eth_current->recv(eth_current); -} -#endif /* ifndef CONFIG_DM_ETH */ - -#ifdef CONFIG_API -static void eth_save_packet(void *packet, int length) -{ - char *p = packet; - int i; - - if ((eth_rcv_last+1) % PKTBUFSRX == eth_rcv_current) - return; - - if (PKTSIZE < length) - return; - - for (i = 0; i < length; i++) - eth_rcv_bufs[eth_rcv_last].data[i] = p[i]; - - eth_rcv_bufs[eth_rcv_last].length = length; - eth_rcv_last = (eth_rcv_last + 1) % PKTBUFSRX; -} - -int eth_receive(void *packet, int length) -{ - char *p = packet; - void *pp = push_packet; - int i; - - if (eth_rcv_current == eth_rcv_last) { - push_packet = eth_save_packet; - eth_rx(); - push_packet = pp; - - if (eth_rcv_current == eth_rcv_last) - return -1; - } - - length = min(eth_rcv_bufs[eth_rcv_current].length, length); - - for (i = 0; i < length; i++) - p[i] = eth_rcv_bufs[eth_rcv_current].data[i]; - - eth_rcv_current = (eth_rcv_current + 1) % PKTBUFSRX; - return length; -} -#endif /* CONFIG_API */ - -static void eth_current_changed(void) -{ - char *act = getenv("ethact"); - char *ethrotate; - - /* - * The call to eth_get_dev() below has a side effect of rotating - * ethernet device if uc_priv->current == NULL. This is not what - * we want when 'ethrotate' variable is 'no'. - */ - ethrotate = getenv("ethrotate"); - if ((ethrotate != NULL) && (strcmp(ethrotate, "no") == 0)) - return; - - /* update current ethernet name */ - if (eth_get_dev()) { - if (act == NULL || strcmp(act, eth_get_name()) != 0) - setenv("ethact", eth_get_name()); - } - /* - * remove the variable completely if there is no active - * interface - */ - else if (act != NULL) - setenv("ethact", NULL); -} - -void eth_try_another(int first_restart) -{ - static void *first_failed; - char *ethrotate; - - /* - * Do not rotate between network interfaces when - * 'ethrotate' variable is set to 'no'. - */ - ethrotate = getenv("ethrotate"); - if ((ethrotate != NULL) && (strcmp(ethrotate, "no") == 0)) - return; - - if (!eth_get_dev()) - return; - - if (first_restart) - first_failed = eth_get_dev(); - - eth_set_current_to_next(); - - eth_current_changed(); - - if (first_failed == eth_get_dev()) - net_restart_wrap = 1; -} - -void eth_set_current(void) -{ - static char *act; - static int env_changed_id; - int env_id; - - env_id = get_env_id(); - if ((act == NULL) || (env_changed_id != env_id)) { - act = getenv("ethact"); - env_changed_id = env_id; - } - - if (act == NULL) { - char *ethprime = getenv("ethprime"); - void *dev = NULL; - - if (ethprime) - dev = eth_get_dev_by_name(ethprime); - if (dev) - eth_set_dev(dev); - else - eth_set_dev(NULL); - } else { - eth_set_dev(eth_get_dev_by_name(act)); - } - - eth_current_changed(); -} - -const char *eth_get_name(void) -{ - return eth_get_dev() ? eth_get_dev()->name : "unknown"; -} diff --git a/net/eth_common.c b/net/eth_common.c new file mode 100644 index 0000000000..288090155e --- /dev/null +++ b/net/eth_common.c @@ -0,0 +1,166 @@ +/* + * (C) Copyright 2001-2015 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Joe Hershberger, National Instruments + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <miiphy.h> +#include <net.h> +#include "eth_internal.h" + +void eth_parse_enetaddr(const char *addr, uchar *enetaddr) +{ + char *end; + int i; + + for (i = 0; i < 6; ++i) { + enetaddr[i] = addr ? simple_strtoul(addr, &end, 16) : 0; + if (addr) + addr = (*end) ? end + 1 : end; + } +} + +int eth_getenv_enetaddr(const char *name, uchar *enetaddr) +{ + eth_parse_enetaddr(getenv(name), enetaddr); + return is_valid_ethaddr(enetaddr); +} + +int eth_setenv_enetaddr(const char *name, const uchar *enetaddr) +{ + char buf[20]; + + sprintf(buf, "%pM", enetaddr); + + return setenv(name, buf); +} + +int eth_getenv_enetaddr_by_index(const char *base_name, int index, + uchar *enetaddr) +{ + char enetvar[32]; + sprintf(enetvar, index ? "%s%daddr" : "%saddr", base_name, index); + return eth_getenv_enetaddr(enetvar, enetaddr); +} + +int eth_setenv_enetaddr_by_index(const char *base_name, int index, + uchar *enetaddr) +{ + char enetvar[32]; + sprintf(enetvar, index ? "%s%daddr" : "%saddr", base_name, index); + return eth_setenv_enetaddr(enetvar, enetaddr); +} + +void eth_common_init(void) +{ + bootstage_mark(BOOTSTAGE_ID_NET_ETH_START); +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) + miiphy_init(); +#endif + +#ifdef CONFIG_PHYLIB + phy_init(); +#endif +} + +int eth_mac_skip(int index) +{ + char enetvar[15]; + char *skip_state; + + sprintf(enetvar, index ? "eth%dmacskip" : "ethmacskip", index); + skip_state = getenv(enetvar); + return skip_state != NULL; +} + +void eth_current_changed(void) +{ + char *act = getenv("ethact"); + char *ethrotate; + + /* + * The call to eth_get_dev() below has a side effect of rotating + * ethernet device if uc_priv->current == NULL. This is not what + * we want when 'ethrotate' variable is 'no'. + */ + ethrotate = getenv("ethrotate"); + if ((ethrotate != NULL) && (strcmp(ethrotate, "no") == 0)) + return; + + /* update current ethernet name */ + if (eth_get_dev()) { + if (act == NULL || strcmp(act, eth_get_name()) != 0) + setenv("ethact", eth_get_name()); + } + /* + * remove the variable completely if there is no active + * interface + */ + else if (act != NULL) + setenv("ethact", NULL); +} + +void eth_try_another(int first_restart) +{ + static void *first_failed; + char *ethrotate; + + /* + * Do not rotate between network interfaces when + * 'ethrotate' variable is set to 'no'. + */ + ethrotate = getenv("ethrotate"); + if ((ethrotate != NULL) && (strcmp(ethrotate, "no") == 0)) + return; + + if (!eth_get_dev()) + return; + + if (first_restart) + first_failed = eth_get_dev(); + + eth_set_current_to_next(); + + eth_current_changed(); + + if (first_failed == eth_get_dev()) + net_restart_wrap = 1; +} + +void eth_set_current(void) +{ + static char *act; + static int env_changed_id; + int env_id; + + env_id = get_env_id(); + if ((act == NULL) || (env_changed_id != env_id)) { + act = getenv("ethact"); + env_changed_id = env_id; + } + + if (act == NULL) { + char *ethprime = getenv("ethprime"); + void *dev = NULL; + + if (ethprime) + dev = eth_get_dev_by_name(ethprime); + if (dev) + eth_set_dev(dev); + else + eth_set_dev(NULL); + } else { + eth_set_dev(eth_get_dev_by_name(act)); + } + + eth_current_changed(); +} + +const char *eth_get_name(void) +{ + return eth_get_dev() ? eth_get_dev()->name : "unknown"; +} diff --git a/net/eth_internal.h b/net/eth_internal.h new file mode 100644 index 0000000000..6e4753cd0d --- /dev/null +++ b/net/eth_internal.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2001-2015 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Joe Hershberger, National Instruments + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ETH_INTERNAL_H +#define __ETH_INTERNAL_H + +/* Do init that is common to driver model and legacy networking */ +void eth_common_init(void); + +/** + * eth_setenv_enetaddr_by_index() - set the MAC address envrionment variable + * + * This sets up an environment variable with the given MAC address (@enetaddr). + * The environment variable to be set is defined by <@base_name><@index>addr. + * If @index is 0 it is omitted. For common Ethernet this means ethaddr, + * eth1addr, etc. + * + * @base_name: Base name for variable, typically "eth" + * @index: Index of interface being updated (>=0) + * @enetaddr: Pointer to MAC address to put into the variable + * @return 0 if OK, other value on error + */ +int eth_setenv_enetaddr_by_index(const char *base_name, int index, + uchar *enetaddr); + +int eth_mac_skip(int index); +void eth_current_changed(void); +#ifdef CONFIG_DM_ETH +void eth_set_dev(struct udevice *dev); +#else +void eth_set_dev(struct eth_device *dev); +#endif +void eth_set_current_to_next(void); + +#endif diff --git a/net/eth_legacy.c b/net/eth_legacy.c new file mode 100644 index 0000000000..bdcd6eaafc --- /dev/null +++ b/net/eth_legacy.c @@ -0,0 +1,439 @@ +/* + * (C) Copyright 2001-2015 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Joe Hershberger, National Instruments + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <environment.h> +#include <net.h> +#include <phy.h> +#include <asm/errno.h> +#include "eth_internal.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * CPU and board-specific Ethernet initializations. Aliased function + * signals caller to move on + */ +static int __def_eth_init(bd_t *bis) +{ + return -1; +} +int cpu_eth_init(bd_t *bis) __attribute__((weak, alias("__def_eth_init"))); +int board_eth_init(bd_t *bis) __attribute__((weak, alias("__def_eth_init"))); + +#ifdef CONFIG_API +static struct { + uchar data[PKTSIZE]; + int length; +} eth_rcv_bufs[PKTBUFSRX]; + +static unsigned int eth_rcv_current, eth_rcv_last; +#endif + +static struct eth_device *eth_devices; +struct eth_device *eth_current; + +void eth_set_current_to_next(void) +{ + eth_current = eth_current->next; +} + +void eth_set_dev(struct eth_device *dev) +{ + eth_current = dev; +} + +struct eth_device *eth_get_dev_by_name(const char *devname) +{ + struct eth_device *dev, *target_dev; + + BUG_ON(devname == NULL); + + if (!eth_devices) + return NULL; + + dev = eth_devices; + target_dev = NULL; + do { + if (strcmp(devname, dev->name) == 0) { + target_dev = dev; + break; + } + dev = dev->next; + } while (dev != eth_devices); + + return target_dev; +} + +struct eth_device *eth_get_dev_by_index(int index) +{ + struct eth_device *dev, *target_dev; + + if (!eth_devices) + return NULL; + + dev = eth_devices; + target_dev = NULL; + do { + if (dev->index == index) { + target_dev = dev; + break; + } + dev = dev->next; + } while (dev != eth_devices); + + return target_dev; +} + +int eth_get_dev_index(void) +{ + if (!eth_current) + return -1; + + return eth_current->index; +} + +static int on_ethaddr(const char *name, const char *value, enum env_op op, + int flags) +{ + int index; + struct eth_device *dev; + + if (!eth_devices) + return 0; + + /* look for an index after "eth" */ + index = simple_strtoul(name + 3, NULL, 10); + + dev = eth_devices; + do { + if (dev->index == index) { + switch (op) { + case env_op_create: + case env_op_overwrite: + eth_parse_enetaddr(value, dev->enetaddr); + break; + case env_op_delete: + memset(dev->enetaddr, 0, 6); + } + } + dev = dev->next; + } while (dev != eth_devices); + + return 0; +} +U_BOOT_ENV_CALLBACK(ethaddr, on_ethaddr); + +int eth_write_hwaddr(struct eth_device *dev, const char *base_name, + int eth_number) +{ + unsigned char env_enetaddr[6]; + int ret = 0; + + eth_getenv_enetaddr_by_index(base_name, eth_number, env_enetaddr); + + if (!is_zero_ethaddr(env_enetaddr)) { + if (!is_zero_ethaddr(dev->enetaddr) && + memcmp(dev->enetaddr, env_enetaddr, 6)) { + printf("\nWarning: %s MAC addresses don't match:\n", + dev->name); + printf("Address in SROM is %pM\n", + dev->enetaddr); + printf("Address in environment is %pM\n", + env_enetaddr); + } + + memcpy(dev->enetaddr, env_enetaddr, 6); + } else if (is_valid_ethaddr(dev->enetaddr)) { + eth_setenv_enetaddr_by_index(base_name, eth_number, + dev->enetaddr); + } else if (is_zero_ethaddr(dev->enetaddr)) { +#ifdef CONFIG_NET_RANDOM_ETHADDR + net_random_ethaddr(dev->enetaddr); + printf("\nWarning: %s (eth%d) using random MAC address - %pM\n", + dev->name, eth_number, dev->enetaddr); +#else + printf("\nError: %s address not set.\n", + dev->name); + return -EINVAL; +#endif + } + + if (dev->write_hwaddr && !eth_mac_skip(eth_number)) { + if (!is_valid_ethaddr(dev->enetaddr)) { + printf("\nError: %s address %pM illegal value\n", + dev->name, dev->enetaddr); + return -EINVAL; + } + + ret = dev->write_hwaddr(dev); + if (ret) + printf("\nWarning: %s failed to set MAC address\n", + dev->name); + } + + return ret; +} + +int eth_register(struct eth_device *dev) +{ + struct eth_device *d; + static int index; + + assert(strlen(dev->name) < sizeof(dev->name)); + + if (!eth_devices) { + eth_devices = dev; + eth_current = dev; + eth_current_changed(); + } else { + for (d = eth_devices; d->next != eth_devices; d = d->next) + ; + d->next = dev; + } + + dev->state = ETH_STATE_INIT; + dev->next = eth_devices; + dev->index = index++; + + return 0; +} + +int eth_unregister(struct eth_device *dev) +{ + struct eth_device *cur; + + /* No device */ + if (!eth_devices) + return -ENODEV; + + for (cur = eth_devices; cur->next != eth_devices && cur->next != dev; + cur = cur->next) + ; + + /* Device not found */ + if (cur->next != dev) + return -ENODEV; + + cur->next = dev->next; + + if (eth_devices == dev) + eth_devices = dev->next == eth_devices ? NULL : dev->next; + + if (eth_current == dev) { + eth_current = eth_devices; + eth_current_changed(); + } + + return 0; +} + +int eth_initialize(void) +{ + int num_devices = 0; + + eth_devices = NULL; + eth_current = NULL; + eth_common_init(); + /* + * If board-specific initialization exists, call it. + * If not, call a CPU-specific one + */ + if (board_eth_init != __def_eth_init) { + if (board_eth_init(gd->bd) < 0) + printf("Board Net Initialization Failed\n"); + } else if (cpu_eth_init != __def_eth_init) { + if (cpu_eth_init(gd->bd) < 0) + printf("CPU Net Initialization Failed\n"); + } else { + printf("Net Initialization Skipped\n"); + } + + if (!eth_devices) { + puts("No ethernet found.\n"); + bootstage_error(BOOTSTAGE_ID_NET_ETH_START); + } else { + struct eth_device *dev = eth_devices; + char *ethprime = getenv("ethprime"); + + bootstage_mark(BOOTSTAGE_ID_NET_ETH_INIT); + do { + if (dev->index) + puts(", "); + + printf("%s", dev->name); + + if (ethprime && strcmp(dev->name, ethprime) == 0) { + eth_current = dev; + puts(" [PRIME]"); + } + + if (strchr(dev->name, ' ')) + puts("\nWarning: eth device name has a space!" + "\n"); + + eth_write_hwaddr(dev, "eth", dev->index); + + dev = dev->next; + num_devices++; + } while (dev != eth_devices); + + eth_current_changed(); + putc('\n'); + } + + return num_devices; +} + +#ifdef CONFIG_MCAST_TFTP +/* Multicast. + * mcast_addr: multicast ipaddr from which multicast Mac is made + * join: 1=join, 0=leave. + */ +int eth_mcast_join(struct in_addr mcast_ip, int join) +{ + u8 mcast_mac[6]; + if (!eth_current || !eth_current->mcast) + return -1; + mcast_mac[5] = htonl(mcast_ip.s_addr) & 0xff; + mcast_mac[4] = (htonl(mcast_ip.s_addr)>>8) & 0xff; + mcast_mac[3] = (htonl(mcast_ip.s_addr)>>16) & 0x7f; + mcast_mac[2] = 0x5e; + mcast_mac[1] = 0x0; + mcast_mac[0] = 0x1; + return eth_current->mcast(eth_current, mcast_mac, join); +} + +/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c + * and this is the ethernet-crc method needed for TSEC -- and perhaps + * some other adapter -- hash tables + */ +#define CRCPOLY_LE 0xedb88320 +u32 ether_crc(size_t len, unsigned char const *p) +{ + int i; + u32 crc; + crc = ~0; + while (len--) { + crc ^= *p++; + for (i = 0; i < 8; i++) + crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0); + } + /* an reverse the bits, cuz of way they arrive -- last-first */ + crc = (crc >> 16) | (crc << 16); + crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00); + crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0); + crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc); + crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa); + return crc; +} + +#endif + + +int eth_init(void) +{ + struct eth_device *old_current; + + if (!eth_current) { + puts("No ethernet found.\n"); + return -ENODEV; + } + + old_current = eth_current; + do { + debug("Trying %s\n", eth_current->name); + + if (eth_current->init(eth_current, gd->bd) >= 0) { + eth_current->state = ETH_STATE_ACTIVE; + + return 0; + } + debug("FAIL\n"); + + eth_try_another(0); + } while (old_current != eth_current); + + return -ETIMEDOUT; +} + +void eth_halt(void) +{ + if (!eth_current) + return; + + eth_current->halt(eth_current); + + eth_current->state = ETH_STATE_PASSIVE; +} + +int eth_is_active(struct eth_device *dev) +{ + return dev && dev->state == ETH_STATE_ACTIVE; +} + +int eth_send(void *packet, int length) +{ + if (!eth_current) + return -ENODEV; + + return eth_current->send(eth_current, packet, length); +} + +int eth_rx(void) +{ + if (!eth_current) + return -ENODEV; + + return eth_current->recv(eth_current); +} + +#ifdef CONFIG_API +static void eth_save_packet(void *packet, int length) +{ + char *p = packet; + int i; + + if ((eth_rcv_last+1) % PKTBUFSRX == eth_rcv_current) + return; + + if (PKTSIZE < length) + return; + + for (i = 0; i < length; i++) + eth_rcv_bufs[eth_rcv_last].data[i] = p[i]; + + eth_rcv_bufs[eth_rcv_last].length = length; + eth_rcv_last = (eth_rcv_last + 1) % PKTBUFSRX; +} + +int eth_receive(void *packet, int length) +{ + char *p = packet; + void *pp = push_packet; + int i; + + if (eth_rcv_current == eth_rcv_last) { + push_packet = eth_save_packet; + eth_rx(); + push_packet = pp; + + if (eth_rcv_current == eth_rcv_last) + return -1; + } + + length = min(eth_rcv_bufs[eth_rcv_current].length, length); + + for (i = 0; i < length; i++) + p[i] = eth_rcv_bufs[eth_rcv_current].data[i]; + + eth_rcv_current = (eth_rcv_current + 1) % PKTBUFSRX; + return length; +} +#endif /* CONFIG_API */ diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 1644f8c48d..ad1d9b5d7d 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -300,6 +300,27 @@ $(obj)/%.dtb: $(src)/%.dts FORCE dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) +# Fonts +# --------------------------------------------------------------------------- + +# Generate an assembly file to wrap the font data +quiet_cmd_S_ttf= TTF $@ +# Modified for U-Boot +cmd_S_ttf= \ +( \ + echo '.section .rodata.ttf.init,"a"'; \ + echo '.balign 16'; \ + echo '.global __ttf_$(*F)_begin'; \ + echo '__ttf_$(*F)_begin:'; \ + echo '.incbin "$<" '; \ + echo '__ttf_$(*F)_end:'; \ + echo '.global __ttf_$(*F)_end'; \ + echo '.balign 16'; \ +) > $@ + +$(obj)/%.S: $(src)/%.ttf + $(call cmd,S_ttf) + # ACPI # --------------------------------------------------------------------------- quiet_cmd_acpi_c_asl= ASL $@ diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index dff16b9d99..f486feb0d0 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -131,22 +131,18 @@ boot.bin: $(obj)/u-boot-spl.bin else MKIMAGEFLAGS_boot.bin = -T zynqimage -spl/boot.bin: $(obj)/u-boot-spl-dtb.bin +spl/boot.bin: $(obj)/u-boot-spl.bin $(call if_changed,mkimage) endif ALL-y += $(obj)/$(SPL_BIN).bin $(obj)/$(SPL_BIN).cfg -ifdef CONFIG_SPL_OF_CONTROL -ALL-$(CONFIG_OF_SEPARATE) += $(obj)/$(SPL_BIN)-pad.bin $(obj)/$(SPL_BIN)-dtb.bin -endif - ifdef CONFIG_SAMSUNG ALL-y += $(obj)/$(BOARD)-spl.bin endif ifdef CONFIG_ARCH_SOCFPGA -ALL-y += $(obj)/$(SPL_BIN)-dtb.sfp +ALL-y += $(obj)/$(SPL_BIN).sfp endif ifdef CONFIG_SUNXI @@ -166,11 +162,22 @@ all: $(ALL-y) quiet_cmd_cat = CAT $@ cmd_cat = cat $(filter-out $(PHONY), $^) > $@ -$(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN).bin $(obj)/$(SPL_BIN)-pad.bin \ +quiet_cmd_copy = COPY $@ + cmd_copy = cp $< $@ + +ifeq ($(CONFIG_SPL_OF_CONTROL),y) +$(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin $(obj)/$(SPL_BIN)-pad.bin \ $(obj)/$(SPL_BIN).dtb FORCE $(call if_changed,cat) -# Create a file that pads from the end of u-boot-spl.bin to bss_end +$(obj)/$(SPL_BIN).bin: $(obj)/$(SPL_BIN)-dtb.bin FORCE + $(call if_changed,copy) +else +$(obj)/$(SPL_BIN).bin: $(obj)/$(SPL_BIN)-nodtb.bin FORCE + $(call if_changed,copy) +endif + +# Create a file that pads from the end of u-boot-spl-nodtb.bin to bss_end $(obj)/$(SPL_BIN)-pad.bin: $(obj)/$(SPL_BIN) @bss_size_str=$(shell $(NM) $< | awk 'BEGIN {size = 0} /__bss_size/ {size = $$1} END {print "ibase=16; " toupper(size)}' | bc); \ dd if=/dev/zero of=$@ bs=1 count=$${bss_size_str} 2>/dev/null; @@ -211,9 +218,9 @@ endif quiet_cmd_objcopy = OBJCOPY $@ cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@ -OBJCOPYFLAGS_$(SPL_BIN).bin = $(SPL_OBJCFLAGS) -O binary +OBJCOPYFLAGS_$(SPL_BIN)-nodtb.bin = $(SPL_OBJCFLAGS) -O binary -$(obj)/$(SPL_BIN).bin: $(obj)/$(SPL_BIN) FORCE +$(obj)/$(SPL_BIN)-nodtb.bin: $(obj)/$(SPL_BIN) FORCE $(call if_changed,objcopy) LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL) @@ -222,8 +229,8 @@ LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE) endif ifdef CONFIG_ARCH_SOCFPGA -MKIMAGEFLAGS_$(SPL_BIN)-dtb.sfp = -T socfpgaimage -$(obj)/$(SPL_BIN)-dtb.sfp: $(obj)/$(SPL_BIN)-dtb.bin FORCE +MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage +$(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE $(call if_changed,mkimage) endif diff --git a/test/dfu/README b/test/dfu/README deleted file mode 100644 index 408d559421..0000000000 --- a/test/dfu/README +++ /dev/null @@ -1,44 +0,0 @@ -DFU TEST CASE DESCRIPTION: - -The prerequisites for running this script are assured by -dfu_gadget_test_init.sh, which is automatically invoked by dfu_gadget_test.sh. -In this file user is able to generate their own set of test files by altering -the default set of TEST_FILES_SIZES variable. -The dfu_gadget_test_init.sh would generate test images only if they are not -already generated. - -On the target device, environment variable "dfu_alt_info" must contain at -least: - - dfu_test.bin fat 0 6;dfudummy.bin fat 0 6 - -Depending on your device, you may need to replace "fat" with -"ext4", and "6" with the relevant partition number. For reference please -consult the config file for TRATS/TRATS2 devices -(../../include/configs/trats{2}.h) - -One can use fat, ext4 or any other supported file system supported by U-Boot. -These can be created by exporting storage devices via UMS (ums 0 mmc 0) and -using standard tools on host (like mkfs.ext4). - -Example usage: -1. On the target: - setenv dfu_alt_info dfu_test.bin fat 0 6\;dfudummy.bin fat 0 6 - dfu 0 mmc 0 -2. On the host: - test/dfu/dfu_gadget_test.sh X Y [test file name] [usb device vendor:product] - e.g. test/dfu/dfu_gadget_test.sh 0 1 - or - e.g. test/dfu/dfu_gadget_test.sh 0 1 ./dat_960.img - or - e.g. test/dfu/dfu_gadget_test.sh 0 1 0451:d022 - or - e.g. test/dfu/dfu_gadget_test.sh 0 1 ./dat_960.img 0451:d022 - -... where X and Y are dfu_test.bin's and dfudummy.bin's alt setting numbers. -They can be obtained from dfu-util -l or $dfu_alt_info. -It is also possible to pass optional [test file name] to force the script to -test one particular file. -If many DFU devices are connected, it may be useful to filter on USB -vendor/product ID (0451:d022). -One can get them by running "lsusb" command on a host PC. diff --git a/test/dfu/dfu_gadget_test.sh b/test/dfu/dfu_gadget_test.sh deleted file mode 100755 index 9c7942257b..0000000000 --- a/test/dfu/dfu_gadget_test.sh +++ /dev/null @@ -1,108 +0,0 @@ -#! /bin/bash - -# Copyright (C) 2014 Samsung Electronics -# Lukasz Majewski <l.majewski@samsung.com> -# -# Script fixes, enhancements and testing: -# Stephen Warren <swarren@nvidia.com> -# -# DFU operation test script -# -# SPDX-License-Identifier: GPL-2.0+ - -set -e # any command return if not equal to zero -clear - -COLOUR_RED="\33[31m" -COLOUR_GREEN="\33[32m" -COLOUR_DEFAULT="\33[0m" - -DIR=./ -SUFFIX=img -RCV_DIR=rcv/ -LOG_FILE=./log/log-`date +%d-%m-%Y_%H-%M-%S` - -cd `dirname $0` -./dfu_gadget_test_init.sh - -cleanup () { - rm -rf $DIR$RCV_DIR -} - -die () { - printf " $COLOUR_RED FAILED $COLOUR_DEFAULT \n" - cleanup - exit 1 -} - -calculate_md5sum () { - MD5SUM=`md5sum $1` - MD5SUM=`echo $MD5SUM | cut -d ' ' -f1` - echo "md5sum:"$MD5SUM -} - -dfu_test_file () { - printf "$COLOUR_GREEN ========================================================================================= $COLOUR_DEFAULT\n" - printf "File:$COLOUR_GREEN %s $COLOUR_DEFAULT\n" $1 - - dfu-util $USB_DEV -D $1 -a $TARGET_ALT_SETTING >> $LOG_FILE 2>&1 || die $? - - echo -n "TX: " - calculate_md5sum $1 - - MD5_TX=$MD5SUM - - dfu-util $USB_DEV -D ${DIR}/dfudummy.bin -a $TARGET_ALT_SETTING_B >> $LOG_FILE 2>&1 || die $? - - N_FILE=$DIR$RCV_DIR${1:2}"_rcv" - - dfu-util $USB_DEV -U $N_FILE -a $TARGET_ALT_SETTING >> $LOG_FILE 2>&1 || die $? - - echo -n "RX: " - calculate_md5sum $N_FILE - MD5_RX=$MD5SUM - - if [ "$MD5_TX" == "$MD5_RX" ]; then - printf " $COLOUR_GREEN -------> OK $COLOUR_DEFAULT \n" - else - printf " $COLOUR_RED -------> FAILED $COLOUR_DEFAULT \n" - cleanup - exit 1 - fi - -} - -printf "$COLOUR_GREEN========================================================================================= $COLOUR_DEFAULT\n" -echo "DFU EP0 transmission test program" -echo "Trouble shoot -> disable DBG (even the KERN_DEBUG) in the UDC driver" -echo "@ -> TRATS2 # dfu 0 mmc 0" -cleanup -mkdir -p $DIR$RCV_DIR -touch $LOG_FILE - -if [ $# -eq 0 ] -then - printf " $COLOUR_RED Please pass alt setting number!! $COLOUR_DEFAULT \n" - exit 0 -fi - -TARGET_ALT_SETTING=$1 -TARGET_ALT_SETTING_B=$2 - -file=$3 -[[ $3 == *':'* ]] && USB_DEV="-d $3" && file="" -[ $# -eq 4 ] && USB_DEV="-d $4" - -if [ -n "$file" ] -then - dfu_test_file $file -else - for f in $DIR*.$SUFFIX - do - dfu_test_file $f - done -fi - -cleanup - -exit 0 diff --git a/test/dfu/dfu_gadget_test_init.sh b/test/dfu/dfu_gadget_test_init.sh deleted file mode 100755 index 640628eecb..0000000000 --- a/test/dfu/dfu_gadget_test_init.sh +++ /dev/null @@ -1,45 +0,0 @@ -#! /bin/bash - -# Copyright (C) 2014 Samsung Electronics -# Lukasz Majewski <l.majewski@samsung.com> -# -# Script fixes, enhancements and testing: -# Stephen Warren <swarren@nvidia.com> -# -# Script for test files generation -# -# SPDX-License-Identifier: GPL-2.0+ - -set -e # any command return if not equal to zero -clear - -COLOUR_RED="\33[31m" -COLOUR_GREEN="\33[32m" -COLOUR_DEFAULT="\33[0m" - -LOG_DIR="./log" - -if [ $# -eq 0 ]; then - TEST_FILES_SIZES="63 64 65 127 128 129 4095 4096 4097 959 960 961 1048575 1048576 8M" -else - TEST_FILES_SIZES=$@ -fi - -printf "Init script for generating data necessary for DFU test script" - -if [ ! -d $LOG_DIR ]; then - `mkdir $LOG_DIR` -fi - -for size in $TEST_FILES_SIZES -do - FILE="./dat_$size.img" - if [ ! -f $FILE ]; then - dd if=/dev/urandom of="./dat_$size.img" bs=$size count=1 > /dev/null 2>&1 || exit $? - fi -done -dd if=/dev/urandom of="./dfudummy.bin" bs=1024 count=1 > /dev/null 2>&1 || exit $? - -printf "$COLOUR_GREEN OK $COLOUR_DEFAULT \n" - -exit 0 diff --git a/test/dm/test-main.c b/test/dm/test-main.c index 91bdda83ab..f2e0048143 100644 --- a/test/dm/test-main.c +++ b/test/dm/test-main.c @@ -81,6 +81,8 @@ static int dm_test_main(const char *test_name) struct unit_test *test; int run_count; + uts->fail_count = 0; + /* * If we have no device tree, or it only has a root node, then these * tests clearly aren't going to work... diff --git a/test/dm/video.c b/test/dm/video.c index 9f5e7fce37..de223281b4 100644 --- a/test/dm/video.c +++ b/test/dm/video.c @@ -86,6 +86,20 @@ static void __maybe_unused see_output(void) while (1); } +/* Select the video console driver to use for a video device */ +static int select_vidconsole(struct unit_test_state *uts, const char *drv_name) +{ + struct sandbox_sdl_plat *plat; + struct udevice *dev; + + ut_assertok(uclass_find_device(UCLASS_VIDEO, 0, &dev)); + ut_assert(!device_active(dev)); + plat = dev_get_platdata(dev); + plat->vidconsole_drv_name = "vidconsole0"; + + return 0; +} + /* Test text output works on the video console */ static int dm_test_video_text(struct unit_test_state *uts) { @@ -95,6 +109,7 @@ static int dm_test_video_text(struct unit_test_state *uts) #define WHITE 0xffff #define SCROLL_LINES 100 + ut_assertok(select_vidconsole(uts, "vidconsole0")); ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); ut_asserteq(46, compress_frame_buffer(dev)); @@ -106,14 +121,14 @@ static int dm_test_video_text(struct unit_test_state *uts) ut_asserteq(46, compress_frame_buffer(dev)); for (i = 0; i < 20; i++) - vidconsole_putc_xy(con, i * 8, 0, ' ' + i); + vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i); ut_asserteq(273, compress_frame_buffer(dev)); vidconsole_set_row(con, 0, WHITE); ut_asserteq(46, compress_frame_buffer(dev)); for (i = 0; i < 20; i++) - vidconsole_putc_xy(con, i * 8, 0, ' ' + i); + vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i); ut_asserteq(273, compress_frame_buffer(dev)); return 0; @@ -124,9 +139,10 @@ DM_TEST(dm_test_video_text, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); static int dm_test_video_chars(struct unit_test_state *uts) { struct udevice *dev, *con; - const char *test_string = "Well\b\b\b\bxhe is\r \n\ta very modest \bman\n\t\tand Has much to\b\bto be modest about."; + const char *test_string = "Well\b\b\b\bxhe is\r \n\ta very \amodest \bman\n\t\tand Has much to\b\bto be modest about."; const char *s; + ut_assertok(select_vidconsole(uts, "vidconsole0")); ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); for (s = test_string; *s; s++) @@ -185,7 +201,10 @@ static int check_vidconsole_output(struct unit_test_state *uts, int rot, /* Test text output through the console uclass */ static int dm_test_video_context(struct unit_test_state *uts) { - return check_vidconsole_output(uts, 0, 788, 453); + ut_assertok(select_vidconsole(uts, "vidconsole0")); + ut_assertok(check_vidconsole_output(uts, 0, 788, 453)); + + return 0; } DM_TEST(dm_test_video_context, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); @@ -269,3 +288,66 @@ static int dm_test_video_bmp_comp(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_video_bmp_comp, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test TrueType console */ +static int dm_test_video_truetype(struct unit_test_state *uts) +{ + struct udevice *dev, *con; + const char *test_string = "Criticism may not be agreeable, but it is necessary. It fulfils the same function as pain in the human body. It calls attention to an unhealthy state of things. Some see private enterprise as a predatory target to be shot, others as a cow to be milked, but few are those who see it as a sturdy horse pulling the wagon. The \aprice OF\b\bof greatness\n\tis responsibility.\n\nBye"; + const char *s; + + ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); + ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); + for (s = test_string; *s; s++) + vidconsole_put_char(con, *s); + ut_asserteq(12619, compress_frame_buffer(dev)); + + return 0; +} +DM_TEST(dm_test_video_truetype, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test scrolling TrueType console */ +static int dm_test_video_truetype_scroll(struct unit_test_state *uts) +{ + struct sandbox_sdl_plat *plat; + struct udevice *dev, *con; + const char *test_string = "Criticism may not be agreeable, but it is necessary. It fulfils the same function as pain in the human body. It calls attention to an unhealthy state of things. Some see private enterprise as a predatory target to be shot, others as a cow to be milked, but few are those who see it as a sturdy horse pulling the wagon. The \aprice OF\b\bof greatness\n\tis responsibility.\n\nBye"; + const char *s; + + ut_assertok(uclass_find_device(UCLASS_VIDEO, 0, &dev)); + ut_assert(!device_active(dev)); + plat = dev_get_platdata(dev); + plat->font_size = 100; + + ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); + ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); + for (s = test_string; *s; s++) + vidconsole_put_char(con, *s); + ut_asserteq(33849, compress_frame_buffer(dev)); + + return 0; +} +DM_TEST(dm_test_video_truetype_scroll, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test TrueType backspace, within and across lines */ +static int dm_test_video_truetype_bs(struct unit_test_state *uts) +{ + struct sandbox_sdl_plat *plat; + struct udevice *dev, *con; + const char *test_string = "...Criticism may or may\b\b\b\b\b\bnot be agreeable, but seldom it is necessary\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\bit is necessary. It fulfils the same function as pain in the human body. It calls attention to an unhealthy state of things."; + const char *s; + + ut_assertok(uclass_find_device(UCLASS_VIDEO, 0, &dev)); + ut_assert(!device_active(dev)); + plat = dev_get_platdata(dev); + plat->font_size = 100; + + ut_assertok(uclass_get_device(UCLASS_VIDEO, 0, &dev)); + ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); + for (s = test_string; *s; s++) + vidconsole_put_char(con, *s); + ut_asserteq(34871, compress_frame_buffer(dev)); + + return 0; +} +DM_TEST(dm_test_video_truetype_bs, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/test/py/conftest.py b/test/py/conftest.py index e1674dfce0..3e162cafcc 100644 --- a/test/py/conftest.py +++ b/test/py/conftest.py @@ -29,7 +29,7 @@ log = None console = None def mkdir_p(path): - '''Create a directory path. + """Create a directory path. This includes creating any intermediate/parent directories. Any errors caused due to already extant directories are ignored. @@ -39,7 +39,7 @@ def mkdir_p(path): Returns: Nothing. - ''' + """ try: os.makedirs(path) @@ -50,14 +50,14 @@ def mkdir_p(path): raise def pytest_addoption(parser): - '''pytest hook: Add custom command-line options to the cmdline parser. + """pytest hook: Add custom command-line options to the cmdline parser. Args: parser: The pytest command-line parser. Returns: Nothing. - ''' + """ parser.addoption('--build-dir', default=None, help='U-Boot build directory (O=)') @@ -73,14 +73,14 @@ def pytest_addoption(parser): help='Compile U-Boot before running tests') def pytest_configure(config): - '''pytest hook: Perform custom initialization at startup time. + """pytest hook: Perform custom initialization at startup time. Args: config: The pytest configuration. Returns: Nothing. - ''' + """ global log global console @@ -190,7 +190,7 @@ def pytest_configure(config): console = u_boot_console_exec_attach.ConsoleExecAttach(log, ubconfig) def pytest_generate_tests(metafunc): - '''pytest hook: parameterize test functions based on custom rules. + """pytest hook: parameterize test functions based on custom rules. If a test function takes parameter(s) (fixture names) of the form brd__xxx or env__xxx, the brd and env configuration dictionaries are consulted to @@ -202,7 +202,7 @@ def pytest_generate_tests(metafunc): Returns: Nothing. - ''' + """ subconfigs = { 'brd': console.config.brd, @@ -225,28 +225,37 @@ def pytest_generate_tests(metafunc): # ... otherwise, see if there's a key that contains a list of # values to use instead. vals = subconfig.get(fn + 's', []) - metafunc.parametrize(fn, vals) - -@pytest.fixture(scope='session') + def fixture_id(index, val): + try: + return val["fixture_id"] + except: + return fn + str(index) + ids = [fixture_id(index, val) for (index, val) in enumerate(vals)] + metafunc.parametrize(fn, vals, ids=ids) + +@pytest.fixture(scope='function') def u_boot_console(request): - '''Generate the value of a test's u_boot_console fixture. + """Generate the value of a test's u_boot_console fixture. Args: request: The pytest request. Returns: The fixture value. - ''' + """ + console.ensure_spawned() return console tests_not_run = set() tests_failed = set() +tests_xpassed = set() +tests_xfailed = set() tests_skipped = set() tests_passed = set() def pytest_itemcollected(item): - '''pytest hook: Called once for each test found during collection. + """pytest hook: Called once for each test found during collection. This enables our custom result analysis code to see the list of all tests that should eventually be run. @@ -256,12 +265,12 @@ def pytest_itemcollected(item): Returns: Nothing. - ''' + """ tests_not_run.add(item.name) def cleanup(): - '''Clean up all global state. + """Clean up all global state. Executed (via atexit) once the entire test process is complete. This includes logging the status of all tests, and the identity of any failed @@ -272,7 +281,7 @@ def cleanup(): Returns: Nothing. - ''' + """ if console: console.close() @@ -282,6 +291,14 @@ def cleanup(): log.status_skipped('%d skipped' % len(tests_skipped)) for test in tests_skipped: log.status_skipped('... ' + test) + if tests_xpassed: + log.status_xpass('%d xpass' % len(tests_xpassed)) + for test in tests_xpassed: + log.status_xpass('... ' + test) + if tests_xfailed: + log.status_xfail('%d xfail' % len(tests_xfailed)) + for test in tests_xfailed: + log.status_xfail('... ' + test) if tests_failed: log.status_fail('%d failed' % len(tests_failed)) for test in tests_failed: @@ -294,7 +311,7 @@ def cleanup(): atexit.register(cleanup) def setup_boardspec(item): - '''Process any 'boardspec' marker for a test. + """Process any 'boardspec' marker for a test. Such a marker lists the set of board types that a test does/doesn't support. If tests are being executed on an unsupported board, the test is @@ -305,7 +322,7 @@ def setup_boardspec(item): Returns: Nothing. - ''' + """ mark = item.get_marker('boardspec') if not mark: @@ -322,7 +339,7 @@ def setup_boardspec(item): pytest.skip('board not supported') def setup_buildconfigspec(item): - '''Process any 'buildconfigspec' marker for a test. + """Process any 'buildconfigspec' marker for a test. Such a marker lists some U-Boot configuration feature that the test requires. If tests are being executed on an U-Boot build that doesn't @@ -333,7 +350,7 @@ def setup_buildconfigspec(item): Returns: Nothing. - ''' + """ mark = item.get_marker('buildconfigspec') if not mark: @@ -343,7 +360,7 @@ def setup_buildconfigspec(item): pytest.skip('.config feature not enabled') def pytest_runtest_setup(item): - '''pytest hook: Configure (set up) a test item. + """pytest hook: Configure (set up) a test item. Called once for each test to perform any custom configuration. This hook is used to skip the test if certain conditions apply. @@ -353,14 +370,14 @@ def pytest_runtest_setup(item): Returns: Nothing. - ''' + """ log.start_section(item.name) setup_boardspec(item) setup_buildconfigspec(item) def pytest_runtest_protocol(item, nextitem): - '''pytest hook: Called to execute a test. + """pytest hook: Called to execute a test. This hook wraps the standard pytest runtestprotocol() function in order to acquire visibility into, and record, each test function's result. @@ -371,36 +388,45 @@ def pytest_runtest_protocol(item, nextitem): Returns: A list of pytest reports (test result data). - ''' + """ reports = runtestprotocol(item, nextitem=nextitem) - failed = None - skipped = None + + failure_cleanup = False + test_list = tests_passed + msg = 'OK' + msg_log = log.status_pass for report in reports: if report.outcome == 'failed': - failed = report + if hasattr(report, 'wasxfail'): + test_list = tests_xpassed + msg = 'XPASSED' + msg_log = log.status_xpass + else: + failure_cleanup = True + test_list = tests_failed + msg = 'FAILED:\n' + str(report.longrepr) + msg_log = log.status_fail break if report.outcome == 'skipped': - if not skipped: - skipped = report - - if failed: - tests_failed.add(item.name) - elif skipped: - tests_skipped.add(item.name) - else: - tests_passed.add(item.name) + if hasattr(report, 'wasxfail'): + failure_cleanup = True + test_list = tests_xfailed + msg = 'XFAILED:\n' + str(report.longrepr) + msg_log = log.status_xfail + break + test_list = tests_skipped + msg = 'SKIPPED:\n' + str(report.longrepr) + msg_log = log.status_skipped + + if failure_cleanup: + console.drain_console() + + test_list.add(item.name) tests_not_run.remove(item.name) try: - if failed: - msg = 'FAILED:\n' + str(failed.longrepr) - log.status_fail(msg) - elif skipped: - msg = 'SKIPPED:\n' + str(skipped.longrepr) - log.status_skipped(msg) - else: - log.status_pass('OK') + msg_log(msg) except: # If something went wrong with logging, it's better to let the test # process continue, which may report other exceptions that triggered @@ -416,7 +442,7 @@ def pytest_runtest_protocol(item, nextitem): log.end_section(item.name) - if failed: + if failure_cleanup: console.cleanup_spawn() return reports diff --git a/test/py/multiplexed_log.css b/test/py/multiplexed_log.css index 50f7b90929..f6240d52da 100644 --- a/test/py/multiplexed_log.css +++ b/test/py/multiplexed_log.css @@ -83,6 +83,14 @@ pre { color: #ffff00 } +.status-xfail { + color: #ff7f00 +} + +.status-xpass { + color: #ff7f00 +} + .status-fail { color: #ff0000 } diff --git a/test/py/multiplexed_log.py b/test/py/multiplexed_log.py index 48f2b51de1..69a577e577 100644 --- a/test/py/multiplexed_log.py +++ b/test/py/multiplexed_log.py @@ -14,12 +14,12 @@ import subprocess mod_dir = os.path.dirname(os.path.abspath(__file__)) class LogfileStream(object): - '''A file-like object used to write a single logical stream of data into + """A file-like object used to write a single logical stream of data into a multiplexed log file. Objects of this type should be created by factory - functions in the Logfile class rather than directly.''' + functions in the Logfile class rather than directly.""" def __init__(self, logfile, name, chained_file): - '''Initialize a new object. + """Initialize a new object. Args: logfile: The Logfile object to log to. @@ -29,26 +29,26 @@ class LogfileStream(object): Returns: Nothing. - ''' + """ self.logfile = logfile self.name = name self.chained_file = chained_file def close(self): - '''Dummy function so that this class is "file-like". + """Dummy function so that this class is "file-like". Args: None. Returns: Nothing. - ''' + """ pass def write(self, data, implicit=False): - '''Write data to the log stream. + """Write data to the log stream. Args: data: The data to write tot he file. @@ -60,33 +60,33 @@ class LogfileStream(object): Returns: Nothing. - ''' + """ self.logfile.write(self, data, implicit) if self.chained_file: self.chained_file.write(data) def flush(self): - '''Flush the log stream, to ensure correct log interleaving. + """Flush the log stream, to ensure correct log interleaving. Args: None. Returns: Nothing. - ''' + """ self.logfile.flush() if self.chained_file: self.chained_file.flush() class RunAndLog(object): - '''A utility object used to execute sub-processes and log their output to + """A utility object used to execute sub-processes and log their output to a multiplexed log file. Objects of this type should be created by factory - functions in the Logfile class rather than directly.''' + functions in the Logfile class rather than directly.""" def __init__(self, logfile, name, chained_file): - '''Initialize a new object. + """Initialize a new object. Args: logfile: The Logfile object to log to. @@ -96,29 +96,33 @@ class RunAndLog(object): Returns: Nothing. - ''' + """ self.logfile = logfile self.name = name self.chained_file = chained_file def close(self): - '''Clean up any resources managed by this object.''' + """Clean up any resources managed by this object.""" pass - def run(self, cmd, cwd=None): - '''Run a command as a sub-process, and log the results. + def run(self, cmd, cwd=None, ignore_errors=False): + """Run a command as a sub-process, and log the results. Args: cmd: The command to execute. cwd: The directory to run the command in. Can be None to use the current directory. + ignore_errors: Indicate whether to ignore errors. If True, the + function will simply return if the command cannot be executed + or exits with an error code, otherwise an exception will be + raised if such problems occur. Returns: Nothing. - ''' + """ - msg = "+" + " ".join(cmd) + "\n" + msg = '+' + ' '.join(cmd) + '\n' if self.chained_file: self.chained_file.write(msg) self.logfile.write(self, msg) @@ -148,7 +152,7 @@ class RunAndLog(object): exception = e if output and not output.endswith('\n'): output += '\n' - if exit_status and not exception: + if exit_status and not exception and not ignore_errors: exception = Exception('Exit code: ' + str(exit_status)) if exception: output += str(exception) + '\n' @@ -159,13 +163,13 @@ class RunAndLog(object): raise exception class SectionCtxMgr(object): - '''A context manager for Python's "with" statement, which allows a certain + """A context manager for Python's "with" statement, which allows a certain portion of test code to be logged to a separate section of the log file. Objects of this type should be created by factory functions in the Logfile - class rather than directly.''' + class rather than directly.""" def __init__(self, log, marker): - '''Initialize a new object. + """Initialize a new object. Args: log: The Logfile object to log to. @@ -173,7 +177,7 @@ class SectionCtxMgr(object): Returns: Nothing. - ''' + """ self.log = log self.marker = marker @@ -185,35 +189,35 @@ class SectionCtxMgr(object): self.log.end_section(self.marker) class Logfile(object): - '''Generates an HTML-formatted log file containing multiple streams of - data, each represented in a well-delineated/-structured fashion.''' + """Generates an HTML-formatted log file containing multiple streams of + data, each represented in a well-delineated/-structured fashion.""" def __init__(self, fn): - '''Initialize a new object. + """Initialize a new object. Args: fn: The filename to write to. Returns: Nothing. - ''' + """ - self.f = open(fn, "wt") + self.f = open(fn, 'wt') self.last_stream = None self.blocks = [] self.cur_evt = 1 - shutil.copy(mod_dir + "/multiplexed_log.css", os.path.dirname(fn)) - self.f.write("""\ + shutil.copy(mod_dir + '/multiplexed_log.css', os.path.dirname(fn)) + self.f.write('''\ <html> <head> <link rel="stylesheet" type="text/css" href="multiplexed_log.css"> </head> <body> <tt> -""") +''') def close(self): - '''Close the log file. + """Close the log file. After calling this function, no more data may be written to the log. @@ -222,22 +226,22 @@ class Logfile(object): Returns: Nothing. - ''' + """ - self.f.write("""\ + self.f.write('''\ </tt> </body> </html> -""") +''') self.f.close() # The set of characters that should be represented as hexadecimal codes in # the log file. - _nonprint = ("%" + "".join(chr(c) for c in range(0, 32) if c not in (9, 10)) + - "".join(chr(c) for c in range(127, 256))) + _nonprint = ('%' + ''.join(chr(c) for c in range(0, 32) if c not in (9, 10)) + + ''.join(chr(c) for c in range(127, 256))) def _escape(self, data): - '''Render data format suitable for inclusion in an HTML document. + """Render data format suitable for inclusion in an HTML document. This includes HTML-escaping certain characters, and translating control characters to a hexadecimal representation. @@ -247,36 +251,36 @@ class Logfile(object): Returns: An escaped version of the data. - ''' + """ - data = data.replace(chr(13), "") - data = "".join((c in self._nonprint) and ("%%%02x" % ord(c)) or + data = data.replace(chr(13), '') + data = ''.join((c in self._nonprint) and ('%%%02x' % ord(c)) or c for c in data) data = cgi.escape(data) return data def _terminate_stream(self): - '''Write HTML to the log file to terminate the current stream's data. + """Write HTML to the log file to terminate the current stream's data. Args: None. Returns: Nothing. - ''' + """ self.cur_evt += 1 if not self.last_stream: return - self.f.write("</pre>\n") - self.f.write("<div class=\"stream-trailer\" id=\"" + - self.last_stream.name + "\">End stream: " + - self.last_stream.name + "</div>\n") - self.f.write("</div>\n") + self.f.write('</pre>\n') + self.f.write('<div class="stream-trailer" id="' + + self.last_stream.name + '">End stream: ' + + self.last_stream.name + '</div>\n') + self.f.write('</div>\n') self.last_stream = None def _note(self, note_type, msg): - '''Write a note or one-off message to the log file. + """Write a note or one-off message to the log file. Args: note_type: The type of note. This must be a value supported by the @@ -285,32 +289,32 @@ class Logfile(object): Returns: Nothing. - ''' + """ self._terminate_stream() - self.f.write("<div class=\"" + note_type + "\">\n<pre>") + self.f.write('<div class="' + note_type + '">\n<pre>') self.f.write(self._escape(msg)) - self.f.write("\n</pre></div>\n") + self.f.write('\n</pre></div>\n') def start_section(self, marker): - '''Begin a new nested section in the log file. + """Begin a new nested section in the log file. Args: marker: The name of the section that is starting. Returns: Nothing. - ''' + """ self._terminate_stream() self.blocks.append(marker) - blk_path = "/".join(self.blocks) - self.f.write("<div class=\"section\" id=\"" + blk_path + "\">\n") - self.f.write("<div class=\"section-header\" id=\"" + blk_path + - "\">Section: " + blk_path + "</div>\n") + blk_path = '/'.join(self.blocks) + self.f.write('<div class="section" id="' + blk_path + '">\n') + self.f.write('<div class="section-header" id="' + blk_path + + '">Section: ' + blk_path + '</div>\n') def end_section(self, marker): - '''Terminate the current nested section in the log file. + """Terminate the current nested section in the log file. This function validates proper nesting of start_section() and end_section() calls. If a mismatch is found, an exception is raised. @@ -320,20 +324,20 @@ class Logfile(object): Returns: Nothing. - ''' + """ if (not self.blocks) or (marker != self.blocks[-1]): - raise Exception("Block nesting mismatch: \"%s\" \"%s\"" % - (marker, "/".join(self.blocks))) + raise Exception('Block nesting mismatch: "%s" "%s"' % + (marker, '/'.join(self.blocks))) self._terminate_stream() - blk_path = "/".join(self.blocks) - self.f.write("<div class=\"section-trailer\" id=\"section-trailer-" + - blk_path + "\">End section: " + blk_path + "</div>\n") - self.f.write("</div>\n") + blk_path = '/'.join(self.blocks) + self.f.write('<div class="section-trailer" id="section-trailer-' + + blk_path + '">End section: ' + blk_path + '</div>\n') + self.f.write('</div>\n') self.blocks.pop() def section(self, marker): - '''Create a temporary section in the log file. + """Create a temporary section in the log file. This function creates a context manager for Python's "with" statement, which allows a certain portion of test code to be logged to a separate @@ -348,96 +352,120 @@ class Logfile(object): Returns: A context manager object. - ''' + """ return SectionCtxMgr(self, marker) def error(self, msg): - '''Write an error note to the log file. + """Write an error note to the log file. Args: msg: A message describing the error. Returns: Nothing. - ''' + """ self._note("error", msg) def warning(self, msg): - '''Write an warning note to the log file. + """Write an warning note to the log file. Args: msg: A message describing the warning. Returns: Nothing. - ''' + """ self._note("warning", msg) def info(self, msg): - '''Write an informational note to the log file. + """Write an informational note to the log file. Args: msg: An informational message. Returns: Nothing. - ''' + """ self._note("info", msg) def action(self, msg): - '''Write an action note to the log file. + """Write an action note to the log file. Args: msg: A message describing the action that is being logged. Returns: Nothing. - ''' + """ self._note("action", msg) def status_pass(self, msg): - '''Write a note to the log file describing test(s) which passed. + """Write a note to the log file describing test(s) which passed. Args: - msg: A message describing passed test(s). + msg: A message describing the passed test(s). Returns: Nothing. - ''' + """ self._note("status-pass", msg) def status_skipped(self, msg): - '''Write a note to the log file describing skipped test(s). + """Write a note to the log file describing skipped test(s). Args: - msg: A message describing passed test(s). + msg: A message describing the skipped test(s). Returns: Nothing. - ''' + """ self._note("status-skipped", msg) + def status_xfail(self, msg): + """Write a note to the log file describing xfailed test(s). + + Args: + msg: A message describing the xfailed test(s). + + Returns: + Nothing. + """ + + self._note("status-xfail", msg) + + def status_xpass(self, msg): + """Write a note to the log file describing xpassed test(s). + + Args: + msg: A message describing the xpassed test(s). + + Returns: + Nothing. + """ + + self._note("status-xpass", msg) + def status_fail(self, msg): - '''Write a note to the log file describing failed test(s). + """Write a note to the log file describing failed test(s). Args: - msg: A message describing passed test(s). + msg: A message describing the failed test(s). Returns: Nothing. - ''' + """ self._note("status-fail", msg) def get_stream(self, name, chained_file=None): - '''Create an object to log a single stream's data into the log file. + """Create an object to log a single stream's data into the log file. This creates a "file-like" object that can be written to in order to write a single stream's data to the log file. The implementation will @@ -452,12 +480,12 @@ class Logfile(object): Returns: A file-like object. - ''' + """ return LogfileStream(self, name, chained_file) def get_runner(self, name, chained_file=None): - '''Create an object that executes processes and logs their output. + """Create an object that executes processes and logs their output. Args: name: The name of this sub-process. @@ -466,12 +494,12 @@ class Logfile(object): Returns: A RunAndLog object. - ''' + """ return RunAndLog(self, name, chained_file) def write(self, stream, data, implicit=False): - '''Write stream data into the log file. + """Write stream data into the log file. This function should only be used by instances of LogfileStream or RunAndLog. @@ -487,29 +515,29 @@ class Logfile(object): Returns: Nothing. - ''' + """ if stream != self.last_stream: self._terminate_stream() - self.f.write("<div class=\"stream\" id=\"%s\">\n" % stream.name) - self.f.write("<div class=\"stream-header\" id=\"" + stream.name + - "\">Stream: " + stream.name + "</div>\n") - self.f.write("<pre>") + self.f.write('<div class="stream" id="%s">\n' % stream.name) + self.f.write('<div class="stream-header" id="' + stream.name + + '">Stream: ' + stream.name + '</div>\n') + self.f.write('<pre>') if implicit: - self.f.write("<span class=\"implicit\">") + self.f.write('<span class="implicit">') self.f.write(self._escape(data)) if implicit: - self.f.write("</span>") + self.f.write('</span>') self.last_stream = stream def flush(self): - '''Flush the log stream, to ensure correct log interleaving. + """Flush the log stream, to ensure correct log interleaving. Args: None. Returns: Nothing. - ''' + """ self.f.flush() diff --git a/test/py/test.py b/test/py/test.py index 9c23898774..95671d4737 100755 --- a/test/py/test.py +++ b/test/py/test.py @@ -16,17 +16,17 @@ import sys sys.argv.pop(0) # argv; py.test test_directory_name user-supplied-arguments -args = ["py.test", os.path.dirname(__file__) + "/tests"] +args = ['py.test', os.path.dirname(__file__) + '/tests'] args.extend(sys.argv) try: - os.execvp("py.test", args) + os.execvp('py.test', args) except: # Log full details of any exception for detailed analysis import traceback traceback.print_exc() # Hint to the user that they likely simply haven't installed the required # dependencies. - print >>sys.stderr, """ + print >>sys.stderr, ''' exec(py.test) failed; perhaps you are missing some dependencies? -See test/py/README.md for the list.""" +See test/py/README.md for the list.''' diff --git a/test/py/tests/test_000_version.py b/test/py/tests/test_000_version.py index d262f0534e..43a02e74f7 100644 --- a/test/py/tests/test_000_version.py +++ b/test/py/tests/test_000_version.py @@ -9,7 +9,7 @@ # command prompt. def test_version(u_boot_console): - '''Test that the "version" command prints the U-Boot version.''' + """Test that the "version" command prints the U-Boot version.""" # "version" prints the U-Boot sign-on message. This is usually considered # an error, so that any unexpected reboot causes an error. Here, this diff --git a/test/py/tests/test_dfu.py b/test/py/tests/test_dfu.py new file mode 100644 index 0000000000..093e8d0678 --- /dev/null +++ b/test/py/tests/test_dfu.py @@ -0,0 +1,279 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0 + +# Test U-Boot's "dfu" command. The test starts DFU in U-Boot, waits for USB +# device enumeration on the host, executes dfu-util multiple times to test +# various transfer sizes, many of which trigger USB driver edge cases, and +# finally aborts the "dfu" command in U-Boot. + +import os +import os.path +import pytest +import u_boot_utils + +""" +Note: This test relies on: + +a) boardenv_* to contain configuration values to define which USB ports are +available for testing. Without this, this test will be automatically skipped. +For example: + +env__usb_dev_ports = ( + { + "fixture_id": "micro_b", + "tgt_usb_ctlr": "0", + "host_usb_dev_node": "/dev/usbdev-p2371-2180", + # This parameter is optional /if/ you only have a single board + # attached to your host at a time. + "host_usb_port_path": "3-13", + }, +) + +env__dfu_configs = ( + # eMMC, partition 1 + { + "fixture_id": "emmc", + "alt_info": "/dfu_test.bin ext4 0 1;/dfu_dummy.bin ext4 0 1", + "cmd_params": "mmc 0", + # This value is optional. + # If present, it specified the set of transfer sizes tested. + # If missing, a default list of sizes will be used, which covers + # various useful corner cases. + # Manually specifying test sizes is useful if you wish to test 4 DFU + # configurations, but don't want to test every single transfer size + # on each, to avoid bloating the overall time taken by testing. + "test_sizes": (63, 64, 65), + }, +) + +b) udev rules to set permissions on devices nodes, so that sudo is not +required. For example: + +ACTION=="add", SUBSYSTEM=="block", SUBSYSTEMS=="usb", KERNELS=="3-13", MODE:="666" + +(You may wish to change the group ID instead of setting the permissions wide +open. All that matters is that the user ID running the test can access the +device.) +""" + +# The set of file sizes to test. These values trigger various edge-cases such +# as one less than, equal to, and one greater than typical USB max packet +# sizes, and similar boundary conditions. +test_sizes_default = ( + 64 - 1, + 64, + 64 + 1, + 128 - 1, + 128, + 128 + 1, + 960 - 1, + 960, + 960 + 1, + 4096 - 1, + 4096, + 4096 + 1, + 1024 * 1024 - 1, + 1024 * 1024, + 8 * 1024 * 1024, +) + +first_usb_dev_port = None + +@pytest.mark.buildconfigspec('cmd_dfu') +def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config): + """Test the "dfu" command; the host system must be able to enumerate a USB + device when "dfu" is running, various DFU transfers are tested, and the + USB device must disappear when "dfu" is aborted. + + Args: + u_boot_console: A U-Boot console connection. + env__usb_dev_port: The single USB device-mode port specification on + which to run the test. See the file-level comment above for + details of the format. + env__dfu_config: The single DFU (memory region) configuration on which + to run the test. See the file-level comment above for details + of the format. + + Returns: + Nothing. + """ + + def start_dfu(): + """Start U-Boot's dfu shell command. + + This also waits for the host-side USB enumeration process to complete. + + Args: + None. + + Returns: + Nothing. + """ + + fh = u_boot_utils.attempt_to_open_file( + env__usb_dev_port['host_usb_dev_node']) + if fh: + fh.close() + raise Exception('USB device present before dfu command invoked') + + u_boot_console.log.action( + 'Starting long-running U-Boot dfu shell command') + + cmd = 'setenv dfu_alt_info "%s"' % env__dfu_config['alt_info'] + u_boot_console.run_command(cmd) + + cmd = 'dfu 0 ' + env__dfu_config['cmd_params'] + u_boot_console.run_command(cmd, wait_for_prompt=False) + u_boot_console.log.action('Waiting for DFU USB device to appear') + fh = u_boot_utils.wait_until_open_succeeds( + env__usb_dev_port['host_usb_dev_node']) + fh.close() + + def stop_dfu(ignore_errors): + """Stop U-Boot's dfu shell command from executing. + + This also waits for the host-side USB de-enumeration process to + complete. + + Args: + ignore_errors: Ignore any errors. This is useful if an error has + already been detected, and the code is performing best-effort + cleanup. In this case, we do not want to mask the original + error by "honoring" any new errors. + + Returns: + Nothing. + """ + + try: + u_boot_console.log.action( + 'Stopping long-running U-Boot dfu shell command') + u_boot_console.ctrlc() + u_boot_console.log.action( + 'Waiting for DFU USB device to disappear') + u_boot_utils.wait_until_file_open_fails( + env__usb_dev_port['host_usb_dev_node'], ignore_errors) + except: + if not ignore_errors: + raise + + def run_dfu_util(alt_setting, fn, up_dn_load_arg): + """Invoke dfu-util on the host. + + Args: + alt_setting: The DFU "alternate setting" identifier to interact + with. + fn: The host-side file name to transfer. + up_dn_load_arg: '-U' or '-D' depending on whether a DFU upload or + download operation should be performed. + + Returns: + Nothing. + """ + + cmd = ['dfu-util', '-a', str(alt_setting), up_dn_load_arg, fn] + if 'host_usb_port_path' in env__usb_dev_port: + cmd += ['-p', env__usb_dev_port['host_usb_port_path']] + u_boot_utils.run_and_log(u_boot_console, cmd) + u_boot_console.wait_for('Ctrl+C to exit ...') + + def dfu_write(alt_setting, fn): + """Write a file to the target board using DFU. + + Args: + alt_setting: The DFU "alternate setting" identifier to interact + with. + fn: The host-side file name to transfer. + + Returns: + Nothing. + """ + + run_dfu_util(alt_setting, fn, '-D') + + def dfu_read(alt_setting, fn): + """Read a file from the target board using DFU. + + Args: + alt_setting: The DFU "alternate setting" identifier to interact + with. + fn: The host-side file name to transfer. + + Returns: + Nothing. + """ + + # dfu-util fails reads/uploads if the host file already exists + if os.path.exists(fn): + os.remove(fn) + run_dfu_util(alt_setting, fn, '-U') + + def dfu_write_read_check(size): + """Test DFU transfers of a specific size of data + + This function first writes data to the board then reads it back and + compares the written and read back data. Measures are taken to avoid + certain types of false positives. + + Args: + size: The data size to test. + + Returns: + Nothing. + """ + + test_f = u_boot_utils.PersistentRandomFile(u_boot_console, + 'dfu_%d.bin' % size, size) + readback_fn = u_boot_console.config.result_dir + '/dfu_readback.bin' + + u_boot_console.log.action('Writing test data to DFU primary ' + + 'altsetting') + dfu_write(0, test_f.abs_fn) + + u_boot_console.log.action('Writing dummy data to DFU secondary ' + + 'altsetting to clear DFU buffers') + dfu_write(1, dummy_f.abs_fn) + + u_boot_console.log.action('Reading DFU primary altsetting for ' + + 'comparison') + dfu_read(0, readback_fn) + + u_boot_console.log.action('Comparing written and read data') + written_hash = test_f.content_hash + read_back_hash = u_boot_utils.md5sum_file(readback_fn, size) + assert(written_hash == read_back_hash) + + # This test may be executed against multiple USB ports. The test takes a + # long time, so we don't want to do the whole thing each time. Instead, + # execute the full test on the first USB port, and perform a very limited + # test on other ports. In the limited case, we solely validate that the + # host PC can enumerate the U-Boot USB device. + global first_usb_dev_port + if not first_usb_dev_port: + first_usb_dev_port = env__usb_dev_port + if env__usb_dev_port == first_usb_dev_port: + sizes = env__dfu_config.get('test_sizes', test_sizes_default) + else: + sizes = [] + + dummy_f = u_boot_utils.PersistentRandomFile(u_boot_console, + 'dfu_dummy.bin', 1024) + + ignore_cleanup_errors = True + try: + start_dfu() + + u_boot_console.log.action( + 'Overwriting DFU primary altsetting with dummy data') + dfu_write(0, dummy_f.abs_fn) + + for size in sizes: + with u_boot_console.log.section('Data size %d' % size): + dfu_write_read_check(size) + # Make the status of each sub-test obvious. If the test didn't + # pass, an exception was thrown so this code isn't executed. + u_boot_console.log.status_pass('OK') + ignore_cleanup_errors = False + finally: + stop_dfu(ignore_cleanup_errors) diff --git a/test/py/tests/test_env.py b/test/py/tests/test_env.py index a3e8dd3033..c41aa5a9d9 100644 --- a/test/py/tests/test_env.py +++ b/test/py/tests/test_env.py @@ -10,34 +10,34 @@ import pytest # FIXME: This might be useful for other tests; # perhaps refactor it into ConsoleBase or some other state object? class StateTestEnv(object): - '''Container that represents the state of all U-Boot environment variables. + """Container that represents the state of all U-Boot environment variables. This enables quick determination of existant/non-existant variable names. - ''' + """ def __init__(self, u_boot_console): - '''Initialize a new StateTestEnv object. + """Initialize a new StateTestEnv object. Args: u_boot_console: A U-Boot console. Returns: Nothing. - ''' + """ self.u_boot_console = u_boot_console self.get_env() self.set_var = self.get_non_existent_var() def get_env(self): - '''Read all current environment variables from U-Boot. + """Read all current environment variables from U-Boot. Args: None. Returns: Nothing. - ''' + """ response = self.u_boot_console.run_command('printenv') self.env = {} @@ -48,27 +48,27 @@ class StateTestEnv(object): self.env[var] = value def get_existent_var(self): - '''Return the name of an environment variable that exists. + """Return the name of an environment variable that exists. Args: None. Returns: The name of an environment variable. - ''' + """ for var in self.env: return var def get_non_existent_var(self): - '''Return the name of an environment variable that does not exist. + """Return the name of an environment variable that does not exist. Args: None. Returns: The name of an environment variable. - ''' + """ n = 0 while True: @@ -77,63 +77,67 @@ class StateTestEnv(object): return var n += 1 -@pytest.fixture(scope='module') +ste = None +@pytest.fixture(scope='function') def state_test_env(u_boot_console): - '''pytest fixture to provide a StateTestEnv object to tests.''' + """pytest fixture to provide a StateTestEnv object to tests.""" - return StateTestEnv(u_boot_console) + global ste + if not ste: + ste = StateTestEnv(u_boot_console) + return ste def unset_var(state_test_env, var): - '''Unset an environment variable. + """Unset an environment variable. This both executes a U-Boot shell command and updates a StateTestEnv object. Args: - state_test_env: The StateTestEnv object to updata. + state_test_env: The StateTestEnv object to update. var: The variable name to unset. Returns: Nothing. - ''' + """ state_test_env.u_boot_console.run_command('setenv %s' % var) if var in state_test_env.env: del state_test_env.env[var] def set_var(state_test_env, var, value): - '''Set an environment variable. + """Set an environment variable. This both executes a U-Boot shell command and updates a StateTestEnv object. Args: - state_test_env: The StateTestEnv object to updata. + state_test_env: The StateTestEnv object to update. var: The variable name to set. value: The value to set the variable to. Returns: Nothing. - ''' + """ state_test_env.u_boot_console.run_command('setenv %s "%s"' % (var, value)) state_test_env.env[var] = value def validate_empty(state_test_env, var): - '''Validate that a variable is not set, using U-Boot shell commands. + """Validate that a variable is not set, using U-Boot shell commands. Args: var: The variable name to test. Returns: Nothing. - ''' + """ response = state_test_env.u_boot_console.run_command('echo $%s' % var) assert response == '' def validate_set(state_test_env, var, value): - '''Validate that a variable is set, using U-Boot shell commands. + """Validate that a variable is set, using U-Boot shell commands. Args: var: The variable name to test. @@ -141,7 +145,7 @@ def validate_set(state_test_env, var, value): Returns: Nothing. - ''' + """ # echo does not preserve leading, internal, or trailing whitespace in the # value. printenv does, and hence allows more complete testing. @@ -149,20 +153,20 @@ def validate_set(state_test_env, var, value): assert response == ('%s=%s' % (var, value)) def test_env_echo_exists(state_test_env): - '''Test echoing a variable that exists.''' + """Test echoing a variable that exists.""" var = state_test_env.get_existent_var() value = state_test_env.env[var] validate_set(state_test_env, var, value) def test_env_echo_non_existent(state_test_env): - '''Test echoing a variable that doesn't exist.''' + """Test echoing a variable that doesn't exist.""" var = state_test_env.set_var validate_empty(state_test_env, var) def test_env_printenv_non_existent(state_test_env): - '''Test printenv error message for non-existant variables.''' + """Test printenv error message for non-existant variables.""" var = state_test_env.set_var c = state_test_env.u_boot_console @@ -171,14 +175,14 @@ def test_env_printenv_non_existent(state_test_env): assert(response == '## Error: "%s" not defined' % var) def test_env_unset_non_existent(state_test_env): - '''Test unsetting a nonexistent variable.''' + """Test unsetting a nonexistent variable.""" var = state_test_env.get_non_existent_var() unset_var(state_test_env, var) validate_empty(state_test_env, var) def test_env_set_non_existent(state_test_env): - '''Test set a non-existant variable.''' + """Test set a non-existant variable.""" var = state_test_env.set_var value = 'foo' @@ -186,7 +190,7 @@ def test_env_set_non_existent(state_test_env): validate_set(state_test_env, var, value) def test_env_set_existing(state_test_env): - '''Test setting an existant variable.''' + """Test setting an existant variable.""" var = state_test_env.set_var value = 'bar' @@ -194,14 +198,14 @@ def test_env_set_existing(state_test_env): validate_set(state_test_env, var, value) def test_env_unset_existing(state_test_env): - '''Test unsetting a variable.''' + """Test unsetting a variable.""" var = state_test_env.set_var unset_var(state_test_env, var) validate_empty(state_test_env, var) def test_env_expansion_spaces(state_test_env): - '''Test expanding a variable that contains a space in its value.''' + """Test expanding a variable that contains a space in its value.""" var_space = None var_test = None diff --git a/test/py/tests/test_help.py b/test/py/tests/test_help.py index 894f3b5f17..420090cf0d 100644 --- a/test/py/tests/test_help.py +++ b/test/py/tests/test_help.py @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0 def test_help(u_boot_console): - '''Test that the "help" command can be executed.''' + """Test that the "help" command can be executed.""" u_boot_console.run_command('help') diff --git a/test/py/tests/test_hush_if_test.py b/test/py/tests/test_hush_if_test.py index cf4c3aeeb7..8b88425a65 100644 --- a/test/py/tests/test_hush_if_test.py +++ b/test/py/tests/test_hush_if_test.py @@ -95,7 +95,7 @@ subtests = ( ) def exec_hush_if(u_boot_console, expr, result): - '''Execute a shell "if" command, and validate its result.''' + """Execute a shell "if" command, and validate its result.""" cmd = 'if ' + expr + '; then echo true; else echo false; fi' response = u_boot_console.run_command(cmd) @@ -103,7 +103,7 @@ def exec_hush_if(u_boot_console, expr, result): @pytest.mark.buildconfigspec('sys_hush_parser') def test_hush_if_test_setup(u_boot_console): - '''Set up environment variables used during the "if" tests.''' + """Set up environment variables used during the "if" tests.""" u_boot_console.run_command('setenv ut_var_nonexistent') u_boot_console.run_command('setenv ut_var_exists 1') @@ -111,13 +111,13 @@ def test_hush_if_test_setup(u_boot_console): @pytest.mark.buildconfigspec('sys_hush_parser') @pytest.mark.parametrize('expr,result', subtests) def test_hush_if_test(u_boot_console, expr, result): - '''Test a single "if test" condition.''' + """Test a single "if test" condition.""" exec_hush_if(u_boot_console, expr, result) @pytest.mark.buildconfigspec('sys_hush_parser') def test_hush_if_test_teardown(u_boot_console): - '''Clean up environment variables used during the "if" tests.''' + """Clean up environment variables used during the "if" tests.""" u_boot_console.run_command('setenv ut_var_exists') @@ -126,7 +126,7 @@ def test_hush_if_test_teardown(u_boot_console): # Of those, only UMS currently allows file removal though. @pytest.mark.boardspec('sandbox') def test_hush_if_test_host_file_exists(u_boot_console): - '''Test the "if test -e" shell command.''' + """Test the "if test -e" shell command.""" test_file = u_boot_console.config.result_dir + \ '/creating_this_file_breaks_u_boot_tests' diff --git a/test/py/tests/test_md.py b/test/py/tests/test_md.py index 94603c7df6..5fe25826b3 100644 --- a/test/py/tests/test_md.py +++ b/test/py/tests/test_md.py @@ -4,13 +4,14 @@ # SPDX-License-Identifier: GPL-2.0 import pytest +import u_boot_utils @pytest.mark.buildconfigspec('cmd_memory') def test_md(u_boot_console): - '''Test that md reads memory as expected, and that memory can be modified - using the mw command.''' + """Test that md reads memory as expected, and that memory can be modified + using the mw command.""" - ram_base = u_boot_console.find_ram_base() + ram_base = u_boot_utils.find_ram_base(u_boot_console) addr = '%08x' % ram_base val = 'a5f09876' expected_response = addr + ': ' + val @@ -23,10 +24,10 @@ def test_md(u_boot_console): @pytest.mark.buildconfigspec('cmd_memory') def test_md_repeat(u_boot_console): - '''Test command repeat (via executing an empty command) operates correctly - for "md"; the command must repeat and dump an incrementing address.''' + """Test command repeat (via executing an empty command) operates correctly + for "md"; the command must repeat and dump an incrementing address.""" - ram_base = u_boot_console.find_ram_base() + ram_base = u_boot_utils.find_ram_base(u_boot_console) addr_base = '%08x' % ram_base words = 0x10 addr_repeat = '%08x' % (ram_base + (words * 4)) diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py new file mode 100644 index 0000000000..07393eb1fd --- /dev/null +++ b/test/py/tests/test_net.py @@ -0,0 +1,155 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0 + +# Test various network-related functionality, such as the dhcp, ping, and +# tftpboot commands. + +import pytest +import u_boot_utils + +""" +Note: This test relies on boardenv_* containing configuration values to define +which the network environment available for testing. Without this, this test +will be automatically skipped. + +For example: + +# Boolean indicating whether the Ethernet device is attached to USB, and hence +# USB enumeration needs to be performed prior to network tests. +# This variable may be omitted if its value is False. +env__net_uses_usb = False + +# Boolean indicating whether the Ethernet device is attached to PCI, and hence +# PCI enumeration needs to be performed prior to network tests. +# This variable may be omitted if its value is False. +env__net_uses_pci = True + +# True if a DHCP server is attached to the network, and should be tested. +# If DHCP testing is not possible or desired, this variable may be omitted or +# set to False. +env__net_dhcp_server = True + +# A list of environment variables that should be set in order to configure a +# static IP. If solely relying on DHCP, this variable may be omitted or set to +# an empty list. +env__net_static_env_vars = [ + ("ipaddr", "10.0.0.100"), + ("netmask", "255.255.255.0"), + ("serverip", "10.0.0.1"), +] + +# Details regarding a file that may be read from a TFTP server. This variable +# may be omitted or set to None if TFTP testing is not possible or desired. +env__net_tftp_readable_file = { + "fn": "ubtest-readable.bin", + "size": 5058624, + "crc32": "c2244b26", +} +""" + +net_set_up = False + +def test_net_pre_commands(u_boot_console): + """Execute any commands required to enable network hardware. + + These commands are provided by the boardenv_* file; see the comment at the + beginning of this file. + """ + + init_usb = u_boot_console.config.env.get('env__net_uses_usb', False) + if init_usb: + u_boot_console.run_command('usb start') + + init_pci = u_boot_console.config.env.get('env__net_uses_pci', False) + if init_pci: + u_boot_console.run_command('pci enum') + +@pytest.mark.buildconfigspec('cmd_dhcp') +def test_net_dhcp(u_boot_console): + """Test the dhcp command. + + The boardenv_* file may be used to enable/disable this test; see the + comment at the beginning of this file. + """ + + test_dhcp = u_boot_console.config.env.get('env__net_dhcp_server', False) + if not test_dhcp: + pytest.skip('No DHCP server available') + + u_boot_console.run_command('setenv autoload no') + output = u_boot_console.run_command('dhcp') + assert 'DHCP client bound to address ' in output + + global net_set_up + net_set_up = True + +@pytest.mark.buildconfigspec('net') +def test_net_setup_static(u_boot_console): + """Set up a static IP configuration. + + The configuration is provided by the boardenv_* file; see the comment at + the beginning of this file. + """ + + env_vars = u_boot_console.config.env.get('env__net_static_env_vars', None) + if not env_vars: + pytest.skip('No static network configuration is defined') + + for (var, val) in env_vars: + u_boot_console.run_command('setenv %s %s' % (var, val)) + + global net_set_up + net_set_up = True + +@pytest.mark.buildconfigspec('cmd_ping') +def test_net_ping(u_boot_console): + """Test the ping command. + + The $serverip (as set up by either test_net_dhcp or test_net_setup_static) + is pinged. The test validates that the host is alive, as reported by the + ping command's output. + """ + + if not net_set_up: + pytest.skip('Network not initialized') + + output = u_boot_console.run_command('ping $serverip') + assert 'is alive' in output + +@pytest.mark.buildconfigspec('cmd_net') +def test_net_tftpboot(u_boot_console): + """Test the tftpboot command. + + A file is downloaded from the TFTP server, its size and optionally its + CRC32 are validated. + + The details of the file to download are provided by the boardenv_* file; + see the comment at the beginning of this file. + """ + + if not net_set_up: + pytest.skip('Network not initialized') + + f = u_boot_console.config.env.get('env__net_tftp_readable_file', None) + if not f: + pytest.skip('No TFTP readable file to read') + + addr = u_boot_utils.find_ram_base(u_boot_console) + fn = f['fn'] + output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn)) + expected_text = 'Bytes transferred = ' + sz = f.get('size', None) + if sz: + expected_text += '%d' % sz + assert expected_text in output + + expected_crc = f.get('crc32', None) + if not expected_crc: + return + + if u_boot_console.config.buildconfig.get('config_cmd_crc32', 'n') != 'y': + return + + output = u_boot_console.run_command('crc32 %x $filesize' % addr) + assert expected_crc in output diff --git a/test/py/tests/test_sandbox_exit.py b/test/py/tests/test_sandbox_exit.py index 2aa8eb4abc..d1aa3083f4 100644 --- a/test/py/tests/test_sandbox_exit.py +++ b/test/py/tests/test_sandbox_exit.py @@ -9,16 +9,14 @@ import signal @pytest.mark.boardspec('sandbox') @pytest.mark.buildconfigspec('reset') def test_reset(u_boot_console): - '''Test that the "reset" command exits sandbox process.''' + """Test that the "reset" command exits sandbox process.""" u_boot_console.run_command('reset', wait_for_prompt=False) assert(u_boot_console.validate_exited()) - u_boot_console.ensure_spawned() @pytest.mark.boardspec('sandbox') def test_ctrl_c(u_boot_console): - '''Test that sending SIGINT to sandbox causes it to exit.''' + """Test that sending SIGINT to sandbox causes it to exit.""" u_boot_console.kill(signal.SIGINT) assert(u_boot_console.validate_exited()) - u_boot_console.ensure_spawned() diff --git a/test/py/tests/test_shell_basics.py b/test/py/tests/test_shell_basics.py index 719ce611d7..702e5e27e0 100644 --- a/test/py/tests/test_shell_basics.py +++ b/test/py/tests/test_shell_basics.py @@ -5,13 +5,13 @@ # Test basic shell functionality, such as commands separate by semi-colons. def test_shell_execute(u_boot_console): - '''Test any shell command.''' + """Test any shell command.""" response = u_boot_console.run_command('echo hello') assert response.strip() == 'hello' def test_shell_semicolon_two(u_boot_console): - '''Test two shell commands separate by a semi-colon.''' + """Test two shell commands separate by a semi-colon.""" cmd = 'echo hello; echo world' response = u_boot_console.run_command(cmd) @@ -19,8 +19,8 @@ def test_shell_semicolon_two(u_boot_console): assert response.index('hello') < response.index('world') def test_shell_semicolon_three(u_boot_console): - '''Test three shell commands separate by a semi-colon, with variable - expansion dependencies between them.''' + """Test three shell commands separate by a semi-colon, with variable + expansion dependencies between them.""" cmd = 'setenv list 1; setenv list ${list}2; setenv list ${list}3; ' + \ 'echo ${list}' @@ -29,9 +29,9 @@ def test_shell_semicolon_three(u_boot_console): u_boot_console.run_command('setenv list') def test_shell_run(u_boot_console): - '''Test the "run" shell command.''' + """Test the "run" shell command.""" - u_boot_console.run_command('setenv foo \"setenv monty 1; setenv python 2\"') + u_boot_console.run_command('setenv foo "setenv monty 1; setenv python 2"') u_boot_console.run_command('run foo') response = u_boot_console.run_command('echo $monty') assert response.strip() == '1' diff --git a/test/py/tests/test_sleep.py b/test/py/tests/test_sleep.py index 64f1ddf9a0..74add891c3 100644 --- a/test/py/tests/test_sleep.py +++ b/test/py/tests/test_sleep.py @@ -6,12 +6,8 @@ import pytest import time def test_sleep(u_boot_console): - '''Test the sleep command, and validate that it sleeps for approximately - the correct amount of time.''' - - # Do this before we time anything, to make sure U-Boot is already running. - # Otherwise, the system boot time is included in the time measurement. - u_boot_console.ensure_spawned() + """Test the sleep command, and validate that it sleeps for approximately + the correct amount of time.""" # 3s isn't too long, but is enough to cross a few second boundaries. sleep_time = 3 diff --git a/test/py/tests/test_ums.py b/test/py/tests/test_ums.py index a137221c7a..8c3ee2b053 100644 --- a/test/py/tests/test_ums.py +++ b/test/py/tests/test_ums.py @@ -2,28 +2,58 @@ # # SPDX-License-Identifier: GPL-2.0 -# Test U-Boot's "ums" command. At present, this test only ensures that a UMS -# device can be enumerated by the host/test machine. In the future, this test -# should be enhanced to validate disk IO. +# Test U-Boot's "ums" command. The test starts UMS in U-Boot, waits for USB +# device enumeration on the host, reads a small block of data from the UMS +# block device, optionally mounts a partition and performs filesystem-based +# read/write tests, and finally aborts the "ums" command in U-Boot. import os +import os.path import pytest +import re import time +import u_boot_utils -''' +""" Note: This test relies on: a) boardenv_* to contain configuration values to define which USB ports are available for testing. Without this, this test will be automatically skipped. For example: +# Leave this list empty if you have no block_devs below with writable +# partitions defined. +env__mount_points = ( + "/mnt/ubtest-mnt-p2371-2180-na", +) + env__usb_dev_ports = ( - {'tgt_usb_ctlr': '0', 'host_ums_dev_node': '/dev/disk/by-path/pci-0000:00:14.0-usb-0:13:1.0-scsi-0:0:0:0'}, + { + "fixture_id": "micro_b", + "tgt_usb_ctlr": "0", + "host_ums_dev_node": "/dev/disk/by-path/pci-0000:00:14.0-usb-0:13:1.0-scsi-0:0:0:0", + }, ) env__block_devs = ( - {'type': 'mmc', 'id': '0'}, # eMMC; always present - {'type': 'mmc', 'id': '1'}, # SD card; present since I plugged one in + # eMMC; always present + { + "fixture_id": "emmc", + "type": "mmc", + "id": "0", + # The following two properties are optional. + # If present, the partition will be mounted and a file written-to and + # read-from it. If missing, only a simple block read test will be + # performed. + "writable_fs_partition": 1, + "writable_fs_subdir": "tmp/", + }, + # SD card; present since I plugged one in + { + "fixture_id": "sd", + "type": "mmc", + "id": "1" + }, ) b) udev rules to set permissions on devices nodes, so that sudo is not @@ -34,47 +64,42 @@ ACTION=="add", SUBSYSTEM=="block", SUBSYSTEMS=="usb", KERNELS=="3-13", MODE:="66 (You may wish to change the group ID instead of setting the permissions wide open. All that matters is that the user ID running the test can access the device.) -''' -def open_ums_device(host_ums_dev_node): - '''Attempt to open a device node, returning either the opened file handle, - or None on any error.''' +c) /etc/fstab entries to allow the block device to be mounted without requiring +root permissions. For example: - try: - return open(host_ums_dev_node, 'rb') - except: - return None - -def wait_for_ums_device(host_ums_dev_node): - '''Continually attempt to open the device node exported by the "ums" - command, and either return the opened file handle, or raise an exception - after a timeout.''' - - for i in xrange(100): - fh = open_ums_device(host_ums_dev_node) - if fh: - return fh - time.sleep(0.1) - raise Exception('UMS device did not appear') - -def wait_for_ums_device_gone(host_ums_dev_node): - '''Continually attempt to open the device node exported by the "ums" - command, and either return once the device has disappeared, or raise an - exception if it does not before a timeout occurs.''' - - for i in xrange(100): - fh = open_ums_device(host_ums_dev_node) - if not fh: - return - fh.close() - time.sleep(0.1) - raise Exception('UMS device did not disappear') +/dev/disk/by-path/pci-0000:00:14.0-usb-0:13:1.0-scsi-0:0:0:0-part1 /mnt/ubtest-mnt-p2371-2180-na ext4 noauto,user,nosuid,nodev + +This entry is only needed if any block_devs above contain a +writable_fs_partition value. +""" @pytest.mark.buildconfigspec('cmd_usb_mass_storage') def test_ums(u_boot_console, env__usb_dev_port, env__block_devs): - '''Test the "ums" command; the host system must be able to enumerate a UMS - device when "ums" is running, and this device must disappear when "ums" is - aborted.''' + """Test the "ums" command; the host system must be able to enumerate a UMS + device when "ums" is running, block and optionally file I/O are tested, + and this device must disappear when "ums" is aborted. + + Args: + u_boot_console: A U-Boot console connection. + env__usb_dev_port: The single USB device-mode port specification on + which to run the test. See the file-level comment above for + details of the format. + env__block_devs: The list of block devices that the target U-Boot + device has attached. See the file-level comment above for details + of the format. + + Returns: + Nothing. + """ + + have_writable_fs_partition = 'writable_fs_partition' in env__block_devs[0] + if not have_writable_fs_partition: + # If 'writable_fs_subdir' is missing, we'll skip all parts of the + # testing which mount filesystems. + u_boot_console.log.warning( + 'boardenv missing "writable_fs_partition"; ' + + 'UMS testing will be limited.') tgt_usb_ctlr = env__usb_dev_port['tgt_usb_ctlr'] host_ums_dev_node = env__usb_dev_port['host_ums_dev_node'] @@ -84,11 +109,129 @@ def test_ums(u_boot_console, env__usb_dev_port, env__block_devs): # device list here. We'll test each block device somewhere else. tgt_dev_type = env__block_devs[0]['type'] tgt_dev_id = env__block_devs[0]['id'] + if have_writable_fs_partition: + mount_point = u_boot_console.config.env['env__mount_points'][0] + mount_subdir = env__block_devs[0]['writable_fs_subdir'] + part_num = env__block_devs[0]['writable_fs_partition'] + host_ums_part_node = '%s-part%d' % (host_ums_dev_node, part_num) + else: + host_ums_part_node = host_ums_dev_node + + test_f = u_boot_utils.PersistentRandomFile(u_boot_console, 'ums.bin', + 1024 * 1024); + if have_writable_fs_partition: + mounted_test_fn = mount_point + '/' + mount_subdir + test_f.fn + + def start_ums(): + """Start U-Boot's ums shell command. + + This also waits for the host-side USB enumeration process to complete. + + Args: + None. + + Returns: + Nothing. + """ + + u_boot_console.log.action( + 'Starting long-running U-Boot ums shell command') + cmd = 'ums %s %s %s' % (tgt_usb_ctlr, tgt_dev_type, tgt_dev_id) + u_boot_console.run_command(cmd, wait_for_prompt=False) + u_boot_console.wait_for(re.compile('UMS: LUN.*[\r\n]')) + fh = u_boot_utils.wait_until_open_succeeds(host_ums_part_node) + u_boot_console.log.action('Reading raw data from UMS device') + fh.read(4096) + fh.close() + + def mount(): + """Mount the block device that U-Boot exports. + + Args: + None. + + Returns: + Nothing. + """ + + u_boot_console.log.action('Mounting exported UMS device') + cmd = ('/bin/mount', host_ums_part_node) + u_boot_utils.run_and_log(u_boot_console, cmd) + + def umount(ignore_errors): + """Unmount the block device that U-Boot exports. - cmd = 'ums %s %s %s' % (tgt_usb_ctlr, tgt_dev_type, tgt_dev_id) - u_boot_console.run_command('ums 0 mmc 0', wait_for_prompt=False) - fh = wait_for_ums_device(host_ums_dev_node) - fh.read(4096) - fh.close() - u_boot_console.ctrlc() - wait_for_ums_device_gone(host_ums_dev_node) + Args: + ignore_errors: Ignore any errors. This is useful if an error has + already been detected, and the code is performing best-effort + cleanup. In this case, we do not want to mask the original + error by "honoring" any new errors. + + Returns: + Nothing. + """ + + u_boot_console.log.action('Unmounting UMS device') + cmd = ('/bin/umount', host_ums_part_node) + u_boot_utils.run_and_log(u_boot_console, cmd, ignore_errors) + + def stop_ums(ignore_errors): + """Stop U-Boot's ums shell command from executing. + + This also waits for the host-side USB de-enumeration process to + complete. + + Args: + ignore_errors: Ignore any errors. This is useful if an error has + already been detected, and the code is performing best-effort + cleanup. In this case, we do not want to mask the original + error by "honoring" any new errors. + + Returns: + Nothing. + """ + + u_boot_console.log.action( + 'Stopping long-running U-Boot ums shell command') + u_boot_console.ctrlc() + u_boot_utils.wait_until_file_open_fails(host_ums_part_node, + ignore_errors) + + ignore_cleanup_errors = True + try: + start_ums() + if not have_writable_fs_partition: + # Skip filesystem-based testing if not configured + return + try: + mount() + u_boot_console.log.action('Writing test file via UMS') + cmd = ('rm', '-f', mounted_test_fn) + u_boot_utils.run_and_log(u_boot_console, cmd) + if os.path.exists(mounted_test_fn): + raise Exception('Could not rm target UMS test file') + cmd = ('cp', test_f.abs_fn, mounted_test_fn) + u_boot_utils.run_and_log(u_boot_console, cmd) + ignore_cleanup_errors = False + finally: + umount(ignore_errors=ignore_cleanup_errors) + finally: + stop_ums(ignore_errors=ignore_cleanup_errors) + + ignore_cleanup_errors = True + try: + start_ums() + try: + mount() + u_boot_console.log.action('Reading test file back via UMS') + read_back_hash = u_boot_utils.md5sum_file(mounted_test_fn) + cmd = ('rm', '-f', mounted_test_fn) + u_boot_utils.run_and_log(u_boot_console, cmd) + ignore_cleanup_errors = False + finally: + umount(ignore_errors=ignore_cleanup_errors) + finally: + stop_ums(ignore_errors=ignore_cleanup_errors) + + written_hash = test_f.content_hash + assert(written_hash == read_back_hash) diff --git a/test/py/tests/test_unknown_cmd.py b/test/py/tests/test_unknown_cmd.py index 2de93e0026..c27ab49d55 100644 --- a/test/py/tests/test_unknown_cmd.py +++ b/test/py/tests/test_unknown_cmd.py @@ -4,8 +4,8 @@ # SPDX-License-Identifier: GPL-2.0 def test_unknown_command(u_boot_console): - '''Test that executing an unknown command causes U-Boot to print an - error.''' + """Test that executing an unknown command causes U-Boot to print an + error.""" # The "unknown command" error is actively expected here, # so error detection for it is disabled. diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py index 520f9a9e9f..392f8cb885 100644 --- a/test/py/u_boot_console_base.py +++ b/test/py/u_boot_console_base.py @@ -14,6 +14,7 @@ import os import pytest import re import sys +import u_boot_spawn # Regexes for text we expect U-Boot to send to the console. pattern_u_boot_spl_signon = re.compile('(U-Boot SPL \\d{4}\\.\\d{2}-[^\r\n]*)') @@ -21,14 +22,27 @@ pattern_u_boot_main_signon = re.compile('(U-Boot \\d{4}\\.\\d{2}-[^\r\n]*)') pattern_stop_autoboot_prompt = re.compile('Hit any key to stop autoboot: ') pattern_unknown_command = re.compile('Unknown command \'.*\' - try \'help\'') pattern_error_notification = re.compile('## Error: ') +pattern_error_please_reset = re.compile('### ERROR ### Please RESET the board ###') + +PAT_ID = 0 +PAT_RE = 1 + +bad_pattern_defs = ( + ('spl_signon', pattern_u_boot_spl_signon), + ('main_signon', pattern_u_boot_main_signon), + ('stop_autoboot_prompt', pattern_stop_autoboot_prompt), + ('unknown_command', pattern_unknown_command), + ('error_notification', pattern_error_notification), + ('error_please_reset', pattern_error_please_reset), +) class ConsoleDisableCheck(object): - '''Context manager (for Python's with statement) that temporarily disables + """Context manager (for Python's with statement) that temporarily disables the specified console output error check. This is useful when deliberately executing a command that is known to trigger one of the error checks, in order to test that the error condition is actually raised. This class is used internally by ConsoleBase::disable_check(); it is not intended for - direct usage.''' + direct usage.""" def __init__(self, console, check_type): self.console = console @@ -36,18 +50,20 @@ class ConsoleDisableCheck(object): def __enter__(self): self.console.disable_check_count[self.check_type] += 1 + self.console.eval_bad_patterns() def __exit__(self, extype, value, traceback): self.console.disable_check_count[self.check_type] -= 1 + self.console.eval_bad_patterns() class ConsoleBase(object): - '''The interface through which test functions interact with the U-Boot + """The interface through which test functions interact with the U-Boot console. This primarily involves executing shell commands, capturing their results, and checking for common error conditions. Some common utilities - are also provided too.''' + are also provided too.""" def __init__(self, log, config, max_fifo_fill): - '''Initialize a U-Boot console connection. + """Initialize a U-Boot console connection. Can only usefully be called by sub-classes. @@ -64,7 +80,7 @@ class ConsoleBase(object): Returns: Nothing. - ''' + """ self.log = log self.config = config @@ -76,19 +92,20 @@ class ConsoleBase(object): self.prompt = self.config.buildconfig['config_sys_prompt'][1:-1] self.prompt_escaped = re.escape(self.prompt) self.p = None - self.disable_check_count = { - 'spl_signon': 0, - 'main_signon': 0, - 'unknown_command': 0, - 'error_notification': 0, - } + self.disable_check_count = {pat[PAT_ID]: 0 for pat in bad_pattern_defs} + self.eval_bad_patterns() self.at_prompt = False self.at_prompt_logevt = None - self.ram_base = None + + def eval_bad_patterns(self): + self.bad_patterns = [pat[PAT_RE] for pat in bad_pattern_defs \ + if self.disable_check_count[pat[PAT_ID]] == 0] + self.bad_pattern_ids = [pat[PAT_ID] for pat in bad_pattern_defs \ + if self.disable_check_count[pat[PAT_ID]] == 0] def close(self): - '''Terminate the connection to the U-Boot console. + """Terminate the connection to the U-Boot console. This function is only useful once all interaction with U-Boot is complete. Once this function is called, data cannot be sent to or @@ -99,7 +116,7 @@ class ConsoleBase(object): Returns: Nothing. - ''' + """ if self.p: self.p.close() @@ -107,7 +124,7 @@ class ConsoleBase(object): def run_command(self, cmd, wait_for_echo=True, send_nl=True, wait_for_prompt=True): - '''Execute a command via the U-Boot console. + """Execute a command via the U-Boot console. The command is always sent to U-Boot. @@ -142,29 +159,12 @@ class ConsoleBase(object): The output from U-Boot during command execution. In other words, the text U-Boot emitted between the point it echod the command string and emitted the subsequent command prompts. - ''' - - self.ensure_spawned() + """ if self.at_prompt and \ self.at_prompt_logevt != self.logstream.logfile.cur_evt: self.logstream.write(self.prompt, implicit=True) - bad_patterns = [] - bad_pattern_ids = [] - if (self.disable_check_count['spl_signon'] == 0 and - self.u_boot_spl_signon): - bad_patterns.append(self.u_boot_spl_signon_escaped) - bad_pattern_ids.append('SPL signon') - if self.disable_check_count['main_signon'] == 0: - bad_patterns.append(self.u_boot_main_signon_escaped) - bad_pattern_ids.append('U-Boot main signon') - if self.disable_check_count['unknown_command'] == 0: - bad_patterns.append(pattern_unknown_command) - bad_pattern_ids.append('Unknown command') - if self.disable_check_count['error_notification'] == 0: - bad_patterns.append(pattern_error_notification) - bad_pattern_ids.append('Error notification') try: self.at_prompt = False if send_nl: @@ -178,18 +178,18 @@ class ConsoleBase(object): continue chunk = re.escape(chunk) chunk = chunk.replace('\\\n', '[\r\n]') - m = self.p.expect([chunk] + bad_patterns) + m = self.p.expect([chunk] + self.bad_patterns) if m != 0: self.at_prompt = False raise Exception('Bad pattern found on console: ' + - bad_pattern_ids[m - 1]) + self.bad_pattern_ids[m - 1]) if not wait_for_prompt: return - m = self.p.expect([self.prompt_escaped] + bad_patterns) + m = self.p.expect([self.prompt_escaped] + self.bad_patterns) if m != 0: self.at_prompt = False raise Exception('Bad pattern found on console: ' + - bad_pattern_ids[m - 1]) + self.bad_pattern_ids[m - 1]) self.at_prompt = True self.at_prompt_logevt = self.logstream.logfile.cur_evt # Only strip \r\n; space/TAB might be significant if testing @@ -201,7 +201,7 @@ class ConsoleBase(object): raise def ctrlc(self): - '''Send a CTRL-C character to U-Boot. + """Send a CTRL-C character to U-Boot. This is useful in order to stop execution of long-running synchronous commands such as "ums". @@ -211,12 +211,72 @@ class ConsoleBase(object): Returns: Nothing. - ''' + """ + self.log.action('Sending Ctrl-C') self.run_command(chr(3), wait_for_echo=False, send_nl=False) + def wait_for(self, text): + """Wait for a pattern to be emitted by U-Boot. + + This is useful when a long-running command such as "dfu" is executing, + and it periodically emits some text that should show up at a specific + location in the log file. + + Args: + text: The text to wait for; either a string (containing raw text, + not a regular expression) or an re object. + + Returns: + Nothing. + """ + + if type(text) == type(''): + text = re.escape(text) + m = self.p.expect([text] + self.bad_patterns) + if m != 0: + raise Exception('Bad pattern found on console: ' + + self.bad_pattern_ids[m - 1]) + + def drain_console(self): + """Read from and log the U-Boot console for a short time. + + U-Boot's console output is only logged when the test code actively + waits for U-Boot to emit specific data. There are cases where tests + can fail without doing this. For example, if a test asks U-Boot to + enable USB device mode, then polls until a host-side device node + exists. In such a case, it is useful to log U-Boot's console output + in case U-Boot printed clues as to why the host-side even did not + occur. This function will do that. + + Args: + None. + + Returns: + Nothing. + """ + + # If we are already not connected to U-Boot, there's nothing to drain. + # This should only happen when a previous call to run_command() or + # wait_for() failed (and hence the output has already been logged), or + # the system is shutting down. + if not self.p: + return + + orig_timeout = self.p.timeout + try: + # Drain the log for a relatively short time. + self.p.timeout = 1000 + # Wait for something U-Boot will likely never send. This will + # cause the console output to be read and logged. + self.p.expect(['This should never match U-Boot output']) + except u_boot_spawn.Timeout: + pass + finally: + self.p.timeout = orig_timeout + def ensure_spawned(self): - '''Ensure a connection to a correctly running U-Boot instance. + """Ensure a connection to a correctly running U-Boot instance. This may require spawning a new Sandbox process or resetting target hardware, as defined by the implementation sub-class. @@ -228,7 +288,7 @@ class ConsoleBase(object): Returns: Nothing. - ''' + """ if self.p: return @@ -243,26 +303,30 @@ class ConsoleBase(object): self.p.timeout = 30000 self.p.logfile_read = self.logstream if self.config.buildconfig.get('CONFIG_SPL', False) == 'y': - self.p.expect([pattern_u_boot_spl_signon]) - self.u_boot_spl_signon = self.p.after - self.u_boot_spl_signon_escaped = re.escape(self.p.after) - else: - self.u_boot_spl_signon = None - self.p.expect([pattern_u_boot_main_signon]) - self.u_boot_main_signon = self.p.after - self.u_boot_main_signon_escaped = re.escape(self.p.after) - build_idx = self.u_boot_main_signon.find(', Build:') + m = self.p.expect([pattern_u_boot_spl_signon] + self.bad_patterns) + if m != 0: + raise Exception('Bad pattern found on console: ' + + self.bad_pattern_ids[m - 1]) + m = self.p.expect([pattern_u_boot_main_signon] + self.bad_patterns) + if m != 0: + raise Exception('Bad pattern found on console: ' + + self.bad_pattern_ids[m - 1]) + signon = self.p.after + build_idx = signon.find(', Build:') if build_idx == -1: - self.u_boot_version_string = self.u_boot_main_signon + self.u_boot_version_string = signon else: - self.u_boot_version_string = self.u_boot_main_signon[:build_idx] + self.u_boot_version_string = signon[:build_idx] while True: - match = self.p.expect([self.prompt_escaped, - pattern_stop_autoboot_prompt]) - if match == 1: + m = self.p.expect([self.prompt_escaped, + pattern_stop_autoboot_prompt] + self.bad_patterns) + if m == 0: + break + if m == 1: self.p.send(chr(3)) # CTRL-C continue - break + raise Exception('Bad pattern found on console: ' + + self.bad_pattern_ids[m - 2]) self.at_prompt = True self.at_prompt_logevt = self.logstream.logfile.cur_evt except Exception as ex: @@ -271,7 +335,7 @@ class ConsoleBase(object): raise def cleanup_spawn(self): - '''Shut down all interaction with the U-Boot instance. + """Shut down all interaction with the U-Boot instance. This is used when an error is detected prior to re-establishing a connection with a fresh U-Boot instance. @@ -283,7 +347,7 @@ class ConsoleBase(object): Returns: Nothing. - ''' + """ try: if self.p: @@ -293,7 +357,7 @@ class ConsoleBase(object): self.p = None def validate_version_string_in_text(self, text): - '''Assert that a command's output includes the U-Boot signon message. + """Assert that a command's output includes the U-Boot signon message. This is primarily useful for validating the "version" command without duplicating the signon text regex in a test function. @@ -303,12 +367,12 @@ class ConsoleBase(object): Returns: Nothing. An exception is raised if the validation fails. - ''' + """ assert(self.u_boot_version_string in text) def disable_check(self, check_type): - '''Temporarily disable an error check of U-Boot's output. + """Temporarily disable an error check of U-Boot's output. Create a new context manager (for use with the "with" statement) which temporarily disables a particular console output error check. @@ -319,42 +383,6 @@ class ConsoleBase(object): Returns: A context manager object. - ''' + """ return ConsoleDisableCheck(self, check_type) - - def find_ram_base(self): - '''Find the running U-Boot's RAM location. - - Probe the running U-Boot to determine the address of the first bank - of RAM. This is useful for tests that test reading/writing RAM, or - load/save files that aren't associated with some standard address - typically represented in an environment variable such as - ${kernel_addr_r}. The value is cached so that it only needs to be - actively read once. - - Args: - None. - - Returns: - The address of U-Boot's first RAM bank, as an integer. - ''' - - if self.config.buildconfig.get('config_cmd_bdi', 'n') != 'y': - pytest.skip('bdinfo command not supported') - if self.ram_base == -1: - pytest.skip('Previously failed to find RAM bank start') - if self.ram_base is not None: - return self.ram_base - - with self.log.section('find_ram_base'): - response = self.run_command('bdinfo') - for l in response.split('\n'): - if '-> start' in l: - self.ram_base = int(l.split('=')[1].strip(), 16) - break - if self.ram_base is None: - self.ram_base = -1 - raise Exception('Failed to find RAM bank start in `bdinfo`') - - return self.ram_base diff --git a/test/py/u_boot_console_exec_attach.py b/test/py/u_boot_console_exec_attach.py index 0ca9e7c178..19520cb3b9 100644 --- a/test/py/u_boot_console_exec_attach.py +++ b/test/py/u_boot_console_exec_attach.py @@ -11,15 +11,15 @@ from u_boot_spawn import Spawn from u_boot_console_base import ConsoleBase class ConsoleExecAttach(ConsoleBase): - '''Represents a physical connection to a U-Boot console, typically via a + """Represents a physical connection to a U-Boot console, typically via a serial port. This implementation executes a sub-process to attach to the console, expecting that the stdin/out of the sub-process will be forwarded to/from the physical hardware. This approach isolates the test infra- structure from the user-/installation-specific details of how to - communicate with, and the identity of, serial ports etc.''' + communicate with, and the identity of, serial ports etc.""" def __init__(self, log, config): - '''Initialize a U-Boot console connection. + """Initialize a U-Boot console connection. Args: log: A multiplexed_log.Logfile instance. @@ -27,7 +27,7 @@ class ConsoleExecAttach(ConsoleBase): Returns: Nothing. - ''' + """ # The max_fifo_fill value might need tweaking per-board/-SoC? # 1 would be safe anywhere, but is very slow (a pexpect issue?). @@ -42,7 +42,7 @@ class ConsoleExecAttach(ConsoleBase): runner.close() def get_spawn(self): - '''Connect to a fresh U-Boot instance. + """Connect to a fresh U-Boot instance. The target board is reset, so that U-Boot begins running from scratch. @@ -51,7 +51,7 @@ class ConsoleExecAttach(ConsoleBase): Returns: A u_boot_spawn.Spawn object that is attached to U-Boot. - ''' + """ args = [self.config.board_type, self.config.board_identity] s = Spawn(['u-boot-test-console'] + args) diff --git a/test/py/u_boot_console_sandbox.py b/test/py/u_boot_console_sandbox.py index 88b137e8c3..a7263f30b8 100644 --- a/test/py/u_boot_console_sandbox.py +++ b/test/py/u_boot_console_sandbox.py @@ -10,11 +10,11 @@ from u_boot_spawn import Spawn from u_boot_console_base import ConsoleBase class ConsoleSandbox(ConsoleBase): - '''Represents a connection to a sandbox U-Boot console, executed as a sub- - process.''' + """Represents a connection to a sandbox U-Boot console, executed as a sub- + process.""" def __init__(self, log, config): - '''Initialize a U-Boot console connection. + """Initialize a U-Boot console connection. Args: log: A multiplexed_log.Logfile instance. @@ -22,12 +22,12 @@ class ConsoleSandbox(ConsoleBase): Returns: Nothing. - ''' + """ super(ConsoleSandbox, self).__init__(log, config, max_fifo_fill=1024) def get_spawn(self): - '''Connect to a fresh U-Boot instance. + """Connect to a fresh U-Boot instance. A new sandbox process is created, so that U-Boot begins running from scratch. @@ -37,26 +37,30 @@ class ConsoleSandbox(ConsoleBase): Returns: A u_boot_spawn.Spawn object that is attached to U-Boot. - ''' + """ - return Spawn([self.config.build_dir + '/u-boot']) + cmd = [ + self.config.build_dir + '/u-boot', + '-d', + self.config.build_dir + '/arch/sandbox/dts/test.dtb' + ] + return Spawn(cmd, cwd=self.config.source_dir) def kill(self, sig): - '''Send a specific Unix signal to the sandbox process. + """Send a specific Unix signal to the sandbox process. Args: sig: The Unix signal to send to the process. Returns: Nothing. - ''' + """ - self.ensure_spawned() self.log.action('kill %d' % sig) self.p.kill(sig) def validate_exited(self): - '''Determine whether the sandbox process has exited. + """Determine whether the sandbox process has exited. If required, this function waits a reasonable time for the process to exit. @@ -66,7 +70,7 @@ class ConsoleSandbox(ConsoleBase): Returns: Boolean indicating whether the process has exited. - ''' + """ p = self.p self.p = None diff --git a/test/py/u_boot_spawn.py b/test/py/u_boot_spawn.py index 1baee63df2..0f52d3e945 100644 --- a/test/py/u_boot_spawn.py +++ b/test/py/u_boot_spawn.py @@ -12,23 +12,25 @@ import select import time class Timeout(Exception): - '''An exception sub-class that indicates that a timeout occurred.''' + """An exception sub-class that indicates that a timeout occurred.""" pass class Spawn(object): - '''Represents the stdio of a freshly created sub-process. Commands may be + """Represents the stdio of a freshly created sub-process. Commands may be sent to the process, and responses waited for. - ''' + """ - def __init__(self, args): - '''Spawn (fork/exec) the sub-process. + def __init__(self, args, cwd=None): + """Spawn (fork/exec) the sub-process. Args: - args: array of processs arguments. argv[0] is the command to execute. + args: array of processs arguments. argv[0] is the command to + execute. + cwd: the directory to run the process in, or None for no change. Returns: Nothing. - ''' + """ self.waited = False self.buf = '' @@ -44,6 +46,8 @@ class Spawn(object): # run under "go" (www.go.cd). Perhaps this happens under any # background (non-interactive) system? signal.signal(signal.SIGHUP, signal.SIG_DFL) + if cwd: + os.chdir(cwd) os.execvp(args[0], args) except: print 'CHILD EXECEPTION:' @@ -56,26 +60,26 @@ class Spawn(object): self.poll.register(self.fd, select.POLLIN | select.POLLPRI | select.POLLERR | select.POLLHUP | select.POLLNVAL) def kill(self, sig): - '''Send unix signal "sig" to the child process. + """Send unix signal "sig" to the child process. Args: sig: The signal number to send. Returns: Nothing. - ''' + """ os.kill(self.pid, sig) def isalive(self): - '''Determine whether the child process is still running. + """Determine whether the child process is still running. Args: None. Returns: Boolean indicating whether process is alive. - ''' + """ if self.waited: return False @@ -88,19 +92,19 @@ class Spawn(object): return False def send(self, data): - '''Send data to the sub-process's stdin. + """Send data to the sub-process's stdin. Args: data: The data to send to the process. Returns: Nothing. - ''' + """ os.write(self.fd, data) def expect(self, patterns): - '''Wait for the sub-process to emit specific data. + """Wait for the sub-process to emit specific data. This function waits for the process to emit one pattern from the supplied list of patterns, or for a timeout to occur. @@ -116,12 +120,13 @@ class Spawn(object): Notable exceptions: Timeout, if the process did not emit any of the patterns within the expected time. - ''' + """ for pi in xrange(len(patterns)): if type(patterns[pi]) == type(''): patterns[pi] = re.compile(patterns[pi]) + tstart_s = time.time() try: while True: earliest_m = None @@ -131,7 +136,7 @@ class Spawn(object): m = pattern.search(self.buf) if not m: continue - if earliest_m and m.start() > earliest_m.start(): + if earliest_m and m.start() >= earliest_m.start(): continue earliest_m = m earliest_pi = pi @@ -142,7 +147,11 @@ class Spawn(object): self.after = self.buf[pos:posafter] self.buf = self.buf[posafter:] return earliest_pi - events = self.poll.poll(self.timeout) + tnow_s = time.time() + tdelta_ms = (tnow_s - tstart_s) * 1000 + if tdelta_ms > self.timeout: + raise Timeout() + events = self.poll.poll(self.timeout - tdelta_ms) if not events: raise Timeout() c = os.read(self.fd, 1024) @@ -156,7 +165,7 @@ class Spawn(object): self.logfile_read.flush() def close(self): - '''Close the stdio connection to the sub-process. + """Close the stdio connection to the sub-process. This also waits a reasonable time for the sub-process to stop running. @@ -165,7 +174,7 @@ class Spawn(object): Returns: Nothing. - ''' + """ os.close(self.fd) for i in xrange(100): diff --git a/test/py/u_boot_utils.py b/test/py/u_boot_utils.py new file mode 100644 index 0000000000..72d24e42aa --- /dev/null +++ b/test/py/u_boot_utils.py @@ -0,0 +1,209 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0 + +# Utility code shared across multiple tests. + +import hashlib +import os +import os.path +import sys +import time + +def md5sum_data(data): + """Calculate the MD5 hash of some data. + + Args: + data: The data to hash. + + Returns: + The hash of the data, as a binary string. + """ + + h = hashlib.md5() + h.update(data) + return h.digest() + +def md5sum_file(fn, max_length=None): + """Calculate the MD5 hash of the contents of a file. + + Args: + fn: The filename of the file to hash. + max_length: The number of bytes to hash. If the file has more + bytes than this, they will be ignored. If None or omitted, the + entire file will be hashed. + + Returns: + The hash of the file content, as a binary string. + """ + + with open(fn, 'rb') as fh: + if max_length: + params = [max_length] + else: + params = [] + data = fh.read(*params) + return md5sum_data(data) + +class PersistentRandomFile(object): + """Generate and store information about a persistent file containing + random data.""" + + def __init__(self, u_boot_console, fn, size): + """Create or process the persistent file. + + If the file does not exist, it is generated. + + If the file does exist, its content is hashed for later comparison. + + These files are always located in the "persistent data directory" of + the current test run. + + Args: + u_boot_console: A console connection to U-Boot. + fn: The filename (without path) to create. + size: The desired size of the file in bytes. + + Returns: + Nothing. + """ + + self.fn = fn + + self.abs_fn = u_boot_console.config.persistent_data_dir + '/' + fn + + if os.path.exists(self.abs_fn): + u_boot_console.log.action('Persistent data file ' + self.abs_fn + + ' already exists') + self.content_hash = md5sum_file(self.abs_fn) + else: + u_boot_console.log.action('Generating ' + self.abs_fn + + ' (random, persistent, %d bytes)' % size) + data = os.urandom(size) + with open(self.abs_fn, 'wb') as fh: + fh.write(data) + self.content_hash = md5sum_data(data) + +def attempt_to_open_file(fn): + """Attempt to open a file, without throwing exceptions. + + Any errors (exceptions) that occur during the attempt to open the file + are ignored. This is useful in order to test whether a file (in + particular, a device node) exists and can be successfully opened, in order + to poll for e.g. USB enumeration completion. + + Args: + fn: The filename to attempt to open. + + Returns: + An open file handle to the file, or None if the file could not be + opened. + """ + + try: + return open(fn, 'rb') + except: + return None + +def wait_until_open_succeeds(fn): + """Poll until a file can be opened, or a timeout occurs. + + Continually attempt to open a file, and return when this succeeds, or + raise an exception after a timeout. + + Args: + fn: The filename to attempt to open. + + Returns: + An open file handle to the file. + """ + + for i in xrange(100): + fh = attempt_to_open_file(fn) + if fh: + return fh + time.sleep(0.1) + raise Exception('File could not be opened') + +def wait_until_file_open_fails(fn, ignore_errors): + """Poll until a file cannot be opened, or a timeout occurs. + + Continually attempt to open a file, and return when this fails, or + raise an exception after a timeout. + + Args: + fn: The filename to attempt to open. + ignore_errors: Indicate whether to ignore timeout errors. If True, the + function will simply return if a timeout occurs, otherwise an + exception will be raised. + + Returns: + Nothing. + """ + + for i in xrange(100): + fh = attempt_to_open_file(fn) + if not fh: + return + fh.close() + time.sleep(0.1) + if ignore_errors: + return + raise Exception('File can still be opened') + +def run_and_log(u_boot_console, cmd, ignore_errors=False): + """Run a command and log its output. + + Args: + u_boot_console: A console connection to U-Boot. + cmd: The command to run, as an array of argv[]. + ignore_errors: Indicate whether to ignore errors. If True, the function + will simply return if the command cannot be executed or exits with + an error code, otherwise an exception will be raised if such + problems occur. + + Returns: + Nothing. + """ + + runner = u_boot_console.log.get_runner(cmd[0], sys.stdout) + runner.run(cmd, ignore_errors=ignore_errors) + runner.close() + +ram_base = None +def find_ram_base(u_boot_console): + """Find the running U-Boot's RAM location. + + Probe the running U-Boot to determine the address of the first bank + of RAM. This is useful for tests that test reading/writing RAM, or + load/save files that aren't associated with some standard address + typically represented in an environment variable such as + ${kernel_addr_r}. The value is cached so that it only needs to be + actively read once. + + Args: + u_boot_console: A console connection to U-Boot. + + Returns: + The address of U-Boot's first RAM bank, as an integer. + """ + + global ram_base + if u_boot_console.config.buildconfig.get('config_cmd_bdi', 'n') != 'y': + pytest.skip('bdinfo command not supported') + if ram_base == -1: + pytest.skip('Previously failed to find RAM bank start') + if ram_base is not None: + return ram_base + + with u_boot_console.log.section('find_ram_base'): + response = u_boot_console.run_command('bdinfo') + for l in response.split('\n'): + if '-> start' in l: + ram_base = int(l.split('=')[1].strip(), 16) + break + if ram_base is None: + ram_base = -1 + raise Exception('Failed to find RAM bank start in `bdinfo`') + + return ram_base diff --git a/test/ums/README b/test/ums/README deleted file mode 100644 index c80fbfefbf..0000000000 --- a/test/ums/README +++ /dev/null @@ -1,30 +0,0 @@ -UMS test script. - -ums_gadget_test.sh -================== - -Example usage: -1. On the target: - create UMS exportable partitions (with e.g. gpt write), or specify a - partition number (PART_NUM) as "-" to use the entire device - ums 0 mmc 0 -2. On the host: - sudo test/ums/ums_gadget_test.sh VID PID PART_NUM [-f FILE_SYSTEM] [test_file] - e.g. sudo test/ums/ums_gadget_test.sh 0525 a4a5 6 -f vfat ./dat_14M.img - -... where: - VID - UMS device USB Vendor ID - PID - UMS device USB Product ID - PART_NUM - is the partition number on which UMS operates or "-" to use the - whole device - -Information about available partitions on the target one can read with using -the 'mmc part' or 'part list' commands. - -The partition num (PART_NUM) can be specified as '-' for using the whole device. - -The [-f FILE_SYSTEM] optional switch allows for formatting target partition to -FILE_SYSTEM. - -The last, optional [test_file] parameter is for specifying the exact test file -to use. diff --git a/test/ums/ums_gadget_test.sh b/test/ums/ums_gadget_test.sh deleted file mode 100755 index 9da486b266..0000000000 --- a/test/ums/ums_gadget_test.sh +++ /dev/null @@ -1,183 +0,0 @@ -#! /bin/bash - -# Copyright (C) 2014 Samsung Electronics -# Lukasz Majewski <l.majewski@samsung.com> -# -# UMS operation test script -# -# SPDX-License-Identifier: GPL-2.0+ - -clear - -COLOUR_RED="\33[31m" -COLOUR_GREEN="\33[32m" -COLOUR_ORANGE="\33[33m" -COLOUR_DEFAULT="\33[0m" - -DIR=./ -SUFFIX=img -RCV_DIR=rcv/ -LOG_FILE=./log/log-`date +%d-%m-%Y_%H-%M-%S` - -cd `dirname $0` -../dfu/dfu_gadget_test_init.sh 33M 97M - -cleanup () { - rm -rf $RCV_DIR $MNT_DIR -} - -control_c() -# run if user hits control-c -{ - echo -en "\n*** CTRL+C ***\n" - umount $MNT_DIR - cleanup - exit 0 -} - -# trap keyboard interrupt (control-c) -trap control_c SIGINT - -die () { - printf " $COLOUR_RED FAILED $COLOUR_DEFAULT \n" - cleanup - exit 1 -} - -calculate_md5sum () { - MD5SUM=`md5sum $1` - MD5SUM=`echo $MD5SUM | cut -d ' ' -f1` - echo "md5sum:"$MD5SUM -} - -ums_test_file () { - printf "$COLOUR_GREEN========================================================================================= $COLOUR_DEFAULT\n" - printf "File:$COLOUR_GREEN %s $COLOUR_DEFAULT\n" $1 - - mount /dev/$MEM_DEV $MNT_DIR - if [ -f $MNT_DIR/dat_* ]; then - rm $MNT_DIR/dat_* - fi - - cp ./$1 $MNT_DIR - - while true; do - umount $MNT_DIR > /dev/null 2>&1 - if [ $? -eq 0 ]; then - break - fi - printf "$COLOUR_ORANGE\tSleeping to wait for umount...$COLOUR_DEFAULT\n" - sleep 1 - done - - echo -n "TX: " - calculate_md5sum $1 - - MD5_TX=$MD5SUM - sleep 1 - N_FILE=$DIR$RCV_DIR${1:2}"_rcv" - - mount /dev/$MEM_DEV $MNT_DIR - cp $MNT_DIR/$1 $N_FILE || die $? - rm $MNT_DIR/$1 - umount $MNT_DIR - - echo -n "RX: " - calculate_md5sum $N_FILE - MD5_RX=$MD5SUM - - if [ "$MD5_TX" == "$MD5_RX" ]; then - printf " $COLOUR_GREEN -------> OK $COLOUR_DEFAULT \n" - else - printf " $COLOUR_RED -------> FAILED $COLOUR_DEFAULT \n" - cleanup - exit 1 - fi -} - -printf "$COLOUR_GREEN========================================================================================= $COLOUR_DEFAULT\n" -echo "U-boot UMS test program" - -if [ $EUID -ne 0 ]; then - echo "You must be root to do this." 1>&2 - exit 100 -fi - -if [ $# -lt 3 ]; then - echo "Wrong number of arguments" - echo "Example:" - echo "sudo ./ums_gadget_test.sh VID PID PART_NUM [-f ext4] [test_file]" - die -fi - -MNT_DIR="/mnt/tmp-ums-test" - -VID=$1; shift -PID=$1; shift -PART_NUM=$1; shift - -if [ "$1" == "-f" ]; then - shift - FS_TO_FORMAT=$1; shift -fi - -TEST_FILE=$1 - -for f in `find /sys -type f -name idProduct`; do - d=`dirname ${f}` - if [ `cat ${d}/idVendor` != "${VID}" ]; then - continue - fi - if [ `cat ${d}/idProduct` != "${PID}" ]; then - continue - fi - USB_DEV=${d} - break -done - -if [ -z "${USB_DEV}" ]; then - echo "Connect target" - echo "e.g. ums 0 mmc 0" - exit 1 -fi - -MEM_DEV=`find $USB_DEV -type d -name "sd[a-z]" | awk -F/ '{print $(NF)}' -` - -mkdir -p $RCV_DIR -if [ ! -d $MNT_DIR ]; then - mkdir -p $MNT_DIR -fi - -if [ "$PART_NUM" == "-" ]; then - PART_NUM="" -fi -MEM_DEV=$MEM_DEV$PART_NUM - -if [ -n "$FS_TO_FORMAT" ]; then - echo -n "Formatting partition /dev/$MEM_DEV to $FS_TO_FORMAT" - mkfs -t $FS_TO_FORMAT /dev/$MEM_DEV > /dev/null 2>&1 - if [ $? -eq 0 ]; then - printf " $COLOUR_GREEN DONE $COLOUR_DEFAULT \n" - else - die - fi -fi - -printf "Mount: /dev/$MEM_DEV \n" - -if [ -n "$TEST_FILE" ]; then - if [ ! -e $TEST_FILE ]; then - echo "No file: $TEST_FILE" - die - fi - ums_test_file $TEST_FILE -else - for file in $DIR*.$SUFFIX - do - ums_test_file $file - done -fi - -cleanup - -exit 0 |