From bd99e6d0e4769922252a7a0e44f319ab9354739d Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Thu, 11 Sep 2014 14:02:03 +0900 Subject: Revert "odroid: set MPLL clock to 880MHz" This reverts commit b09200639d4c052e2bdf0df6fe843b7a8bcf01cc. --- board/samsung/odroid/odroid.c | 60 +++++++++++++++++++++---------------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index fd5d2d2ca9..ac19527a90 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -195,8 +195,8 @@ static void board_clock_init(void) while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) continue; - /* Set MPLL to 880MHz */ - set = SDIV(0) | PDIV(3) | MDIV(110) | FSEL(0) | PLL_ENABLE(1); + /* Set MPLL to 800MHz */ + set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); @@ -220,15 +220,15 @@ static void board_clock_init(void) DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7); /* * For: - * MOUTdmc = 880 MHz - * MOUTdphy = 880 MHz + * MOUTdmc = 800 MHz + * MOUTdphy = 800 MHz * - * aclk_acp = MOUTdmc / (ratio + 1) = 220 (3) - * pclk_acp = aclk_acp / (ratio + 1) = 110 (1) - * sclk_dphy = MOUTdphy / (ratio + 1) = 440 (1) - * sclk_dmc = MOUTdmc / (ratio + 1) = 440 (1) - * aclk_dmcd = sclk_dmc / (ratio + 1) = 220 (1) - * aclk_dmcp = aclk_dmcd / (ratio + 1) = 110 (1) + * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3) + * pclk_acp = aclk_acp / (ratio + 1) = 100 (1) + * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1) + * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1) + * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1) + * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1) */ set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) | DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1); @@ -244,13 +244,13 @@ static void board_clock_init(void) C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127); /* * For: - * MOUTg2d = 880 MHz - * MOUTc2c = 880 Mhz + * MOUTg2d = 800 MHz + * MOUTc2c = 800 Mhz * MOUTpwi = 108 MHz * - * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 440 (1) - * sclk_c2c = MOUTc2c / (ratio + 1) = 440 (1) - * aclk_c2c = sclk_c2c / (ratio + 1) = 220 (1) + * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1) + * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) + * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) */ set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) | @@ -282,9 +282,9 @@ static void board_clock_init(void) clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | UART3_RATIO(15) | UART4_RATIO(15); /* - * For MOUTuart0-4: 880MHz + * For MOUTuart0-4: 800MHz * - * SCLK_UARTx = MOUTuartX / (ratio + 1) = 110 (7) + * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7) */ set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) | UART3_RATIO(7) | UART4_RATIO(7); @@ -298,12 +298,12 @@ static void board_clock_init(void) clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) | MMC1_PRE_RATIO(255); /* - * For MOUTmmc0-3 = 880 MHz (MPLL) + * For MOUTmmc0-3 = 800 MHz (MPLL) * - * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 110 (7) - * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 60 (1) - * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 110 (7) - * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 60 (1) + * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7) + * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1) + * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7) + * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1) */ set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) | MMC1_PRE_RATIO(1); @@ -318,12 +318,12 @@ static void board_clock_init(void) clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) | MMC3_PRE_RATIO(255); /* - * For MOUTmmc0-3 = 880 MHz (MPLL) + * For MOUTmmc0-3 = 800 MHz (MPLL) * - * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 110 (7) - * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 60 (1) - * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 110 (7) - * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 60 (1) + * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7) + * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1) + * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7) + * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1) */ set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) | MMC3_PRE_RATIO(1); @@ -337,10 +337,10 @@ static void board_clock_init(void) /* CLK_DIV_FSYS3 */ clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255); /* - * For MOUTmmc4 = 880 MHz (MPLL) + * For MOUTmmc4 = 800 MHz (MPLL) * - * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 110 (7) - * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 110 (0) + * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7) + * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0) */ set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0); -- cgit v1.2.3 From 93a0ea501e1eca1ae5d7d2624906b656c765e5e8 Mon Sep 17 00:00:00 2001 From: Andrew Ruder Date: Tue, 12 Aug 2014 09:26:00 -0500 Subject: arm: mx31: use common timer functions This patch moves mx31 to the common timer functions added in commit 8dfafdd - Introduce common timer functions The (removed) mx31 timer code (specifically __udelay()) could deadlock at the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed the 32-bit boundary, the while condition became unconditionally true and locks the processor. Rather than patch the specific mx31 issues, simply move everything over to the common code. Signed-off-by: Andrew Ruder Cc: Marek Vasut Cc: Linus Walleij Cc: Wolfgang Denk Cc: Fabio Estevam Cc: Helmut Raiger --- arch/arm/cpu/arm1136/mx31/timer.c | 104 +----------------------------- arch/arm/include/asm/arch-mx31/imx-regs.h | 10 +++ 2 files changed, 12 insertions(+), 102 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c index f111242e53..3a81ce427c 100644 --- a/arch/arm/cpu/arm1136/mx31/timer.c +++ b/arch/arm/cpu/arm1136/mx31/timer.c @@ -7,9 +7,6 @@ #include #include -#include -#include -#include #include #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ @@ -28,57 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* - * "time" is measured in 1 / CONFIG_SYS_HZ seconds, - * "tick" is internal timer period - */ - -#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION -/* ~0.4% error - measured with stop-watch on 100s boot-delay */ -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, MXC_CLK32); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - time *= MXC_CLK32; - do_div(time, CONFIG_SYS_HZ); - return time; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us = us * MXC_CLK32 + 999999; - do_div(us, 1000000); - return us; -} -#else -/* ~2% error */ -#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) -#define US_PER_TICK (1000000 / MXC_CLK32) - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - do_div(tick, TICK_PER_TIME); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - return time * TICK_PER_TIME; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us += US_PER_TICK - 1; - do_div(us, US_PER_TICK); - return us; -} -#endif - /* The 32768Hz 32-bit timer overruns in 131072 seconds */ int timer_init(void) { @@ -95,53 +41,7 @@ int timer_init(void) return 0; } -unsigned long long get_ticks(void) -{ - ulong now = GPTCNT; /* current tick value */ - - if (now >= gd->arch.lastinc) /* normal mode (non roll) */ - /* move stamp forward with absolut diff ticks */ - gd->arch.tbl += (now - gd->arch.lastinc); - else /* we have rollover of incrementer */ - gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now; - gd->arch.lastinc = now; - return gd->arch.tbl; -} - -ulong get_timer_masked(void) -{ - /* - * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ - * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in - * 5 * 10^6 days - long enough. - */ - return tick_to_time(get_ticks()); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds AND preserve advance timestamp value */ -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = us_to_tick(usec); - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp) /* loop till event */ - /*NOP*/; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) +unsigned long timer_read_counter(void) { - return MXC_CLK32; + return GPTCNT; } diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index f23350e5c2..71ebd243d7 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -909,9 +909,19 @@ struct esdc_regs { #define MXC_CSPIPERIOD_32KHZ (1 << 15) #define MAX_SPI_BYTES 4 + #define MXC_SPI_BASE_ADDRESSES \ 0x43fa4000, \ 0x50010000, \ 0x53f84000, +/* + * Generic timer support + */ +#ifdef CONFIG_MX31_CLK32 +#define CONFIG_SYS_TIMER_RATE CONFIG_MX31_CLK32 +#else +#define CONFIG_SYS_TIMER_RATE 32768 +#endif + #endif /* __ASM_ARCH_MX31_IMX_REGS_H */ -- cgit v1.2.3 From 816264fc6672dbb7c7b22ad9e67b8d0056873394 Mon Sep 17 00:00:00 2001 From: Andrew Ruder Date: Tue, 12 Aug 2014 09:26:01 -0500 Subject: arm: mx35: use common timer functions This patch moves mx35 to the common timer functions added in commit 8dfafdd - Introduce common timer functions The (removed) mx35 timer code (specifically __udelay()) could deadlock at the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed the 32-bit boundary, the while condition became unconditionally true and locks the processor. Rather than patch the specific mx35 issues, simply move everything over to the common code. Signed-off-by: Andrew Ruder Cc: Marek Vasut Cc: Stefano Babic --- arch/arm/cpu/arm1136/mx35/timer.c | 83 ------------------------------- arch/arm/include/asm/arch-mx35/imx-regs.h | 12 +++++ 2 files changed, 12 insertions(+), 83 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c index cc6166f938..4edf533e2a 100644 --- a/arch/arm/cpu/arm1136/mx35/timer.c +++ b/arch/arm/cpu/arm1136/mx35/timer.c @@ -9,43 +9,17 @@ #include #include -#include #include #include -#include DECLARE_GLOBAL_DATA_PTR; -#define timestamp (gd->arch.tbl) -#define lastinc (gd->arch.lastinc) - /* General purpose timers bitfields */ #define GPTCR_SWR (1<<15) /* Software reset */ #define GPTCR_FRR (1<<9) /* Freerun / restart */ #define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ #define GPTCR_TEN (1) /* Timer enable */ -/* - * "time" is measured in 1 / CONFIG_SYS_HZ seconds, - * "tick" is internal timer period - */ -/* ~0.4% error - measured with stop-watch on 100s boot-delay */ -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, MXC_CLK32); - - return tick; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us = us * MXC_CLK32 + 999999; - do_div(us, 1000000); - - return us; -} - /* * nothing really to do with interrupts, just starts up a counter. * The 32KHz 32-bit timer overruns in 134217 seconds @@ -71,60 +45,3 @@ int timer_init(void) return 0; } - -unsigned long long get_ticks(void) -{ - struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; - ulong now = readl(&gpt->counter); /* current tick value */ - - if (now >= lastinc) { - /* - * normal mode (non roll) - * move stamp forward with absolut diff ticks - */ - timestamp += (now - lastinc); - } else { - /* we have rollover of incrementer */ - timestamp += (0xFFFFFFFF - lastinc) + now; - } - lastinc = now; - return timestamp; -} - -ulong get_timer_masked(void) -{ - /* - * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ - * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in - * 5 * 10^6 days - long enough. - */ - return tick_to_time(get_ticks()); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds AND preserve advance timstamp value */ -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = us_to_tick(usec); - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp) /* loop till event */ - /*NOP*/; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return MXC_CLK32; -} diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index b5300291a9..28a47ed44d 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -372,4 +372,16 @@ struct aips_regs { #define CCM_RCSR_NF_16BIT_SEL (1 << 14) #endif + +/* + * Generic timer support + */ +#ifdef CONFIG_MX35_CLK32 +#define CONFIG_SYS_TIMER_RATE CONFIG_MX35_CLK32 +#else +#define CONFIG_SYS_TIMER_RATE 32768 +#endif + +#define CONFIG_SYS_TIMER_COUNTER (GPT1_BASE_ADDR+36) + #endif /* __ASM_ARCH_MX35_H */ -- cgit v1.2.3 From 72d7beabf72867da0a2e4dd37381cc3838ca8316 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Fri, 12 Sep 2014 13:06:35 +0200 Subject: mtd: nand: add Freescale vf610_nfc driver This adds initial support for Freescale NFC (NAND Flash Controller) found in ARM Vybrid SoC's, Power Architecture MPC5125 and others. The driver is called vf610_nfc since this is the first supported and tested hardware platform supported by the driver. Signed-off-by: Stefan Agner Acked-by: Bill Pringlemeir --- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/vf610_nfc.c | 724 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 725 insertions(+) create mode 100644 drivers/mtd/nand/vf610_nfc.c diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index bf1312a373..eef86d1eca 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o +obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o obj-$(CONFIG_NAND_MXC) += mxc_nand.o obj-$(CONFIG_NAND_MXS) += mxs_nand.o obj-$(CONFIG_NAND_NDFC) += ndfc.o diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c new file mode 100644 index 0000000000..7feb3a7b1e --- /dev/null +++ b/drivers/mtd/nand/vf610_nfc.c @@ -0,0 +1,724 @@ +/* + * Copyright 2009-2014 Freescale Semiconductor, Inc. and others + * + * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver. + * Ported to U-Boot by Stefan Agner + * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir + * Jason ported to M54418TWR and MVFA5. + * Authors: Stefan Agner + * Bill Pringlemeir + * Shaohui Xie + * Jason Jin + * + * Based on original driver mpc5121_nfc.c. + * + * This is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Limitations: + * - Untested on MPC5125 and M54418. + * - DMA not used. + * - 2K pages or less. + * - Only 2K page w. 64+OOB and hardware ECC. + */ + +#include +#include + +#include +#include +#include + +#include +#include +#include + +/* Register Offsets */ +#define NFC_FLASH_CMD1 0x3F00 +#define NFC_FLASH_CMD2 0x3F04 +#define NFC_COL_ADDR 0x3F08 +#define NFC_ROW_ADDR 0x3F0c +#define NFC_ROW_ADDR_INC 0x3F14 +#define NFC_FLASH_STATUS1 0x3F18 +#define NFC_FLASH_STATUS2 0x3F1c +#define NFC_CACHE_SWAP 0x3F28 +#define NFC_SECTOR_SIZE 0x3F2c +#define NFC_FLASH_CONFIG 0x3F30 +#define NFC_IRQ_STATUS 0x3F38 + +/* Addresses for NFC MAIN RAM BUFFER areas */ +#define NFC_MAIN_AREA(n) ((n) * 0x1000) + +#define PAGE_2K 0x0800 +#define OOB_64 0x0040 + +/* + * NFC_CMD2[CODE] values. See section: + * - 31.4.7 Flash Command Code Description, Vybrid manual + * - 23.8.6 Flash Command Sequencer, MPC5125 manual + * + * Briefly these are bitmasks of controller cycles. + */ +#define READ_PAGE_CMD_CODE 0x7EE0 +#define PROGRAM_PAGE_CMD_CODE 0x7FC0 +#define ERASE_CMD_CODE 0x4EC0 +#define READ_ID_CMD_CODE 0x4804 +#define RESET_CMD_CODE 0x4040 +#define STATUS_READ_CMD_CODE 0x4068 + +/* NFC ECC mode define */ +#define ECC_BYPASS 0 +#define ECC_45_BYTE 6 + +/*** Register Mask and bit definitions */ + +/* NFC_FLASH_CMD1 Field */ +#define CMD_BYTE2_MASK 0xFF000000 +#define CMD_BYTE2_SHIFT 24 + +/* NFC_FLASH_CM2 Field */ +#define CMD_BYTE1_MASK 0xFF000000 +#define CMD_BYTE1_SHIFT 24 +#define CMD_CODE_MASK 0x00FFFF00 +#define CMD_CODE_SHIFT 8 +#define BUFNO_MASK 0x00000006 +#define BUFNO_SHIFT 1 +#define START_BIT (1<<0) + +/* NFC_COL_ADDR Field */ +#define COL_ADDR_MASK 0x0000FFFF +#define COL_ADDR_SHIFT 0 + +/* NFC_ROW_ADDR Field */ +#define ROW_ADDR_MASK 0x00FFFFFF +#define ROW_ADDR_SHIFT 0 +#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000 +#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28 +#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000 +#define ROW_ADDR_CHIP_SEL_SHIFT 24 + +/* NFC_FLASH_STATUS2 Field */ +#define STATUS_BYTE1_MASK 0x000000FF + +/* NFC_FLASH_CONFIG Field */ +#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000 +#define CONFIG_ECC_SRAM_ADDR_SHIFT 22 +#define CONFIG_ECC_SRAM_REQ_BIT (1<<21) +#define CONFIG_DMA_REQ_BIT (1<<20) +#define CONFIG_ECC_MODE_MASK 0x000E0000 +#define CONFIG_ECC_MODE_SHIFT 17 +#define CONFIG_FAST_FLASH_BIT (1<<16) +#define CONFIG_16BIT (1<<7) +#define CONFIG_BOOT_MODE_BIT (1<<6) +#define CONFIG_ADDR_AUTO_INCR_BIT (1<<5) +#define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4) +#define CONFIG_PAGE_CNT_MASK 0xF +#define CONFIG_PAGE_CNT_SHIFT 0 + +/* NFC_IRQ_STATUS Field */ +#define IDLE_IRQ_BIT (1<<29) +#define IDLE_EN_BIT (1<<20) +#define CMD_DONE_CLEAR_BIT (1<<18) +#define IDLE_CLEAR_BIT (1<<17) + +#define NFC_TIMEOUT (1000) + +/* ECC status placed at end of buffers. */ +#define ECC_SRAM_ADDR ((PAGE_2K+256-8) >> 3) +#define ECC_STATUS_MASK 0x80 +#define ECC_ERR_COUNT 0x3F + +/* + * ECC status is stored at NFC_CFG[ECCADD] +4 for little-endian + * and +7 for big-endian SOC. + */ +#ifdef CONFIG_VF610 +#define ECC_OFFSET 4 +#else +#define ECC_OFFSET 7 +#endif + +struct vf610_nfc { + struct mtd_info *mtd; + struct nand_chip chip; + void __iomem *regs; + uint column; + int spareonly; + int page; + /* Status and ID are in alternate locations. */ + int alt_buf; +#define ALT_BUF_ID 1 +#define ALT_BUF_STAT 2 + struct clk *clk; +}; + +#define mtd_to_nfc(_mtd) \ + (struct vf610_nfc *)((struct nand_chip *)_mtd->priv)->priv + +static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; +static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION, + .offs = 11, + .len = 4, + .veroffs = 15, + .maxblocks = 4, + .pattern = bbt_pattern, +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | + NAND_BBT_2BIT | NAND_BBT_VERSION, + .offs = 11, + .len = 4, + .veroffs = 15, + .maxblocks = 4, + .pattern = mirror_pattern, +}; + +static struct nand_ecclayout vf610_nfc_ecc45 = { + .eccbytes = 45, + .eccpos = {19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63}, + .oobfree = { + {.offset = 8, + .length = 11} } +}; + +static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + + return readl(nfc->regs + reg); +} + +static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + + writel(val, nfc->regs + reg); +} + +static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits) +{ + vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits); +} + +static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits) +{ + vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits); +} + +static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg, + u32 mask, u32 shift, u32 val) +{ + vf610_nfc_write(mtd, reg, + (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift); +} + +static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n) +{ + /* + * Use this accessor for the interal SRAM buffers. On ARM we can + * treat the SRAM buffer as if its memory, hence use memcpy + */ + memcpy(dst, src, n); +} + +/* Clear flags for upcoming command */ +static inline void vf610_nfc_clear_status(void __iomem *regbase) +{ + void __iomem *reg = regbase + NFC_IRQ_STATUS; + u32 tmp = __raw_readl(reg); + tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT; + __raw_writel(tmp, reg); +} + +/* Wait for complete operation */ +static inline void vf610_nfc_done(struct mtd_info *mtd) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + uint start; + + /* + * Barrier is needed after this write. This write need + * to be done before reading the next register the first + * time. + * vf610_nfc_set implicates such a barrier by using writel + * to write to the register. + */ + vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT); + + start = get_timer(0); + + while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) { + if (get_timer(start) > NFC_TIMEOUT) { + printf("Timeout while waiting for !BUSY.\n"); + return; + } + } + vf610_nfc_clear_status(nfc->regs); +} + +static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col) +{ + u32 flash_id; + + if (col < 4) { + flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1); + return (flash_id >> (3-col)*8) & 0xff; + } else { + flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2); + return flash_id >> 24; + } +} + +static u8 vf610_nfc_get_status(struct mtd_info *mtd) +{ + return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK; +} + +/* Single command */ +static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1, + u32 cmd_code) +{ + void __iomem *reg = regbase + NFC_FLASH_CMD2; + u32 tmp; + vf610_nfc_clear_status(regbase); + + tmp = __raw_readl(reg); + tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK); + tmp |= cmd_byte1 << CMD_BYTE1_SHIFT; + tmp |= cmd_code << CMD_CODE_SHIFT; + __raw_writel(tmp, reg); +} + +/* Two commands */ +static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1, + u32 cmd_byte2, u32 cmd_code) +{ + void __iomem *reg = regbase + NFC_FLASH_CMD1; + u32 tmp; + vf610_nfc_send_command(regbase, cmd_byte1, cmd_code); + + tmp = __raw_readl(reg); + tmp &= ~CMD_BYTE2_MASK; + tmp |= cmd_byte2 << CMD_BYTE2_SHIFT; + __raw_writel(tmp, reg); +} + +static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) +{ + if (column != -1) { + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + if (nfc->chip.options | NAND_BUSWIDTH_16) + column = column/2; + vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK, + COL_ADDR_SHIFT, column); + } + if (page != -1) + vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK, + ROW_ADDR_SHIFT, page); +} + +/* Send command to NAND chip */ +static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, + int column, int page) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + + nfc->column = max(column, 0); + nfc->spareonly = 0; + nfc->alt_buf = 0; + + switch (command) { + case NAND_CMD_PAGEPROG: + nfc->page = -1; + vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN, + command, PROGRAM_PAGE_CMD_CODE); + vf610_nfc_addr_cycle(mtd, column, page); + break; + + case NAND_CMD_RESET: + vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE); + break; + /* + * NFC does not support sub-page reads and writes, + * so emulate them using full page transfers. + */ + case NAND_CMD_READOOB: + nfc->spareonly = 1; + case NAND_CMD_SEQIN: /* Pre-read for partial writes. */ + case NAND_CMD_READ0: + column = 0; + /* Already read? */ + if (nfc->page == page) + return; + nfc->page = page; + vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0, + NAND_CMD_READSTART, READ_PAGE_CMD_CODE); + vf610_nfc_addr_cycle(mtd, column, page); + break; + + case NAND_CMD_ERASE1: + if (nfc->page == page) + nfc->page = -1; + vf610_nfc_send_commands(nfc->regs, command, + NAND_CMD_ERASE2, ERASE_CMD_CODE); + vf610_nfc_addr_cycle(mtd, column, page); + break; + + case NAND_CMD_READID: + nfc->alt_buf = ALT_BUF_ID; + vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE); + break; + + case NAND_CMD_STATUS: + nfc->alt_buf = ALT_BUF_STAT; + vf610_nfc_send_command(nfc->regs, command, + STATUS_READ_CMD_CODE); + break; + default: + return; + } + + vf610_nfc_done(mtd); +} + +static inline void vf610_nfc_read_spare(struct mtd_info *mtd, void *buf, + int len) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + + len = min(mtd->oobsize, (uint)len); + if (len > 0) + vf610_nfc_memcpy(buf, nfc->regs + mtd->writesize, len); +} + +/* Read data from NFC buffers */ +static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + uint c = nfc->column; + uint l; + + /* Handle main area */ + if (!nfc->spareonly) { + l = min((uint)len, mtd->writesize - c); + nfc->column += l; + + if (!nfc->alt_buf) + vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, + l); + else + if (nfc->alt_buf & ALT_BUF_ID) + *buf = vf610_nfc_get_id(mtd, c); + else + *buf = vf610_nfc_get_status(mtd); + + buf += l; + len -= l; + } + + /* Handle spare area access */ + if (len) { + nfc->column += len; + vf610_nfc_read_spare(mtd, buf, len); + } +} + +/* Write data to NFC buffers */ +static void vf610_nfc_write_buf(struct mtd_info *mtd, const u_char *buf, + int len) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + uint c = nfc->column; + uint l; + + l = min((uint)len, mtd->writesize + mtd->oobsize - c); + nfc->column += l; + vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l); +} + +/* Read byte from NFC buffers */ +static u8 vf610_nfc_read_byte(struct mtd_info *mtd) +{ + u8 tmp; + vf610_nfc_read_buf(mtd, &tmp, sizeof(tmp)); + return tmp; +} + +/* Read word from NFC buffers */ +static u16 vf610_nfc_read_word(struct mtd_info *mtd) +{ + u16 tmp; + vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp)); + return tmp; +} + +/* If not provided, upper layers apply a fixed delay. */ +static int vf610_nfc_dev_ready(struct mtd_info *mtd) +{ + /* NFC handles R/B internally; always ready. */ + return 1; +} + +/* + * This function supports Vybrid only (MPC5125 would have full RB and four CS) + */ +static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip) +{ +#ifdef CONFIG_VF610 + u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR); + tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK); + tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT; + + if (chip == 0) + tmp |= 1 << ROW_ADDR_CHIP_SEL_SHIFT; + else if (chip == 1) + tmp |= 2 << ROW_ADDR_CHIP_SEL_SHIFT; + + vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp); +#endif +} + +/* Count the number of 0's in buff upto max_bits */ +static inline int count_written_bits(uint8_t *buff, int size, int max_bits) +{ + uint32_t *buff32 = (uint32_t *)buff; + int k, written_bits = 0; + + for (k = 0; k < (size / 4); k++) { + written_bits += hweight32(~buff32[k]); + if (written_bits > max_bits) + break; + } + + return written_bits; +} + +static inline int vf610_nfc_correct_data(struct mtd_info *mtd, u_char *dat) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + u8 ecc_status; + u8 ecc_count; + int flip; + + ecc_status = __raw_readb(nfc->regs + ECC_SRAM_ADDR * 8 + ECC_OFFSET); + ecc_count = ecc_status & ECC_ERR_COUNT; + if (!(ecc_status & ECC_STATUS_MASK)) + return ecc_count; + + /* If 'ecc_count' zero or less then buffer is all 0xff or erased. */ + flip = count_written_bits(dat, nfc->chip.ecc.size, ecc_count); + + /* ECC failed. */ + if (flip > ecc_count) { + nfc->page = -1; + return -1; + } + + /* Erased page. */ + memset(dat, 0xff, nfc->chip.ecc.size); + return 0; +} + + +static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int oob_required, int page) +{ + int eccsize = chip->ecc.size; + int stat; + uint8_t *p = buf; + + + vf610_nfc_read_buf(mtd, p, eccsize); + + if (oob_required) + vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize); + + stat = vf610_nfc_correct_data(mtd, p); + + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + + return 0; +} + +/* + * ECC will be calculated automatically + */ +static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf, int oob_required) +{ + vf610_nfc_write_buf(mtd, buf, mtd->writesize); + if (oob_required) + vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize); + + return 0; +} + +struct vf610_nfc_config { + int hardware_ecc; + int width; + int flash_bbt; +}; + +static int vf610_nfc_nand_init(int devnum, void __iomem *addr) +{ + struct mtd_info *mtd = &nand_info[devnum]; + struct nand_chip *chip; + struct vf610_nfc *nfc; + int err = 0; + int page_sz; + struct vf610_nfc_config cfg = { + .hardware_ecc = 1, +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT + .width = 16, +#else + .width = 8, +#endif + .flash_bbt = 1, + }; + + nfc = malloc(sizeof(*nfc)); + if (!nfc) { + printf(KERN_ERR "%s: Memory exhausted!\n", __func__); + return -ENOMEM; + } + + chip = &nfc->chip; + nfc->regs = addr; + + mtd->priv = chip; + chip->priv = nfc; + + if (cfg.width == 16) { + chip->options |= NAND_BUSWIDTH_16; + vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); + } else { + chip->options &= ~NAND_BUSWIDTH_16; + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); + } + + chip->dev_ready = vf610_nfc_dev_ready; + chip->cmdfunc = vf610_nfc_command; + chip->read_byte = vf610_nfc_read_byte; + chip->read_word = vf610_nfc_read_word; + chip->read_buf = vf610_nfc_read_buf; + chip->write_buf = vf610_nfc_write_buf; + chip->select_chip = vf610_nfc_select_chip; + + /* Bad block options. */ + if (cfg.flash_bbt) + chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_CREATE; + + /* Default to software ECC until flash ID. */ + vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, + CONFIG_ECC_MODE_MASK, + CONFIG_ECC_MODE_SHIFT, ECC_BYPASS); + + chip->bbt_td = &bbt_main_descr; + chip->bbt_md = &bbt_mirror_descr; + + page_sz = PAGE_2K + OOB_64; + page_sz += cfg.width == 16 ? 1 : 0; + vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz); + + /* Set configuration register. */ + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT); + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT); + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT); + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT); + vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT); + + /* Enable Idle IRQ */ + vf610_nfc_set(mtd, NFC_IRQ_STATUS, IDLE_EN_BIT); + + /* PAGE_CNT = 1 */ + vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK, + CONFIG_PAGE_CNT_SHIFT, 1); + + /* Set ECC_STATUS offset */ + vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, + CONFIG_ECC_SRAM_ADDR_MASK, + CONFIG_ECC_SRAM_ADDR_SHIFT, ECC_SRAM_ADDR); + + /* first scan to find the device and get the page size */ + if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) { + err = -ENXIO; + goto error; + } + + chip->ecc.mode = NAND_ECC_SOFT; /* default */ + + page_sz = mtd->writesize + mtd->oobsize; + + /* Single buffer only, max 256 OOB minus ECC status */ + if (page_sz > PAGE_2K + 256 - 8) { + dev_err(nfc->dev, "Unsupported flash size\n"); + err = -ENXIO; + goto error; + } + page_sz += cfg.width == 16 ? 1 : 0; + vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz); + + if (cfg.hardware_ecc) { + if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) { + dev_err(nfc->dev, "Unsupported flash with hwecc\n"); + err = -ENXIO; + goto error; + } + + chip->ecc.layout = &vf610_nfc_ecc45; + + /* propagate ecc.layout to mtd_info */ + mtd->ecclayout = chip->ecc.layout; + chip->ecc.read_page = vf610_nfc_read_page; + chip->ecc.write_page = vf610_nfc_write_page; + chip->ecc.mode = NAND_ECC_HW; + + chip->ecc.bytes = 45; + chip->ecc.size = PAGE_2K; + chip->ecc.strength = 24; + + /* set ECC mode to 45 bytes OOB with 24 bits correction */ + vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, + CONFIG_ECC_MODE_MASK, + CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE); + + /* Enable ECC_STATUS */ + vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT); + } + + /* second phase scan */ + err = nand_scan_tail(mtd); + if (err) + return err; + + err = nand_register(devnum); + if (err) + return err; + + return 0; + +error: + return err; +} + +void board_nand_init(void) +{ + int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE); + if (err) + printf("VF610 NAND init failed (err %d)\n", err); +} -- cgit v1.2.3 From d6d07a9bec3bc30a58c45f8e6343c92dfef96fee Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Fri, 12 Sep 2014 13:06:36 +0200 Subject: arm: vf610: add NAND support for vf610twr This adds NAND support for the Vybrid tower system (TWR-VF65GS10) provided by the vf610_nfc driver. Full 16-Bit bus width is supported. Also an aditional config vf610twr_nand is introduced which gets the environment from NAND. However, booting U-Boot from NAND is not yet possible due to missing boot configuration block (BCB). Signed-off-by: Stefan Agner --- board/freescale/vf610twr/vf610twr.c | 47 ++++++++++++++++++++++++++++++++++--- configs/vf610twr_defconfig | 2 +- configs/vf610twr_nand_defconfig | 3 +++ include/configs/vf610twr.h | 46 +++++++++++++++++++++++++++++++++++- 4 files changed, 93 insertions(+), 5 deletions(-) create mode 100644 configs/vf610twr_nand_defconfig diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 54a9f2c7c3..4d0979632a 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -278,6 +278,39 @@ static void setup_iomux_i2c(void) imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); } +#ifdef CONFIG_NAND_VF610_NFC +static void setup_iomux_nfc(void) +{ + static const iomux_v3_cfg_t nfc_pads[] = { + VF610_PAD_PTD31__NF_IO15, + VF610_PAD_PTD30__NF_IO14, + VF610_PAD_PTD29__NF_IO13, + VF610_PAD_PTD28__NF_IO12, + VF610_PAD_PTD27__NF_IO11, + VF610_PAD_PTD26__NF_IO10, + VF610_PAD_PTD25__NF_IO9, + VF610_PAD_PTD24__NF_IO8, + VF610_PAD_PTD23__NF_IO7, + VF610_PAD_PTD22__NF_IO6, + VF610_PAD_PTD21__NF_IO5, + VF610_PAD_PTD20__NF_IO4, + VF610_PAD_PTD19__NF_IO3, + VF610_PAD_PTD18__NF_IO2, + VF610_PAD_PTD17__NF_IO1, + VF610_PAD_PTD16__NF_IO0, + VF610_PAD_PTB24__NF_WE_B, + VF610_PAD_PTB25__NF_CE0_B, + VF610_PAD_PTB27__NF_RE_B, + VF610_PAD_PTC26__NF_RB_B, + VF610_PAD_PTC27__NF_ALE, + VF610_PAD_PTC28__NF_CLE + }; + + imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); +} +#endif + + static void setup_iomux_qspi(void) { static const iomux_v3_cfg_t qspi0_pads[] = { @@ -354,6 +387,8 @@ static void clock_init(void) CCM_CCGR7_SDHC1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, + CCM_CCGR10_NFC_CTRL_MASK); clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); @@ -373,14 +408,17 @@ static void clock_init(void) CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | CCM_CACRR_ARM_CLK_DIV(0)); clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, - CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3)); + CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) | + CCM_CSCMR1_NFC_CLK_SEL(0)); clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, CCM_CSCDR1_RMII_CLK_EN); clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, - CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0)); + CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | + CCM_CSCDR2_NFC_EN); clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | - CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3)); + CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) | + CCM_CSCDR3_NFC_PRE_DIV(5)); clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, CCM_CSCMR2_RMII_CLK_SEL(0)); } @@ -411,6 +449,9 @@ int board_early_init_f(void) setup_iomux_enet(); setup_iomux_i2c(); setup_iomux_qspi(); +#ifdef CONFIG_NAND_VF610_NFC + setup_iomux_nfc(); +#endif return 0; } diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig index 10e6432bb4..7de374a406 100644 --- a/configs/vf610twr_defconfig +++ b/configs/vf610twr_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC" CONFIG_ARM=y CONFIG_TARGET_VF610TWR=y diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig new file mode 100644 index 0000000000..e78db26ff6 --- /dev/null +++ b/configs/vf610twr_nand_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND" +CONFIG_ARM=y +CONFIG_TARGET_VF610TWR=y diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 0342550412..6fd0b173eb 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -14,6 +14,7 @@ #define CONFIG_VF610 +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -44,6 +45,41 @@ #undef CONFIG_CMD_IMLS +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_VF610_NFC +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_USE_ARCH_MEMCPY +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR + +/* UBI */ +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS + +/* Dynamic MTD partition support */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define MTDIDS_DEFAULT "nand0=fsl_nfc" +#define MTDPARTS_DEFAULT "mtdparts=fsl_nfc:" \ + "128k(vf-bcb)ro," \ + "1408k(u-boot)ro," \ + "512k(u-boot-env)," \ + "4m(kernel)," \ + "512k(fdt)," \ + "-(rootfs)" +#endif + #define CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 @@ -218,11 +254,19 @@ /* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH +#ifdef CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_OFFSET (12 * 64 * 1024) #define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE (64 * 2048) +#define CONFIG_ENV_SECT_SIZE (64 * 2048) +#define CONFIG_ENV_RANGE (512 * 1024) +#define CONFIG_ENV_OFFSET 0x180000 +#endif #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ -- cgit v1.2.3 From 152adee1b6174611903b81fa8d3b9797d70b0ca1 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 15 Sep 2014 14:59:16 +0800 Subject: imx:mx6sxsabresd: change CONFIG_SYS_FSL_ESDHC_ADDR Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR which is used in board_mmc_init. If board_mmc_init failed, cpu_mmc_init->fsl_esdhc_mmc_init will use CONFIG_SYS_FSL_ESDHC_ADDR to initialize sdhc. So set this macro to correct value. Signed-off-by: Peng Fan --- include/configs/mx6sxsabresd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index b92d9443d4..fd74c6980d 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -159,7 +159,7 @@ /* MMC Configuration */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR #define CONFIG_MMC #define CONFIG_CMD_MMC -- cgit v1.2.3 From 95083b3a0887e1653df04ef4e1aa3c42920ffa11 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 15 Sep 2014 14:59:17 +0800 Subject: imx:mx6qarm2: change CONFIG_SYS_FSL_ESDHC_ADDR Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR. USDHC3 and USDHC4 are both initialized in board_mmc_init. There is no restriction on USDHC3 addr or USDHC4 addr should be assigned to CONFIG_SYS_FSL_ESDHC_ADDR. So, just choose USDHC4_BASE_ADDR to avoid errors when fsl_esdhc_mmc_init is invoked. Signed-off-by: Peng Fan --- include/configs/mx6qarm2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index 35c0a85080..e2469a1165 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -37,7 +37,7 @@ /* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_MMC -- cgit v1.2.3 From 08129d618c3906a696bdaf758bd7e923ea43eced Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 15 Sep 2014 14:59:18 +0800 Subject: imx:mx6slevk: change CONFIG_SYS_FSL_ESDHC_ADDR Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC2_BASE_ADDR which is used in board_mmc_init. Signed-off-by: Peng Fan --- include/configs/mx6slevk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 194d7bdb76..55b983c7ad 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -40,7 +40,7 @@ /* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR #define CONFIG_MMC #define CONFIG_CMD_MMC -- cgit v1.2.3 From bcaa075a637af55e2d59e7333eddb250758bd545 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 13 Sep 2014 18:21:35 -0300 Subject: mx6sxsabresd: Staticize i2c_pad_info1 i2c_pad_info1 is only used locally, so it can be made static. Fix the following sparse warning: board/freescale/mx6sxsabresd/mx6sxsabresd.c:160:22: warning: symbol 'i2c_pad_info1' was not declared. Should it be static? Signed-off-by: Fabio Estevam --- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 5eaec1bdb1..68d37184a3 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -157,7 +157,7 @@ int board_eth_init(bd_t *bis) #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) /* I2C1 for PMIC */ -struct i2c_pads_info i2c_pad_info1 = { +static struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, -- cgit v1.2.3 From 067a659317639187fd170f73b10dfc5c2a7df9da Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 13 Sep 2014 18:21:36 -0300 Subject: mx6qsabreauto: Staticize when possible Turn all local symbols into static in order to make sparse happy. Signed-off-by: Fabio Estevam --- board/freescale/mx6qsabreauto/mx6qsabreauto.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 928dadf809..dd6d2a660f 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -50,12 +50,12 @@ int dram_init(void) return 0; } -iomux_v3_cfg_t const uart4_pads[] = { +static iomux_v3_cfg_t const uart4_pads[] = { MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -iomux_v3_cfg_t const enet_pads[] = { +static iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -74,7 +74,7 @@ iomux_v3_cfg_t const enet_pads[] = { }; /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */ -struct i2c_pads_info i2c_pad_info1 = { +static struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, @@ -91,7 +91,7 @@ struct i2c_pads_info i2c_pad_info1 = { * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor, * Compass Sensor, Accelerometer, Res Touch */ -struct i2c_pads_info i2c_pad_info2 = { +static struct i2c_pads_info i2c_pad_info2 = { .scl = { .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, @@ -104,11 +104,11 @@ struct i2c_pads_info i2c_pad_info2 = { } }; -iomux_v3_cfg_t const i2c3_pads[] = { +static iomux_v3_cfg_t const i2c3_pads[] = { MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -iomux_v3_cfg_t const port_exp[] = { +static iomux_v3_cfg_t const port_exp[] = { MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), }; @@ -117,7 +117,7 @@ static void setup_iomux_enet(void) imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); } -iomux_v3_cfg_t const usdhc3_pads[] = { +static iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -138,7 +138,7 @@ static void setup_iomux_uart(void) } #ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg[1] = { +static struct fsl_esdhc_cfg usdhc_cfg[1] = { {USDHC3_BASE_ADDR}, }; -- cgit v1.2.3 From 0fdfafd225a0cead05a0b332f189c2f667b5f1d6 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 16 Sep 2014 16:02:00 +0200 Subject: imx: Fix warning by building vf610twr_nand commit d6d07a9b... arm: vf610: add NAND support for vf610twr generates the following warnings: WARNING: no status info for 'vf610twr_nand' WARNING: no maintainers for 'vf610twr_nand'WARNING: no status info for 'vf610twr_nand' This is due to the fact that vf610twr_nand_defconfig has no Maintainer. This patch proposed Alison as Maintainer and fix it. Signed-off-by: Stefano Babic Acked-by: Alison Wang CC: Stefan Agner --- board/freescale/vf610twr/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/vf610twr/MAINTAINERS b/board/freescale/vf610twr/MAINTAINERS index 56a09c9ad9..f2997f05c3 100644 --- a/board/freescale/vf610twr/MAINTAINERS +++ b/board/freescale/vf610twr/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/vf610twr/ F: include/configs/vf610twr.h F: configs/vf610twr_defconfig +F: configs/vf610twr_nand_defconfig -- cgit v1.2.3 From e425436ca83e3c285000d53acc1700b63d39893b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 20 Sep 2014 20:05:36 -0300 Subject: cm_fx6: Remove CONFIG_NETMASK We should not hardcode CONFIG_NETMASK in the config file. Signed-off-by: Fabio Estevam Acked-by: Igor Grinberg Acked-by: Nikita Kiryanov --- include/configs/cm_fx6.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 10d02b4e18..7cf241e31d 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -222,7 +222,6 @@ #define CONFIG_MII #define CONFIG_ETHPRIME "FEC0" #define CONFIG_ARP_TIMEOUT 200UL -#define CONFIG_NETMASK 255.255.255.0 #define CONFIG_NET_RETRY_COUNT 5 /* USB */ -- cgit v1.2.3 From 9992792be07517647fa2f07a54263d7051ff420f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 16 Sep 2014 20:03:40 -0300 Subject: mx51evk: Fix CONFIG_SYS_FSL_ESDHC_ADDR We should pass the SDHC1 base address into CONFIG_SYS_FSL_ESDHC_ADDR. Signed-off-by: Fabio Estevam --- include/configs/mx51evk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index b389475ebe..b0d401c928 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -69,7 +69,7 @@ * MMC Configs * */ #define CONFIG_FSL_ESDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR #define CONFIG_SYS_FSL_ESDHC_NUM 2 #define CONFIG_MMC -- cgit v1.2.3 From 7a56bddd7fb9fe27c775cadd18ebde6f883d7cff Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 16 Sep 2014 20:03:41 -0300 Subject: mx51evk: Add generic board support Let's enable CONFIG_SYS_GENERIC_BOARD in order to get rid of warnings related to generic board not being supported. Signed-off-by: Fabio Estevam --- include/configs/mx51evk.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index b0d401c928..d6e8ec4e13 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -26,6 +26,7 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_OF_LIBFDT -- cgit v1.2.3 From 05d1c24517726c73fabb16c483a5cbd3737ed2a6 Mon Sep 17 00:00:00 2001 From: Guillaume GARDET Date: Thu, 11 Sep 2014 11:59:52 +0200 Subject: imx: nitrogen6x: Make use of both uSD and SD slots to load script or kernel on Sabrelite board Sabrelite board has two solts: 0 is SD3 (bottom) slot and 1 is uSD4 (top) slot. This patch makes use of both slots instead of only one. Signed-off-by: Guillaume GARDET Cc: Stefano Babic Cc: Eric Nelson Reviewed-by: Eric Nelson Acked-by: Eric Nelson Reviewed-by: Eric Nelson Acked-by: Eric Nelson --- include/configs/nitrogen6x.h | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index d4b0ac9fdb..2a1eb3b773 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -186,7 +186,7 @@ "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=0\0" \ + "mmcdevs=0 1\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ @@ -238,16 +238,19 @@ "fi;\0" #define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" + "for mmcdev in ${mmcdevs}; do " \ + "mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "done; " \ + "run netboot; " #else #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc1\0" \ -- cgit v1.2.3 From 7972913512568bc48ca6ea1f2b1cc25db61275ff Mon Sep 17 00:00:00 2001 From: Nitin Garg Date: Mon, 15 Sep 2014 08:56:46 -0500 Subject: imx: ddr: Move mx6q_4x_mt41j128.cfg to mx6sabresd board Provide cgtqmx6eval board its own variant of ddr setup config file. Move board/freescale/imx/ddr/ mx6q_4x_mt41j128.cfg to board/freescale/mx6sabresd/ as this is was designed for the mx6sabresd board. Signed-off-by: Nitin Garg Acked-by: Stefano Babic --- board/congatec/cgtqmx6eval/imximage.cfg | 169 ++++++++++++++++++++++++ board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 169 ------------------------ board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg | 169 ++++++++++++++++++++++++ configs/cgtqmx6qeval_defconfig | 2 +- configs/mx6qsabresd_defconfig | 2 +- 5 files changed, 340 insertions(+), 171 deletions(-) create mode 100644 board/congatec/cgtqmx6eval/imximage.cfg delete mode 100644 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg create mode 100644 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg diff --git a/board/congatec/cgtqmx6eval/imximage.cfg b/board/congatec/cgtqmx6eval/imximage.cfg new file mode 100644 index 0000000000..bb6c60b4c3 --- /dev/null +++ b/board/congatec/cgtqmx6eval/imximage.cfg @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 + +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 + +DATA 4 0x020e05ac 0x00020030 +DATA 4 0x020e05b4 0x00020030 +DATA 4 0x020e0528 0x00020030 +DATA 4 0x020e0520 0x00020030 + +DATA 4 0x020e0514 0x00020030 +DATA 4 0x020e0510 0x00020030 +DATA 4 0x020e05bc 0x00020030 +DATA 4 0x020e05c4 0x00020030 + +DATA 4 0x020e056c 0x00020030 +DATA 4 0x020e0578 0x00020030 +DATA 4 0x020e0588 0x00020030 +DATA 4 0x020e0594 0x00020030 + +DATA 4 0x020e057c 0x00020030 +DATA 4 0x020e0590 0x00003000 +DATA 4 0x020e0598 0x00003000 +DATA 4 0x020e058c 0x00000000 + +DATA 4 0x020e059c 0x00003030 +DATA 4 0x020e05a0 0x00003030 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 + +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 + +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e0750 0x00020000 + +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0798 0x000C0000 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +DATA 4 0x021b0018 0x00081740 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b000c 0x555A7974 +DATA 4 0x021b0010 0xDB538F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b002c 0x000026D2 + +DATA 4 0x021b0030 0x005A1023 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x831A0000 + +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x0408803A +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x0000803B +DATA 4 0x021b001c 0x00428031 +DATA 4 0x021b001c 0x00428039 +DATA 4 0x021b001c 0x19308030 +DATA 4 0x021b001c 0x19308038 + +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b001c 0x04008048 +DATA 4 0x021b0800 0xA1380003 +DATA 4 0x021b4800 0xA1380003 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b4818 0x00022227 + +DATA 4 0x021b083c 0x434B0350 +DATA 4 0x021b0840 0x034C0359 +DATA 4 0x021b483c 0x434B0350 +DATA 4 0x021b4840 0x03650348 +DATA 4 0x021b0848 0x4436383B +DATA 4 0x021b4848 0x39393341 +DATA 4 0x021b0850 0x35373933 +DATA 4 0x021b4850 0x48254A36 + +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F + +DATA 4 0x021b480c 0x00440044 +DATA 4 0x021b4810 0x00440044 + +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +DATA 4 0x021b001c 0x00000000 +DATA 4 0x021b0404 0x00011006 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x000000fb diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg deleted file mode 100644 index bb6c60b4c3..0000000000 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * Jason Liu - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -DATA 4 0x020e05a8 0x00000030 -DATA 4 0x020e05b0 0x00000030 -DATA 4 0x020e0524 0x00000030 -DATA 4 0x020e051c 0x00000030 - -DATA 4 0x020e0518 0x00000030 -DATA 4 0x020e050c 0x00000030 -DATA 4 0x020e05b8 0x00000030 -DATA 4 0x020e05c0 0x00000030 - -DATA 4 0x020e05ac 0x00020030 -DATA 4 0x020e05b4 0x00020030 -DATA 4 0x020e0528 0x00020030 -DATA 4 0x020e0520 0x00020030 - -DATA 4 0x020e0514 0x00020030 -DATA 4 0x020e0510 0x00020030 -DATA 4 0x020e05bc 0x00020030 -DATA 4 0x020e05c4 0x00020030 - -DATA 4 0x020e056c 0x00020030 -DATA 4 0x020e0578 0x00020030 -DATA 4 0x020e0588 0x00020030 -DATA 4 0x020e0594 0x00020030 - -DATA 4 0x020e057c 0x00020030 -DATA 4 0x020e0590 0x00003000 -DATA 4 0x020e0598 0x00003000 -DATA 4 0x020e058c 0x00000000 - -DATA 4 0x020e059c 0x00003030 -DATA 4 0x020e05a0 0x00003030 -DATA 4 0x020e0784 0x00000030 -DATA 4 0x020e0788 0x00000030 - -DATA 4 0x020e0794 0x00000030 -DATA 4 0x020e079c 0x00000030 -DATA 4 0x020e07a0 0x00000030 -DATA 4 0x020e07a4 0x00000030 - -DATA 4 0x020e07a8 0x00000030 -DATA 4 0x020e0748 0x00000030 -DATA 4 0x020e074c 0x00000030 -DATA 4 0x020e0750 0x00020000 - -DATA 4 0x020e0758 0x00000000 -DATA 4 0x020e0774 0x00020000 -DATA 4 0x020e078c 0x00000030 -DATA 4 0x020e0798 0x000C0000 - -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 - -DATA 4 0x021b481c 0x33333333 -DATA 4 0x021b4820 0x33333333 -DATA 4 0x021b4824 0x33333333 -DATA 4 0x021b4828 0x33333333 - -DATA 4 0x021b0018 0x00081740 - -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b000c 0x555A7974 -DATA 4 0x021b0010 0xDB538F64 -DATA 4 0x021b0014 0x01FF00DB -DATA 4 0x021b002c 0x000026D2 - -DATA 4 0x021b0030 0x005A1023 -DATA 4 0x021b0008 0x09444040 -DATA 4 0x021b0004 0x00025576 -DATA 4 0x021b0040 0x00000027 -DATA 4 0x021b0000 0x831A0000 - -DATA 4 0x021b001c 0x04088032 -DATA 4 0x021b001c 0x0408803A -DATA 4 0x021b001c 0x00008033 -DATA 4 0x021b001c 0x0000803B -DATA 4 0x021b001c 0x00428031 -DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x19308030 -DATA 4 0x021b001c 0x19308038 - -DATA 4 0x021b001c 0x04008040 -DATA 4 0x021b001c 0x04008048 -DATA 4 0x021b0800 0xA1380003 -DATA 4 0x021b4800 0xA1380003 -DATA 4 0x021b0020 0x00005800 -DATA 4 0x021b0818 0x00022227 -DATA 4 0x021b4818 0x00022227 - -DATA 4 0x021b083c 0x434B0350 -DATA 4 0x021b0840 0x034C0359 -DATA 4 0x021b483c 0x434B0350 -DATA 4 0x021b4840 0x03650348 -DATA 4 0x021b0848 0x4436383B -DATA 4 0x021b4848 0x39393341 -DATA 4 0x021b0850 0x35373933 -DATA 4 0x021b4850 0x48254A36 - -DATA 4 0x021b080c 0x001F001F -DATA 4 0x021b0810 0x001F001F - -DATA 4 0x021b480c 0x00440044 -DATA 4 0x021b4810 0x00440044 - -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b48b8 0x00000800 - -DATA 4 0x021b001c 0x00000000 -DATA 4 0x021b0404 0x00011006 - -/* set the default clock gate to save power */ -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4 0x020e0010 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F - -/* - * Setup CCM_CCOSR register as follows: - * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root - * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz - */ -DATA 4 0x020c4060 0x000000fb diff --git a/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg new file mode 100644 index 0000000000..bb6c60b4c3 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 + +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 + +DATA 4 0x020e05ac 0x00020030 +DATA 4 0x020e05b4 0x00020030 +DATA 4 0x020e0528 0x00020030 +DATA 4 0x020e0520 0x00020030 + +DATA 4 0x020e0514 0x00020030 +DATA 4 0x020e0510 0x00020030 +DATA 4 0x020e05bc 0x00020030 +DATA 4 0x020e05c4 0x00020030 + +DATA 4 0x020e056c 0x00020030 +DATA 4 0x020e0578 0x00020030 +DATA 4 0x020e0588 0x00020030 +DATA 4 0x020e0594 0x00020030 + +DATA 4 0x020e057c 0x00020030 +DATA 4 0x020e0590 0x00003000 +DATA 4 0x020e0598 0x00003000 +DATA 4 0x020e058c 0x00000000 + +DATA 4 0x020e059c 0x00003030 +DATA 4 0x020e05a0 0x00003030 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 + +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 + +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e0750 0x00020000 + +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0798 0x000C0000 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +DATA 4 0x021b0018 0x00081740 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b000c 0x555A7974 +DATA 4 0x021b0010 0xDB538F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b002c 0x000026D2 + +DATA 4 0x021b0030 0x005A1023 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x831A0000 + +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x0408803A +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x0000803B +DATA 4 0x021b001c 0x00428031 +DATA 4 0x021b001c 0x00428039 +DATA 4 0x021b001c 0x19308030 +DATA 4 0x021b001c 0x19308038 + +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b001c 0x04008048 +DATA 4 0x021b0800 0xA1380003 +DATA 4 0x021b4800 0xA1380003 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b4818 0x00022227 + +DATA 4 0x021b083c 0x434B0350 +DATA 4 0x021b0840 0x034C0359 +DATA 4 0x021b483c 0x434B0350 +DATA 4 0x021b4840 0x03650348 +DATA 4 0x021b0848 0x4436383B +DATA 4 0x021b4848 0x39393341 +DATA 4 0x021b0850 0x35373933 +DATA 4 0x021b4850 0x48254A36 + +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F + +DATA 4 0x021b480c 0x00440044 +DATA 4 0x021b4810 0x00440044 + +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +DATA 4 0x021b001c 0x00000000 +DATA 4 0x021b0404 0x00011006 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x000000fb diff --git a/configs/cgtqmx6qeval_defconfig b/configs/cgtqmx6qeval_defconfig index 669938138c..4eba4bea6d 100644 --- a/configs/cgtqmx6qeval_defconfig +++ b/configs/cgtqmx6qeval_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q" CONFIG_ARM=y CONFIG_TARGET_CGTQMX6EVAL=y diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig index dc8e254df9..67c1b77e05 100644 --- a/configs/mx6qsabresd_defconfig +++ b/configs/mx6qsabresd_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q" CONFIG_ARM=y CONFIG_TARGET_MX6SABRESD=y -- cgit v1.2.3 From 3098ef429c1ee6678ac1c643cb7246c13137070d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 16 Sep 2014 11:13:12 -0300 Subject: mx25pdk: Fix CONFIG_SYS_FSL_ESDHC_ADDR We should pass the MMC1 base address into CONFIG_SYS_FSL_ESDHC_ADDR. Signed-off-by: Fabio Estevam --- include/configs/mx25pdk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index d464ad964b..34199af203 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -100,7 +100,7 @@ #define CONFIG_MMC #define CONFIG_GENERIC_MMC #define CONFIG_FSL_ESDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR IMX_MMC_SDHC1_BASE #define CONFIG_SYS_FSL_ESDHC_NUM 1 /* PMIC Configs */ -- cgit v1.2.3 From 4f797c4c1c93b508928786f539cd6a4a98a68f22 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 16 Sep 2014 11:13:13 -0300 Subject: mx25pdk: Add generic board support Let's enable CONFIG_SYS_GENERIC_BOARD in order to get rid of warnings related to generic board support is not in place. Signed-off-by: Fabio Estevam --- include/configs/mx25pdk.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index 34199af203..c02e29be9a 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -14,6 +14,7 @@ #define CONFIG_MX25 #define CONFIG_SYS_TEXT_BASE 0x81200000 #define CONFIG_MXC_GPIO +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_TIMER_RATE 32768 #define CONFIG_SYS_TIMER_COUNTER \ -- cgit v1.2.3 From 36c1ca4d46ef11ac7b3c0afb5c42dadb4e8773f3 Mon Sep 17 00:00:00 2001 From: Nitin Garg Date: Tue, 16 Sep 2014 13:33:25 -0500 Subject: imx: Support i.MX6 High Assurance Boot authentication When CONFIG_SECURE_BOOT is enabled, the signed images like kernel and dtb can be authenticated using iMX6 CAAM. The added command hab_auth_img can be used for HAB authentication of images. The command takes the image DDR location, IVT (Image Vector Table) offset inside image as parameters. Detailed info about signing images can be found in Freescale AppNote AN4581. Signed-off-by: Nitin Garg --- arch/arm/cpu/armv7/mx6/clock.c | 27 ++++++ arch/arm/cpu/armv7/mx6/hab.c | 169 +++++++++++++++++++++++++++++++++- arch/arm/cpu/armv7/mx6/soc.c | 15 +++ arch/arm/include/asm/arch-mx6/clock.h | 1 + 4 files changed, 211 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 336e557a27..d200531030 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -642,6 +642,33 @@ int enable_pcie_clock(void) BM_ANADIG_PLL_ENET_ENABLE_PCIE); } +#ifdef CONFIG_SECURE_BOOT +void hab_caam_clock_enable(unsigned char enable) +{ + u32 reg; + + /* CG4 ~ CG6, CAAM clocks */ + reg = __raw_readl(&imx_ccm->CCGR0); + if (enable) + reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | + MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | + MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK); + else + reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | + MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | + MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK); + __raw_writel(reg, &imx_ccm->CCGR0); + + /* EMI slow clk */ + reg = __raw_readl(&imx_ccm->CCGR6); + if (enable) + reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK; + else + reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK; + __raw_writel(reg, &imx_ccm->CCGR6); +} +#endif + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/cpu/armv7/mx6/hab.c index f6810a680d..8dee595eaf 100644 --- a/arch/arm/cpu/armv7/mx6/hab.c +++ b/arch/arm/cpu/armv7/mx6/hab.c @@ -1,12 +1,14 @@ /* - * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2010-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ #include #include +#include #include +#include #include /* -------- start of HAB API updates ------------*/ @@ -71,6 +73,44 @@ ((hab_rvt_exit_t *)HAB_RVT_EXIT) \ ) +#define IVT_SIZE 0x20 +#define ALIGN_SIZE 0x1000 +#define CSF_PAD_SIZE 0x2000 +#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8 +#define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0 +#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18 + +/* + * +------------+ 0x0 (DDR_UIMAGE_START) - + * | Header | | + * +------------+ 0x40 | + * | | | + * | | | + * | | | + * | | | + * | Image Data | | + * . | | + * . | > Stuff to be authenticated ----+ + * . | | | + * | | | | + * | | | | + * +------------+ | | + * | | | | + * | Fill Data | | | + * | | | | + * +------------+ Align to ALIGN_SIZE | | + * | IVT | | | + * +------------+ + IVT_SIZE - | + * | | | + * | CSF DATA | <---------------------------------------------------------+ + * | | + * +------------+ + * | | + * | Fill Data | + * | | + * +------------+ + CSF_PAD_SIZE + */ + bool is_hab_enabled(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -144,6 +184,108 @@ int get_hab_status(void) return 0; } +uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size) +{ + uint32_t load_addr = 0; + size_t bytes; + ptrdiff_t ivt_offset = 0; + int result = 0; + ulong start; + hab_rvt_authenticate_image_t *hab_rvt_authenticate_image; + hab_rvt_entry_t *hab_rvt_entry; + hab_rvt_exit_t *hab_rvt_exit; + + hab_rvt_authenticate_image = hab_rvt_authenticate_image_p; + hab_rvt_entry = hab_rvt_entry_p; + hab_rvt_exit = hab_rvt_exit_p; + + if (is_hab_enabled()) { + printf("\nAuthenticate image from DDR location 0x%x...\n", + ddr_start); + + hab_caam_clock_enable(1); + + if (hab_rvt_entry() == HAB_SUCCESS) { + /* If not already aligned, Align to ALIGN_SIZE */ + ivt_offset = (image_size + ALIGN_SIZE - 1) & + ~(ALIGN_SIZE - 1); + + start = ddr_start; + bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE; +#ifdef DEBUG + printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", + ivt_offset, ddr_start + ivt_offset); + puts("Dumping IVT\n"); + print_buffer(ddr_start + ivt_offset, + (void *)(ddr_start + ivt_offset), + 4, 0x8, 0); + + puts("Dumping CSF Header\n"); + print_buffer(ddr_start + ivt_offset+IVT_SIZE, + (void *)(ddr_start + ivt_offset+IVT_SIZE), + 4, 0x10, 0); + + get_hab_status(); + + puts("\nCalling authenticate_image in ROM\n"); + printf("\tivt_offset = 0x%x\n", ivt_offset); + printf("\tstart = 0x%08lx\n", start); + printf("\tbytes = 0x%x\n", bytes); +#endif + /* + * If the MMU is enabled, we have to notify the ROM + * code, or it won't flush the caches when needed. + * This is done, by setting the "pu_irom_mmu_enabled" + * word to 1. You can find its address by looking in + * the ROM map. This is critical for + * authenticate_image(). If MMU is enabled, without + * setting this bit, authentication will fail and may + * crash. + */ + /* Check MMU enabled */ + if (get_cr() & CR_M) { + if (is_cpu_type(MXC_CPU_MX6Q) || + is_cpu_type(MXC_CPU_MX6D)) { + /* + * This won't work on Rev 1.0.0 of + * i.MX6Q/D, since their ROM doesn't + * do cache flushes. don't think any + * exist, so we ignore them. + */ + writel(1, MX6DQ_PU_IROM_MMU_EN_VAR); + } else if (is_cpu_type(MXC_CPU_MX6DL) || + is_cpu_type(MXC_CPU_MX6SOLO)) { + writel(1, MX6DLS_PU_IROM_MMU_EN_VAR); + } else if (is_cpu_type(MXC_CPU_MX6SL)) { + writel(1, MX6SL_PU_IROM_MMU_EN_VAR); + } + } + + load_addr = (uint32_t)hab_rvt_authenticate_image( + HAB_CID_UBOOT, + ivt_offset, (void **)&start, + (size_t *)&bytes, NULL); + if (hab_rvt_exit() != HAB_SUCCESS) { + puts("hab exit function fail\n"); + load_addr = 0; + } + } else { + puts("hab entry function fail\n"); + } + + hab_caam_clock_enable(0); + + get_hab_status(); + } else { + puts("hab fuse not enabled\n"); + } + + if ((!is_hab_enabled()) || (load_addr != 0)) + result = 1; + + return result; +} + int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { if ((argc != 1)) { @@ -156,8 +298,33 @@ int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + ulong addr, ivt_offset; + int rcode = 0; + + if (argc < 3) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + ivt_offset = simple_strtoul(argv[2], NULL, 16); + + rcode = authenticate_image(addr, ivt_offset); + + return rcode; +} + U_BOOT_CMD( hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status, "display HAB status", "" ); + +U_BOOT_CMD( + hab_auth_img, 3, 0, do_authenticate_image, + "authenticate image via HAB", + "addr ivt_offset\n" + "addr - image hex address\n" + "ivt_offset - hex offset of IVT in the image" + ); diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index ba21cfe580..05683a3400 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -273,10 +273,25 @@ int board_postclk_init(void) #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) + enum dcache_option option = DCACHE_WRITETHROUGH; +#else + enum dcache_option option = DCACHE_WRITEBACK; +#endif + /* Avoid random hang when download by usb */ invalidate_dcache_all(); + /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); + + /* Enable caching on OCRAM and ROM */ + mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR, + ROMCP_ARB_END_ADDR, + option); + mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, + IRAM_SIZE, + option); } #endif diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index c11674ff8a..3c58a0ab60 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -53,6 +53,7 @@ u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); void setup_gpmi_io_clk(u32 cfg); +void hab_caam_clock_enable(unsigned char enable); void enable_ocotp_clk(unsigned char enable); void enable_usboh3_clk(unsigned char enable); void enable_uart_clk(unsigned char enable); -- cgit v1.2.3 From dd24b57bb78422eba6780f0b6cc4c0b049a82371 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 28 Apr 2014 03:38:39 +0200 Subject: usb: ehci: mxs: Add board-specific callbacks Add board-specific callbacks for enabling/disabling port power into the MXS EHCI controller driver. This is in-line with the names of callbacks on other systems. Signed-off-by: Marek Vasut Cc: Stefano Babic --- drivers/usb/host/ehci-mxs.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index 4d652b32db..6b8d969bb0 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -77,6 +77,16 @@ static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable) return 0; } +int __weak board_ehci_hcd_init(int port) +{ + return 0; +} + +int __weak board_ehci_hcd_exit(int port) +{ + return 0; +} + int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { @@ -90,6 +100,10 @@ int ehci_hcd_init(int index, enum usb_init_type init, return -EINVAL; } + ret = board_ehci_hcd_init(index); + if (ret) + return ret; + port = &mxs_port[index]; /* Reset the PHY block */ @@ -154,5 +168,7 @@ int ehci_hcd_stop(int index) /* Disable USB clock */ ret = ehci_mxs_toggle_clock(port, 0); + board_ehci_hcd_exit(index); + return ret; } -- cgit v1.2.3 From be0ecdbed5efc7833275701ebdb1ff8ef7ffd4c0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 28 Apr 2014 03:38:40 +0200 Subject: arm: mxs: Wait when disabling VDDMEM current limiter According to i.MX23 datasheet Table 32-17, we must wait for the supply to settle before disabling the current limiter. Indeed, not waiting a little here causes the system to crash at times. Signed-off-by: Marek Vasut Cc: Stefano Babic --- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 3baf4ddefc..de8841a0e1 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -240,9 +240,14 @@ static void mx23_mem_setup_vddmem(void) struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; + /* We must wait before and after disabling the current limiter! */ + early_delay(10000); + clrbits_le32(&power_regs->hw_power_vddmemctrl, POWER_VDDMEMCTRL_ENABLE_ILIMIT); + early_delay(10000); + } static void mx23_mem_init(void) -- cgit v1.2.3 From 7c604e98c2213619af6a8c3064418af9b689cf56 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 28 Apr 2014 03:38:41 +0200 Subject: arm: mxs: Wait for DRAM to start Instead of waiting for a fixed period of time and hoping for the best that the DRAM will start, read back an EMI status register which tells us exactly when the DRAM started. Signed-off-by: Marek Vasut Cc: Stefano Babic --- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index de8841a0e1..97ef67d8c5 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -274,7 +274,13 @@ static void mx23_mem_init(void) setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16); clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17); - early_delay(20000); + + /* Wait for EMI_STAT bit DRAM_HALTED */ + for (;;) { + if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1))) + break; + early_delay(1000); + } /* Adjust EMI port priority. */ clrsetbits_le32(0x80020000, 0x1f << 16, 0x2); -- cgit v1.2.3 From ca11db2603e58cfee8e64931dcc3c87023ecb1cf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 28 Apr 2014 03:38:42 +0200 Subject: arm: mxs: olinuxino: Enable USB only when needed Enable the power to the USB port only when the USB port is really needed. Do not enable the power unconditionally. Signed-off-by: Marek Vasut Cc: Stefano Babic --- board/olimex/mx23_olinuxino/mx23_olinuxino.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index e2a03a110b..65cbbf15b7 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -30,13 +30,25 @@ int board_early_init_f(void) /* SSP0 clock at 96MHz */ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + return 0; +} + #ifdef CONFIG_CMD_USB - /* Enable LAN9512 */ +int board_ehci_hcd_init(int port) +{ + /* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */ gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1); -#endif + udelay(100); + return 0; +} +int board_ehci_hcd_exit(int port) +{ + /* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */ + gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 0); return 0; } +#endif int dram_init(void) { -- cgit v1.2.3 From 1fb065feae451b8f22cb9b8b156508ea541c36d7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 28 Apr 2014 03:38:43 +0200 Subject: arm: mxs: olinuxino: Fine-tune DRAM configuration Add fine-tuning for the DRAM configuration according to the DRAM chip datasheet. THis configuration applies to both Hynix HY5DU12622DTP and Samsung K5H511538J-D43 . Signed-off-by: Marek Vasut Cc: Stefano Babic --- board/olimex/mx23_olinuxino/mx23_olinuxino.c | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index 65cbbf15b7..313ab20e26 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -78,3 +78,33 @@ int board_init(void) return 0; } + +/* Fine-tune the DRAM configuration. */ +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + /* Enable Auto Precharge. */ + dram_vals[3] |= 1 << 8; + /* Enable Fast Writes. */ + dram_vals[5] |= 1 << 8; + /* tEMRS = 3*tCK */ + dram_vals[10] &= ~(0x3 << 8); + dram_vals[10] |= (0x3 << 8); + /* CASLAT = 3*tCK */ + dram_vals[11] &= ~(0x3 << 0); + dram_vals[11] |= (0x3 << 0); + /* tCKE = 1*tCK */ + dram_vals[12] &= ~(0x7 << 0); + dram_vals[12] |= (0x1 << 0); + /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */ + dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0)); + dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0); + /* tDAL = 6*tCK */ + dram_vals[15] &= ~(0xf << 16); + dram_vals[15] |= (0x6 << 16); + /* tREF = 1040*tCK */ + dram_vals[26] &= ~0xffff; + dram_vals[26] |= 0x0410; + /* tRAS_MAX = 9334*tCK */ + dram_vals[32] &= ~0xffff; + dram_vals[32] |= 0x2475; +} -- cgit v1.2.3 From e7380a1fdc90a88c450458f87899199bd8f4681e Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Tue, 9 Sep 2014 10:16:57 +0800 Subject: imx: mx6qarm2: Add the kernel FDT Loading support To support loading FDT file for kernel, add the fdt address, file and loading script to arm2 board default environment. Signed-off-by: Ye.Li --- include/configs/mx6qarm2.h | 41 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index e2469a1165..a8c496d065 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -69,15 +69,19 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_LOADADDR 0x10800000 +#define CONFIG_LOADADDR 0x12000000 #define CONFIG_SYS_TEXT_BASE 0x17800000 #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc3\0" \ + "fdt_file=imx6q-arm2.dtb\0" \ + "fdt_addr=0x18000000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ "mmcdev=1\0" \ "mmcpart=2\0" \ "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ @@ -88,15 +92,46 @@ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "bootz\0" \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ "run netargs; " \ - "dhcp ${image}; bootz\0" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev};" \ -- cgit v1.2.3 From adca1875c8090dea9b163550d8607ccba5418819 Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Tue, 9 Sep 2014 10:16:58 +0800 Subject: imx: mx6qarm2: Change the mmcroot and mmcpart env value 1. Set the image load partition to the first FAT partition. 2. Set the kernel rootfs partition to the second partition. Signed-off-by: Ye.Li --- include/configs/mx6qarm2.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index a8c496d065..aa01647c97 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -83,8 +83,8 @@ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "mmcdev=1\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadbootscript=" \ -- cgit v1.2.3 From 9293d7fd502ce29302fadb8b4ccb9231ec0bcc66 Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Tue, 9 Sep 2014 10:17:00 +0800 Subject: imx: mx6: Checking PLL2 PFD0 and PFD2 for periph_clk before PFD reset Checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source, do not reset this PFD to avoid system hang. Customers may set this in DDR script or use BT_FREQ to select low freq boot. Signed-off-by: Ye.Li --- arch/arm/cpu/armv7/mx6/soc.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 05683a3400..6352422253 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -354,10 +354,10 @@ const struct boot_mode soc_boot_modes[] = { void s_init(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int is_6q = is_cpu_type(MXC_CPU_MX6Q); + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; u32 mask480; u32 mask528; - + u32 reg, periph1, periph2; if (is_cpu_type(MXC_CPU_MX6SX)) return; @@ -372,15 +372,23 @@ void s_init(void) ANATOP_PFD_CLKGATE_MASK(1) | ANATOP_PFD_CLKGATE_MASK(2) | ANATOP_PFD_CLKGATE_MASK(3); - mask528 = ANATOP_PFD_CLKGATE_MASK(0) | - ANATOP_PFD_CLKGATE_MASK(1) | + mask528 = ANATOP_PFD_CLKGATE_MASK(1) | ANATOP_PFD_CLKGATE_MASK(3); - /* - * Don't reset PFD2 on DL/S - */ - if (is_6q) + reg = readl(&ccm->cbcmr); + periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) + >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET); + periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET); + + /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */ + if ((periph2 != 0x2) && (periph1 != 0x2)) + mask528 |= ANATOP_PFD_CLKGATE_MASK(0); + + if ((periph2 != 0x1) && (periph1 != 0x1) && + (periph2 != 0x3) && (periph1 != 0x3)) mask528 |= ANATOP_PFD_CLKGATE_MASK(2); + writel(mask480, &anatop->pfd_480_set); writel(mask528, &anatop->pfd_528_set); writel(mask480, &anatop->pfd_480_clr); -- cgit v1.2.3 From 5546ad0734bb5eed2b3cd6333dbcec51ae45185a Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Mon, 15 Sep 2014 17:23:14 +0800 Subject: usb: ehci-mx6: Rename the USB register base address The mx6sl/mx6sx has 2 OTG and 1 host. So they have name "USBO2H_USB_BASE_ADDR" in imx-regs.h. The driver hard codes the USB base address name to "USBOH3", which causes the driver failed to build for mx6sl/mx6sx. This patch uniform the address name to "USB_BASE_ADDR" for all mx6 series. Signed-off-by: Ye.Li --- arch/arm/include/asm/arch-mx6/imx-regs.h | 9 ++------- drivers/usb/host/ehci-mx6.c | 4 ++-- 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 22614fcd0e..a159309bb9 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -215,13 +215,8 @@ #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) -#ifdef CONFIG_MX6SL -#define USBO2H_PL301_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) -#define USBO2H_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) -#else -#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) -#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) -#endif +#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) +#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) #ifdef CONFIG_MX6SL diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index c0a557b2ad..9ec5a0a539 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -174,7 +174,7 @@ struct usbnc_regs { static void usb_oc_config(int index) { - struct usbnc_regs *usbnc = (struct usbnc_regs *)(USBOH3_USB_BASE_ADDR + + struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET); void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]); u32 val; @@ -207,7 +207,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { enum usb_init_type type; - struct usb_ehci *ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR + + struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR + (0x200 * index)); if (index > 3) -- cgit v1.2.3 From 4ba9b1c2e3805c1399b2c432b5c0b2f1d985b88a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 23 Sep 2014 13:18:18 +0200 Subject: arm: m28evk: Test if bootscript exists before loading it Make sure the boot.scr exists on the card before loading it from the card to avoid annoying message on the console. Signed-off-by: Marek Vasut Cc: Stefano Babic --- include/configs/m28evk.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index fccd29dc26..2d9ad5f23c 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -279,10 +279,12 @@ "bootm ${kernel_addr_r}\0" \ "try_bootscript=" \ "mmc rescan;" \ + "if test -e mmc 0:2 ${bootscript} ; then " \ "if ext4load mmc 0:2 ${kernel_addr_r} ${bootscript};" \ "then;" \ "\techo Running bootscript...;" \ "\tsource ${kernel_addr_r};" \ + "fi ; " \ "fi\0" /* The rest of the configuration is shared */ -- cgit v1.2.3 From 14b256e5c084e1b693f4ad73c6a8beee7ffcb4af Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 23 Sep 2014 13:18:19 +0200 Subject: arm: m53evk: Test if bootscript exists before loading it Make sure the boot.scr exists on the card before loading it from the card to avoid annoying message on the console. Signed-off-by: Marek Vasut Cc: Stefano Babic --- include/configs/m53evk.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index df6a226109..ad9c39c16c 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -348,10 +348,12 @@ "bootm ${kernel_addr_r}\0" \ "try_bootscript=" \ "mmc rescan;" \ + "if test -e mmc 0:1 ${bootscript} ; then " \ "if ext4load mmc 0:1 ${kernel_addr_r} ${bootscript};" \ "then;" \ "\techo Running bootscript...;" \ "\tsource ${kernel_addr_r};" \ + "fi ; " \ "fi\0" #endif /* __M53EVK_CONFIG_H__ */ -- cgit v1.2.3 From fc532a921aae1151dd39322d8f50b55a735de8d5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 23 Sep 2014 13:18:20 +0200 Subject: arm: m28evk: Enable FS_GENERIC Enable the CONFIG_CMD_FS_GENERIC on m28evk to avoid per-fs specific commands and tweak the environment to cater for this new option. Signed-off-by: Marek Vasut Cc: Stefano Babic --- include/configs/m28evk.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 2d9ad5f23c..322b45fd99 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -32,6 +32,7 @@ #define CONFIG_CMD_EXT4 #define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_GPIO #define CONFIG_CMD_GREPENV #define CONFIG_CMD_I2C @@ -236,7 +237,7 @@ "addargs=run addcons addmtd addmisc\0" \ "mmcload=" \ "mmc rescan ; " \ - "ext4load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \ + "load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \ "ubiload=" \ "ubi part UBI ; ubifsmount ubi0:rootfs ; " \ "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \ @@ -280,7 +281,7 @@ "try_bootscript=" \ "mmc rescan;" \ "if test -e mmc 0:2 ${bootscript} ; then " \ - "if ext4load mmc 0:2 ${kernel_addr_r} ${bootscript};" \ + "if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \ "then;" \ "\techo Running bootscript...;" \ "\tsource ${kernel_addr_r};" \ -- cgit v1.2.3 From febae49a2b282283db98c1217aa04c4538704585 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 23 Sep 2014 13:18:21 +0200 Subject: arm: m53evk: Enable FS_GENERIC Enable the CONFIG_CMD_FS_GENERIC on m53evk to avoid per-fs specific commands and tweak the environment to cater for this new option. Signed-off-by: Marek Vasut Cc: Stefano Babic --- include/configs/m53evk.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index ad9c39c16c..ee4eb10e46 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -38,6 +38,7 @@ #define CONFIG_CMD_EXT4 #define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_GREPENV #define CONFIG_CMD_I2C #define CONFIG_CMD_MII @@ -305,7 +306,7 @@ "addargs=run addcons addmtd addmisc\0" \ "mmcload=" \ "mmc rescan ; " \ - "ext4load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \ + "load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \ "ubiload=" \ "ubi part UBI ; ubifsmount ubi0:rootfs ; " \ "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \ @@ -349,7 +350,7 @@ "try_bootscript=" \ "mmc rescan;" \ "if test -e mmc 0:1 ${bootscript} ; then " \ - "if ext4load mmc 0:1 ${kernel_addr_r} ${bootscript};" \ + "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \ "then;" \ "\techo Running bootscript...;" \ "\tsource ${kernel_addr_r};" \ -- cgit v1.2.3 From b357503f1cdedade6d31991fa6aabb4174f92989 Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Mon, 29 Sep 2014 23:26:28 +0800 Subject: imx: mx6dlarm2: Add support for i.MX6DL arm2 DDR3 board This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2 shared the same board with i.MX6Q ARM2 board since the i.MX6DL is pin-pin compatible with i.MX6Q. The patch also support the DDR 32-BIT mode option. Please define CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT mode.But due to the board design, it's 64bit DDR buswidth physically, so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it. Signed-off-by: Ye.Li --- board/freescale/mx6qarm2/MAINTAINERS | 2 + board/freescale/mx6qarm2/imximage_mx6dl.cfg | 143 ++++++++++++++++++++++++++++ board/freescale/mx6qarm2/mx6qarm2.c | 4 + configs/mx6dlarm2_defconfig | 3 + configs/mx6qarm2_defconfig | 2 +- include/configs/mx6qarm2.h | 5 +- 6 files changed, 157 insertions(+), 2 deletions(-) create mode 100644 board/freescale/mx6qarm2/imximage_mx6dl.cfg create mode 100644 configs/mx6dlarm2_defconfig diff --git a/board/freescale/mx6qarm2/MAINTAINERS b/board/freescale/mx6qarm2/MAINTAINERS index 42c19d13ec..c8d594b17f 100644 --- a/board/freescale/mx6qarm2/MAINTAINERS +++ b/board/freescale/mx6qarm2/MAINTAINERS @@ -1,6 +1,8 @@ MX6QARM2 BOARD M: Jason Liu +M: Ye Li S: Maintained F: board/freescale/mx6qarm2/ F: include/configs/mx6qarm2.h F: configs/mx6qarm2_defconfig +F: configs/mx6dlarm2_defconfig diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg new file mode 100644 index 0000000000..eef723c254 --- /dev/null +++ b/board/freescale/mx6qarm2/imximage_mx6dl.cfg @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0798 0x000c0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e0590 0x00003000 +DATA 4 0x020e0598 0x00003000 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00003030 +DATA 4 0x020e05a0 0x00003030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 + +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b4800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x00370037 +DATA 4 0x021b4810 0x00370037 +DATA 4 0x021b083c 0x422f0220 +DATA 4 0x021b0840 0x021f0219 +DATA 4 0x021b483C 0x422f0220 +DATA 4 0x021b4840 0x022d022f +DATA 4 0x021b0848 0x47494b49 +DATA 4 0x021b4848 0x48484c47 +DATA 4 0x021b0850 0x39382b2f +DATA 4 0x021b4850 0x2f35312c +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 + +DATA 4 0x021b000c 0x40445323 +DATA 4 0x021b0010 0xb66e8c63 + +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00081740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x00440e21 +#ifdef CONFIG_DDR_32BIT +DATA 4 0x021b0040 0x00000017 +DATA 4 0x021b0000 0xc3190000 +#else +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0xc31a0000 +#endif +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x0400803a +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x0000803b +DATA 4 0x021b001c 0x00428031 +DATA 4 0x021b001c 0x00428039 +DATA 4 0x021b001c 0x07208030 +DATA 4 0x021b001c 0x07208038 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b001c 0x04008048 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00000007 +DATA 4 0x021b4818 0x00000007 +DATA 4 0x021b0004 0x0002556d +DATA 4 0x021b4004 0x00011006 +DATA 4 0x021b001c 0x00000000 + +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +DATA 4 0x020e0010 0xF00000CF +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 6c51f3a182..f2e577d514 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -224,7 +224,11 @@ int board_init(void) int checkboard(void) { +#ifdef CONFIG_MX6DL + puts("Board: MX6DL-Armadillo2\n"); +#else puts("Board: MX6Q-Armadillo2\n"); +#endif return 0; } diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig new file mode 100644 index 0000000000..b4b78e5ab5 --- /dev/null +++ b/configs/mx6dlarm2_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL" +CONFIG_ARM=y +CONFIG_TARGET_MX6QARM2=y diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig index bdcc672b57..a251615a38 100644 --- a/configs/mx6qarm2_defconfig +++ b/configs/mx6qarm2_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q" CONFIG_ARM=y CONFIG_TARGET_MX6QARM2=y diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index aa01647c97..ed57e4aa87 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -10,7 +10,6 @@ #define __CONFIG_H #define CONFIG_MX6 -#define CONFIG_MX6Q #include "mx6_common.h" @@ -169,7 +168,11 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#ifdef CONFIG_DDR_32BIT +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) +#else #define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) +#endif #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -- cgit v1.2.3 From 661139faf7b03a8d88da55ee36ad4b0fb7e35964 Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Mon, 29 Sep 2014 23:26:29 +0800 Subject: imx: mx6dlarm2: Add support for i.MX6Q/DL arm2 LPDDR2 boards Update the ddr scripts for LPDDR2 and add two build configs for LPDDR2 arm2 board. Since the LPDDR2 arm2 board has different DDR size, use CONFIG_DDR_MB in defconfig to replace the PHYS_SDRAM_SIZE. Signed-off-by: Ye.Li --- board/freescale/mx6qarm2/MAINTAINERS | 2 + board/freescale/mx6qarm2/imximage.cfg | 189 +++++++++++++++- board/freescale/mx6qarm2/imximage_mx6dl.cfg | 319 ++++++++++++++++++++++++++++ board/freescale/mx6qarm2/mx6qarm2.c | 7 +- configs/mx6dlarm2_defconfig | 2 +- configs/mx6dlarm2_lpddr2_defconfig | 3 + configs/mx6qarm2_defconfig | 2 +- configs/mx6qarm2_lpddr2_defconfig | 3 + include/configs/mx6qarm2.h | 5 - 9 files changed, 518 insertions(+), 14 deletions(-) create mode 100644 configs/mx6dlarm2_lpddr2_defconfig create mode 100644 configs/mx6qarm2_lpddr2_defconfig diff --git a/board/freescale/mx6qarm2/MAINTAINERS b/board/freescale/mx6qarm2/MAINTAINERS index c8d594b17f..52cf7f935a 100644 --- a/board/freescale/mx6qarm2/MAINTAINERS +++ b/board/freescale/mx6qarm2/MAINTAINERS @@ -6,3 +6,5 @@ F: board/freescale/mx6qarm2/ F: include/configs/mx6qarm2.h F: configs/mx6qarm2_defconfig F: configs/mx6dlarm2_defconfig +F: configs/mx6qarm2_lpddr2_defconfig +F: configs/mx6dlarm2_lpddr2_defconfig diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg index 710f34d9a5..c85bde510e 100644 --- a/board/freescale/mx6qarm2/imximage.cfg +++ b/board/freescale/mx6qarm2/imximage.cfg @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. * Jason Liu * * SPDX-License-Identifier: GPL-2.0+ @@ -30,6 +30,185 @@ BOOT_FROM sd * Address absolute address of the register * value value to be stored in the register */ +#ifdef CONFIG_MX6DQ_LPDDR2 +/* DCD */ +DATA 4 0x020C4018 0x60324 + +DATA 4 0x020E05a8 0x00003038 +DATA 4 0x020E05b0 0x00003038 +DATA 4 0x020E0524 0x00003038 +DATA 4 0x020E051c 0x00003038 + +DATA 4 0x020E0518 0x00003038 +DATA 4 0x020E050c 0x00003038 +DATA 4 0x020E05b8 0x00003038 +DATA 4 0x020E05c0 0x00003038 + +DATA 4 0x020E05ac 0x00000038 +DATA 4 0x020E05b4 0x00000038 +DATA 4 0x020E0528 0x00000038 +DATA 4 0x020E0520 0x00000038 + +DATA 4 0x020E0514 0x00000038 +DATA 4 0x020E0510 0x00000038 +DATA 4 0x020E05bc 0x00000038 +DATA 4 0x020E05c4 0x00000038 + +DATA 4 0x020E056c 0x00000038 +DATA 4 0x020E0578 0x00000038 +DATA 4 0x020E0588 0x00000038 +DATA 4 0x020E0594 0x00000038 + +DATA 4 0x020E057c 0x00000038 +DATA 4 0x020E0590 0x00000038 +DATA 4 0x020E0598 0x00000038 +DATA 4 0x020E058c 0x00000000 + +DATA 4 0x020E059c 0x00000038 +DATA 4 0x020E05a0 0x00000038 +DATA 4 0x020E0784 0x00000038 +DATA 4 0x020E0788 0x00000038 + +DATA 4 0x020E0794 0x00000038 +DATA 4 0x020E079c 0x00000038 +DATA 4 0x020E07a0 0x00000038 +DATA 4 0x020E07a4 0x00000038 + +DATA 4 0x020E07a8 0x00000038 +DATA 4 0x020E0748 0x00000038 +DATA 4 0x020E074c 0x00000038 +DATA 4 0x020E0750 0x00020000 + +DATA 4 0x020E0758 0x00000000 +DATA 4 0x020E0774 0x00020000 +DATA 4 0x020E078c 0x00000038 +DATA 4 0x020E0798 0x00080000 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b401c 0x00008000 + +DATA 4 0x021b085c 0x1b5f01ff +DATA 4 0x021b485c 0x1b5f01ff + +DATA 4 0x021b0800 0xa1390000 +DATA 4 0x021b4800 0xa1390000 + +DATA 4 0x021b0890 0x00400000 +DATA 4 0x021b4890 0x00400000 + +DATA 4 0x021b48bc 0x00055555 + +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b0834 0xf3333333 +DATA 4 0x021b0838 0xf3333333 +DATA 4 0x021b482c 0xf3333333 +DATA 4 0x021b4830 0xf3333333 +DATA 4 0x021b4834 0xf3333333 +DATA 4 0x021b4838 0xf3333333 + +DATA 4 0x021b0848 0x49383b39 +DATA 4 0x021b0850 0x30364738 +DATA 4 0x021b4848 0x3e3c3846 +DATA 4 0x021b4850 0x4c294b35 + +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x0 +DATA 4 0x021b483c 0x20000000 +DATA 4 0x021b4840 0x0 + +DATA 4 0x021b0858 0xf00 +DATA 4 0x021b4858 0xf00 + +DATA 4 0x021b08b8 0x800 +DATA 4 0x021b48b8 0x800 + +DATA 4 0x021b000c 0x555a61a5 +DATA 4 0x021b0004 0x20036 +DATA 4 0x021b0010 0x160e83 +DATA 4 0x021b0014 0xdd +DATA 4 0x021b0018 0x8174c +DATA 4 0x021b002c 0xf9f26d2 +DATA 4 0x021b0030 0x20e +DATA 4 0x021b0038 0x200aac +DATA 4 0x021b0008 0x0 + +DATA 4 0x021b0040 0x5f + +DATA 4 0x021b0000 0xc3010000 + +DATA 4 0x021b400c 0x555a61a5 +DATA 4 0x021b4004 0x20036 +DATA 4 0x021b4010 0x160e83 +DATA 4 0x021b4014 0xdd +DATA 4 0x021b4018 0x8174c +DATA 4 0x021b402c 0xf9f26d2 +DATA 4 0x021b4030 0x20e +DATA 4 0x021b4038 0x200aac +DATA 4 0x021b4008 0x0 + +DATA 4 0x021b4040 0x3f +DATA 4 0x021b4000 0xc3010000 + +DATA 4 0x021b001c 0x3f8030 +DATA 4 0x021b001c 0xff0a8030 +DATA 4 0x021b001c 0xc2018030 +DATA 4 0x021b001c 0x6028030 +DATA 4 0x021b001c 0x2038030 + +DATA 4 0x021b401c 0x3f8030 +DATA 4 0x021b401c 0xff0a8030 +DATA 4 0x021b401c 0xc2018030 +DATA 4 0x021b401c 0x6028030 +DATA 4 0x021b401c 0x2038030 + +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b4800 0xa1390003 + +DATA 4 0x021b0020 0x7800 +DATA 4 0x021b4020 0x7800 + +DATA 4 0x021b0818 0x0 +DATA 4 0x021b4818 0x0 + +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b4800 0xa1390003 + +DATA 4 0x021b08b8 0x800 +DATA 4 0x021b48b8 0x800 + +DATA 4 0x021b001c 0x0 +DATA 4 0x021b401c 0x0 + +DATA 4 0x021b0404 0x00011006 + +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +#else DATA 4 0x020e05a8 0x00000030 DATA 4 0x020e05b0 0x00000030 DATA 4 0x020e0524 0x00000030 @@ -142,12 +321,8 @@ DATA 4 0x021b48b8 0x00000800 DATA 4 0x021b001c 0x00000000 DATA 4 0x021b0404 0x00011006 -DATA 4 0x020e0010 0xF00000FF -DATA 4 0x020e0018 0x00070007 -DATA 4 0x020e001c 0x00070007 - DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC00 +DATA 4 0x020c406c 0x0030FC03 DATA 4 0x020c4070 0x0FFFC000 DATA 4 0x020c4074 0x3FF00000 DATA 4 0x020c4078 0x00FFF300 @@ -159,3 +334,5 @@ DATA 4 0x020e0010 0xF00000CF /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F + +#endif /* CONFIG_MX6DQ_LPDDR2 */ diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg index eef723c254..ae8dcc626e 100644 --- a/board/freescale/mx6qarm2/imximage_mx6dl.cfg +++ b/board/freescale/mx6qarm2/imximage_mx6dl.cfg @@ -30,6 +30,324 @@ BOOT_FROM sd * Address absolute address of the register * value value to be stored in the register */ + + + +#ifdef CONFIG_MX6DL_LPDDR2 + +/* IOMUX SETTINGS */ +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */ +DATA 4 0x020E04bc 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ +DATA 4 0x020E04c0 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */ +DATA 4 0x020E04c4 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */ +DATA 4 0x020E04c8 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */ +DATA 4 0x020E04cc 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */ +DATA 4 0x020E04d0 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */ +DATA 4 0x020E04d4 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */ +DATA 4 0x020E04d8 0x00003028 + +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ +DATA 4 0x020E0470 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ +DATA 4 0x020E0474 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */ +DATA 4 0x020E0478 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */ +DATA 4 0x020E047c 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */ +DATA 4 0x020E0480 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */ +DATA 4 0x020E0484 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */ +DATA 4 0x020E0488 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */ +DATA 4 0x020E048c 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ +DATA 4 0x020E0464 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ +DATA 4 0x020E0490 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ +DATA 4 0x020E04ac 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */ +DATA 4 0x020E04b0 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ +DATA 4 0x020E0494 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */ +DATA 4 0x020E04a4 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */ +DATA 4 0x020E04a8 0x00000038 +/* + * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 + * DSE can be configured using Group Control Register: + * IOMUXC_SW_PAD_CTL_GRP_CTLDS + */ +DATA 4 0x020E04a0 0x00000000 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */ +DATA 4 0x020E04b4 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */ +DATA 4 0x020E04b8 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B0DS */ +DATA 4 0x020E0764 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B1DS */ +DATA 4 0x020E0770 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B2DS */ +DATA 4 0x020E0778 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B3DS */ +DATA 4 0x020E077c 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B4DS */ +DATA 4 0x020E0780 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B5DS */ +DATA 4 0x020E0784 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B6DS */ +DATA 4 0x020E078c 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B7DS */ +DATA 4 0x020E0748 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ +DATA 4 0x020E074c 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ +DATA 4 0x020E076c 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ +DATA 4 0x020E0750 0x00020000 +/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ +DATA 4 0x020E0754 0x00000000 +/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ +DATA 4 0x020E0760 0x00020000 +/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ +DATA 4 0x020E0774 0x00080000 + +/* + * DDR Controller Registers + * + * Manufacturer: Mocron + * Device Part Number: MT42L64M64D2KH-18 + * Clock Freq.: 528MHz + * MMDC channels: Both MMDC0, MMDC1 + *Density per CS in Gb: 256M + * Chip Selects used: 2 + * Number of Banks: 8 + * Row address: 14 + * Column address: 9 + * Data bus width 32 + */ + +/* MMDC_P0_BASE_ADDR = 0x021b0000 */ +/* MMDC_P1_BASE_ADDR = 0x021b4000 */ + +/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ +DATA 4 0x021b001c 0x00008000 + +/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ +DATA 4 0x021b401c 0x00008000 + +/*LPDDR2 ZQ params */ +DATA 4 0x021b085c 0x1b5f01ff +DATA 4 0x021b485c 0x1b5f01ff + +/* Calibration setup. */ +/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */ +DATA 4 0x021b0800 0xa1390003 + +/*ca bus abs delay */ +DATA 4 0x021b0890 0x00400000 +/*ca bus abs delay */ +DATA 4 0x021b4890 0x00400000 +/* values of 20,40,50,60,7f tried. no difference seen */ + +/* DDR_PHY_P1_MPWRCADL */ +DATA 4 0x021b48bc 0x00055555 + +/*frc_msr.*/ +DATA 4 0x021b08b8 0x00000800 +/*frc_msr.*/ +DATA 4 0x021b48b8 0x00000800 + +/* DDR_PHY_P0_MPREDQBY0DL3 */ +DATA 4 0x021b081c 0x33333333 +/* DDR_PHY_P0_MPREDQBY1DL3 */ +DATA 4 0x021b0820 0x33333333 +/* DDR_PHY_P0_MPREDQBY2DL3 */ +DATA 4 0x021b0824 0x33333333 +/* DDR_PHY_P0_MPREDQBY3DL3 */ +DATA 4 0x021b0828 0x33333333 +/* DDR_PHY_P1_MPREDQBY0DL3 */ +DATA 4 0x021b481c 0x33333333 +/* DDR_PHY_P1_MPREDQBY1DL3 */ +DATA 4 0x021b4820 0x33333333 +/* DDR_PHY_P1_MPREDQBY2DL3 */ +DATA 4 0x021b4824 0x33333333 +/* DDR_PHY_P1_MPREDQBY3DL3 */ +DATA 4 0x021b4828 0x33333333 + +/* + * Read and write data delay, per byte. + * For optimized DDR operation it is recommended to run mmdc_calibration + * on your board, and replace 4 delay register assigns with resulted values + * Note: + * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section + * should be skipped, or the write/read calibration comming after that + * will stall + * b. The calibration code that runs for both MMDC0 & MMDC1 should be used. + */ + +DATA 4 0x021b0848 0x4b4b524f +DATA 4 0x021b4848 0x494f4c44 + +DATA 4 0x021b0850 0x3c3d303c +DATA 4 0x021b4850 0x3c343d38 + +/*dqs gating dis */ +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x0 +DATA 4 0x021b483c 0x20000000 +DATA 4 0x021b4840 0x0 + +/*clk delay */ +DATA 4 0x021b0858 0xa00 +/*clk delay */ +DATA 4 0x021b4858 0xa00 + +/*frc_msr */ +DATA 4 0x021b08b8 0x00000800 +/*frc_msr */ +DATA 4 0x021b48b8 0x00000800 +/* Calibration setup end */ + +/* Channel0 - startng address 0x80000000 */ +/* MMDC0_MDCFG0 */ +DATA 4 0x021b000c 0x34386145 + +/* MMDC0_MDPDC */ +DATA 4 0x021b0004 0x00020036 +/* MMDC0_MDCFG1 */ +DATA 4 0x021b0010 0x00100c83 +/* MMDC0_MDCFG2 */ +DATA 4 0x021b0014 0x000000Dc +/* MMDC0_MDMISC */ +DATA 4 0x021b0018 0x0000174C +/* MMDC0_MDRWD;*/ +DATA 4 0x021b002c 0x0f9f26d2 +/* MMDC0_MDOR */ +DATA 4 0x021b0030 0x0000020e +/* MMDC0_MDCFG3LP */ +DATA 4 0x021b0038 0x00190778 +/* MMDC0_MDOTC */ +DATA 4 0x021b0008 0x00000000 + +/* CS0_END */ +DATA 4 0x021b0040 0x0000005f +/* ROC */ +DATA 4 0x021b0404 0x0000000f + +/* MMDC0_MDCTL */ +DATA 4 0x021b0000 0xc3010000 + +/* Channel1 - starting address 0x10000000 */ +/* MMDC1_MDCFG0 */ +DATA 4 0x021b400c 0x34386145 + +/* MMDC1_MDPDC */ +DATA 4 0x021b4004 0x00020036 +/* MMDC1_MDCFG1 */ +DATA 4 0x021b4010 0x00100c83 +/* MMDC1_MDCFG2 */ +DATA 4 0x021b4014 0x000000Dc +/* MMDC1_MDMISC */ +DATA 4 0x021b4018 0x0000174C +/* MMDC1_MDRWD;*/ +DATA 4 0x021b402c 0x0f9f26d2 +/* MMDC1_MDOR */ +DATA 4 0x021b4030 0x0000020e +/* MMDC1_MDCFG3LP */ +DATA 4 0x021b4038 0x00190778 +/* MMDC1_MDOTC */ +DATA 4 0x021b4008 0x00000000 + +/* CS0_END */ +DATA 4 0x021b4040 0x0000003f + +/* MMDC1_MDCTL */ +DATA 4 0x021b4000 0xc3010000 + +/* Channel0 : Configure DDR device:*/ +/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ +DATA 4 0x021b001c 0x003f8030 +/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ +DATA 4 0x021b001c 0xff0a8030 +/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ +DATA 4 0x021b001c 0xa2018030 +/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ +DATA 4 0x021b001c 0x06028030 +/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ +DATA 4 0x021b001c 0x01038030 + +/* Channel1 : Configure DDR device:*/ +/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ +DATA 4 0x021b401c 0x003f8030 +/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ +DATA 4 0x021b401c 0xff0a8030 +/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ +DATA 4 0x021b401c 0xa2018030 +/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ +DATA 4 0x021b401c 0x06028030 +/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ +DATA 4 0x021b401c 0x01038030 + +/* MMDC0_MDREF */ +DATA 4 0x021b0020 0x00005800 +/* MMDC1_MDREF */ +DATA 4 0x021b4020 0x00005800 + +/* DDR_PHY_P0_MPODTCTRL */ +DATA 4 0x021b0818 0x0 +/* DDR_PHY_P1_MPODTCTRL */ +DATA 4 0x021b4818 0x0 + +/* + * calibration values based on calibration compare of 0x00ffff00: + * Note, these calibration values are based on Freescale's board + * May need to run calibration on target board to fine tune these + */ + +/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */ +DATA 4 0x021b0800 0xa1310003 + +/* DDR_PHY_P0_MPMUR0, frc_msr */ +DATA 4 0x021b08b8 0x00000800 +/* DDR_PHY_P1_MPMUR0, frc_msr */ +DATA 4 0x021b48b8 0x00000800 + +/* + * MMDC0_MDSCR, clear this register + * (especially the configuration bit as initialization is complete) + */ +DATA 4 0x021b001c 0x00000000 +/* + * MMDC0_MDSCR, clear this register + * (especially the configuration bit as initialization is complete) + */ +DATA 4 0x021b401c 0x00000000 + +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +DATA 4 0x020e0010 0xF00000CF +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +#else /* CONFIG_MX6DL_LPDDR2 */ + DATA 4 0x020e0798 0x000c0000 DATA 4 0x020e0758 0x00000000 DATA 4 0x020e0588 0x00000030 @@ -141,3 +459,4 @@ DATA 4 0x020c4080 0x000003FF DATA 4 0x020e0010 0xF00000CF DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F +#endif /* CONFIG_MX6DL_LPDDR2 */ diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index f2e577d514..667dca532f 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -32,7 +32,12 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); +#if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \ + defined(CONFIG_DDR_32BIT) + gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2; +#else + gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; +#endif return 0; } diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig index b4b78e5ab5..de0193f4cc 100644 --- a/configs/mx6dlarm2_defconfig +++ b/configs/mx6dlarm2_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048" CONFIG_ARM=y CONFIG_TARGET_MX6QARM2=y diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig new file mode 100644 index 0000000000..cc432cfb54 --- /dev/null +++ b/configs/mx6dlarm2_lpddr2_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512" +CONFIG_ARM=y +CONFIG_TARGET_MX6QARM2=y diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig index a251615a38..3fe3559a17 100644 --- a/configs/mx6qarm2_defconfig +++ b/configs/mx6qarm2_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048" CONFIG_ARM=y CONFIG_TARGET_MX6QARM2=y diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig new file mode 100644 index 0000000000..491e22a057 --- /dev/null +++ b/configs/mx6qarm2_lpddr2_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512" +CONFIG_ARM=y +CONFIG_TARGET_MX6QARM2=y diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index ed57e4aa87..6e01fa0435 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -168,11 +168,6 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#ifdef CONFIG_DDR_32BIT -#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#else -#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) -#endif #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -- cgit v1.2.3 From 13bc86037e832f547dacda81339d74177f2e569d Mon Sep 17 00:00:00 2001 From: Nitin Garg Date: Tue, 30 Sep 2014 11:39:29 -0500 Subject: imx6sx: Fix i.MX6SX HAB api function table offset i.MX6SX ROM implements unified table sections. The HAB function table is at offset 0x100. Update the HAB function pointers accordingly. Signed-off-by: Nitin Garg Tested-by: Fabio Estevam --- arch/arm/include/asm/arch-mx6/hab.h | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/hab.h b/arch/arm/include/asm/arch-mx6/hab.h index 1f12695f67..c9e5318bfb 100644 --- a/arch/arm/include/asm/arch-mx6/hab.h +++ b/arch/arm/include/asm/arch-mx6/hab.h @@ -53,11 +53,17 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t, void **, size_t *, hab_loader_callback_f_t); typedef void hapi_clock_init_t(void); -#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4) -#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8) -#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4) -#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098) -#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C) +#ifdef CONFIG_MX6SX +#define HAB_RVT_BASE 0x00000100 +#else +#define HAB_RVT_BASE 0x00000094 +#endif + +#define HAB_RVT_ENTRY (*(uint32_t *)(HAB_RVT_BASE + 0x04)) +#define HAB_RVT_EXIT (*(uint32_t *)(HAB_RVT_BASE + 0x08)) +#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10)) +#define HAB_RVT_REPORT_EVENT (*(uint32_t *)(HAB_RVT_BASE + 0x20)) +#define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24)) #define HAB_RVT_REPORT_EVENT_NEW (*(uint32_t *)0x000000B8) #define HAB_RVT_REPORT_STATUS_NEW (*(uint32_t *)0x000000BC) -- cgit v1.2.3 From 1dd42e313b1b7416d756d9fd9899b300fd238793 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 30 Sep 2014 12:41:17 +0200 Subject: ARM: mx6: gw_ventana: Remove superfluous memset of GD in board_init_f Zeroing GD in board_init_f() is not needed any more. As its now done in crt0.S. The patch that clears the GD in crt0.S is this one: aae2aef9 [arm: Set up global data before board_init_f()] from Simon. Signed-off-by: Stefan Roese Cc: Tim Harvey Cc: Stefano Babic Acked-by: Tim Harvey --- board/gateworks/gw_ventana/gw_ventana_spl.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 9fc253bb82..ca35b3cb7e 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -402,13 +402,6 @@ void board_init_f(ulong dummy) struct ventana_board_info ventana_info; int board_model; - /* - * Zero out global data: - * - this shoudl be done by crt0.S - * - failure to zero it will cause i2c_setup to fail - */ - memset((void *)gd, 0, sizeof(struct global_data)); - /* setup AIPS and disable watchdog */ arch_cpu_init(); -- cgit v1.2.3 From 9f87640c03ea686bde5788ae14b13666620102f7 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 24 Sep 2014 15:21:58 -0300 Subject: wandboard: Select CONFIG_CMD_FUSE Select CONFIG_CMD_FUSE so that the fuse API commands can be used. Signed-off-by: Fabio Estevam --- include/configs/wandboard.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 7d96908f0e..9fb501a341 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -110,6 +110,11 @@ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_CMD_FUSE +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) #define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb" #elif defined(CONFIG_MX6Q) -- cgit v1.2.3 From 4dfb0e4d3e75763d6fbe8788316bea9ba23e8e01 Mon Sep 17 00:00:00 2001 From: DrEagle Date: Sun, 7 Sep 2014 18:01:20 +0200 Subject: ARM: sheevaplug: change env location This patch move the environment offset in sheevaplug. The size of the u-boot binary is become too big. Fix saving environments was result of corrupting the u-boot. Signed-off-by: Gerald Kerma Changes in v2: - patch description Changes in v1: - fix sheevaplug environment offset Signed-off-by: Prafulla Wadaskar --- include/configs/sheevaplug.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 4747adfeb0..d89bc37206 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -54,8 +54,8 @@ * it has to be rounded to sector size */ #define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x60000 -#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ +#define CONFIG_ENV_ADDR 0x80000 +#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ /* * Default environment variables -- cgit v1.2.3 From 0f88a5a98eb9d8d5158b074a127a4bf8d4ce8610 Mon Sep 17 00:00:00 2001 From: DrEagle Date: Sun, 7 Sep 2014 18:01:21 +0200 Subject: ARM: sheevaplug: add MVSATA driver This patch add MVSATA driver to sheevaplug Signed-off-by: Gerald Kerma Changes in v1: - add MVSATA driver to sheevaplug - enable ext4 FS support Signed-off-by: Prafulla Wadaskar --- include/configs/sheevaplug.h | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index d89bc37206..9661b8fd36 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -1,5 +1,6 @@ /* - * (C) Copyright 2009 + * (C) Copyright 2009-2014 + * Gerald Kerma * Marvell Semiconductor * Written-by: Prafulla Wadaskar * @@ -22,13 +23,22 @@ #define CONFIG_MACH_SHEEVAPLUG /* Machine type */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +/* + * Compression configuration + */ +#define CONFIG_BZIP2 +#define CONFIG_LZMA +#define CONFIG_LZO + /* * Commands configuration */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ #include +#define CONFIG_CMD_BOOTZ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV +#define CONFIG_CMD_IDE #define CONFIG_CMD_MII #define CONFIG_CMD_MMC #define CONFIG_CMD_NAND @@ -91,10 +101,24 @@ #define CONFIG_SYS_MMC_BASE KW_SDIO_BASE #endif /* CONFIG_CMD_MMC */ +/* + * SATA driver configuration + */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_IDE_PREINIT +#define CONFIG_DOS_PARTITION +#define CONFIG_MVSATA_IDE_USE_PORT0 +#define CONFIG_MVSATA_IDE_USE_PORT1 +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /* CONFIG_CMD_IDE */ + /* * File system */ #define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 #define CONFIG_CMD_FAT #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_UBI -- cgit v1.2.3 From 65ae9523d9a5868075be40ef2582c75190cee6af Mon Sep 17 00:00:00 2001 From: DrEagle Date: Sun, 7 Sep 2014 18:01:22 +0200 Subject: ARM: sheevaplug: add MTD defaults This patch add MTDIDS and MTDPARTS defaults settings to sheevaplug Signed-off-by: Gerald Kerma Changes in v1: - add MTDIDS and MTDPARTS default to sheevaplug Signed-off-by: Prafulla Wadaskar --- include/configs/sheevaplug.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 9661b8fd36..0a3118d82a 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -83,6 +83,11 @@ "x_bootcmd_usb=usb start\0" \ "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" +#define MTDIDS_DEFAULT "nand0=orion_nand" + +#define MTDPARTS_DEFAULT \ + "mtdparts="CONFIG_MTDPARTS + /* * Ethernet Driver configuration */ -- cgit v1.2.3 From 1e3d64031608d668509b6fe0825f7708bb6b6a0d Mon Sep 17 00:00:00 2001 From: DrEagle Date: Sun, 7 Sep 2014 18:01:23 +0200 Subject: ARM: sheevaplug: redefine MTDPARTS This patch redefine MTDPARTS Signed-off-by: Gerald Kerma Changes in v1: - redefine MTDPARTS Signed-off-by: Prafulla Wadaskar --- include/configs/sheevaplug.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 0a3118d82a..62f46b7e19 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -74,8 +74,10 @@ "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ "${x_bootcmd_usb}; bootm 0x6400000;" -#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \ - "3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0" +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:512K(uboot)," \ + "512K(env),1M(script),6M(kernel)," \ + "12M(ramdisk),4M(spare),-(rootfs)" #define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \ -- cgit v1.2.3 From 8ca21cbea2671bad315cc93ab636a95d95bac058 Mon Sep 17 00:00:00 2001 From: DrEagle Date: Sun, 7 Sep 2014 18:01:24 +0200 Subject: ARM: sheevaplug: add HUSH parser This patch add HUSH command parser Signed-off-by: Gerald Kerma Changes in v1: - add HUSH command parser Signed-off-by: Prafulla Wadaskar --- include/configs/sheevaplug.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 62f46b7e19..71be823899 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -30,6 +30,11 @@ #define CONFIG_LZMA #define CONFIG_LZO +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ + /* * Commands configuration */ -- cgit v1.2.3 From 4b0abf9f3c024225987ec92ea9ae9e8a1ac5950d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 3 Oct 2014 19:21:03 +0900 Subject: mtd: denali: add Denali controller configs to Kconfig Commit 3eb3e72a3f66 (nand/denali: Adding Denali NAND driver support) introduced some new options, and some of them were documented by commit f9860cf081ef (nand/denali: Document CONFIG symbols). This commit allows users to enable/disable them via Kconfig with more detailed help docs. Signed-off-by: Masahiro Yamada Cc: Chin Liang See Cc: Scott Wood --- doc/README.nand | 6 ------ drivers/mtd/Kconfig | 1 + drivers/mtd/nand/Kconfig | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 33 insertions(+), 6 deletions(-) create mode 100644 drivers/mtd/nand/Kconfig diff --git a/doc/README.nand b/doc/README.nand index 320d752952..e29188f1ec 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -215,12 +215,6 @@ Configuration Options: Platform specific options ========================= - CONFIG_NAND_DENALI - Enables the denali.c driver. - - CONFIG_SYS_NAND_DENALI_64BIT - Indicates that the Denali NAND controller is the 64-bit variant. - CONFIG_NAND_OMAP_GPMC Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. GPMC controller is used for parallel NAND flash devices, and can diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index e69de29bb2..415ab4eba9 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -0,0 +1 @@ +source "drivers/mtd/nand/Kconfig" diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig new file mode 100644 index 0000000000..1d9bf4802c --- /dev/null +++ b/drivers/mtd/nand/Kconfig @@ -0,0 +1,32 @@ +menu "NAND Device Support" + +if !SPL_BUILD + +config NAND_DENALI + bool "Support Denali NAND controller" + help + Enable support for the Denali NAND controller. + +config SYS_NAND_DENALI_64BIT + bool "Use 64-bit variant of Denali NAND controller" + depends on NAND_DENALI + help + The Denali NAND controller IP has some variations in terms of + the bus interface. The DMA setup sequence is completely differenct + between 32bit / 64bit AXI bus variants. + + If your Denali NAND controller is the 64-bit variant, say Y. + Otherwise (32 bit), say N. + +config NAND_DENALI_SPARE_AREA_SKIP_BYTES + int "Number of bytes skipped in OOB area" + depends on NAND_DENALI + range 0 63 + help + This option specifies the number of bytes to skip from the beginning + of OOB area before last ECC sector data starts. This is potentially + used to preserve the bad block marker in the OOB area. + +endif + +endmenu -- cgit v1.2.3 From 845034e6b217d5ff73de03213ede9b17646a91b1 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 3 Oct 2014 19:21:04 +0900 Subject: mtd: denali: add Denali NAND driver for SPL The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP. This driver requires two CONFIG macros: - CONFIG_SPL_NAND_DENALI Define to enable this driver. - CONFIG_SYS_NAND_BAD_BLOCK_POS Specify bad block mark position in the oob space. Typically 0. Signed-off-by: Masahiro Yamada Cc: Chin Liang See Cc: Scott Wood --- drivers/mtd/nand/Kconfig | 10 ++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/denali_spl.c | 231 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 242 insertions(+) create mode 100644 drivers/mtd/nand/denali_spl.c diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 1d9bf4802c..75c2c065c8 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -29,4 +29,14 @@ config NAND_DENALI_SPARE_AREA_SKIP_BYTES endif +if SPL_BUILD + +config SPL_NAND_DENALI + bool "Support Denali NAND controller for SPL" + help + This is a small implementation of the Denali NAND controller + for use on SPL. + +endif + endmenu diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index f298f8434a..47eb34f9c5 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -12,6 +12,7 @@ NORMAL_DRIVERS=y endif obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o +obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o diff --git a/drivers/mtd/nand/denali_spl.c b/drivers/mtd/nand/denali_spl.c new file mode 100644 index 0000000000..65fdde8a65 --- /dev/null +++ b/drivers/mtd/nand/denali_spl.c @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "denali.h" + +#define SPARE_ACCESS 0x41 +#define MAIN_ACCESS 0x42 +#define PIPELINE_ACCESS 0x2000 + +#define BANK(x) ((x) << 24) + +static void __iomem *denali_flash_mem = + (void __iomem *)CONFIG_SYS_NAND_DATA_BASE; +static void __iomem *denali_flash_reg = + (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; + +static const int flash_bank; +static uint8_t page_buffer[NAND_MAX_PAGESIZE]; +static int page_size, oob_size, pages_per_block; + +static void index_addr(uint32_t address, uint32_t data) +{ + writel(address, denali_flash_mem + INDEX_CTRL_REG); + writel(data, denali_flash_mem + INDEX_DATA_REG); +} + +static int wait_for_irq(uint32_t irq_mask) +{ + unsigned long timeout = 1000000; + uint32_t intr_status; + + do { + intr_status = readl(denali_flash_reg + INTR_STATUS(flash_bank)); + + if (intr_status & INTR_STATUS__ECC_UNCOR_ERR) { + debug("Uncorrected ECC detected\n"); + return -EIO; + } + + if (intr_status & irq_mask) + break; + + udelay(1); + timeout--; + } while (timeout); + + if (!timeout) { + debug("Timeout with interrupt status %08x\n", intr_status); + return -EIO; + } + + return 0; +} + +static void read_data_from_flash_mem(uint8_t *buf, int len) +{ + int i; + uint32_t *buf32; + + /* transfer the data from the flash */ + buf32 = (uint32_t *)buf; + + /* + * Let's take care of unaligned access although it rarely happens. + * Avoid put_unaligned() for the normal use cases since it leads to + * a bit performance regression. + */ + if ((unsigned long)buf32 % 4) { + for (i = 0; i < len / 4; i++) + put_unaligned(readl(denali_flash_mem + INDEX_DATA_REG), + buf32++); + } else { + for (i = 0; i < len / 4; i++) + *buf32++ = readl(denali_flash_mem + INDEX_DATA_REG); + } + + if (len % 4) { + u32 tmp; + + tmp = cpu_to_le32(readl(denali_flash_mem + INDEX_DATA_REG)); + buf = (uint8_t *)buf32; + for (i = 0; i < len % 4; i++) { + *buf++ = tmp; + tmp >>= 8; + } + } +} + +int denali_send_pipeline_cmd(int page, int ecc_en, int access_type) +{ + uint32_t addr, cmd; + static uint32_t page_count = 1; + + writel(ecc_en, denali_flash_reg + ECC_ENABLE); + + /* clear all bits of intr_status. */ + writel(0xffff, denali_flash_reg + INTR_STATUS(flash_bank)); + + addr = BANK(flash_bank) | page; + + /* setup the acccess type */ + cmd = MODE_10 | addr; + index_addr(cmd, access_type); + + /* setup the pipeline command */ + index_addr(cmd, PIPELINE_ACCESS | page_count); + + cmd = MODE_01 | addr; + writel(cmd, denali_flash_mem + INDEX_CTRL_REG); + + return wait_for_irq(INTR_STATUS__LOAD_COMP); +} + +static int nand_read_oob(void *buf, int page) +{ + int ret; + + ret = denali_send_pipeline_cmd(page, 0, SPARE_ACCESS); + if (ret < 0) + return ret; + + read_data_from_flash_mem(buf, oob_size); + + return 0; +} + +static int nand_read_page(void *buf, int page) +{ + int ret; + + ret = denali_send_pipeline_cmd(page, 1, MAIN_ACCESS); + if (ret < 0) + return ret; + + read_data_from_flash_mem(buf, page_size); + + return 0; +} + +static int nand_block_isbad(int block) +{ + int ret; + + ret = nand_read_oob(page_buffer, block * pages_per_block); + if (ret < 0) + return ret; + + return page_buffer[CONFIG_SYS_NAND_BAD_BLOCK_POS] != 0xff; +} + +/* nand_init() - initialize data to make nand usable by SPL */ +void nand_init(void) +{ + /* access to main area */ + writel(0, denali_flash_reg + TRANSFER_SPARE_REG); + + /* + * These registers are expected to be already set by the hardware + * or earlier boot code. So we read these values out. + */ + page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE); + oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE); + pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK); +} + +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) +{ + int block, page, column, readlen; + int ret; + int force_bad_block_check = 1; + + page = offs / page_size; + column = offs % page_size; + + block = page / pages_per_block; + page = page % pages_per_block; + + while (size) { + if (force_bad_block_check || page == 0) { + ret = nand_block_isbad(block); + if (ret < 0) + return ret; + + if (ret) { + block++; + continue; + } + } + + force_bad_block_check = 0; + + if (unlikely(column || size < page_size)) { + /* Partial page read */ + ret = nand_read_page(page_buffer, + block * pages_per_block + page); + if (ret < 0) + return ret; + + readlen = min(page_size - column, size); + memcpy(dst, page_buffer, readlen); + + column = 0; + } else { + ret = nand_read_page(dst, + block * pages_per_block + page); + if (ret < 0) + return ret; + + readlen = page_size; + } + + size -= readlen; + dst += readlen; + page++; + if (page == pages_per_block) { + block++; + page = 0; + } + } + + return 0; +} + +void nand_deselect(void) {} -- cgit v1.2.3 From 7f368553fcada0b38e8a096fcba4fcd64e0d2020 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 3 Oct 2014 19:21:05 +0900 Subject: serial: add UniPhier serial driver The driver for on-chip UART used on Panasonic UniPhier platform. Signed-off-by: Masahiro Yamada --- drivers/serial/Makefile | 1 + drivers/serial/serial.c | 2 + drivers/serial/serial_uniphier.c | 204 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 207 insertions(+) create mode 100644 drivers/serial/serial_uniphier.c diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 853a8c6919..b4f299bb0e 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o obj-$(CONFIG_MXS_AUART) += mxs_auart.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o +obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index bbe60af627..82fbbd92e2 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -157,6 +157,7 @@ serial_initfunc(sh_serial_initialize); serial_initfunc(arm_dcc_initialize); serial_initfunc(mxs_auart_initialize); serial_initfunc(arc_serial_initialize); +serial_initfunc(uniphier_serial_initialize); /** * serial_register() - Register serial driver with serial driver core @@ -250,6 +251,7 @@ void serial_initialize(void) arm_dcc_initialize(); mxs_auart_initialize(); arc_serial_initialize(); + uniphier_serial_initialize(); serial_assign(default_serial_console()->name); } diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c new file mode 100644 index 0000000000..f8c9d921e2 --- /dev/null +++ b/drivers/serial/serial_uniphier.c @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * Based on serial_ns16550.c + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define UART_REG(x) \ + u8 x; \ + u8 postpad_##x[3]; + +/* + * Note: Register map is slightly different from that of 16550. + */ +struct uniphier_serial { + UART_REG(rbr); /* 0x00 */ + UART_REG(ier); /* 0x04 */ + UART_REG(iir); /* 0x08 */ + UART_REG(fcr); /* 0x0c */ + u8 mcr; /* 0x10 */ + u8 lcr; + u16 __postpad; + UART_REG(lsr); /* 0x14 */ + UART_REG(msr); /* 0x18 */ + u32 __none1; + u32 __none2; + u16 dlr; + u16 __postpad2; +}; + +#define thr rbr + +/* + * These are the definitions for the Line Control Register + */ +#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ + +/* + * These are the definitions for the Line Status Register + */ +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ + +DECLARE_GLOBAL_DATA_PTR; + +static void uniphier_serial_init(struct uniphier_serial *port) +{ + const unsigned int mode_x_div = 16; + unsigned int divisor; + + writeb(UART_LCR_WLS_8, &port->lcr); + + divisor = DIV_ROUND_CLOSEST(CONFIG_SYS_UNIPHIER_UART_CLK, + mode_x_div * gd->baudrate); + + writew(divisor, &port->dlr); +} + +static void uniphier_serial_setbrg(struct uniphier_serial *port) +{ + uniphier_serial_init(port); +} + +static int uniphier_serial_tstc(struct uniphier_serial *port) +{ + return (readb(&port->lsr) & UART_LSR_DR) != 0; +} + +static int uniphier_serial_getc(struct uniphier_serial *port) +{ + while (!uniphier_serial_tstc(port)) + ; + + return readb(&port->rbr); +} + +static void uniphier_serial_putc(struct uniphier_serial *port, const char c) +{ + if (c == '\n') + uniphier_serial_putc(port, '\r'); + + while (!(readb(&port->lsr) & UART_LSR_THRE)) + ; + + writeb(c, &port->thr); +} + +static struct uniphier_serial *serial_ports[4] = { +#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE0 + (struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE0, +#else + NULL, +#endif +#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE1 + (struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE1, +#else + NULL, +#endif +#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE2 + (struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE2, +#else + NULL, +#endif +#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE3 + (struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE3, +#else + NULL, +#endif +}; + +/* Multi serial device functions */ +#define DECLARE_ESERIAL_FUNCTIONS(port) \ + static int eserial##port##_init(void) \ + { \ + uniphier_serial_init(serial_ports[port]); \ + return 0 ; \ + } \ + static void eserial##port##_setbrg(void) \ + { \ + uniphier_serial_setbrg(serial_ports[port]); \ + } \ + static int eserial##port##_getc(void) \ + { \ + return uniphier_serial_getc(serial_ports[port]); \ + } \ + static int eserial##port##_tstc(void) \ + { \ + return uniphier_serial_tstc(serial_ports[port]); \ + } \ + static void eserial##port##_putc(const char c) \ + { \ + uniphier_serial_putc(serial_ports[port], c); \ + } + +/* Serial device descriptor */ +#define INIT_ESERIAL_STRUCTURE(port, __name) { \ + .name = __name, \ + .start = eserial##port##_init, \ + .stop = NULL, \ + .setbrg = eserial##port##_setbrg, \ + .getc = eserial##port##_getc, \ + .tstc = eserial##port##_tstc, \ + .putc = eserial##port##_putc, \ + .puts = default_serial_puts, \ +} + +#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0) +DECLARE_ESERIAL_FUNCTIONS(0); +struct serial_device uniphier_serial0_device = + INIT_ESERIAL_STRUCTURE(0, "ttyS0"); +#endif +#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1) +DECLARE_ESERIAL_FUNCTIONS(1); +struct serial_device uniphier_serial1_device = + INIT_ESERIAL_STRUCTURE(1, "ttyS1"); +#endif +#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2) +DECLARE_ESERIAL_FUNCTIONS(2); +struct serial_device uniphier_serial2_device = + INIT_ESERIAL_STRUCTURE(2, "ttyS2"); +#endif +#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3) +DECLARE_ESERIAL_FUNCTIONS(3); +struct serial_device uniphier_serial3_device = + INIT_ESERIAL_STRUCTURE(3, "ttyS3"); +#endif + +__weak struct serial_device *default_serial_console(void) +{ +#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0) + return &uniphier_serial0_device; +#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1) + return &uniphier_serial1_device; +#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2) + return &uniphier_serial2_device; +#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3) + return &uniphier_serial3_device; +#else +#error "No uniphier serial ports configured." +#endif +} + +void uniphier_serial_initialize(void) +{ +#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0) + serial_register(&uniphier_serial0_device); +#endif +#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1) + serial_register(&uniphier_serial1_device); +#endif +#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2) + serial_register(&uniphier_serial2_device); +#endif +#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3) + serial_register(&uniphier_serial3_device); +#endif +} -- cgit v1.2.3 From 5894ca007d217a2fa845facfbb62c6512396a145 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 3 Oct 2014 19:21:06 +0900 Subject: ARM: UniPhier: add UniPhier SoC support code These are used by Panasonic UniPhier SoC family. Signed-off-by: Masahiro Yamada --- arch/arm/cpu/armv7/uniphier/Makefile | 23 + arch/arm/cpu/armv7/uniphier/board_common.c | 32 + arch/arm/cpu/armv7/uniphier/board_late_init.c | 91 ++ arch/arm/cpu/armv7/uniphier/cache_uniphier.c | 154 +++ arch/arm/cpu/armv7/uniphier/cmd_pinmon.c | 33 + arch/arm/cpu/armv7/uniphier/cpu_info.c | 59 ++ arch/arm/cpu/armv7/uniphier/dram_init.c | 37 + arch/arm/cpu/armv7/uniphier/init_page_table.c | 1068 ++++++++++++++++++++ arch/arm/cpu/armv7/uniphier/lowlevel_init.S | 159 +++ arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c | 33 + arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c | 16 + .../armv7/uniphier/ph1-ld4/board_postclk_init.c | 42 + arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c | 29 + arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c | 63 ++ arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c | 189 ++++ arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c | 44 + arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c | 28 + arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c | 162 +++ arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c | 16 + .../armv7/uniphier/ph1-pro4/board_postclk_init.c | 39 + arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c | 66 ++ arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c | 29 + arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c | 45 + arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c | 168 +++ .../arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c | 18 + arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c | 75 ++ arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c | 28 + arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c | 136 +++ arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 10 + arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c | 16 + .../armv7/uniphier/ph1-sld8/board_postclk_init.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c | 29 + arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c | 57 ++ arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c | 201 ++++ .../arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c | 51 + arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c | 142 +++ arch/arm/cpu/armv7/uniphier/reset.c | 29 + arch/arm/cpu/armv7/uniphier/smp.S | 54 + arch/arm/cpu/armv7/uniphier/spl.c | 17 + arch/arm/cpu/armv7/uniphier/support_card.c | 180 ++++ arch/arm/cpu/armv7/uniphier/timer.c | 39 + arch/arm/include/asm/arch-uniphier/arm-mpcore.h | 46 + arch/arm/include/asm/arch-uniphier/bcu-regs.h | 30 + arch/arm/include/asm/arch-uniphier/board.h | 35 + arch/arm/include/asm/arch-uniphier/boot-device.h | 20 + arch/arm/include/asm/arch-uniphier/led.h | 101 ++ arch/arm/include/asm/arch-uniphier/sbc-regs.h | 108 ++ arch/arm/include/asm/arch-uniphier/sc-regs.h | 62 ++ arch/arm/include/asm/arch-uniphier/sg-regs.h | 182 ++++ arch/arm/include/asm/arch-uniphier/ssc-regs.h | 67 ++ arch/arm/include/asm/arch-uniphier/umc-regs.h | 119 +++ include/configs/ph1_ld4.h | 59 ++ include/configs/ph1_pro4.h | 61 ++ include/configs/ph1_sld8.h | 61 ++ include/configs/uniphier-common.h | 266 +++++ 63 files changed, 4951 insertions(+) create mode 100644 arch/arm/cpu/armv7/uniphier/Makefile create mode 100644 arch/arm/cpu/armv7/uniphier/board_common.c create mode 100644 arch/arm/cpu/armv7/uniphier/board_late_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/cache_uniphier.c create mode 100644 arch/arm/cpu/armv7/uniphier/cmd_pinmon.c create mode 100644 arch/arm/cpu/armv7/uniphier/cpu_info.c create mode 100644 arch/arm/cpu/armv7/uniphier/dram_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/init_page_table.c create mode 100644 arch/arm/cpu/armv7/uniphier/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c create mode 100644 arch/arm/cpu/armv7/uniphier/reset.c create mode 100644 arch/arm/cpu/armv7/uniphier/smp.S create mode 100644 arch/arm/cpu/armv7/uniphier/spl.c create mode 100644 arch/arm/cpu/armv7/uniphier/support_card.c create mode 100644 arch/arm/cpu/armv7/uniphier/timer.c create mode 100644 arch/arm/include/asm/arch-uniphier/arm-mpcore.h create mode 100644 arch/arm/include/asm/arch-uniphier/bcu-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/board.h create mode 100644 arch/arm/include/asm/arch-uniphier/boot-device.h create mode 100644 arch/arm/include/asm/arch-uniphier/led.h create mode 100644 arch/arm/include/asm/arch-uniphier/sbc-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/sc-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/sg-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/ssc-regs.h create mode 100644 arch/arm/include/asm/arch-uniphier/umc-regs.h create mode 100644 include/configs/ph1_ld4.h create mode 100644 include/configs/ph1_pro4.h create mode 100644 include/configs/ph1_sld8.h create mode 100644 include/configs/uniphier-common.h diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile new file mode 100644 index 0000000000..7cedddaadc --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/Makefile @@ -0,0 +1,23 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_SPL_BUILD) += lowlevel_init.o init_page_table.o +obj-$(CONFIG_SPL_BUILD) += spl.o + +obj-y += timer.o +obj-y += reset.o +obj-y += cache_uniphier.o +obj-y += dram_init.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o +obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o +obj-$(CONFIG_UNIPHIER_SMP) += smp.o +obj-$(if $(CONFIG_SPL_BUILD),,y) += cmd_pinmon.o + +obj-y += board_common.o +obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o +obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o + +obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/ +obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/ +obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/ diff --git a/arch/arm/cpu/armv7/uniphier/board_common.c b/arch/arm/cpu/armv7/uniphier/board_common.c new file mode 100644 index 0000000000..3fb26c6d84 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/board_common.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + led_write(U, B, O, O); + + return 0; +} + +#if CONFIG_NR_DRAM_BANKS >= 2 +void dram_init_banksize(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE; + gd->bd->bi_dram[0].size = CONFIG_SDRAM0_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE; + gd->bd->bi_dram[1].size = CONFIG_SDRAM1_SIZE; +} +#endif diff --git a/arch/arm/cpu/armv7/uniphier/board_late_init.c b/arch/arm/cpu/armv7/uniphier/board_late_init.c new file mode 100644 index 0000000000..37300206f6 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/board_late_init.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include <../drivers/mtd/nand/denali.h> + +static void nand_denali_wp_disable(void) +{ +#ifdef CONFIG_NAND_DENALI + /* + * Since the boot rom enables the write protection for NAND boot mode, + * it must be disabled somewhere for "nand write", "nand erase", etc. + * The workaround is here to not disturb the Denali NAND controller + * driver just for a really SoC-specific thing. + */ + void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; + + writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT); +#endif +} + +static void nand_denali_fixup(void) +{ +#if defined(CONFIG_NAND_DENALI) && \ + (defined(CONFIG_MACH_PH1_SLD8) || defined(CONFIG_MACH_PH1_PRO4)) + /* + * The Denali NAND controller on some of UniPhier SoCs does not + * automatically query the device parameters. For those SoCs, + * some registers must be set after the device is probed. + */ + void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; + struct mtd_info *mtd; + struct nand_chip *chip; + + if (nand_curr_device < 0 || + nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE) { + /* NAND was not detected. Just return. */ + return; + } + + mtd = &nand_info[nand_curr_device]; + chip = mtd->priv; + + writel(mtd->erasesize / mtd->writesize, denali_reg + PAGES_PER_BLOCK); + writel(0, denali_reg + DEVICE_WIDTH); + writel(mtd->writesize, denali_reg + DEVICE_MAIN_AREA_SIZE); + writel(mtd->oobsize, denali_reg + DEVICE_SPARE_AREA_SIZE); + writel(1, denali_reg + DEVICES_CONNECTED); + + /* + * chip->scan_bbt in nand_scan_tail() has been skipped. + * It should be done in here. + */ + chip->scan_bbt(mtd); +#endif +} + +int board_late_init(void) +{ + puts("MODE: "); + + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC1: + printf("eMMC Boot\n"); + setenv("bootmode", "emmcboot"); + nand_denali_fixup(); + break; + case BOOT_DEVICE_NAND: + printf("NAND Boot\n"); + setenv("bootmode", "nandboot"); + nand_denali_wp_disable(); + break; + case BOOT_DEVICE_NOR: + printf("NOR Boot\n"); + setenv("bootmode", "norboot"); + nand_denali_fixup(); + break; + default: + printf("Unsupported Boot Mode\n"); + return -1; + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/uniphier/cache_uniphier.c b/arch/arm/cpu/armv7/uniphier/cache_uniphier.c new file mode 100644 index 0000000000..e47f977fe5 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/cache_uniphier.c @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#ifdef CONFIG_UNIPHIER_L2CACHE_ON +static void uniphier_cache_maint_all(u32 operation) +{ + /* try until the command is successfully set */ + do { + writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM); + } while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE)); + + /* wait until the operation is completed */ + while (readl(SSCOLPQS) != SSCOLPQS_EF) + ; + + /* clear the complete notification flag */ + writel(SSCOLPQS_EF, SSCOLPQS); + + writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */ + readl(SSCOPE); /* need a read back to confirm */ +} + +void v7_outer_cache_flush_all(void) +{ + uniphier_cache_maint_all(SSCOQM_CM_WB_INV); +} + +void v7_outer_cache_inval_all(void) +{ + uniphier_cache_maint_all(SSCOQM_CM_INV); +} + +static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation) +{ + /* try until the command is successfully set */ + do { + writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation, SSCOQM); + writel(start, SSCOQAD); + writel(size, SSCOQSZ); + + } while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE)); + + /* wait until the operation is completed */ + while (readl(SSCOLPQS) != SSCOLPQS_EF) + ; + + /* clear the complete notification flag */ + writel(SSCOLPQS_EF, SSCOLPQS); +} + +static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) +{ + u32 size; + + /* + * If start address is not aligned to cache-line, + * do cache operation for the first cache-line + */ + start = start & ~(SSC_LINE_SIZE - 1); + + if (start == 0 && end >= (u32)(-SSC_LINE_SIZE)) { + /* this means cache operation for all range */ + uniphier_cache_maint_all(operation); + return; + } + + /* + * If end address is not aligned to cache-line, + * do cache operation for the last cache-line + */ + size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE - 1); + + while (size) { + u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ? + SSC_RANGE_OP_MAX_SIZE : size; + __uniphier_cache_maint_range(start, chunk_size, operation); + + start += chunk_size; + size -= chunk_size; + } + + writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */ + readl(SSCOPE); /* need a read back to confirm */ +} + +void v7_outer_cache_flush_range(u32 start, u32 end) +{ + uniphier_cache_maint_range(start, end, SSCOQM_CM_WB_INV); +} + +void v7_outer_cache_inval_range(u32 start, u32 end) +{ + uniphier_cache_maint_range(start, end, SSCOQM_CM_INV); +} + +void v7_outer_cache_enable(void) +{ + u32 tmp; + tmp = readl(SSCC); + tmp |= SSCC_ON; + writel(tmp, SSCC); +} +#endif + +void v7_outer_cache_disable(void) +{ + u32 tmp; + tmp = readl(SSCC); + tmp &= ~SSCC_ON; + writel(tmp, SSCC); +} + +void wakeup_secondary(void); + +void enable_caches(void) +{ + uint32_t reg; + +#ifdef CONFIG_UNIPHIER_SMP + /* + * The secondary CPU must move to DDR, + * before L2 disable. + * On SPL, the Page Table is located on the L2. + */ + wakeup_secondary(); +#endif + /* + * UniPhier SoCs must use L2 cache for init stack pointer. + * We disable L2 and L1 in this order. + * If CONFIG_SYS_DCACHE_OFF is not defined, + * caches are enabled again with a new page table. + */ + + /* L2 disable */ + v7_outer_cache_disable(); + + /* L1 disable */ + reg = get_cr(); + reg &= ~(CR_C | CR_M); + set_cr(reg); + +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} diff --git a/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c b/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c new file mode 100644 index 0000000000..eef9f39840 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct boot_device_info *table; + u32 mode_sel, n = 0; + + mode_sel = get_boot_mode_sel(); + + puts("Boot Mode Pin:\n"); + + for (table = boot_device_table; strlen(table->info); table++) { + printf(" %c %02x %s\n", n == mode_sel ? '*' : ' ', n, + table->info); + n++; + } + + return 0; +} + +U_BOOT_CMD( + pinmon, 1, 1, do_pinmon, + "pin monitor", + "" +); diff --git a/arch/arm/cpu/armv7/uniphier/cpu_info.c b/arch/arm/cpu/armv7/uniphier/cpu_info.c new file mode 100644 index 0000000000..86d079ad56 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/cpu_info.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2013-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int print_cpuinfo(void) +{ + u32 revision, type, model, rev, required_model = 1, required_rev = 1; + + revision = readl(SG_REVISION); + type = (revision & SG_REVISION_TYPE_MASK) >> SG_REVISION_TYPE_SHIFT; + model = (revision & SG_REVISION_MODEL_MASK) >> SG_REVISION_MODEL_SHIFT; + rev = (revision & SG_REVISION_REV_MASK) >> SG_REVISION_REV_SHIFT; + + puts("CPU: "); + + switch (type) { + case 0x25: + puts("PH1-sLD3 (MN2WS0220)"); + required_model = 2; + break; + case 0x26: + puts("PH1-LD4 (MN2WS0250)"); + required_rev = 2; + break; + case 0x28: + puts("PH1-Pro4 (MN2WS0230)"); + break; + case 0x29: + puts("PH1-sLD8 (MN2WS0270)"); + break; + default: + printf("Unknown Processor ID (0x%x)\n", revision); + return -1; + } + + if (model > 1) + printf(" model %d", model); + + printf(" (rev. %d)\n", rev); + + if (model < required_model) { + printf("Sorry, this model is not supported.\n"); + printf("Required model is %d.", required_model); + return -1; + } else if (rev < required_rev) { + printf("Sorry, this revision is not supported.\n"); + printf("Required revision is %d.", required_rev); + return -1; + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/uniphier/dram_init.c b/arch/arm/cpu/armv7/uniphier/dram_init.c new file mode 100644 index 0000000000..5465a0e6bf --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/dram_init.c @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int umc_init(void); +void enable_dpll_ssc(void); + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + led_write(B, 4, , ); + + { + int res; + + res = umc_init(); + if (res < 0) + return res; + } + led_write(B, 5, , ); + + enable_dpll_ssc(); +#endif + + led_write(B, 6, , ); + + return 0; +} diff --git a/arch/arm/cpu/armv7/uniphier/init_page_table.c b/arch/arm/cpu/armv7/uniphier/init_page_table.c new file mode 100644 index 0000000000..d2738350a3 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/init_page_table.c @@ -0,0 +1,1068 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* encoding without TEX remap */ +#define NO_MAP 0x00000000 /* No Map */ +#define DEVICE 0x00002002 /* Non-shareable Device */ +#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */ + +#define SSC NORMAL /* System Cache: Normal */ +#define EXT DEVICE /* External Bus: Device */ +#define REG DEVICE /* IO Register: Device */ +#define DDR DEVICE /* DDR SDRAM: Device */ + +#ifdef CONFIG_SPL_BUILD +#define IS_SPL_TEXT_AREA(x) ((x) == ((CONFIG_SPL_TEXT_BASE) >> 20)) +#else +#define IS_SPL_TEXT_AREA(x) ((x) == ((CONFIG_SYS_TEXT_BASE) >> 20)) +#endif + +#define IS_INIT_STACK_AREA(x) ((x) == ((CONFIG_SYS_INIT_SP_ADDR) >> 20)) + +#define IS_SSC(x) ((IS_SPL_TEXT_AREA(x)) || \ + (IS_INIT_STACK_AREA(x))) +#define IS_EXT(x) ((x) < 0x100) +#define IS_REG(x) (0x500 <= (x) && (x) < 0x700) +#define IS_DDR(x) (0x800 <= (x) && (x) < 0xf00) + +#define MMU_FLAGS(x) (IS_SSC(x)) ? SSC : \ + (IS_EXT(x)) ? EXT : \ + (IS_REG(x)) ? REG : \ + (IS_DDR(x)) ? DDR : \ + NO_MAP + +#define TBL_ENTRY(x) (((x) << 20) | (MMU_FLAGS(x))) + +const u32 __aligned(PGTABLE_SIZE) init_page_table[PGTABLE_SIZE / sizeof(u32)] + = { + TBL_ENTRY(0x000), TBL_ENTRY(0x001), TBL_ENTRY(0x002), TBL_ENTRY(0x003), + TBL_ENTRY(0x004), TBL_ENTRY(0x005), TBL_ENTRY(0x006), TBL_ENTRY(0x007), + TBL_ENTRY(0x008), TBL_ENTRY(0x009), TBL_ENTRY(0x00a), TBL_ENTRY(0x00b), + TBL_ENTRY(0x00c), TBL_ENTRY(0x00d), TBL_ENTRY(0x00e), TBL_ENTRY(0x00f), + TBL_ENTRY(0x010), TBL_ENTRY(0x011), TBL_ENTRY(0x012), TBL_ENTRY(0x013), + TBL_ENTRY(0x014), TBL_ENTRY(0x015), TBL_ENTRY(0x016), TBL_ENTRY(0x017), + TBL_ENTRY(0x018), TBL_ENTRY(0x019), TBL_ENTRY(0x01a), TBL_ENTRY(0x01b), + TBL_ENTRY(0x01c), TBL_ENTRY(0x01d), TBL_ENTRY(0x01e), TBL_ENTRY(0x01f), + TBL_ENTRY(0x020), TBL_ENTRY(0x021), TBL_ENTRY(0x022), TBL_ENTRY(0x023), + TBL_ENTRY(0x024), TBL_ENTRY(0x025), TBL_ENTRY(0x026), TBL_ENTRY(0x027), + TBL_ENTRY(0x028), TBL_ENTRY(0x029), TBL_ENTRY(0x02a), TBL_ENTRY(0x02b), + TBL_ENTRY(0x02c), TBL_ENTRY(0x02d), TBL_ENTRY(0x02e), TBL_ENTRY(0x02f), + TBL_ENTRY(0x030), TBL_ENTRY(0x031), TBL_ENTRY(0x032), TBL_ENTRY(0x033), + TBL_ENTRY(0x034), TBL_ENTRY(0x035), TBL_ENTRY(0x036), TBL_ENTRY(0x037), + TBL_ENTRY(0x038), TBL_ENTRY(0x039), TBL_ENTRY(0x03a), TBL_ENTRY(0x03b), + TBL_ENTRY(0x03c), TBL_ENTRY(0x03d), TBL_ENTRY(0x03e), TBL_ENTRY(0x03f), + TBL_ENTRY(0x040), TBL_ENTRY(0x041), TBL_ENTRY(0x042), TBL_ENTRY(0x043), + TBL_ENTRY(0x044), TBL_ENTRY(0x045), TBL_ENTRY(0x046), TBL_ENTRY(0x047), + TBL_ENTRY(0x048), TBL_ENTRY(0x049), TBL_ENTRY(0x04a), TBL_ENTRY(0x04b), + TBL_ENTRY(0x04c), TBL_ENTRY(0x04d), TBL_ENTRY(0x04e), TBL_ENTRY(0x04f), + TBL_ENTRY(0x050), TBL_ENTRY(0x051), TBL_ENTRY(0x052), TBL_ENTRY(0x053), + TBL_ENTRY(0x054), TBL_ENTRY(0x055), TBL_ENTRY(0x056), TBL_ENTRY(0x057), + TBL_ENTRY(0x058), TBL_ENTRY(0x059), TBL_ENTRY(0x05a), TBL_ENTRY(0x05b), + TBL_ENTRY(0x05c), TBL_ENTRY(0x05d), TBL_ENTRY(0x05e), TBL_ENTRY(0x05f), + TBL_ENTRY(0x060), TBL_ENTRY(0x061), TBL_ENTRY(0x062), TBL_ENTRY(0x063), + TBL_ENTRY(0x064), TBL_ENTRY(0x065), TBL_ENTRY(0x066), TBL_ENTRY(0x067), + TBL_ENTRY(0x068), TBL_ENTRY(0x069), TBL_ENTRY(0x06a), TBL_ENTRY(0x06b), + TBL_ENTRY(0x06c), TBL_ENTRY(0x06d), TBL_ENTRY(0x06e), TBL_ENTRY(0x06f), + TBL_ENTRY(0x070), TBL_ENTRY(0x071), TBL_ENTRY(0x072), TBL_ENTRY(0x073), + TBL_ENTRY(0x074), TBL_ENTRY(0x075), TBL_ENTRY(0x076), TBL_ENTRY(0x077), + TBL_ENTRY(0x078), TBL_ENTRY(0x079), TBL_ENTRY(0x07a), TBL_ENTRY(0x07b), + TBL_ENTRY(0x07c), TBL_ENTRY(0x07d), TBL_ENTRY(0x07e), TBL_ENTRY(0x07f), + TBL_ENTRY(0x080), TBL_ENTRY(0x081), TBL_ENTRY(0x082), TBL_ENTRY(0x083), + TBL_ENTRY(0x084), TBL_ENTRY(0x085), TBL_ENTRY(0x086), TBL_ENTRY(0x087), + TBL_ENTRY(0x088), TBL_ENTRY(0x089), TBL_ENTRY(0x08a), TBL_ENTRY(0x08b), + TBL_ENTRY(0x08c), TBL_ENTRY(0x08d), TBL_ENTRY(0x08e), TBL_ENTRY(0x08f), + TBL_ENTRY(0x090), TBL_ENTRY(0x091), TBL_ENTRY(0x092), TBL_ENTRY(0x093), + TBL_ENTRY(0x094), TBL_ENTRY(0x095), TBL_ENTRY(0x096), TBL_ENTRY(0x097), + TBL_ENTRY(0x098), TBL_ENTRY(0x099), TBL_ENTRY(0x09a), TBL_ENTRY(0x09b), + TBL_ENTRY(0x09c), TBL_ENTRY(0x09d), TBL_ENTRY(0x09e), TBL_ENTRY(0x09f), + TBL_ENTRY(0x0a0), TBL_ENTRY(0x0a1), TBL_ENTRY(0x0a2), TBL_ENTRY(0x0a3), + TBL_ENTRY(0x0a4), TBL_ENTRY(0x0a5), TBL_ENTRY(0x0a6), TBL_ENTRY(0x0a7), + TBL_ENTRY(0x0a8), TBL_ENTRY(0x0a9), TBL_ENTRY(0x0aa), TBL_ENTRY(0x0ab), + TBL_ENTRY(0x0ac), TBL_ENTRY(0x0ad), TBL_ENTRY(0x0ae), TBL_ENTRY(0x0af), + TBL_ENTRY(0x0b0), TBL_ENTRY(0x0b1), TBL_ENTRY(0x0b2), TBL_ENTRY(0x0b3), + TBL_ENTRY(0x0b4), TBL_ENTRY(0x0b5), TBL_ENTRY(0x0b6), TBL_ENTRY(0x0b7), + TBL_ENTRY(0x0b8), TBL_ENTRY(0x0b9), TBL_ENTRY(0x0ba), TBL_ENTRY(0x0bb), + TBL_ENTRY(0x0bc), TBL_ENTRY(0x0bd), TBL_ENTRY(0x0be), TBL_ENTRY(0x0bf), + TBL_ENTRY(0x0c0), TBL_ENTRY(0x0c1), TBL_ENTRY(0x0c2), TBL_ENTRY(0x0c3), + TBL_ENTRY(0x0c4), TBL_ENTRY(0x0c5), TBL_ENTRY(0x0c6), TBL_ENTRY(0x0c7), + TBL_ENTRY(0x0c8), TBL_ENTRY(0x0c9), TBL_ENTRY(0x0ca), TBL_ENTRY(0x0cb), + TBL_ENTRY(0x0cc), TBL_ENTRY(0x0cd), TBL_ENTRY(0x0ce), TBL_ENTRY(0x0cf), + TBL_ENTRY(0x0d0), TBL_ENTRY(0x0d1), TBL_ENTRY(0x0d2), TBL_ENTRY(0x0d3), + TBL_ENTRY(0x0d4), TBL_ENTRY(0x0d5), TBL_ENTRY(0x0d6), TBL_ENTRY(0x0d7), + TBL_ENTRY(0x0d8), TBL_ENTRY(0x0d9), TBL_ENTRY(0x0da), TBL_ENTRY(0x0db), + TBL_ENTRY(0x0dc), TBL_ENTRY(0x0dd), TBL_ENTRY(0x0de), TBL_ENTRY(0x0df), + TBL_ENTRY(0x0e0), TBL_ENTRY(0x0e1), TBL_ENTRY(0x0e2), TBL_ENTRY(0x0e3), + TBL_ENTRY(0x0e4), TBL_ENTRY(0x0e5), TBL_ENTRY(0x0e6), TBL_ENTRY(0x0e7), + TBL_ENTRY(0x0e8), TBL_ENTRY(0x0e9), TBL_ENTRY(0x0ea), TBL_ENTRY(0x0eb), + TBL_ENTRY(0x0ec), TBL_ENTRY(0x0ed), TBL_ENTRY(0x0ee), TBL_ENTRY(0x0ef), + TBL_ENTRY(0x0f0), TBL_ENTRY(0x0f1), TBL_ENTRY(0x0f2), TBL_ENTRY(0x0f3), + TBL_ENTRY(0x0f4), TBL_ENTRY(0x0f5), TBL_ENTRY(0x0f6), TBL_ENTRY(0x0f7), + TBL_ENTRY(0x0f8), TBL_ENTRY(0x0f9), TBL_ENTRY(0x0fa), TBL_ENTRY(0x0fb), + TBL_ENTRY(0x0fc), TBL_ENTRY(0x0fd), TBL_ENTRY(0x0fe), TBL_ENTRY(0x0ff), + TBL_ENTRY(0x100), TBL_ENTRY(0x101), TBL_ENTRY(0x102), TBL_ENTRY(0x103), + TBL_ENTRY(0x104), TBL_ENTRY(0x105), TBL_ENTRY(0x106), TBL_ENTRY(0x107), + TBL_ENTRY(0x108), TBL_ENTRY(0x109), TBL_ENTRY(0x10a), TBL_ENTRY(0x10b), + TBL_ENTRY(0x10c), TBL_ENTRY(0x10d), TBL_ENTRY(0x10e), TBL_ENTRY(0x10f), + TBL_ENTRY(0x110), TBL_ENTRY(0x111), TBL_ENTRY(0x112), TBL_ENTRY(0x113), + TBL_ENTRY(0x114), TBL_ENTRY(0x115), TBL_ENTRY(0x116), TBL_ENTRY(0x117), + TBL_ENTRY(0x118), TBL_ENTRY(0x119), TBL_ENTRY(0x11a), TBL_ENTRY(0x11b), + TBL_ENTRY(0x11c), TBL_ENTRY(0x11d), TBL_ENTRY(0x11e), TBL_ENTRY(0x11f), + TBL_ENTRY(0x120), TBL_ENTRY(0x121), TBL_ENTRY(0x122), TBL_ENTRY(0x123), + TBL_ENTRY(0x124), TBL_ENTRY(0x125), TBL_ENTRY(0x126), TBL_ENTRY(0x127), + TBL_ENTRY(0x128), TBL_ENTRY(0x129), TBL_ENTRY(0x12a), TBL_ENTRY(0x12b), + TBL_ENTRY(0x12c), TBL_ENTRY(0x12d), TBL_ENTRY(0x12e), TBL_ENTRY(0x12f), + TBL_ENTRY(0x130), TBL_ENTRY(0x131), TBL_ENTRY(0x132), TBL_ENTRY(0x133), + TBL_ENTRY(0x134), TBL_ENTRY(0x135), TBL_ENTRY(0x136), TBL_ENTRY(0x137), + TBL_ENTRY(0x138), TBL_ENTRY(0x139), TBL_ENTRY(0x13a), TBL_ENTRY(0x13b), + TBL_ENTRY(0x13c), TBL_ENTRY(0x13d), TBL_ENTRY(0x13e), TBL_ENTRY(0x13f), + TBL_ENTRY(0x140), TBL_ENTRY(0x141), TBL_ENTRY(0x142), TBL_ENTRY(0x143), + TBL_ENTRY(0x144), TBL_ENTRY(0x145), TBL_ENTRY(0x146), TBL_ENTRY(0x147), + TBL_ENTRY(0x148), TBL_ENTRY(0x149), TBL_ENTRY(0x14a), TBL_ENTRY(0x14b), + TBL_ENTRY(0x14c), TBL_ENTRY(0x14d), TBL_ENTRY(0x14e), TBL_ENTRY(0x14f), + TBL_ENTRY(0x150), TBL_ENTRY(0x151), TBL_ENTRY(0x152), TBL_ENTRY(0x153), + TBL_ENTRY(0x154), TBL_ENTRY(0x155), TBL_ENTRY(0x156), TBL_ENTRY(0x157), + TBL_ENTRY(0x158), TBL_ENTRY(0x159), TBL_ENTRY(0x15a), TBL_ENTRY(0x15b), + TBL_ENTRY(0x15c), TBL_ENTRY(0x15d), TBL_ENTRY(0x15e), TBL_ENTRY(0x15f), + TBL_ENTRY(0x160), TBL_ENTRY(0x161), TBL_ENTRY(0x162), TBL_ENTRY(0x163), + TBL_ENTRY(0x164), TBL_ENTRY(0x165), TBL_ENTRY(0x166), TBL_ENTRY(0x167), + TBL_ENTRY(0x168), TBL_ENTRY(0x169), TBL_ENTRY(0x16a), TBL_ENTRY(0x16b), + TBL_ENTRY(0x16c), TBL_ENTRY(0x16d), TBL_ENTRY(0x16e), TBL_ENTRY(0x16f), + TBL_ENTRY(0x170), TBL_ENTRY(0x171), TBL_ENTRY(0x172), TBL_ENTRY(0x173), + TBL_ENTRY(0x174), TBL_ENTRY(0x175), TBL_ENTRY(0x176), TBL_ENTRY(0x177), + TBL_ENTRY(0x178), TBL_ENTRY(0x179), TBL_ENTRY(0x17a), TBL_ENTRY(0x17b), + TBL_ENTRY(0x17c), TBL_ENTRY(0x17d), TBL_ENTRY(0x17e), TBL_ENTRY(0x17f), + TBL_ENTRY(0x180), TBL_ENTRY(0x181), TBL_ENTRY(0x182), TBL_ENTRY(0x183), + TBL_ENTRY(0x184), TBL_ENTRY(0x185), TBL_ENTRY(0x186), TBL_ENTRY(0x187), + TBL_ENTRY(0x188), TBL_ENTRY(0x189), TBL_ENTRY(0x18a), TBL_ENTRY(0x18b), + TBL_ENTRY(0x18c), TBL_ENTRY(0x18d), TBL_ENTRY(0x18e), TBL_ENTRY(0x18f), + TBL_ENTRY(0x190), TBL_ENTRY(0x191), TBL_ENTRY(0x192), TBL_ENTRY(0x193), + TBL_ENTRY(0x194), TBL_ENTRY(0x195), TBL_ENTRY(0x196), TBL_ENTRY(0x197), + TBL_ENTRY(0x198), TBL_ENTRY(0x199), TBL_ENTRY(0x19a), TBL_ENTRY(0x19b), + TBL_ENTRY(0x19c), TBL_ENTRY(0x19d), TBL_ENTRY(0x19e), TBL_ENTRY(0x19f), + TBL_ENTRY(0x1a0), TBL_ENTRY(0x1a1), TBL_ENTRY(0x1a2), TBL_ENTRY(0x1a3), + TBL_ENTRY(0x1a4), TBL_ENTRY(0x1a5), TBL_ENTRY(0x1a6), TBL_ENTRY(0x1a7), + TBL_ENTRY(0x1a8), TBL_ENTRY(0x1a9), TBL_ENTRY(0x1aa), TBL_ENTRY(0x1ab), + TBL_ENTRY(0x1ac), TBL_ENTRY(0x1ad), TBL_ENTRY(0x1ae), TBL_ENTRY(0x1af), + TBL_ENTRY(0x1b0), TBL_ENTRY(0x1b1), TBL_ENTRY(0x1b2), TBL_ENTRY(0x1b3), + TBL_ENTRY(0x1b4), TBL_ENTRY(0x1b5), TBL_ENTRY(0x1b6), TBL_ENTRY(0x1b7), + TBL_ENTRY(0x1b8), TBL_ENTRY(0x1b9), TBL_ENTRY(0x1ba), TBL_ENTRY(0x1bb), + TBL_ENTRY(0x1bc), TBL_ENTRY(0x1bd), TBL_ENTRY(0x1be), TBL_ENTRY(0x1bf), + TBL_ENTRY(0x1c0), TBL_ENTRY(0x1c1), TBL_ENTRY(0x1c2), TBL_ENTRY(0x1c3), + TBL_ENTRY(0x1c4), TBL_ENTRY(0x1c5), TBL_ENTRY(0x1c6), TBL_ENTRY(0x1c7), + TBL_ENTRY(0x1c8), TBL_ENTRY(0x1c9), TBL_ENTRY(0x1ca), TBL_ENTRY(0x1cb), + TBL_ENTRY(0x1cc), TBL_ENTRY(0x1cd), TBL_ENTRY(0x1ce), TBL_ENTRY(0x1cf), + TBL_ENTRY(0x1d0), TBL_ENTRY(0x1d1), TBL_ENTRY(0x1d2), TBL_ENTRY(0x1d3), + TBL_ENTRY(0x1d4), TBL_ENTRY(0x1d5), TBL_ENTRY(0x1d6), TBL_ENTRY(0x1d7), + TBL_ENTRY(0x1d8), TBL_ENTRY(0x1d9), TBL_ENTRY(0x1da), TBL_ENTRY(0x1db), + TBL_ENTRY(0x1dc), TBL_ENTRY(0x1dd), TBL_ENTRY(0x1de), TBL_ENTRY(0x1df), + TBL_ENTRY(0x1e0), TBL_ENTRY(0x1e1), TBL_ENTRY(0x1e2), TBL_ENTRY(0x1e3), + TBL_ENTRY(0x1e4), TBL_ENTRY(0x1e5), TBL_ENTRY(0x1e6), TBL_ENTRY(0x1e7), + TBL_ENTRY(0x1e8), TBL_ENTRY(0x1e9), TBL_ENTRY(0x1ea), TBL_ENTRY(0x1eb), + TBL_ENTRY(0x1ec), TBL_ENTRY(0x1ed), TBL_ENTRY(0x1ee), TBL_ENTRY(0x1ef), + TBL_ENTRY(0x1f0), TBL_ENTRY(0x1f1), TBL_ENTRY(0x1f2), TBL_ENTRY(0x1f3), + TBL_ENTRY(0x1f4), TBL_ENTRY(0x1f5), TBL_ENTRY(0x1f6), TBL_ENTRY(0x1f7), + TBL_ENTRY(0x1f8), TBL_ENTRY(0x1f9), TBL_ENTRY(0x1fa), TBL_ENTRY(0x1fb), + TBL_ENTRY(0x1fc), TBL_ENTRY(0x1fd), TBL_ENTRY(0x1fe), TBL_ENTRY(0x1ff), + TBL_ENTRY(0x200), TBL_ENTRY(0x201), TBL_ENTRY(0x202), TBL_ENTRY(0x203), + TBL_ENTRY(0x204), TBL_ENTRY(0x205), TBL_ENTRY(0x206), TBL_ENTRY(0x207), + TBL_ENTRY(0x208), TBL_ENTRY(0x209), TBL_ENTRY(0x20a), TBL_ENTRY(0x20b), + TBL_ENTRY(0x20c), TBL_ENTRY(0x20d), TBL_ENTRY(0x20e), TBL_ENTRY(0x20f), + TBL_ENTRY(0x210), TBL_ENTRY(0x211), TBL_ENTRY(0x212), TBL_ENTRY(0x213), + TBL_ENTRY(0x214), TBL_ENTRY(0x215), TBL_ENTRY(0x216), TBL_ENTRY(0x217), + TBL_ENTRY(0x218), TBL_ENTRY(0x219), TBL_ENTRY(0x21a), TBL_ENTRY(0x21b), + TBL_ENTRY(0x21c), TBL_ENTRY(0x21d), TBL_ENTRY(0x21e), TBL_ENTRY(0x21f), + TBL_ENTRY(0x220), TBL_ENTRY(0x221), TBL_ENTRY(0x222), TBL_ENTRY(0x223), + TBL_ENTRY(0x224), TBL_ENTRY(0x225), TBL_ENTRY(0x226), TBL_ENTRY(0x227), + TBL_ENTRY(0x228), TBL_ENTRY(0x229), TBL_ENTRY(0x22a), TBL_ENTRY(0x22b), + TBL_ENTRY(0x22c), TBL_ENTRY(0x22d), TBL_ENTRY(0x22e), TBL_ENTRY(0x22f), + TBL_ENTRY(0x230), TBL_ENTRY(0x231), TBL_ENTRY(0x232), TBL_ENTRY(0x233), + TBL_ENTRY(0x234), TBL_ENTRY(0x235), TBL_ENTRY(0x236), TBL_ENTRY(0x237), + TBL_ENTRY(0x238), TBL_ENTRY(0x239), TBL_ENTRY(0x23a), TBL_ENTRY(0x23b), + TBL_ENTRY(0x23c), TBL_ENTRY(0x23d), TBL_ENTRY(0x23e), TBL_ENTRY(0x23f), + TBL_ENTRY(0x240), TBL_ENTRY(0x241), TBL_ENTRY(0x242), TBL_ENTRY(0x243), + TBL_ENTRY(0x244), TBL_ENTRY(0x245), TBL_ENTRY(0x246), TBL_ENTRY(0x247), + TBL_ENTRY(0x248), TBL_ENTRY(0x249), TBL_ENTRY(0x24a), TBL_ENTRY(0x24b), + TBL_ENTRY(0x24c), TBL_ENTRY(0x24d), TBL_ENTRY(0x24e), TBL_ENTRY(0x24f), + TBL_ENTRY(0x250), TBL_ENTRY(0x251), TBL_ENTRY(0x252), TBL_ENTRY(0x253), + TBL_ENTRY(0x254), TBL_ENTRY(0x255), TBL_ENTRY(0x256), TBL_ENTRY(0x257), + TBL_ENTRY(0x258), TBL_ENTRY(0x259), TBL_ENTRY(0x25a), TBL_ENTRY(0x25b), + TBL_ENTRY(0x25c), TBL_ENTRY(0x25d), TBL_ENTRY(0x25e), TBL_ENTRY(0x25f), + TBL_ENTRY(0x260), TBL_ENTRY(0x261), TBL_ENTRY(0x262), TBL_ENTRY(0x263), + TBL_ENTRY(0x264), TBL_ENTRY(0x265), TBL_ENTRY(0x266), TBL_ENTRY(0x267), + TBL_ENTRY(0x268), TBL_ENTRY(0x269), TBL_ENTRY(0x26a), TBL_ENTRY(0x26b), + TBL_ENTRY(0x26c), TBL_ENTRY(0x26d), TBL_ENTRY(0x26e), TBL_ENTRY(0x26f), + TBL_ENTRY(0x270), TBL_ENTRY(0x271), TBL_ENTRY(0x272), TBL_ENTRY(0x273), + TBL_ENTRY(0x274), TBL_ENTRY(0x275), TBL_ENTRY(0x276), TBL_ENTRY(0x277), + TBL_ENTRY(0x278), TBL_ENTRY(0x279), TBL_ENTRY(0x27a), TBL_ENTRY(0x27b), + TBL_ENTRY(0x27c), TBL_ENTRY(0x27d), TBL_ENTRY(0x27e), TBL_ENTRY(0x27f), + TBL_ENTRY(0x280), TBL_ENTRY(0x281), TBL_ENTRY(0x282), TBL_ENTRY(0x283), + TBL_ENTRY(0x284), TBL_ENTRY(0x285), TBL_ENTRY(0x286), TBL_ENTRY(0x287), + TBL_ENTRY(0x288), TBL_ENTRY(0x289), TBL_ENTRY(0x28a), TBL_ENTRY(0x28b), + TBL_ENTRY(0x28c), TBL_ENTRY(0x28d), TBL_ENTRY(0x28e), TBL_ENTRY(0x28f), + TBL_ENTRY(0x290), TBL_ENTRY(0x291), TBL_ENTRY(0x292), TBL_ENTRY(0x293), + TBL_ENTRY(0x294), TBL_ENTRY(0x295), TBL_ENTRY(0x296), TBL_ENTRY(0x297), + TBL_ENTRY(0x298), TBL_ENTRY(0x299), TBL_ENTRY(0x29a), TBL_ENTRY(0x29b), + TBL_ENTRY(0x29c), TBL_ENTRY(0x29d), TBL_ENTRY(0x29e), TBL_ENTRY(0x29f), + TBL_ENTRY(0x2a0), TBL_ENTRY(0x2a1), TBL_ENTRY(0x2a2), TBL_ENTRY(0x2a3), + TBL_ENTRY(0x2a4), TBL_ENTRY(0x2a5), TBL_ENTRY(0x2a6), TBL_ENTRY(0x2a7), + TBL_ENTRY(0x2a8), TBL_ENTRY(0x2a9), TBL_ENTRY(0x2aa), TBL_ENTRY(0x2ab), + TBL_ENTRY(0x2ac), TBL_ENTRY(0x2ad), TBL_ENTRY(0x2ae), TBL_ENTRY(0x2af), + TBL_ENTRY(0x2b0), TBL_ENTRY(0x2b1), TBL_ENTRY(0x2b2), TBL_ENTRY(0x2b3), + TBL_ENTRY(0x2b4), TBL_ENTRY(0x2b5), TBL_ENTRY(0x2b6), TBL_ENTRY(0x2b7), + TBL_ENTRY(0x2b8), TBL_ENTRY(0x2b9), TBL_ENTRY(0x2ba), TBL_ENTRY(0x2bb), + TBL_ENTRY(0x2bc), TBL_ENTRY(0x2bd), TBL_ENTRY(0x2be), TBL_ENTRY(0x2bf), + TBL_ENTRY(0x2c0), TBL_ENTRY(0x2c1), TBL_ENTRY(0x2c2), TBL_ENTRY(0x2c3), + TBL_ENTRY(0x2c4), TBL_ENTRY(0x2c5), TBL_ENTRY(0x2c6), TBL_ENTRY(0x2c7), + TBL_ENTRY(0x2c8), TBL_ENTRY(0x2c9), TBL_ENTRY(0x2ca), TBL_ENTRY(0x2cb), + TBL_ENTRY(0x2cc), TBL_ENTRY(0x2cd), TBL_ENTRY(0x2ce), TBL_ENTRY(0x2cf), + TBL_ENTRY(0x2d0), TBL_ENTRY(0x2d1), TBL_ENTRY(0x2d2), TBL_ENTRY(0x2d3), + TBL_ENTRY(0x2d4), TBL_ENTRY(0x2d5), TBL_ENTRY(0x2d6), TBL_ENTRY(0x2d7), + TBL_ENTRY(0x2d8), TBL_ENTRY(0x2d9), TBL_ENTRY(0x2da), TBL_ENTRY(0x2db), + TBL_ENTRY(0x2dc), TBL_ENTRY(0x2dd), TBL_ENTRY(0x2de), TBL_ENTRY(0x2df), + TBL_ENTRY(0x2e0), TBL_ENTRY(0x2e1), TBL_ENTRY(0x2e2), TBL_ENTRY(0x2e3), + TBL_ENTRY(0x2e4), TBL_ENTRY(0x2e5), TBL_ENTRY(0x2e6), TBL_ENTRY(0x2e7), + TBL_ENTRY(0x2e8), TBL_ENTRY(0x2e9), TBL_ENTRY(0x2ea), TBL_ENTRY(0x2eb), + TBL_ENTRY(0x2ec), TBL_ENTRY(0x2ed), TBL_ENTRY(0x2ee), TBL_ENTRY(0x2ef), + TBL_ENTRY(0x2f0), TBL_ENTRY(0x2f1), TBL_ENTRY(0x2f2), TBL_ENTRY(0x2f3), + TBL_ENTRY(0x2f4), TBL_ENTRY(0x2f5), TBL_ENTRY(0x2f6), TBL_ENTRY(0x2f7), + TBL_ENTRY(0x2f8), TBL_ENTRY(0x2f9), TBL_ENTRY(0x2fa), TBL_ENTRY(0x2fb), + TBL_ENTRY(0x2fc), TBL_ENTRY(0x2fd), TBL_ENTRY(0x2fe), TBL_ENTRY(0x2ff), + TBL_ENTRY(0x300), TBL_ENTRY(0x301), TBL_ENTRY(0x302), TBL_ENTRY(0x303), + TBL_ENTRY(0x304), TBL_ENTRY(0x305), TBL_ENTRY(0x306), TBL_ENTRY(0x307), + TBL_ENTRY(0x308), TBL_ENTRY(0x309), TBL_ENTRY(0x30a), TBL_ENTRY(0x30b), + TBL_ENTRY(0x30c), TBL_ENTRY(0x30d), TBL_ENTRY(0x30e), TBL_ENTRY(0x30f), + TBL_ENTRY(0x310), TBL_ENTRY(0x311), TBL_ENTRY(0x312), TBL_ENTRY(0x313), + TBL_ENTRY(0x314), TBL_ENTRY(0x315), TBL_ENTRY(0x316), TBL_ENTRY(0x317), + TBL_ENTRY(0x318), TBL_ENTRY(0x319), TBL_ENTRY(0x31a), TBL_ENTRY(0x31b), + TBL_ENTRY(0x31c), TBL_ENTRY(0x31d), TBL_ENTRY(0x31e), TBL_ENTRY(0x31f), + TBL_ENTRY(0x320), TBL_ENTRY(0x321), TBL_ENTRY(0x322), TBL_ENTRY(0x323), + TBL_ENTRY(0x324), TBL_ENTRY(0x325), TBL_ENTRY(0x326), TBL_ENTRY(0x327), + TBL_ENTRY(0x328), TBL_ENTRY(0x329), TBL_ENTRY(0x32a), TBL_ENTRY(0x32b), + TBL_ENTRY(0x32c), TBL_ENTRY(0x32d), TBL_ENTRY(0x32e), TBL_ENTRY(0x32f), + TBL_ENTRY(0x330), TBL_ENTRY(0x331), TBL_ENTRY(0x332), TBL_ENTRY(0x333), + TBL_ENTRY(0x334), TBL_ENTRY(0x335), TBL_ENTRY(0x336), TBL_ENTRY(0x337), + TBL_ENTRY(0x338), TBL_ENTRY(0x339), TBL_ENTRY(0x33a), TBL_ENTRY(0x33b), + TBL_ENTRY(0x33c), TBL_ENTRY(0x33d), TBL_ENTRY(0x33e), TBL_ENTRY(0x33f), + TBL_ENTRY(0x340), TBL_ENTRY(0x341), TBL_ENTRY(0x342), TBL_ENTRY(0x343), + TBL_ENTRY(0x344), TBL_ENTRY(0x345), TBL_ENTRY(0x346), TBL_ENTRY(0x347), + TBL_ENTRY(0x348), TBL_ENTRY(0x349), TBL_ENTRY(0x34a), TBL_ENTRY(0x34b), + TBL_ENTRY(0x34c), TBL_ENTRY(0x34d), TBL_ENTRY(0x34e), TBL_ENTRY(0x34f), + TBL_ENTRY(0x350), TBL_ENTRY(0x351), TBL_ENTRY(0x352), TBL_ENTRY(0x353), + TBL_ENTRY(0x354), TBL_ENTRY(0x355), TBL_ENTRY(0x356), TBL_ENTRY(0x357), + TBL_ENTRY(0x358), TBL_ENTRY(0x359), TBL_ENTRY(0x35a), TBL_ENTRY(0x35b), + TBL_ENTRY(0x35c), TBL_ENTRY(0x35d), TBL_ENTRY(0x35e), TBL_ENTRY(0x35f), + TBL_ENTRY(0x360), TBL_ENTRY(0x361), TBL_ENTRY(0x362), TBL_ENTRY(0x363), + TBL_ENTRY(0x364), TBL_ENTRY(0x365), TBL_ENTRY(0x366), TBL_ENTRY(0x367), + TBL_ENTRY(0x368), TBL_ENTRY(0x369), TBL_ENTRY(0x36a), TBL_ENTRY(0x36b), + TBL_ENTRY(0x36c), TBL_ENTRY(0x36d), TBL_ENTRY(0x36e), TBL_ENTRY(0x36f), + TBL_ENTRY(0x370), TBL_ENTRY(0x371), TBL_ENTRY(0x372), TBL_ENTRY(0x373), + TBL_ENTRY(0x374), TBL_ENTRY(0x375), TBL_ENTRY(0x376), TBL_ENTRY(0x377), + TBL_ENTRY(0x378), TBL_ENTRY(0x379), TBL_ENTRY(0x37a), TBL_ENTRY(0x37b), + TBL_ENTRY(0x37c), TBL_ENTRY(0x37d), TBL_ENTRY(0x37e), TBL_ENTRY(0x37f), + TBL_ENTRY(0x380), TBL_ENTRY(0x381), TBL_ENTRY(0x382), TBL_ENTRY(0x383), + TBL_ENTRY(0x384), TBL_ENTRY(0x385), TBL_ENTRY(0x386), TBL_ENTRY(0x387), + TBL_ENTRY(0x388), TBL_ENTRY(0x389), TBL_ENTRY(0x38a), TBL_ENTRY(0x38b), + TBL_ENTRY(0x38c), TBL_ENTRY(0x38d), TBL_ENTRY(0x38e), TBL_ENTRY(0x38f), + TBL_ENTRY(0x390), TBL_ENTRY(0x391), TBL_ENTRY(0x392), TBL_ENTRY(0x393), + TBL_ENTRY(0x394), TBL_ENTRY(0x395), TBL_ENTRY(0x396), TBL_ENTRY(0x397), + TBL_ENTRY(0x398), TBL_ENTRY(0x399), TBL_ENTRY(0x39a), TBL_ENTRY(0x39b), + TBL_ENTRY(0x39c), TBL_ENTRY(0x39d), TBL_ENTRY(0x39e), TBL_ENTRY(0x39f), + TBL_ENTRY(0x3a0), TBL_ENTRY(0x3a1), TBL_ENTRY(0x3a2), TBL_ENTRY(0x3a3), + TBL_ENTRY(0x3a4), TBL_ENTRY(0x3a5), TBL_ENTRY(0x3a6), TBL_ENTRY(0x3a7), + TBL_ENTRY(0x3a8), TBL_ENTRY(0x3a9), TBL_ENTRY(0x3aa), TBL_ENTRY(0x3ab), + TBL_ENTRY(0x3ac), TBL_ENTRY(0x3ad), TBL_ENTRY(0x3ae), TBL_ENTRY(0x3af), + TBL_ENTRY(0x3b0), TBL_ENTRY(0x3b1), TBL_ENTRY(0x3b2), TBL_ENTRY(0x3b3), + TBL_ENTRY(0x3b4), TBL_ENTRY(0x3b5), TBL_ENTRY(0x3b6), TBL_ENTRY(0x3b7), + TBL_ENTRY(0x3b8), TBL_ENTRY(0x3b9), TBL_ENTRY(0x3ba), TBL_ENTRY(0x3bb), + TBL_ENTRY(0x3bc), TBL_ENTRY(0x3bd), TBL_ENTRY(0x3be), TBL_ENTRY(0x3bf), + TBL_ENTRY(0x3c0), TBL_ENTRY(0x3c1), TBL_ENTRY(0x3c2), TBL_ENTRY(0x3c3), + TBL_ENTRY(0x3c4), TBL_ENTRY(0x3c5), TBL_ENTRY(0x3c6), TBL_ENTRY(0x3c7), + TBL_ENTRY(0x3c8), TBL_ENTRY(0x3c9), TBL_ENTRY(0x3ca), TBL_ENTRY(0x3cb), + TBL_ENTRY(0x3cc), TBL_ENTRY(0x3cd), TBL_ENTRY(0x3ce), TBL_ENTRY(0x3cf), + TBL_ENTRY(0x3d0), TBL_ENTRY(0x3d1), TBL_ENTRY(0x3d2), TBL_ENTRY(0x3d3), + TBL_ENTRY(0x3d4), TBL_ENTRY(0x3d5), TBL_ENTRY(0x3d6), TBL_ENTRY(0x3d7), + TBL_ENTRY(0x3d8), TBL_ENTRY(0x3d9), TBL_ENTRY(0x3da), TBL_ENTRY(0x3db), + TBL_ENTRY(0x3dc), TBL_ENTRY(0x3dd), TBL_ENTRY(0x3de), TBL_ENTRY(0x3df), + TBL_ENTRY(0x3e0), TBL_ENTRY(0x3e1), TBL_ENTRY(0x3e2), TBL_ENTRY(0x3e3), + TBL_ENTRY(0x3e4), TBL_ENTRY(0x3e5), TBL_ENTRY(0x3e6), TBL_ENTRY(0x3e7), + TBL_ENTRY(0x3e8), TBL_ENTRY(0x3e9), TBL_ENTRY(0x3ea), TBL_ENTRY(0x3eb), + TBL_ENTRY(0x3ec), TBL_ENTRY(0x3ed), TBL_ENTRY(0x3ee), TBL_ENTRY(0x3ef), + TBL_ENTRY(0x3f0), TBL_ENTRY(0x3f1), TBL_ENTRY(0x3f2), TBL_ENTRY(0x3f3), + TBL_ENTRY(0x3f4), TBL_ENTRY(0x3f5), TBL_ENTRY(0x3f6), TBL_ENTRY(0x3f7), + TBL_ENTRY(0x3f8), TBL_ENTRY(0x3f9), TBL_ENTRY(0x3fa), TBL_ENTRY(0x3fb), + TBL_ENTRY(0x3fc), TBL_ENTRY(0x3fd), TBL_ENTRY(0x3fe), TBL_ENTRY(0x3ff), + TBL_ENTRY(0x400), TBL_ENTRY(0x401), TBL_ENTRY(0x402), TBL_ENTRY(0x403), + TBL_ENTRY(0x404), TBL_ENTRY(0x405), TBL_ENTRY(0x406), TBL_ENTRY(0x407), + TBL_ENTRY(0x408), TBL_ENTRY(0x409), TBL_ENTRY(0x40a), TBL_ENTRY(0x40b), + TBL_ENTRY(0x40c), TBL_ENTRY(0x40d), TBL_ENTRY(0x40e), TBL_ENTRY(0x40f), + TBL_ENTRY(0x410), TBL_ENTRY(0x411), TBL_ENTRY(0x412), TBL_ENTRY(0x413), + TBL_ENTRY(0x414), TBL_ENTRY(0x415), TBL_ENTRY(0x416), TBL_ENTRY(0x417), + TBL_ENTRY(0x418), TBL_ENTRY(0x419), TBL_ENTRY(0x41a), TBL_ENTRY(0x41b), + TBL_ENTRY(0x41c), TBL_ENTRY(0x41d), TBL_ENTRY(0x41e), TBL_ENTRY(0x41f), + TBL_ENTRY(0x420), TBL_ENTRY(0x421), TBL_ENTRY(0x422), TBL_ENTRY(0x423), + TBL_ENTRY(0x424), TBL_ENTRY(0x425), TBL_ENTRY(0x426), TBL_ENTRY(0x427), + TBL_ENTRY(0x428), TBL_ENTRY(0x429), TBL_ENTRY(0x42a), TBL_ENTRY(0x42b), + TBL_ENTRY(0x42c), TBL_ENTRY(0x42d), TBL_ENTRY(0x42e), TBL_ENTRY(0x42f), + TBL_ENTRY(0x430), TBL_ENTRY(0x431), TBL_ENTRY(0x432), TBL_ENTRY(0x433), + TBL_ENTRY(0x434), TBL_ENTRY(0x435), TBL_ENTRY(0x436), TBL_ENTRY(0x437), + TBL_ENTRY(0x438), TBL_ENTRY(0x439), TBL_ENTRY(0x43a), TBL_ENTRY(0x43b), + TBL_ENTRY(0x43c), TBL_ENTRY(0x43d), TBL_ENTRY(0x43e), TBL_ENTRY(0x43f), + TBL_ENTRY(0x440), TBL_ENTRY(0x441), TBL_ENTRY(0x442), TBL_ENTRY(0x443), + TBL_ENTRY(0x444), TBL_ENTRY(0x445), TBL_ENTRY(0x446), TBL_ENTRY(0x447), + TBL_ENTRY(0x448), TBL_ENTRY(0x449), TBL_ENTRY(0x44a), TBL_ENTRY(0x44b), + TBL_ENTRY(0x44c), TBL_ENTRY(0x44d), TBL_ENTRY(0x44e), TBL_ENTRY(0x44f), + TBL_ENTRY(0x450), TBL_ENTRY(0x451), TBL_ENTRY(0x452), TBL_ENTRY(0x453), + TBL_ENTRY(0x454), TBL_ENTRY(0x455), TBL_ENTRY(0x456), TBL_ENTRY(0x457), + TBL_ENTRY(0x458), TBL_ENTRY(0x459), TBL_ENTRY(0x45a), TBL_ENTRY(0x45b), + TBL_ENTRY(0x45c), TBL_ENTRY(0x45d), TBL_ENTRY(0x45e), TBL_ENTRY(0x45f), + TBL_ENTRY(0x460), TBL_ENTRY(0x461), TBL_ENTRY(0x462), TBL_ENTRY(0x463), + TBL_ENTRY(0x464), TBL_ENTRY(0x465), TBL_ENTRY(0x466), TBL_ENTRY(0x467), + TBL_ENTRY(0x468), TBL_ENTRY(0x469), TBL_ENTRY(0x46a), TBL_ENTRY(0x46b), + TBL_ENTRY(0x46c), TBL_ENTRY(0x46d), TBL_ENTRY(0x46e), TBL_ENTRY(0x46f), + TBL_ENTRY(0x470), TBL_ENTRY(0x471), TBL_ENTRY(0x472), TBL_ENTRY(0x473), + TBL_ENTRY(0x474), TBL_ENTRY(0x475), TBL_ENTRY(0x476), TBL_ENTRY(0x477), + TBL_ENTRY(0x478), TBL_ENTRY(0x479), TBL_ENTRY(0x47a), TBL_ENTRY(0x47b), + TBL_ENTRY(0x47c), TBL_ENTRY(0x47d), TBL_ENTRY(0x47e), TBL_ENTRY(0x47f), + TBL_ENTRY(0x480), TBL_ENTRY(0x481), TBL_ENTRY(0x482), TBL_ENTRY(0x483), + TBL_ENTRY(0x484), TBL_ENTRY(0x485), TBL_ENTRY(0x486), TBL_ENTRY(0x487), + TBL_ENTRY(0x488), TBL_ENTRY(0x489), TBL_ENTRY(0x48a), TBL_ENTRY(0x48b), + TBL_ENTRY(0x48c), TBL_ENTRY(0x48d), TBL_ENTRY(0x48e), TBL_ENTRY(0x48f), + TBL_ENTRY(0x490), TBL_ENTRY(0x491), TBL_ENTRY(0x492), TBL_ENTRY(0x493), + TBL_ENTRY(0x494), TBL_ENTRY(0x495), TBL_ENTRY(0x496), TBL_ENTRY(0x497), + TBL_ENTRY(0x498), TBL_ENTRY(0x499), TBL_ENTRY(0x49a), TBL_ENTRY(0x49b), + TBL_ENTRY(0x49c), TBL_ENTRY(0x49d), TBL_ENTRY(0x49e), TBL_ENTRY(0x49f), + TBL_ENTRY(0x4a0), TBL_ENTRY(0x4a1), TBL_ENTRY(0x4a2), TBL_ENTRY(0x4a3), + TBL_ENTRY(0x4a4), TBL_ENTRY(0x4a5), TBL_ENTRY(0x4a6), TBL_ENTRY(0x4a7), + TBL_ENTRY(0x4a8), TBL_ENTRY(0x4a9), TBL_ENTRY(0x4aa), TBL_ENTRY(0x4ab), + TBL_ENTRY(0x4ac), TBL_ENTRY(0x4ad), TBL_ENTRY(0x4ae), TBL_ENTRY(0x4af), + TBL_ENTRY(0x4b0), TBL_ENTRY(0x4b1), TBL_ENTRY(0x4b2), TBL_ENTRY(0x4b3), + TBL_ENTRY(0x4b4), TBL_ENTRY(0x4b5), TBL_ENTRY(0x4b6), TBL_ENTRY(0x4b7), + TBL_ENTRY(0x4b8), TBL_ENTRY(0x4b9), TBL_ENTRY(0x4ba), TBL_ENTRY(0x4bb), + TBL_ENTRY(0x4bc), TBL_ENTRY(0x4bd), TBL_ENTRY(0x4be), TBL_ENTRY(0x4bf), + TBL_ENTRY(0x4c0), TBL_ENTRY(0x4c1), TBL_ENTRY(0x4c2), TBL_ENTRY(0x4c3), + TBL_ENTRY(0x4c4), TBL_ENTRY(0x4c5), TBL_ENTRY(0x4c6), TBL_ENTRY(0x4c7), + TBL_ENTRY(0x4c8), TBL_ENTRY(0x4c9), TBL_ENTRY(0x4ca), TBL_ENTRY(0x4cb), + TBL_ENTRY(0x4cc), TBL_ENTRY(0x4cd), TBL_ENTRY(0x4ce), TBL_ENTRY(0x4cf), + TBL_ENTRY(0x4d0), TBL_ENTRY(0x4d1), TBL_ENTRY(0x4d2), TBL_ENTRY(0x4d3), + TBL_ENTRY(0x4d4), TBL_ENTRY(0x4d5), TBL_ENTRY(0x4d6), TBL_ENTRY(0x4d7), + TBL_ENTRY(0x4d8), TBL_ENTRY(0x4d9), TBL_ENTRY(0x4da), TBL_ENTRY(0x4db), + TBL_ENTRY(0x4dc), TBL_ENTRY(0x4dd), TBL_ENTRY(0x4de), TBL_ENTRY(0x4df), + TBL_ENTRY(0x4e0), TBL_ENTRY(0x4e1), TBL_ENTRY(0x4e2), TBL_ENTRY(0x4e3), + TBL_ENTRY(0x4e4), TBL_ENTRY(0x4e5), TBL_ENTRY(0x4e6), TBL_ENTRY(0x4e7), + TBL_ENTRY(0x4e8), TBL_ENTRY(0x4e9), TBL_ENTRY(0x4ea), TBL_ENTRY(0x4eb), + TBL_ENTRY(0x4ec), TBL_ENTRY(0x4ed), TBL_ENTRY(0x4ee), TBL_ENTRY(0x4ef), + TBL_ENTRY(0x4f0), TBL_ENTRY(0x4f1), TBL_ENTRY(0x4f2), TBL_ENTRY(0x4f3), + TBL_ENTRY(0x4f4), TBL_ENTRY(0x4f5), TBL_ENTRY(0x4f6), TBL_ENTRY(0x4f7), + TBL_ENTRY(0x4f8), TBL_ENTRY(0x4f9), TBL_ENTRY(0x4fa), TBL_ENTRY(0x4fb), + TBL_ENTRY(0x4fc), TBL_ENTRY(0x4fd), TBL_ENTRY(0x4fe), TBL_ENTRY(0x4ff), + TBL_ENTRY(0x500), TBL_ENTRY(0x501), TBL_ENTRY(0x502), TBL_ENTRY(0x503), + TBL_ENTRY(0x504), TBL_ENTRY(0x505), TBL_ENTRY(0x506), TBL_ENTRY(0x507), + TBL_ENTRY(0x508), TBL_ENTRY(0x509), TBL_ENTRY(0x50a), TBL_ENTRY(0x50b), + TBL_ENTRY(0x50c), TBL_ENTRY(0x50d), TBL_ENTRY(0x50e), TBL_ENTRY(0x50f), + TBL_ENTRY(0x510), TBL_ENTRY(0x511), TBL_ENTRY(0x512), TBL_ENTRY(0x513), + TBL_ENTRY(0x514), TBL_ENTRY(0x515), TBL_ENTRY(0x516), TBL_ENTRY(0x517), + TBL_ENTRY(0x518), TBL_ENTRY(0x519), TBL_ENTRY(0x51a), TBL_ENTRY(0x51b), + TBL_ENTRY(0x51c), TBL_ENTRY(0x51d), TBL_ENTRY(0x51e), TBL_ENTRY(0x51f), + TBL_ENTRY(0x520), TBL_ENTRY(0x521), TBL_ENTRY(0x522), TBL_ENTRY(0x523), + TBL_ENTRY(0x524), TBL_ENTRY(0x525), TBL_ENTRY(0x526), TBL_ENTRY(0x527), + TBL_ENTRY(0x528), TBL_ENTRY(0x529), TBL_ENTRY(0x52a), TBL_ENTRY(0x52b), + TBL_ENTRY(0x52c), TBL_ENTRY(0x52d), TBL_ENTRY(0x52e), TBL_ENTRY(0x52f), + TBL_ENTRY(0x530), TBL_ENTRY(0x531), TBL_ENTRY(0x532), TBL_ENTRY(0x533), + TBL_ENTRY(0x534), TBL_ENTRY(0x535), TBL_ENTRY(0x536), TBL_ENTRY(0x537), + TBL_ENTRY(0x538), TBL_ENTRY(0x539), TBL_ENTRY(0x53a), TBL_ENTRY(0x53b), + TBL_ENTRY(0x53c), TBL_ENTRY(0x53d), TBL_ENTRY(0x53e), TBL_ENTRY(0x53f), + TBL_ENTRY(0x540), TBL_ENTRY(0x541), TBL_ENTRY(0x542), TBL_ENTRY(0x543), + TBL_ENTRY(0x544), TBL_ENTRY(0x545), TBL_ENTRY(0x546), TBL_ENTRY(0x547), + TBL_ENTRY(0x548), TBL_ENTRY(0x549), TBL_ENTRY(0x54a), TBL_ENTRY(0x54b), + TBL_ENTRY(0x54c), TBL_ENTRY(0x54d), TBL_ENTRY(0x54e), TBL_ENTRY(0x54f), + TBL_ENTRY(0x550), TBL_ENTRY(0x551), TBL_ENTRY(0x552), TBL_ENTRY(0x553), + TBL_ENTRY(0x554), TBL_ENTRY(0x555), TBL_ENTRY(0x556), TBL_ENTRY(0x557), + TBL_ENTRY(0x558), TBL_ENTRY(0x559), TBL_ENTRY(0x55a), TBL_ENTRY(0x55b), + TBL_ENTRY(0x55c), TBL_ENTRY(0x55d), TBL_ENTRY(0x55e), TBL_ENTRY(0x55f), + TBL_ENTRY(0x560), TBL_ENTRY(0x561), TBL_ENTRY(0x562), TBL_ENTRY(0x563), + TBL_ENTRY(0x564), TBL_ENTRY(0x565), TBL_ENTRY(0x566), TBL_ENTRY(0x567), + TBL_ENTRY(0x568), TBL_ENTRY(0x569), TBL_ENTRY(0x56a), TBL_ENTRY(0x56b), + TBL_ENTRY(0x56c), TBL_ENTRY(0x56d), TBL_ENTRY(0x56e), TBL_ENTRY(0x56f), + TBL_ENTRY(0x570), TBL_ENTRY(0x571), TBL_ENTRY(0x572), TBL_ENTRY(0x573), + TBL_ENTRY(0x574), TBL_ENTRY(0x575), TBL_ENTRY(0x576), TBL_ENTRY(0x577), + TBL_ENTRY(0x578), TBL_ENTRY(0x579), TBL_ENTRY(0x57a), TBL_ENTRY(0x57b), + TBL_ENTRY(0x57c), TBL_ENTRY(0x57d), TBL_ENTRY(0x57e), TBL_ENTRY(0x57f), + TBL_ENTRY(0x580), TBL_ENTRY(0x581), TBL_ENTRY(0x582), TBL_ENTRY(0x583), + TBL_ENTRY(0x584), TBL_ENTRY(0x585), TBL_ENTRY(0x586), TBL_ENTRY(0x587), + TBL_ENTRY(0x588), TBL_ENTRY(0x589), TBL_ENTRY(0x58a), TBL_ENTRY(0x58b), + TBL_ENTRY(0x58c), TBL_ENTRY(0x58d), TBL_ENTRY(0x58e), TBL_ENTRY(0x58f), + TBL_ENTRY(0x590), TBL_ENTRY(0x591), TBL_ENTRY(0x592), TBL_ENTRY(0x593), + TBL_ENTRY(0x594), TBL_ENTRY(0x595), TBL_ENTRY(0x596), TBL_ENTRY(0x597), + TBL_ENTRY(0x598), TBL_ENTRY(0x599), TBL_ENTRY(0x59a), TBL_ENTRY(0x59b), + TBL_ENTRY(0x59c), TBL_ENTRY(0x59d), TBL_ENTRY(0x59e), TBL_ENTRY(0x59f), + TBL_ENTRY(0x5a0), TBL_ENTRY(0x5a1), TBL_ENTRY(0x5a2), TBL_ENTRY(0x5a3), + TBL_ENTRY(0x5a4), TBL_ENTRY(0x5a5), TBL_ENTRY(0x5a6), TBL_ENTRY(0x5a7), + TBL_ENTRY(0x5a8), TBL_ENTRY(0x5a9), TBL_ENTRY(0x5aa), TBL_ENTRY(0x5ab), + TBL_ENTRY(0x5ac), TBL_ENTRY(0x5ad), TBL_ENTRY(0x5ae), TBL_ENTRY(0x5af), + TBL_ENTRY(0x5b0), TBL_ENTRY(0x5b1), TBL_ENTRY(0x5b2), TBL_ENTRY(0x5b3), + TBL_ENTRY(0x5b4), TBL_ENTRY(0x5b5), TBL_ENTRY(0x5b6), TBL_ENTRY(0x5b7), + TBL_ENTRY(0x5b8), TBL_ENTRY(0x5b9), TBL_ENTRY(0x5ba), TBL_ENTRY(0x5bb), + TBL_ENTRY(0x5bc), TBL_ENTRY(0x5bd), TBL_ENTRY(0x5be), TBL_ENTRY(0x5bf), + TBL_ENTRY(0x5c0), TBL_ENTRY(0x5c1), TBL_ENTRY(0x5c2), TBL_ENTRY(0x5c3), + TBL_ENTRY(0x5c4), TBL_ENTRY(0x5c5), TBL_ENTRY(0x5c6), TBL_ENTRY(0x5c7), + TBL_ENTRY(0x5c8), TBL_ENTRY(0x5c9), TBL_ENTRY(0x5ca), TBL_ENTRY(0x5cb), + TBL_ENTRY(0x5cc), TBL_ENTRY(0x5cd), TBL_ENTRY(0x5ce), TBL_ENTRY(0x5cf), + TBL_ENTRY(0x5d0), TBL_ENTRY(0x5d1), TBL_ENTRY(0x5d2), TBL_ENTRY(0x5d3), + TBL_ENTRY(0x5d4), TBL_ENTRY(0x5d5), TBL_ENTRY(0x5d6), TBL_ENTRY(0x5d7), + TBL_ENTRY(0x5d8), TBL_ENTRY(0x5d9), TBL_ENTRY(0x5da), TBL_ENTRY(0x5db), + TBL_ENTRY(0x5dc), TBL_ENTRY(0x5dd), TBL_ENTRY(0x5de), TBL_ENTRY(0x5df), + TBL_ENTRY(0x5e0), TBL_ENTRY(0x5e1), TBL_ENTRY(0x5e2), TBL_ENTRY(0x5e3), + TBL_ENTRY(0x5e4), TBL_ENTRY(0x5e5), TBL_ENTRY(0x5e6), TBL_ENTRY(0x5e7), + TBL_ENTRY(0x5e8), TBL_ENTRY(0x5e9), TBL_ENTRY(0x5ea), TBL_ENTRY(0x5eb), + TBL_ENTRY(0x5ec), TBL_ENTRY(0x5ed), TBL_ENTRY(0x5ee), TBL_ENTRY(0x5ef), + TBL_ENTRY(0x5f0), TBL_ENTRY(0x5f1), TBL_ENTRY(0x5f2), TBL_ENTRY(0x5f3), + TBL_ENTRY(0x5f4), TBL_ENTRY(0x5f5), TBL_ENTRY(0x5f6), TBL_ENTRY(0x5f7), + TBL_ENTRY(0x5f8), TBL_ENTRY(0x5f9), TBL_ENTRY(0x5fa), TBL_ENTRY(0x5fb), + TBL_ENTRY(0x5fc), TBL_ENTRY(0x5fd), TBL_ENTRY(0x5fe), TBL_ENTRY(0x5ff), + TBL_ENTRY(0x600), TBL_ENTRY(0x601), TBL_ENTRY(0x602), TBL_ENTRY(0x603), + TBL_ENTRY(0x604), TBL_ENTRY(0x605), TBL_ENTRY(0x606), TBL_ENTRY(0x607), + TBL_ENTRY(0x608), TBL_ENTRY(0x609), TBL_ENTRY(0x60a), TBL_ENTRY(0x60b), + TBL_ENTRY(0x60c), TBL_ENTRY(0x60d), TBL_ENTRY(0x60e), TBL_ENTRY(0x60f), + TBL_ENTRY(0x610), TBL_ENTRY(0x611), TBL_ENTRY(0x612), TBL_ENTRY(0x613), + TBL_ENTRY(0x614), TBL_ENTRY(0x615), TBL_ENTRY(0x616), TBL_ENTRY(0x617), + TBL_ENTRY(0x618), TBL_ENTRY(0x619), TBL_ENTRY(0x61a), TBL_ENTRY(0x61b), + TBL_ENTRY(0x61c), TBL_ENTRY(0x61d), TBL_ENTRY(0x61e), TBL_ENTRY(0x61f), + TBL_ENTRY(0x620), TBL_ENTRY(0x621), TBL_ENTRY(0x622), TBL_ENTRY(0x623), + TBL_ENTRY(0x624), TBL_ENTRY(0x625), TBL_ENTRY(0x626), TBL_ENTRY(0x627), + TBL_ENTRY(0x628), TBL_ENTRY(0x629), TBL_ENTRY(0x62a), TBL_ENTRY(0x62b), + TBL_ENTRY(0x62c), TBL_ENTRY(0x62d), TBL_ENTRY(0x62e), TBL_ENTRY(0x62f), + TBL_ENTRY(0x630), TBL_ENTRY(0x631), TBL_ENTRY(0x632), TBL_ENTRY(0x633), + TBL_ENTRY(0x634), TBL_ENTRY(0x635), TBL_ENTRY(0x636), TBL_ENTRY(0x637), + TBL_ENTRY(0x638), TBL_ENTRY(0x639), TBL_ENTRY(0x63a), TBL_ENTRY(0x63b), + TBL_ENTRY(0x63c), TBL_ENTRY(0x63d), TBL_ENTRY(0x63e), TBL_ENTRY(0x63f), + TBL_ENTRY(0x640), TBL_ENTRY(0x641), TBL_ENTRY(0x642), TBL_ENTRY(0x643), + TBL_ENTRY(0x644), TBL_ENTRY(0x645), TBL_ENTRY(0x646), TBL_ENTRY(0x647), + TBL_ENTRY(0x648), TBL_ENTRY(0x649), TBL_ENTRY(0x64a), TBL_ENTRY(0x64b), + TBL_ENTRY(0x64c), TBL_ENTRY(0x64d), TBL_ENTRY(0x64e), TBL_ENTRY(0x64f), + TBL_ENTRY(0x650), TBL_ENTRY(0x651), TBL_ENTRY(0x652), TBL_ENTRY(0x653), + TBL_ENTRY(0x654), TBL_ENTRY(0x655), TBL_ENTRY(0x656), TBL_ENTRY(0x657), + TBL_ENTRY(0x658), TBL_ENTRY(0x659), TBL_ENTRY(0x65a), TBL_ENTRY(0x65b), + TBL_ENTRY(0x65c), TBL_ENTRY(0x65d), TBL_ENTRY(0x65e), TBL_ENTRY(0x65f), + TBL_ENTRY(0x660), TBL_ENTRY(0x661), TBL_ENTRY(0x662), TBL_ENTRY(0x663), + TBL_ENTRY(0x664), TBL_ENTRY(0x665), TBL_ENTRY(0x666), TBL_ENTRY(0x667), + TBL_ENTRY(0x668), TBL_ENTRY(0x669), TBL_ENTRY(0x66a), TBL_ENTRY(0x66b), + TBL_ENTRY(0x66c), TBL_ENTRY(0x66d), TBL_ENTRY(0x66e), TBL_ENTRY(0x66f), + TBL_ENTRY(0x670), TBL_ENTRY(0x671), TBL_ENTRY(0x672), TBL_ENTRY(0x673), + TBL_ENTRY(0x674), TBL_ENTRY(0x675), TBL_ENTRY(0x676), TBL_ENTRY(0x677), + TBL_ENTRY(0x678), TBL_ENTRY(0x679), TBL_ENTRY(0x67a), TBL_ENTRY(0x67b), + TBL_ENTRY(0x67c), TBL_ENTRY(0x67d), TBL_ENTRY(0x67e), TBL_ENTRY(0x67f), + TBL_ENTRY(0x680), TBL_ENTRY(0x681), TBL_ENTRY(0x682), TBL_ENTRY(0x683), + TBL_ENTRY(0x684), TBL_ENTRY(0x685), TBL_ENTRY(0x686), TBL_ENTRY(0x687), + TBL_ENTRY(0x688), TBL_ENTRY(0x689), TBL_ENTRY(0x68a), TBL_ENTRY(0x68b), + TBL_ENTRY(0x68c), TBL_ENTRY(0x68d), TBL_ENTRY(0x68e), TBL_ENTRY(0x68f), + TBL_ENTRY(0x690), TBL_ENTRY(0x691), TBL_ENTRY(0x692), TBL_ENTRY(0x693), + TBL_ENTRY(0x694), TBL_ENTRY(0x695), TBL_ENTRY(0x696), TBL_ENTRY(0x697), + TBL_ENTRY(0x698), TBL_ENTRY(0x699), TBL_ENTRY(0x69a), TBL_ENTRY(0x69b), + TBL_ENTRY(0x69c), TBL_ENTRY(0x69d), TBL_ENTRY(0x69e), TBL_ENTRY(0x69f), + TBL_ENTRY(0x6a0), TBL_ENTRY(0x6a1), TBL_ENTRY(0x6a2), TBL_ENTRY(0x6a3), + TBL_ENTRY(0x6a4), TBL_ENTRY(0x6a5), TBL_ENTRY(0x6a6), TBL_ENTRY(0x6a7), + TBL_ENTRY(0x6a8), TBL_ENTRY(0x6a9), TBL_ENTRY(0x6aa), TBL_ENTRY(0x6ab), + TBL_ENTRY(0x6ac), TBL_ENTRY(0x6ad), TBL_ENTRY(0x6ae), TBL_ENTRY(0x6af), + TBL_ENTRY(0x6b0), TBL_ENTRY(0x6b1), TBL_ENTRY(0x6b2), TBL_ENTRY(0x6b3), + TBL_ENTRY(0x6b4), TBL_ENTRY(0x6b5), TBL_ENTRY(0x6b6), TBL_ENTRY(0x6b7), + TBL_ENTRY(0x6b8), TBL_ENTRY(0x6b9), TBL_ENTRY(0x6ba), TBL_ENTRY(0x6bb), + TBL_ENTRY(0x6bc), TBL_ENTRY(0x6bd), TBL_ENTRY(0x6be), TBL_ENTRY(0x6bf), + TBL_ENTRY(0x6c0), TBL_ENTRY(0x6c1), TBL_ENTRY(0x6c2), TBL_ENTRY(0x6c3), + TBL_ENTRY(0x6c4), TBL_ENTRY(0x6c5), TBL_ENTRY(0x6c6), TBL_ENTRY(0x6c7), + TBL_ENTRY(0x6c8), TBL_ENTRY(0x6c9), TBL_ENTRY(0x6ca), TBL_ENTRY(0x6cb), + TBL_ENTRY(0x6cc), TBL_ENTRY(0x6cd), TBL_ENTRY(0x6ce), TBL_ENTRY(0x6cf), + TBL_ENTRY(0x6d0), TBL_ENTRY(0x6d1), TBL_ENTRY(0x6d2), TBL_ENTRY(0x6d3), + TBL_ENTRY(0x6d4), TBL_ENTRY(0x6d5), TBL_ENTRY(0x6d6), TBL_ENTRY(0x6d7), + TBL_ENTRY(0x6d8), TBL_ENTRY(0x6d9), TBL_ENTRY(0x6da), TBL_ENTRY(0x6db), + TBL_ENTRY(0x6dc), TBL_ENTRY(0x6dd), TBL_ENTRY(0x6de), TBL_ENTRY(0x6df), + TBL_ENTRY(0x6e0), TBL_ENTRY(0x6e1), TBL_ENTRY(0x6e2), TBL_ENTRY(0x6e3), + TBL_ENTRY(0x6e4), TBL_ENTRY(0x6e5), TBL_ENTRY(0x6e6), TBL_ENTRY(0x6e7), + TBL_ENTRY(0x6e8), TBL_ENTRY(0x6e9), TBL_ENTRY(0x6ea), TBL_ENTRY(0x6eb), + TBL_ENTRY(0x6ec), TBL_ENTRY(0x6ed), TBL_ENTRY(0x6ee), TBL_ENTRY(0x6ef), + TBL_ENTRY(0x6f0), TBL_ENTRY(0x6f1), TBL_ENTRY(0x6f2), TBL_ENTRY(0x6f3), + TBL_ENTRY(0x6f4), TBL_ENTRY(0x6f5), TBL_ENTRY(0x6f6), TBL_ENTRY(0x6f7), + TBL_ENTRY(0x6f8), TBL_ENTRY(0x6f9), TBL_ENTRY(0x6fa), TBL_ENTRY(0x6fb), + TBL_ENTRY(0x6fc), TBL_ENTRY(0x6fd), TBL_ENTRY(0x6fe), TBL_ENTRY(0x6ff), + TBL_ENTRY(0x700), TBL_ENTRY(0x701), TBL_ENTRY(0x702), TBL_ENTRY(0x703), + TBL_ENTRY(0x704), TBL_ENTRY(0x705), TBL_ENTRY(0x706), TBL_ENTRY(0x707), + TBL_ENTRY(0x708), TBL_ENTRY(0x709), TBL_ENTRY(0x70a), TBL_ENTRY(0x70b), + TBL_ENTRY(0x70c), TBL_ENTRY(0x70d), TBL_ENTRY(0x70e), TBL_ENTRY(0x70f), + TBL_ENTRY(0x710), TBL_ENTRY(0x711), TBL_ENTRY(0x712), TBL_ENTRY(0x713), + TBL_ENTRY(0x714), TBL_ENTRY(0x715), TBL_ENTRY(0x716), TBL_ENTRY(0x717), + TBL_ENTRY(0x718), TBL_ENTRY(0x719), TBL_ENTRY(0x71a), TBL_ENTRY(0x71b), + TBL_ENTRY(0x71c), TBL_ENTRY(0x71d), TBL_ENTRY(0x71e), TBL_ENTRY(0x71f), + TBL_ENTRY(0x720), TBL_ENTRY(0x721), TBL_ENTRY(0x722), TBL_ENTRY(0x723), + TBL_ENTRY(0x724), TBL_ENTRY(0x725), TBL_ENTRY(0x726), TBL_ENTRY(0x727), + TBL_ENTRY(0x728), TBL_ENTRY(0x729), TBL_ENTRY(0x72a), TBL_ENTRY(0x72b), + TBL_ENTRY(0x72c), TBL_ENTRY(0x72d), TBL_ENTRY(0x72e), TBL_ENTRY(0x72f), + TBL_ENTRY(0x730), TBL_ENTRY(0x731), TBL_ENTRY(0x732), TBL_ENTRY(0x733), + TBL_ENTRY(0x734), TBL_ENTRY(0x735), TBL_ENTRY(0x736), TBL_ENTRY(0x737), + TBL_ENTRY(0x738), TBL_ENTRY(0x739), TBL_ENTRY(0x73a), TBL_ENTRY(0x73b), + TBL_ENTRY(0x73c), TBL_ENTRY(0x73d), TBL_ENTRY(0x73e), TBL_ENTRY(0x73f), + TBL_ENTRY(0x740), TBL_ENTRY(0x741), TBL_ENTRY(0x742), TBL_ENTRY(0x743), + TBL_ENTRY(0x744), TBL_ENTRY(0x745), TBL_ENTRY(0x746), TBL_ENTRY(0x747), + TBL_ENTRY(0x748), TBL_ENTRY(0x749), TBL_ENTRY(0x74a), TBL_ENTRY(0x74b), + TBL_ENTRY(0x74c), TBL_ENTRY(0x74d), TBL_ENTRY(0x74e), TBL_ENTRY(0x74f), + TBL_ENTRY(0x750), TBL_ENTRY(0x751), TBL_ENTRY(0x752), TBL_ENTRY(0x753), + TBL_ENTRY(0x754), TBL_ENTRY(0x755), TBL_ENTRY(0x756), TBL_ENTRY(0x757), + TBL_ENTRY(0x758), TBL_ENTRY(0x759), TBL_ENTRY(0x75a), TBL_ENTRY(0x75b), + TBL_ENTRY(0x75c), TBL_ENTRY(0x75d), TBL_ENTRY(0x75e), TBL_ENTRY(0x75f), + TBL_ENTRY(0x760), TBL_ENTRY(0x761), TBL_ENTRY(0x762), TBL_ENTRY(0x763), + TBL_ENTRY(0x764), TBL_ENTRY(0x765), TBL_ENTRY(0x766), TBL_ENTRY(0x767), + TBL_ENTRY(0x768), TBL_ENTRY(0x769), TBL_ENTRY(0x76a), TBL_ENTRY(0x76b), + TBL_ENTRY(0x76c), TBL_ENTRY(0x76d), TBL_ENTRY(0x76e), TBL_ENTRY(0x76f), + TBL_ENTRY(0x770), TBL_ENTRY(0x771), TBL_ENTRY(0x772), TBL_ENTRY(0x773), + TBL_ENTRY(0x774), TBL_ENTRY(0x775), TBL_ENTRY(0x776), TBL_ENTRY(0x777), + TBL_ENTRY(0x778), TBL_ENTRY(0x779), TBL_ENTRY(0x77a), TBL_ENTRY(0x77b), + TBL_ENTRY(0x77c), TBL_ENTRY(0x77d), TBL_ENTRY(0x77e), TBL_ENTRY(0x77f), + TBL_ENTRY(0x780), TBL_ENTRY(0x781), TBL_ENTRY(0x782), TBL_ENTRY(0x783), + TBL_ENTRY(0x784), TBL_ENTRY(0x785), TBL_ENTRY(0x786), TBL_ENTRY(0x787), + TBL_ENTRY(0x788), TBL_ENTRY(0x789), TBL_ENTRY(0x78a), TBL_ENTRY(0x78b), + TBL_ENTRY(0x78c), TBL_ENTRY(0x78d), TBL_ENTRY(0x78e), TBL_ENTRY(0x78f), + TBL_ENTRY(0x790), TBL_ENTRY(0x791), TBL_ENTRY(0x792), TBL_ENTRY(0x793), + TBL_ENTRY(0x794), TBL_ENTRY(0x795), TBL_ENTRY(0x796), TBL_ENTRY(0x797), + TBL_ENTRY(0x798), TBL_ENTRY(0x799), TBL_ENTRY(0x79a), TBL_ENTRY(0x79b), + TBL_ENTRY(0x79c), TBL_ENTRY(0x79d), TBL_ENTRY(0x79e), TBL_ENTRY(0x79f), + TBL_ENTRY(0x7a0), TBL_ENTRY(0x7a1), TBL_ENTRY(0x7a2), TBL_ENTRY(0x7a3), + TBL_ENTRY(0x7a4), TBL_ENTRY(0x7a5), TBL_ENTRY(0x7a6), TBL_ENTRY(0x7a7), + TBL_ENTRY(0x7a8), TBL_ENTRY(0x7a9), TBL_ENTRY(0x7aa), TBL_ENTRY(0x7ab), + TBL_ENTRY(0x7ac), TBL_ENTRY(0x7ad), TBL_ENTRY(0x7ae), TBL_ENTRY(0x7af), + TBL_ENTRY(0x7b0), TBL_ENTRY(0x7b1), TBL_ENTRY(0x7b2), TBL_ENTRY(0x7b3), + TBL_ENTRY(0x7b4), TBL_ENTRY(0x7b5), TBL_ENTRY(0x7b6), TBL_ENTRY(0x7b7), + TBL_ENTRY(0x7b8), TBL_ENTRY(0x7b9), TBL_ENTRY(0x7ba), TBL_ENTRY(0x7bb), + TBL_ENTRY(0x7bc), TBL_ENTRY(0x7bd), TBL_ENTRY(0x7be), TBL_ENTRY(0x7bf), + TBL_ENTRY(0x7c0), TBL_ENTRY(0x7c1), TBL_ENTRY(0x7c2), TBL_ENTRY(0x7c3), + TBL_ENTRY(0x7c4), TBL_ENTRY(0x7c5), TBL_ENTRY(0x7c6), TBL_ENTRY(0x7c7), + TBL_ENTRY(0x7c8), TBL_ENTRY(0x7c9), TBL_ENTRY(0x7ca), TBL_ENTRY(0x7cb), + TBL_ENTRY(0x7cc), TBL_ENTRY(0x7cd), TBL_ENTRY(0x7ce), TBL_ENTRY(0x7cf), + TBL_ENTRY(0x7d0), TBL_ENTRY(0x7d1), TBL_ENTRY(0x7d2), TBL_ENTRY(0x7d3), + TBL_ENTRY(0x7d4), TBL_ENTRY(0x7d5), TBL_ENTRY(0x7d6), TBL_ENTRY(0x7d7), + TBL_ENTRY(0x7d8), TBL_ENTRY(0x7d9), TBL_ENTRY(0x7da), TBL_ENTRY(0x7db), + TBL_ENTRY(0x7dc), TBL_ENTRY(0x7dd), TBL_ENTRY(0x7de), TBL_ENTRY(0x7df), + TBL_ENTRY(0x7e0), TBL_ENTRY(0x7e1), TBL_ENTRY(0x7e2), TBL_ENTRY(0x7e3), + TBL_ENTRY(0x7e4), TBL_ENTRY(0x7e5), TBL_ENTRY(0x7e6), TBL_ENTRY(0x7e7), + TBL_ENTRY(0x7e8), TBL_ENTRY(0x7e9), TBL_ENTRY(0x7ea), TBL_ENTRY(0x7eb), + TBL_ENTRY(0x7ec), TBL_ENTRY(0x7ed), TBL_ENTRY(0x7ee), TBL_ENTRY(0x7ef), + TBL_ENTRY(0x7f0), TBL_ENTRY(0x7f1), TBL_ENTRY(0x7f2), TBL_ENTRY(0x7f3), + TBL_ENTRY(0x7f4), TBL_ENTRY(0x7f5), TBL_ENTRY(0x7f6), TBL_ENTRY(0x7f7), + TBL_ENTRY(0x7f8), TBL_ENTRY(0x7f9), TBL_ENTRY(0x7fa), TBL_ENTRY(0x7fb), + TBL_ENTRY(0x7fc), TBL_ENTRY(0x7fd), TBL_ENTRY(0x7fe), TBL_ENTRY(0x7ff), + TBL_ENTRY(0x800), TBL_ENTRY(0x801), TBL_ENTRY(0x802), TBL_ENTRY(0x803), + TBL_ENTRY(0x804), TBL_ENTRY(0x805), TBL_ENTRY(0x806), TBL_ENTRY(0x807), + TBL_ENTRY(0x808), TBL_ENTRY(0x809), TBL_ENTRY(0x80a), TBL_ENTRY(0x80b), + TBL_ENTRY(0x80c), TBL_ENTRY(0x80d), TBL_ENTRY(0x80e), TBL_ENTRY(0x80f), + TBL_ENTRY(0x810), TBL_ENTRY(0x811), TBL_ENTRY(0x812), TBL_ENTRY(0x813), + TBL_ENTRY(0x814), TBL_ENTRY(0x815), TBL_ENTRY(0x816), TBL_ENTRY(0x817), + TBL_ENTRY(0x818), TBL_ENTRY(0x819), TBL_ENTRY(0x81a), TBL_ENTRY(0x81b), + TBL_ENTRY(0x81c), TBL_ENTRY(0x81d), TBL_ENTRY(0x81e), TBL_ENTRY(0x81f), + TBL_ENTRY(0x820), TBL_ENTRY(0x821), TBL_ENTRY(0x822), TBL_ENTRY(0x823), + TBL_ENTRY(0x824), TBL_ENTRY(0x825), TBL_ENTRY(0x826), TBL_ENTRY(0x827), + TBL_ENTRY(0x828), TBL_ENTRY(0x829), TBL_ENTRY(0x82a), TBL_ENTRY(0x82b), + TBL_ENTRY(0x82c), TBL_ENTRY(0x82d), TBL_ENTRY(0x82e), TBL_ENTRY(0x82f), + TBL_ENTRY(0x830), TBL_ENTRY(0x831), TBL_ENTRY(0x832), TBL_ENTRY(0x833), + TBL_ENTRY(0x834), TBL_ENTRY(0x835), TBL_ENTRY(0x836), TBL_ENTRY(0x837), + TBL_ENTRY(0x838), TBL_ENTRY(0x839), TBL_ENTRY(0x83a), TBL_ENTRY(0x83b), + TBL_ENTRY(0x83c), TBL_ENTRY(0x83d), TBL_ENTRY(0x83e), TBL_ENTRY(0x83f), + TBL_ENTRY(0x840), TBL_ENTRY(0x841), TBL_ENTRY(0x842), TBL_ENTRY(0x843), + TBL_ENTRY(0x844), TBL_ENTRY(0x845), TBL_ENTRY(0x846), TBL_ENTRY(0x847), + TBL_ENTRY(0x848), TBL_ENTRY(0x849), TBL_ENTRY(0x84a), TBL_ENTRY(0x84b), + TBL_ENTRY(0x84c), TBL_ENTRY(0x84d), TBL_ENTRY(0x84e), TBL_ENTRY(0x84f), + TBL_ENTRY(0x850), TBL_ENTRY(0x851), TBL_ENTRY(0x852), TBL_ENTRY(0x853), + TBL_ENTRY(0x854), TBL_ENTRY(0x855), TBL_ENTRY(0x856), TBL_ENTRY(0x857), + TBL_ENTRY(0x858), TBL_ENTRY(0x859), TBL_ENTRY(0x85a), TBL_ENTRY(0x85b), + TBL_ENTRY(0x85c), TBL_ENTRY(0x85d), TBL_ENTRY(0x85e), TBL_ENTRY(0x85f), + TBL_ENTRY(0x860), TBL_ENTRY(0x861), TBL_ENTRY(0x862), TBL_ENTRY(0x863), + TBL_ENTRY(0x864), TBL_ENTRY(0x865), TBL_ENTRY(0x866), TBL_ENTRY(0x867), + TBL_ENTRY(0x868), TBL_ENTRY(0x869), TBL_ENTRY(0x86a), TBL_ENTRY(0x86b), + TBL_ENTRY(0x86c), TBL_ENTRY(0x86d), TBL_ENTRY(0x86e), TBL_ENTRY(0x86f), + TBL_ENTRY(0x870), TBL_ENTRY(0x871), TBL_ENTRY(0x872), TBL_ENTRY(0x873), + TBL_ENTRY(0x874), TBL_ENTRY(0x875), TBL_ENTRY(0x876), TBL_ENTRY(0x877), + TBL_ENTRY(0x878), TBL_ENTRY(0x879), TBL_ENTRY(0x87a), TBL_ENTRY(0x87b), + TBL_ENTRY(0x87c), TBL_ENTRY(0x87d), TBL_ENTRY(0x87e), TBL_ENTRY(0x87f), + TBL_ENTRY(0x880), TBL_ENTRY(0x881), TBL_ENTRY(0x882), TBL_ENTRY(0x883), + TBL_ENTRY(0x884), TBL_ENTRY(0x885), TBL_ENTRY(0x886), TBL_ENTRY(0x887), + TBL_ENTRY(0x888), TBL_ENTRY(0x889), TBL_ENTRY(0x88a), TBL_ENTRY(0x88b), + TBL_ENTRY(0x88c), TBL_ENTRY(0x88d), TBL_ENTRY(0x88e), TBL_ENTRY(0x88f), + TBL_ENTRY(0x890), TBL_ENTRY(0x891), TBL_ENTRY(0x892), TBL_ENTRY(0x893), + TBL_ENTRY(0x894), TBL_ENTRY(0x895), TBL_ENTRY(0x896), TBL_ENTRY(0x897), + TBL_ENTRY(0x898), TBL_ENTRY(0x899), TBL_ENTRY(0x89a), TBL_ENTRY(0x89b), + TBL_ENTRY(0x89c), TBL_ENTRY(0x89d), TBL_ENTRY(0x89e), TBL_ENTRY(0x89f), + TBL_ENTRY(0x8a0), TBL_ENTRY(0x8a1), TBL_ENTRY(0x8a2), TBL_ENTRY(0x8a3), + TBL_ENTRY(0x8a4), TBL_ENTRY(0x8a5), TBL_ENTRY(0x8a6), TBL_ENTRY(0x8a7), + TBL_ENTRY(0x8a8), TBL_ENTRY(0x8a9), TBL_ENTRY(0x8aa), TBL_ENTRY(0x8ab), + TBL_ENTRY(0x8ac), TBL_ENTRY(0x8ad), TBL_ENTRY(0x8ae), TBL_ENTRY(0x8af), + TBL_ENTRY(0x8b0), TBL_ENTRY(0x8b1), TBL_ENTRY(0x8b2), TBL_ENTRY(0x8b3), + TBL_ENTRY(0x8b4), TBL_ENTRY(0x8b5), TBL_ENTRY(0x8b6), TBL_ENTRY(0x8b7), + TBL_ENTRY(0x8b8), TBL_ENTRY(0x8b9), TBL_ENTRY(0x8ba), TBL_ENTRY(0x8bb), + TBL_ENTRY(0x8bc), TBL_ENTRY(0x8bd), TBL_ENTRY(0x8be), TBL_ENTRY(0x8bf), + TBL_ENTRY(0x8c0), TBL_ENTRY(0x8c1), TBL_ENTRY(0x8c2), TBL_ENTRY(0x8c3), + TBL_ENTRY(0x8c4), TBL_ENTRY(0x8c5), TBL_ENTRY(0x8c6), TBL_ENTRY(0x8c7), + TBL_ENTRY(0x8c8), TBL_ENTRY(0x8c9), TBL_ENTRY(0x8ca), TBL_ENTRY(0x8cb), + TBL_ENTRY(0x8cc), TBL_ENTRY(0x8cd), TBL_ENTRY(0x8ce), TBL_ENTRY(0x8cf), + TBL_ENTRY(0x8d0), TBL_ENTRY(0x8d1), TBL_ENTRY(0x8d2), TBL_ENTRY(0x8d3), + TBL_ENTRY(0x8d4), TBL_ENTRY(0x8d5), TBL_ENTRY(0x8d6), TBL_ENTRY(0x8d7), + TBL_ENTRY(0x8d8), TBL_ENTRY(0x8d9), TBL_ENTRY(0x8da), TBL_ENTRY(0x8db), + TBL_ENTRY(0x8dc), TBL_ENTRY(0x8dd), TBL_ENTRY(0x8de), TBL_ENTRY(0x8df), + TBL_ENTRY(0x8e0), TBL_ENTRY(0x8e1), TBL_ENTRY(0x8e2), TBL_ENTRY(0x8e3), + TBL_ENTRY(0x8e4), TBL_ENTRY(0x8e5), TBL_ENTRY(0x8e6), TBL_ENTRY(0x8e7), + TBL_ENTRY(0x8e8), TBL_ENTRY(0x8e9), TBL_ENTRY(0x8ea), TBL_ENTRY(0x8eb), + TBL_ENTRY(0x8ec), TBL_ENTRY(0x8ed), TBL_ENTRY(0x8ee), TBL_ENTRY(0x8ef), + TBL_ENTRY(0x8f0), TBL_ENTRY(0x8f1), TBL_ENTRY(0x8f2), TBL_ENTRY(0x8f3), + TBL_ENTRY(0x8f4), TBL_ENTRY(0x8f5), TBL_ENTRY(0x8f6), TBL_ENTRY(0x8f7), + TBL_ENTRY(0x8f8), TBL_ENTRY(0x8f9), TBL_ENTRY(0x8fa), TBL_ENTRY(0x8fb), + TBL_ENTRY(0x8fc), TBL_ENTRY(0x8fd), TBL_ENTRY(0x8fe), TBL_ENTRY(0x8ff), + TBL_ENTRY(0x900), TBL_ENTRY(0x901), TBL_ENTRY(0x902), TBL_ENTRY(0x903), + TBL_ENTRY(0x904), TBL_ENTRY(0x905), TBL_ENTRY(0x906), TBL_ENTRY(0x907), + TBL_ENTRY(0x908), TBL_ENTRY(0x909), TBL_ENTRY(0x90a), TBL_ENTRY(0x90b), + TBL_ENTRY(0x90c), TBL_ENTRY(0x90d), TBL_ENTRY(0x90e), TBL_ENTRY(0x90f), + TBL_ENTRY(0x910), TBL_ENTRY(0x911), TBL_ENTRY(0x912), TBL_ENTRY(0x913), + TBL_ENTRY(0x914), TBL_ENTRY(0x915), TBL_ENTRY(0x916), TBL_ENTRY(0x917), + TBL_ENTRY(0x918), TBL_ENTRY(0x919), TBL_ENTRY(0x91a), TBL_ENTRY(0x91b), + TBL_ENTRY(0x91c), TBL_ENTRY(0x91d), TBL_ENTRY(0x91e), TBL_ENTRY(0x91f), + TBL_ENTRY(0x920), TBL_ENTRY(0x921), TBL_ENTRY(0x922), TBL_ENTRY(0x923), + TBL_ENTRY(0x924), TBL_ENTRY(0x925), TBL_ENTRY(0x926), TBL_ENTRY(0x927), + TBL_ENTRY(0x928), TBL_ENTRY(0x929), TBL_ENTRY(0x92a), TBL_ENTRY(0x92b), + TBL_ENTRY(0x92c), TBL_ENTRY(0x92d), TBL_ENTRY(0x92e), TBL_ENTRY(0x92f), + TBL_ENTRY(0x930), TBL_ENTRY(0x931), TBL_ENTRY(0x932), TBL_ENTRY(0x933), + TBL_ENTRY(0x934), TBL_ENTRY(0x935), TBL_ENTRY(0x936), TBL_ENTRY(0x937), + TBL_ENTRY(0x938), TBL_ENTRY(0x939), TBL_ENTRY(0x93a), TBL_ENTRY(0x93b), + TBL_ENTRY(0x93c), TBL_ENTRY(0x93d), TBL_ENTRY(0x93e), TBL_ENTRY(0x93f), + TBL_ENTRY(0x940), TBL_ENTRY(0x941), TBL_ENTRY(0x942), TBL_ENTRY(0x943), + TBL_ENTRY(0x944), TBL_ENTRY(0x945), TBL_ENTRY(0x946), TBL_ENTRY(0x947), + TBL_ENTRY(0x948), TBL_ENTRY(0x949), TBL_ENTRY(0x94a), TBL_ENTRY(0x94b), + TBL_ENTRY(0x94c), TBL_ENTRY(0x94d), TBL_ENTRY(0x94e), TBL_ENTRY(0x94f), + TBL_ENTRY(0x950), TBL_ENTRY(0x951), TBL_ENTRY(0x952), TBL_ENTRY(0x953), + TBL_ENTRY(0x954), TBL_ENTRY(0x955), TBL_ENTRY(0x956), TBL_ENTRY(0x957), + TBL_ENTRY(0x958), TBL_ENTRY(0x959), TBL_ENTRY(0x95a), TBL_ENTRY(0x95b), + TBL_ENTRY(0x95c), TBL_ENTRY(0x95d), TBL_ENTRY(0x95e), TBL_ENTRY(0x95f), + TBL_ENTRY(0x960), TBL_ENTRY(0x961), TBL_ENTRY(0x962), TBL_ENTRY(0x963), + TBL_ENTRY(0x964), TBL_ENTRY(0x965), TBL_ENTRY(0x966), TBL_ENTRY(0x967), + TBL_ENTRY(0x968), TBL_ENTRY(0x969), TBL_ENTRY(0x96a), TBL_ENTRY(0x96b), + TBL_ENTRY(0x96c), TBL_ENTRY(0x96d), TBL_ENTRY(0x96e), TBL_ENTRY(0x96f), + TBL_ENTRY(0x970), TBL_ENTRY(0x971), TBL_ENTRY(0x972), TBL_ENTRY(0x973), + TBL_ENTRY(0x974), TBL_ENTRY(0x975), TBL_ENTRY(0x976), TBL_ENTRY(0x977), + TBL_ENTRY(0x978), TBL_ENTRY(0x979), TBL_ENTRY(0x97a), TBL_ENTRY(0x97b), + TBL_ENTRY(0x97c), TBL_ENTRY(0x97d), TBL_ENTRY(0x97e), TBL_ENTRY(0x97f), + TBL_ENTRY(0x980), TBL_ENTRY(0x981), TBL_ENTRY(0x982), TBL_ENTRY(0x983), + TBL_ENTRY(0x984), TBL_ENTRY(0x985), TBL_ENTRY(0x986), TBL_ENTRY(0x987), + TBL_ENTRY(0x988), TBL_ENTRY(0x989), TBL_ENTRY(0x98a), TBL_ENTRY(0x98b), + TBL_ENTRY(0x98c), TBL_ENTRY(0x98d), TBL_ENTRY(0x98e), TBL_ENTRY(0x98f), + TBL_ENTRY(0x990), TBL_ENTRY(0x991), TBL_ENTRY(0x992), TBL_ENTRY(0x993), + TBL_ENTRY(0x994), TBL_ENTRY(0x995), TBL_ENTRY(0x996), TBL_ENTRY(0x997), + TBL_ENTRY(0x998), TBL_ENTRY(0x999), TBL_ENTRY(0x99a), TBL_ENTRY(0x99b), + TBL_ENTRY(0x99c), TBL_ENTRY(0x99d), TBL_ENTRY(0x99e), TBL_ENTRY(0x99f), + TBL_ENTRY(0x9a0), TBL_ENTRY(0x9a1), TBL_ENTRY(0x9a2), TBL_ENTRY(0x9a3), + TBL_ENTRY(0x9a4), TBL_ENTRY(0x9a5), TBL_ENTRY(0x9a6), TBL_ENTRY(0x9a7), + TBL_ENTRY(0x9a8), TBL_ENTRY(0x9a9), TBL_ENTRY(0x9aa), TBL_ENTRY(0x9ab), + TBL_ENTRY(0x9ac), TBL_ENTRY(0x9ad), TBL_ENTRY(0x9ae), TBL_ENTRY(0x9af), + TBL_ENTRY(0x9b0), TBL_ENTRY(0x9b1), TBL_ENTRY(0x9b2), TBL_ENTRY(0x9b3), + TBL_ENTRY(0x9b4), TBL_ENTRY(0x9b5), TBL_ENTRY(0x9b6), TBL_ENTRY(0x9b7), + TBL_ENTRY(0x9b8), TBL_ENTRY(0x9b9), TBL_ENTRY(0x9ba), TBL_ENTRY(0x9bb), + TBL_ENTRY(0x9bc), TBL_ENTRY(0x9bd), TBL_ENTRY(0x9be), TBL_ENTRY(0x9bf), + TBL_ENTRY(0x9c0), TBL_ENTRY(0x9c1), TBL_ENTRY(0x9c2), TBL_ENTRY(0x9c3), + TBL_ENTRY(0x9c4), TBL_ENTRY(0x9c5), TBL_ENTRY(0x9c6), TBL_ENTRY(0x9c7), + TBL_ENTRY(0x9c8), TBL_ENTRY(0x9c9), TBL_ENTRY(0x9ca), TBL_ENTRY(0x9cb), + TBL_ENTRY(0x9cc), TBL_ENTRY(0x9cd), TBL_ENTRY(0x9ce), TBL_ENTRY(0x9cf), + TBL_ENTRY(0x9d0), TBL_ENTRY(0x9d1), TBL_ENTRY(0x9d2), TBL_ENTRY(0x9d3), + TBL_ENTRY(0x9d4), TBL_ENTRY(0x9d5), TBL_ENTRY(0x9d6), TBL_ENTRY(0x9d7), + TBL_ENTRY(0x9d8), TBL_ENTRY(0x9d9), TBL_ENTRY(0x9da), TBL_ENTRY(0x9db), + TBL_ENTRY(0x9dc), TBL_ENTRY(0x9dd), TBL_ENTRY(0x9de), TBL_ENTRY(0x9df), + TBL_ENTRY(0x9e0), TBL_ENTRY(0x9e1), TBL_ENTRY(0x9e2), TBL_ENTRY(0x9e3), + TBL_ENTRY(0x9e4), TBL_ENTRY(0x9e5), TBL_ENTRY(0x9e6), TBL_ENTRY(0x9e7), + TBL_ENTRY(0x9e8), TBL_ENTRY(0x9e9), TBL_ENTRY(0x9ea), TBL_ENTRY(0x9eb), + TBL_ENTRY(0x9ec), TBL_ENTRY(0x9ed), TBL_ENTRY(0x9ee), TBL_ENTRY(0x9ef), + TBL_ENTRY(0x9f0), TBL_ENTRY(0x9f1), TBL_ENTRY(0x9f2), TBL_ENTRY(0x9f3), + TBL_ENTRY(0x9f4), TBL_ENTRY(0x9f5), TBL_ENTRY(0x9f6), TBL_ENTRY(0x9f7), + TBL_ENTRY(0x9f8), TBL_ENTRY(0x9f9), TBL_ENTRY(0x9fa), TBL_ENTRY(0x9fb), + TBL_ENTRY(0x9fc), TBL_ENTRY(0x9fd), TBL_ENTRY(0x9fe), TBL_ENTRY(0x9ff), + TBL_ENTRY(0xa00), TBL_ENTRY(0xa01), TBL_ENTRY(0xa02), TBL_ENTRY(0xa03), + TBL_ENTRY(0xa04), TBL_ENTRY(0xa05), TBL_ENTRY(0xa06), TBL_ENTRY(0xa07), + TBL_ENTRY(0xa08), TBL_ENTRY(0xa09), TBL_ENTRY(0xa0a), TBL_ENTRY(0xa0b), + TBL_ENTRY(0xa0c), TBL_ENTRY(0xa0d), TBL_ENTRY(0xa0e), TBL_ENTRY(0xa0f), + TBL_ENTRY(0xa10), TBL_ENTRY(0xa11), TBL_ENTRY(0xa12), TBL_ENTRY(0xa13), + TBL_ENTRY(0xa14), TBL_ENTRY(0xa15), TBL_ENTRY(0xa16), TBL_ENTRY(0xa17), + TBL_ENTRY(0xa18), TBL_ENTRY(0xa19), TBL_ENTRY(0xa1a), TBL_ENTRY(0xa1b), + TBL_ENTRY(0xa1c), TBL_ENTRY(0xa1d), TBL_ENTRY(0xa1e), TBL_ENTRY(0xa1f), + TBL_ENTRY(0xa20), TBL_ENTRY(0xa21), TBL_ENTRY(0xa22), TBL_ENTRY(0xa23), + TBL_ENTRY(0xa24), TBL_ENTRY(0xa25), TBL_ENTRY(0xa26), TBL_ENTRY(0xa27), + TBL_ENTRY(0xa28), TBL_ENTRY(0xa29), TBL_ENTRY(0xa2a), TBL_ENTRY(0xa2b), + TBL_ENTRY(0xa2c), TBL_ENTRY(0xa2d), TBL_ENTRY(0xa2e), TBL_ENTRY(0xa2f), + TBL_ENTRY(0xa30), TBL_ENTRY(0xa31), TBL_ENTRY(0xa32), TBL_ENTRY(0xa33), + TBL_ENTRY(0xa34), TBL_ENTRY(0xa35), TBL_ENTRY(0xa36), TBL_ENTRY(0xa37), + TBL_ENTRY(0xa38), TBL_ENTRY(0xa39), TBL_ENTRY(0xa3a), TBL_ENTRY(0xa3b), + TBL_ENTRY(0xa3c), TBL_ENTRY(0xa3d), TBL_ENTRY(0xa3e), TBL_ENTRY(0xa3f), + TBL_ENTRY(0xa40), TBL_ENTRY(0xa41), TBL_ENTRY(0xa42), TBL_ENTRY(0xa43), + TBL_ENTRY(0xa44), TBL_ENTRY(0xa45), TBL_ENTRY(0xa46), TBL_ENTRY(0xa47), + TBL_ENTRY(0xa48), TBL_ENTRY(0xa49), TBL_ENTRY(0xa4a), TBL_ENTRY(0xa4b), + TBL_ENTRY(0xa4c), TBL_ENTRY(0xa4d), TBL_ENTRY(0xa4e), TBL_ENTRY(0xa4f), + TBL_ENTRY(0xa50), TBL_ENTRY(0xa51), TBL_ENTRY(0xa52), TBL_ENTRY(0xa53), + TBL_ENTRY(0xa54), TBL_ENTRY(0xa55), TBL_ENTRY(0xa56), TBL_ENTRY(0xa57), + TBL_ENTRY(0xa58), TBL_ENTRY(0xa59), TBL_ENTRY(0xa5a), TBL_ENTRY(0xa5b), + TBL_ENTRY(0xa5c), TBL_ENTRY(0xa5d), TBL_ENTRY(0xa5e), TBL_ENTRY(0xa5f), + TBL_ENTRY(0xa60), TBL_ENTRY(0xa61), TBL_ENTRY(0xa62), TBL_ENTRY(0xa63), + TBL_ENTRY(0xa64), TBL_ENTRY(0xa65), TBL_ENTRY(0xa66), TBL_ENTRY(0xa67), + TBL_ENTRY(0xa68), TBL_ENTRY(0xa69), TBL_ENTRY(0xa6a), TBL_ENTRY(0xa6b), + TBL_ENTRY(0xa6c), TBL_ENTRY(0xa6d), TBL_ENTRY(0xa6e), TBL_ENTRY(0xa6f), + TBL_ENTRY(0xa70), TBL_ENTRY(0xa71), TBL_ENTRY(0xa72), TBL_ENTRY(0xa73), + TBL_ENTRY(0xa74), TBL_ENTRY(0xa75), TBL_ENTRY(0xa76), TBL_ENTRY(0xa77), + TBL_ENTRY(0xa78), TBL_ENTRY(0xa79), TBL_ENTRY(0xa7a), TBL_ENTRY(0xa7b), + TBL_ENTRY(0xa7c), TBL_ENTRY(0xa7d), TBL_ENTRY(0xa7e), TBL_ENTRY(0xa7f), + TBL_ENTRY(0xa80), TBL_ENTRY(0xa81), TBL_ENTRY(0xa82), TBL_ENTRY(0xa83), + TBL_ENTRY(0xa84), TBL_ENTRY(0xa85), TBL_ENTRY(0xa86), TBL_ENTRY(0xa87), + TBL_ENTRY(0xa88), TBL_ENTRY(0xa89), TBL_ENTRY(0xa8a), TBL_ENTRY(0xa8b), + TBL_ENTRY(0xa8c), TBL_ENTRY(0xa8d), TBL_ENTRY(0xa8e), TBL_ENTRY(0xa8f), + TBL_ENTRY(0xa90), TBL_ENTRY(0xa91), TBL_ENTRY(0xa92), TBL_ENTRY(0xa93), + TBL_ENTRY(0xa94), TBL_ENTRY(0xa95), TBL_ENTRY(0xa96), TBL_ENTRY(0xa97), + TBL_ENTRY(0xa98), TBL_ENTRY(0xa99), TBL_ENTRY(0xa9a), TBL_ENTRY(0xa9b), + TBL_ENTRY(0xa9c), TBL_ENTRY(0xa9d), TBL_ENTRY(0xa9e), TBL_ENTRY(0xa9f), + TBL_ENTRY(0xaa0), TBL_ENTRY(0xaa1), TBL_ENTRY(0xaa2), TBL_ENTRY(0xaa3), + TBL_ENTRY(0xaa4), TBL_ENTRY(0xaa5), TBL_ENTRY(0xaa6), TBL_ENTRY(0xaa7), + TBL_ENTRY(0xaa8), TBL_ENTRY(0xaa9), TBL_ENTRY(0xaaa), TBL_ENTRY(0xaab), + TBL_ENTRY(0xaac), TBL_ENTRY(0xaad), TBL_ENTRY(0xaae), TBL_ENTRY(0xaaf), + TBL_ENTRY(0xab0), TBL_ENTRY(0xab1), TBL_ENTRY(0xab2), TBL_ENTRY(0xab3), + TBL_ENTRY(0xab4), TBL_ENTRY(0xab5), TBL_ENTRY(0xab6), TBL_ENTRY(0xab7), + TBL_ENTRY(0xab8), TBL_ENTRY(0xab9), TBL_ENTRY(0xaba), TBL_ENTRY(0xabb), + TBL_ENTRY(0xabc), TBL_ENTRY(0xabd), TBL_ENTRY(0xabe), TBL_ENTRY(0xabf), + TBL_ENTRY(0xac0), TBL_ENTRY(0xac1), TBL_ENTRY(0xac2), TBL_ENTRY(0xac3), + TBL_ENTRY(0xac4), TBL_ENTRY(0xac5), TBL_ENTRY(0xac6), TBL_ENTRY(0xac7), + TBL_ENTRY(0xac8), TBL_ENTRY(0xac9), TBL_ENTRY(0xaca), TBL_ENTRY(0xacb), + TBL_ENTRY(0xacc), TBL_ENTRY(0xacd), TBL_ENTRY(0xace), TBL_ENTRY(0xacf), + TBL_ENTRY(0xad0), TBL_ENTRY(0xad1), TBL_ENTRY(0xad2), TBL_ENTRY(0xad3), + TBL_ENTRY(0xad4), TBL_ENTRY(0xad5), TBL_ENTRY(0xad6), TBL_ENTRY(0xad7), + TBL_ENTRY(0xad8), TBL_ENTRY(0xad9), TBL_ENTRY(0xada), TBL_ENTRY(0xadb), + TBL_ENTRY(0xadc), TBL_ENTRY(0xadd), TBL_ENTRY(0xade), TBL_ENTRY(0xadf), + TBL_ENTRY(0xae0), TBL_ENTRY(0xae1), TBL_ENTRY(0xae2), TBL_ENTRY(0xae3), + TBL_ENTRY(0xae4), TBL_ENTRY(0xae5), TBL_ENTRY(0xae6), TBL_ENTRY(0xae7), + TBL_ENTRY(0xae8), TBL_ENTRY(0xae9), TBL_ENTRY(0xaea), TBL_ENTRY(0xaeb), + TBL_ENTRY(0xaec), TBL_ENTRY(0xaed), TBL_ENTRY(0xaee), TBL_ENTRY(0xaef), + TBL_ENTRY(0xaf0), TBL_ENTRY(0xaf1), TBL_ENTRY(0xaf2), TBL_ENTRY(0xaf3), + TBL_ENTRY(0xaf4), TBL_ENTRY(0xaf5), TBL_ENTRY(0xaf6), TBL_ENTRY(0xaf7), + TBL_ENTRY(0xaf8), TBL_ENTRY(0xaf9), TBL_ENTRY(0xafa), TBL_ENTRY(0xafb), + TBL_ENTRY(0xafc), TBL_ENTRY(0xafd), TBL_ENTRY(0xafe), TBL_ENTRY(0xaff), + TBL_ENTRY(0xb00), TBL_ENTRY(0xb01), TBL_ENTRY(0xb02), TBL_ENTRY(0xb03), + TBL_ENTRY(0xb04), TBL_ENTRY(0xb05), TBL_ENTRY(0xb06), TBL_ENTRY(0xb07), + TBL_ENTRY(0xb08), TBL_ENTRY(0xb09), TBL_ENTRY(0xb0a), TBL_ENTRY(0xb0b), + TBL_ENTRY(0xb0c), TBL_ENTRY(0xb0d), TBL_ENTRY(0xb0e), TBL_ENTRY(0xb0f), + TBL_ENTRY(0xb10), TBL_ENTRY(0xb11), TBL_ENTRY(0xb12), TBL_ENTRY(0xb13), + TBL_ENTRY(0xb14), TBL_ENTRY(0xb15), TBL_ENTRY(0xb16), TBL_ENTRY(0xb17), + TBL_ENTRY(0xb18), TBL_ENTRY(0xb19), TBL_ENTRY(0xb1a), TBL_ENTRY(0xb1b), + TBL_ENTRY(0xb1c), TBL_ENTRY(0xb1d), TBL_ENTRY(0xb1e), TBL_ENTRY(0xb1f), + TBL_ENTRY(0xb20), TBL_ENTRY(0xb21), TBL_ENTRY(0xb22), TBL_ENTRY(0xb23), + TBL_ENTRY(0xb24), TBL_ENTRY(0xb25), TBL_ENTRY(0xb26), TBL_ENTRY(0xb27), + TBL_ENTRY(0xb28), TBL_ENTRY(0xb29), TBL_ENTRY(0xb2a), TBL_ENTRY(0xb2b), + TBL_ENTRY(0xb2c), TBL_ENTRY(0xb2d), TBL_ENTRY(0xb2e), TBL_ENTRY(0xb2f), + TBL_ENTRY(0xb30), TBL_ENTRY(0xb31), TBL_ENTRY(0xb32), TBL_ENTRY(0xb33), + TBL_ENTRY(0xb34), TBL_ENTRY(0xb35), TBL_ENTRY(0xb36), TBL_ENTRY(0xb37), + TBL_ENTRY(0xb38), TBL_ENTRY(0xb39), TBL_ENTRY(0xb3a), TBL_ENTRY(0xb3b), + TBL_ENTRY(0xb3c), TBL_ENTRY(0xb3d), TBL_ENTRY(0xb3e), TBL_ENTRY(0xb3f), + TBL_ENTRY(0xb40), TBL_ENTRY(0xb41), TBL_ENTRY(0xb42), TBL_ENTRY(0xb43), + TBL_ENTRY(0xb44), TBL_ENTRY(0xb45), TBL_ENTRY(0xb46), TBL_ENTRY(0xb47), + TBL_ENTRY(0xb48), TBL_ENTRY(0xb49), TBL_ENTRY(0xb4a), TBL_ENTRY(0xb4b), + TBL_ENTRY(0xb4c), TBL_ENTRY(0xb4d), TBL_ENTRY(0xb4e), TBL_ENTRY(0xb4f), + TBL_ENTRY(0xb50), TBL_ENTRY(0xb51), TBL_ENTRY(0xb52), TBL_ENTRY(0xb53), + TBL_ENTRY(0xb54), TBL_ENTRY(0xb55), TBL_ENTRY(0xb56), TBL_ENTRY(0xb57), + TBL_ENTRY(0xb58), TBL_ENTRY(0xb59), TBL_ENTRY(0xb5a), TBL_ENTRY(0xb5b), + TBL_ENTRY(0xb5c), TBL_ENTRY(0xb5d), TBL_ENTRY(0xb5e), TBL_ENTRY(0xb5f), + TBL_ENTRY(0xb60), TBL_ENTRY(0xb61), TBL_ENTRY(0xb62), TBL_ENTRY(0xb63), + TBL_ENTRY(0xb64), TBL_ENTRY(0xb65), TBL_ENTRY(0xb66), TBL_ENTRY(0xb67), + TBL_ENTRY(0xb68), TBL_ENTRY(0xb69), TBL_ENTRY(0xb6a), TBL_ENTRY(0xb6b), + TBL_ENTRY(0xb6c), TBL_ENTRY(0xb6d), TBL_ENTRY(0xb6e), TBL_ENTRY(0xb6f), + TBL_ENTRY(0xb70), TBL_ENTRY(0xb71), TBL_ENTRY(0xb72), TBL_ENTRY(0xb73), + TBL_ENTRY(0xb74), TBL_ENTRY(0xb75), TBL_ENTRY(0xb76), TBL_ENTRY(0xb77), + TBL_ENTRY(0xb78), TBL_ENTRY(0xb79), TBL_ENTRY(0xb7a), TBL_ENTRY(0xb7b), + TBL_ENTRY(0xb7c), TBL_ENTRY(0xb7d), TBL_ENTRY(0xb7e), TBL_ENTRY(0xb7f), + TBL_ENTRY(0xb80), TBL_ENTRY(0xb81), TBL_ENTRY(0xb82), TBL_ENTRY(0xb83), + TBL_ENTRY(0xb84), TBL_ENTRY(0xb85), TBL_ENTRY(0xb86), TBL_ENTRY(0xb87), + TBL_ENTRY(0xb88), TBL_ENTRY(0xb89), TBL_ENTRY(0xb8a), TBL_ENTRY(0xb8b), + TBL_ENTRY(0xb8c), TBL_ENTRY(0xb8d), TBL_ENTRY(0xb8e), TBL_ENTRY(0xb8f), + TBL_ENTRY(0xb90), TBL_ENTRY(0xb91), TBL_ENTRY(0xb92), TBL_ENTRY(0xb93), + TBL_ENTRY(0xb94), TBL_ENTRY(0xb95), TBL_ENTRY(0xb96), TBL_ENTRY(0xb97), + TBL_ENTRY(0xb98), TBL_ENTRY(0xb99), TBL_ENTRY(0xb9a), TBL_ENTRY(0xb9b), + TBL_ENTRY(0xb9c), TBL_ENTRY(0xb9d), TBL_ENTRY(0xb9e), TBL_ENTRY(0xb9f), + TBL_ENTRY(0xba0), TBL_ENTRY(0xba1), TBL_ENTRY(0xba2), TBL_ENTRY(0xba3), + TBL_ENTRY(0xba4), TBL_ENTRY(0xba5), TBL_ENTRY(0xba6), TBL_ENTRY(0xba7), + TBL_ENTRY(0xba8), TBL_ENTRY(0xba9), TBL_ENTRY(0xbaa), TBL_ENTRY(0xbab), + TBL_ENTRY(0xbac), TBL_ENTRY(0xbad), TBL_ENTRY(0xbae), TBL_ENTRY(0xbaf), + TBL_ENTRY(0xbb0), TBL_ENTRY(0xbb1), TBL_ENTRY(0xbb2), TBL_ENTRY(0xbb3), + TBL_ENTRY(0xbb4), TBL_ENTRY(0xbb5), TBL_ENTRY(0xbb6), TBL_ENTRY(0xbb7), + TBL_ENTRY(0xbb8), TBL_ENTRY(0xbb9), TBL_ENTRY(0xbba), TBL_ENTRY(0xbbb), + TBL_ENTRY(0xbbc), TBL_ENTRY(0xbbd), TBL_ENTRY(0xbbe), TBL_ENTRY(0xbbf), + TBL_ENTRY(0xbc0), TBL_ENTRY(0xbc1), TBL_ENTRY(0xbc2), TBL_ENTRY(0xbc3), + TBL_ENTRY(0xbc4), TBL_ENTRY(0xbc5), TBL_ENTRY(0xbc6), TBL_ENTRY(0xbc7), + TBL_ENTRY(0xbc8), TBL_ENTRY(0xbc9), TBL_ENTRY(0xbca), TBL_ENTRY(0xbcb), + TBL_ENTRY(0xbcc), TBL_ENTRY(0xbcd), TBL_ENTRY(0xbce), TBL_ENTRY(0xbcf), + TBL_ENTRY(0xbd0), TBL_ENTRY(0xbd1), TBL_ENTRY(0xbd2), TBL_ENTRY(0xbd3), + TBL_ENTRY(0xbd4), TBL_ENTRY(0xbd5), TBL_ENTRY(0xbd6), TBL_ENTRY(0xbd7), + TBL_ENTRY(0xbd8), TBL_ENTRY(0xbd9), TBL_ENTRY(0xbda), TBL_ENTRY(0xbdb), + TBL_ENTRY(0xbdc), TBL_ENTRY(0xbdd), TBL_ENTRY(0xbde), TBL_ENTRY(0xbdf), + TBL_ENTRY(0xbe0), TBL_ENTRY(0xbe1), TBL_ENTRY(0xbe2), TBL_ENTRY(0xbe3), + TBL_ENTRY(0xbe4), TBL_ENTRY(0xbe5), TBL_ENTRY(0xbe6), TBL_ENTRY(0xbe7), + TBL_ENTRY(0xbe8), TBL_ENTRY(0xbe9), TBL_ENTRY(0xbea), TBL_ENTRY(0xbeb), + TBL_ENTRY(0xbec), TBL_ENTRY(0xbed), TBL_ENTRY(0xbee), TBL_ENTRY(0xbef), + TBL_ENTRY(0xbf0), TBL_ENTRY(0xbf1), TBL_ENTRY(0xbf2), TBL_ENTRY(0xbf3), + TBL_ENTRY(0xbf4), TBL_ENTRY(0xbf5), TBL_ENTRY(0xbf6), TBL_ENTRY(0xbf7), + TBL_ENTRY(0xbf8), TBL_ENTRY(0xbf9), TBL_ENTRY(0xbfa), TBL_ENTRY(0xbfb), + TBL_ENTRY(0xbfc), TBL_ENTRY(0xbfd), TBL_ENTRY(0xbfe), TBL_ENTRY(0xbff), + TBL_ENTRY(0xc00), TBL_ENTRY(0xc01), TBL_ENTRY(0xc02), TBL_ENTRY(0xc03), + TBL_ENTRY(0xc04), TBL_ENTRY(0xc05), TBL_ENTRY(0xc06), TBL_ENTRY(0xc07), + TBL_ENTRY(0xc08), TBL_ENTRY(0xc09), TBL_ENTRY(0xc0a), TBL_ENTRY(0xc0b), + TBL_ENTRY(0xc0c), TBL_ENTRY(0xc0d), TBL_ENTRY(0xc0e), TBL_ENTRY(0xc0f), + TBL_ENTRY(0xc10), TBL_ENTRY(0xc11), TBL_ENTRY(0xc12), TBL_ENTRY(0xc13), + TBL_ENTRY(0xc14), TBL_ENTRY(0xc15), TBL_ENTRY(0xc16), TBL_ENTRY(0xc17), + TBL_ENTRY(0xc18), TBL_ENTRY(0xc19), TBL_ENTRY(0xc1a), TBL_ENTRY(0xc1b), + TBL_ENTRY(0xc1c), TBL_ENTRY(0xc1d), TBL_ENTRY(0xc1e), TBL_ENTRY(0xc1f), + TBL_ENTRY(0xc20), TBL_ENTRY(0xc21), TBL_ENTRY(0xc22), TBL_ENTRY(0xc23), + TBL_ENTRY(0xc24), TBL_ENTRY(0xc25), TBL_ENTRY(0xc26), TBL_ENTRY(0xc27), + TBL_ENTRY(0xc28), TBL_ENTRY(0xc29), TBL_ENTRY(0xc2a), TBL_ENTRY(0xc2b), + TBL_ENTRY(0xc2c), TBL_ENTRY(0xc2d), TBL_ENTRY(0xc2e), TBL_ENTRY(0xc2f), + TBL_ENTRY(0xc30), TBL_ENTRY(0xc31), TBL_ENTRY(0xc32), TBL_ENTRY(0xc33), + TBL_ENTRY(0xc34), TBL_ENTRY(0xc35), TBL_ENTRY(0xc36), TBL_ENTRY(0xc37), + TBL_ENTRY(0xc38), TBL_ENTRY(0xc39), TBL_ENTRY(0xc3a), TBL_ENTRY(0xc3b), + TBL_ENTRY(0xc3c), TBL_ENTRY(0xc3d), TBL_ENTRY(0xc3e), TBL_ENTRY(0xc3f), + TBL_ENTRY(0xc40), TBL_ENTRY(0xc41), TBL_ENTRY(0xc42), TBL_ENTRY(0xc43), + TBL_ENTRY(0xc44), TBL_ENTRY(0xc45), TBL_ENTRY(0xc46), TBL_ENTRY(0xc47), + TBL_ENTRY(0xc48), TBL_ENTRY(0xc49), TBL_ENTRY(0xc4a), TBL_ENTRY(0xc4b), + TBL_ENTRY(0xc4c), TBL_ENTRY(0xc4d), TBL_ENTRY(0xc4e), TBL_ENTRY(0xc4f), + TBL_ENTRY(0xc50), TBL_ENTRY(0xc51), TBL_ENTRY(0xc52), TBL_ENTRY(0xc53), + TBL_ENTRY(0xc54), TBL_ENTRY(0xc55), TBL_ENTRY(0xc56), TBL_ENTRY(0xc57), + TBL_ENTRY(0xc58), TBL_ENTRY(0xc59), TBL_ENTRY(0xc5a), TBL_ENTRY(0xc5b), + TBL_ENTRY(0xc5c), TBL_ENTRY(0xc5d), TBL_ENTRY(0xc5e), TBL_ENTRY(0xc5f), + TBL_ENTRY(0xc60), TBL_ENTRY(0xc61), TBL_ENTRY(0xc62), TBL_ENTRY(0xc63), + TBL_ENTRY(0xc64), TBL_ENTRY(0xc65), TBL_ENTRY(0xc66), TBL_ENTRY(0xc67), + TBL_ENTRY(0xc68), TBL_ENTRY(0xc69), TBL_ENTRY(0xc6a), TBL_ENTRY(0xc6b), + TBL_ENTRY(0xc6c), TBL_ENTRY(0xc6d), TBL_ENTRY(0xc6e), TBL_ENTRY(0xc6f), + TBL_ENTRY(0xc70), TBL_ENTRY(0xc71), TBL_ENTRY(0xc72), TBL_ENTRY(0xc73), + TBL_ENTRY(0xc74), TBL_ENTRY(0xc75), TBL_ENTRY(0xc76), TBL_ENTRY(0xc77), + TBL_ENTRY(0xc78), TBL_ENTRY(0xc79), TBL_ENTRY(0xc7a), TBL_ENTRY(0xc7b), + TBL_ENTRY(0xc7c), TBL_ENTRY(0xc7d), TBL_ENTRY(0xc7e), TBL_ENTRY(0xc7f), + TBL_ENTRY(0xc80), TBL_ENTRY(0xc81), TBL_ENTRY(0xc82), TBL_ENTRY(0xc83), + TBL_ENTRY(0xc84), TBL_ENTRY(0xc85), TBL_ENTRY(0xc86), TBL_ENTRY(0xc87), + TBL_ENTRY(0xc88), TBL_ENTRY(0xc89), TBL_ENTRY(0xc8a), TBL_ENTRY(0xc8b), + TBL_ENTRY(0xc8c), TBL_ENTRY(0xc8d), TBL_ENTRY(0xc8e), TBL_ENTRY(0xc8f), + TBL_ENTRY(0xc90), TBL_ENTRY(0xc91), TBL_ENTRY(0xc92), TBL_ENTRY(0xc93), + TBL_ENTRY(0xc94), TBL_ENTRY(0xc95), TBL_ENTRY(0xc96), TBL_ENTRY(0xc97), + TBL_ENTRY(0xc98), TBL_ENTRY(0xc99), TBL_ENTRY(0xc9a), TBL_ENTRY(0xc9b), + TBL_ENTRY(0xc9c), TBL_ENTRY(0xc9d), TBL_ENTRY(0xc9e), TBL_ENTRY(0xc9f), + TBL_ENTRY(0xca0), TBL_ENTRY(0xca1), TBL_ENTRY(0xca2), TBL_ENTRY(0xca3), + TBL_ENTRY(0xca4), TBL_ENTRY(0xca5), TBL_ENTRY(0xca6), TBL_ENTRY(0xca7), + TBL_ENTRY(0xca8), TBL_ENTRY(0xca9), TBL_ENTRY(0xcaa), TBL_ENTRY(0xcab), + TBL_ENTRY(0xcac), TBL_ENTRY(0xcad), TBL_ENTRY(0xcae), TBL_ENTRY(0xcaf), + TBL_ENTRY(0xcb0), TBL_ENTRY(0xcb1), TBL_ENTRY(0xcb2), TBL_ENTRY(0xcb3), + TBL_ENTRY(0xcb4), TBL_ENTRY(0xcb5), TBL_ENTRY(0xcb6), TBL_ENTRY(0xcb7), + TBL_ENTRY(0xcb8), TBL_ENTRY(0xcb9), TBL_ENTRY(0xcba), TBL_ENTRY(0xcbb), + TBL_ENTRY(0xcbc), TBL_ENTRY(0xcbd), TBL_ENTRY(0xcbe), TBL_ENTRY(0xcbf), + TBL_ENTRY(0xcc0), TBL_ENTRY(0xcc1), TBL_ENTRY(0xcc2), TBL_ENTRY(0xcc3), + TBL_ENTRY(0xcc4), TBL_ENTRY(0xcc5), TBL_ENTRY(0xcc6), TBL_ENTRY(0xcc7), + TBL_ENTRY(0xcc8), TBL_ENTRY(0xcc9), TBL_ENTRY(0xcca), TBL_ENTRY(0xccb), + TBL_ENTRY(0xccc), TBL_ENTRY(0xccd), TBL_ENTRY(0xcce), TBL_ENTRY(0xccf), + TBL_ENTRY(0xcd0), TBL_ENTRY(0xcd1), TBL_ENTRY(0xcd2), TBL_ENTRY(0xcd3), + TBL_ENTRY(0xcd4), TBL_ENTRY(0xcd5), TBL_ENTRY(0xcd6), TBL_ENTRY(0xcd7), + TBL_ENTRY(0xcd8), TBL_ENTRY(0xcd9), TBL_ENTRY(0xcda), TBL_ENTRY(0xcdb), + TBL_ENTRY(0xcdc), TBL_ENTRY(0xcdd), TBL_ENTRY(0xcde), TBL_ENTRY(0xcdf), + TBL_ENTRY(0xce0), TBL_ENTRY(0xce1), TBL_ENTRY(0xce2), TBL_ENTRY(0xce3), + TBL_ENTRY(0xce4), TBL_ENTRY(0xce5), TBL_ENTRY(0xce6), TBL_ENTRY(0xce7), + TBL_ENTRY(0xce8), TBL_ENTRY(0xce9), TBL_ENTRY(0xcea), TBL_ENTRY(0xceb), + TBL_ENTRY(0xcec), TBL_ENTRY(0xced), TBL_ENTRY(0xcee), TBL_ENTRY(0xcef), + TBL_ENTRY(0xcf0), TBL_ENTRY(0xcf1), TBL_ENTRY(0xcf2), TBL_ENTRY(0xcf3), + TBL_ENTRY(0xcf4), TBL_ENTRY(0xcf5), TBL_ENTRY(0xcf6), TBL_ENTRY(0xcf7), + TBL_ENTRY(0xcf8), TBL_ENTRY(0xcf9), TBL_ENTRY(0xcfa), TBL_ENTRY(0xcfb), + TBL_ENTRY(0xcfc), TBL_ENTRY(0xcfd), TBL_ENTRY(0xcfe), TBL_ENTRY(0xcff), + TBL_ENTRY(0xd00), TBL_ENTRY(0xd01), TBL_ENTRY(0xd02), TBL_ENTRY(0xd03), + TBL_ENTRY(0xd04), TBL_ENTRY(0xd05), TBL_ENTRY(0xd06), TBL_ENTRY(0xd07), + TBL_ENTRY(0xd08), TBL_ENTRY(0xd09), TBL_ENTRY(0xd0a), TBL_ENTRY(0xd0b), + TBL_ENTRY(0xd0c), TBL_ENTRY(0xd0d), TBL_ENTRY(0xd0e), TBL_ENTRY(0xd0f), + TBL_ENTRY(0xd10), TBL_ENTRY(0xd11), TBL_ENTRY(0xd12), TBL_ENTRY(0xd13), + TBL_ENTRY(0xd14), TBL_ENTRY(0xd15), TBL_ENTRY(0xd16), TBL_ENTRY(0xd17), + TBL_ENTRY(0xd18), TBL_ENTRY(0xd19), TBL_ENTRY(0xd1a), TBL_ENTRY(0xd1b), + TBL_ENTRY(0xd1c), TBL_ENTRY(0xd1d), TBL_ENTRY(0xd1e), TBL_ENTRY(0xd1f), + TBL_ENTRY(0xd20), TBL_ENTRY(0xd21), TBL_ENTRY(0xd22), TBL_ENTRY(0xd23), + TBL_ENTRY(0xd24), TBL_ENTRY(0xd25), TBL_ENTRY(0xd26), TBL_ENTRY(0xd27), + TBL_ENTRY(0xd28), TBL_ENTRY(0xd29), TBL_ENTRY(0xd2a), TBL_ENTRY(0xd2b), + TBL_ENTRY(0xd2c), TBL_ENTRY(0xd2d), TBL_ENTRY(0xd2e), TBL_ENTRY(0xd2f), + TBL_ENTRY(0xd30), TBL_ENTRY(0xd31), TBL_ENTRY(0xd32), TBL_ENTRY(0xd33), + TBL_ENTRY(0xd34), TBL_ENTRY(0xd35), TBL_ENTRY(0xd36), TBL_ENTRY(0xd37), + TBL_ENTRY(0xd38), TBL_ENTRY(0xd39), TBL_ENTRY(0xd3a), TBL_ENTRY(0xd3b), + TBL_ENTRY(0xd3c), TBL_ENTRY(0xd3d), TBL_ENTRY(0xd3e), TBL_ENTRY(0xd3f), + TBL_ENTRY(0xd40), TBL_ENTRY(0xd41), TBL_ENTRY(0xd42), TBL_ENTRY(0xd43), + TBL_ENTRY(0xd44), TBL_ENTRY(0xd45), TBL_ENTRY(0xd46), TBL_ENTRY(0xd47), + TBL_ENTRY(0xd48), TBL_ENTRY(0xd49), TBL_ENTRY(0xd4a), TBL_ENTRY(0xd4b), + TBL_ENTRY(0xd4c), TBL_ENTRY(0xd4d), TBL_ENTRY(0xd4e), TBL_ENTRY(0xd4f), + TBL_ENTRY(0xd50), TBL_ENTRY(0xd51), TBL_ENTRY(0xd52), TBL_ENTRY(0xd53), + TBL_ENTRY(0xd54), TBL_ENTRY(0xd55), TBL_ENTRY(0xd56), TBL_ENTRY(0xd57), + TBL_ENTRY(0xd58), TBL_ENTRY(0xd59), TBL_ENTRY(0xd5a), TBL_ENTRY(0xd5b), + TBL_ENTRY(0xd5c), TBL_ENTRY(0xd5d), TBL_ENTRY(0xd5e), TBL_ENTRY(0xd5f), + TBL_ENTRY(0xd60), TBL_ENTRY(0xd61), TBL_ENTRY(0xd62), TBL_ENTRY(0xd63), + TBL_ENTRY(0xd64), TBL_ENTRY(0xd65), TBL_ENTRY(0xd66), TBL_ENTRY(0xd67), + TBL_ENTRY(0xd68), TBL_ENTRY(0xd69), TBL_ENTRY(0xd6a), TBL_ENTRY(0xd6b), + TBL_ENTRY(0xd6c), TBL_ENTRY(0xd6d), TBL_ENTRY(0xd6e), TBL_ENTRY(0xd6f), + TBL_ENTRY(0xd70), TBL_ENTRY(0xd71), TBL_ENTRY(0xd72), TBL_ENTRY(0xd73), + TBL_ENTRY(0xd74), TBL_ENTRY(0xd75), TBL_ENTRY(0xd76), TBL_ENTRY(0xd77), + TBL_ENTRY(0xd78), TBL_ENTRY(0xd79), TBL_ENTRY(0xd7a), TBL_ENTRY(0xd7b), + TBL_ENTRY(0xd7c), TBL_ENTRY(0xd7d), TBL_ENTRY(0xd7e), TBL_ENTRY(0xd7f), + TBL_ENTRY(0xd80), TBL_ENTRY(0xd81), TBL_ENTRY(0xd82), TBL_ENTRY(0xd83), + TBL_ENTRY(0xd84), TBL_ENTRY(0xd85), TBL_ENTRY(0xd86), TBL_ENTRY(0xd87), + TBL_ENTRY(0xd88), TBL_ENTRY(0xd89), TBL_ENTRY(0xd8a), TBL_ENTRY(0xd8b), + TBL_ENTRY(0xd8c), TBL_ENTRY(0xd8d), TBL_ENTRY(0xd8e), TBL_ENTRY(0xd8f), + TBL_ENTRY(0xd90), TBL_ENTRY(0xd91), TBL_ENTRY(0xd92), TBL_ENTRY(0xd93), + TBL_ENTRY(0xd94), TBL_ENTRY(0xd95), TBL_ENTRY(0xd96), TBL_ENTRY(0xd97), + TBL_ENTRY(0xd98), TBL_ENTRY(0xd99), TBL_ENTRY(0xd9a), TBL_ENTRY(0xd9b), + TBL_ENTRY(0xd9c), TBL_ENTRY(0xd9d), TBL_ENTRY(0xd9e), TBL_ENTRY(0xd9f), + TBL_ENTRY(0xda0), TBL_ENTRY(0xda1), TBL_ENTRY(0xda2), TBL_ENTRY(0xda3), + TBL_ENTRY(0xda4), TBL_ENTRY(0xda5), TBL_ENTRY(0xda6), TBL_ENTRY(0xda7), + TBL_ENTRY(0xda8), TBL_ENTRY(0xda9), TBL_ENTRY(0xdaa), TBL_ENTRY(0xdab), + TBL_ENTRY(0xdac), TBL_ENTRY(0xdad), TBL_ENTRY(0xdae), TBL_ENTRY(0xdaf), + TBL_ENTRY(0xdb0), TBL_ENTRY(0xdb1), TBL_ENTRY(0xdb2), TBL_ENTRY(0xdb3), + TBL_ENTRY(0xdb4), TBL_ENTRY(0xdb5), TBL_ENTRY(0xdb6), TBL_ENTRY(0xdb7), + TBL_ENTRY(0xdb8), TBL_ENTRY(0xdb9), TBL_ENTRY(0xdba), TBL_ENTRY(0xdbb), + TBL_ENTRY(0xdbc), TBL_ENTRY(0xdbd), TBL_ENTRY(0xdbe), TBL_ENTRY(0xdbf), + TBL_ENTRY(0xdc0), TBL_ENTRY(0xdc1), TBL_ENTRY(0xdc2), TBL_ENTRY(0xdc3), + TBL_ENTRY(0xdc4), TBL_ENTRY(0xdc5), TBL_ENTRY(0xdc6), TBL_ENTRY(0xdc7), + TBL_ENTRY(0xdc8), TBL_ENTRY(0xdc9), TBL_ENTRY(0xdca), TBL_ENTRY(0xdcb), + TBL_ENTRY(0xdcc), TBL_ENTRY(0xdcd), TBL_ENTRY(0xdce), TBL_ENTRY(0xdcf), + TBL_ENTRY(0xdd0), TBL_ENTRY(0xdd1), TBL_ENTRY(0xdd2), TBL_ENTRY(0xdd3), + TBL_ENTRY(0xdd4), TBL_ENTRY(0xdd5), TBL_ENTRY(0xdd6), TBL_ENTRY(0xdd7), + TBL_ENTRY(0xdd8), TBL_ENTRY(0xdd9), TBL_ENTRY(0xdda), TBL_ENTRY(0xddb), + TBL_ENTRY(0xddc), TBL_ENTRY(0xddd), TBL_ENTRY(0xdde), TBL_ENTRY(0xddf), + TBL_ENTRY(0xde0), TBL_ENTRY(0xde1), TBL_ENTRY(0xde2), TBL_ENTRY(0xde3), + TBL_ENTRY(0xde4), TBL_ENTRY(0xde5), TBL_ENTRY(0xde6), TBL_ENTRY(0xde7), + TBL_ENTRY(0xde8), TBL_ENTRY(0xde9), TBL_ENTRY(0xdea), TBL_ENTRY(0xdeb), + TBL_ENTRY(0xdec), TBL_ENTRY(0xded), TBL_ENTRY(0xdee), TBL_ENTRY(0xdef), + TBL_ENTRY(0xdf0), TBL_ENTRY(0xdf1), TBL_ENTRY(0xdf2), TBL_ENTRY(0xdf3), + TBL_ENTRY(0xdf4), TBL_ENTRY(0xdf5), TBL_ENTRY(0xdf6), TBL_ENTRY(0xdf7), + TBL_ENTRY(0xdf8), TBL_ENTRY(0xdf9), TBL_ENTRY(0xdfa), TBL_ENTRY(0xdfb), + TBL_ENTRY(0xdfc), TBL_ENTRY(0xdfd), TBL_ENTRY(0xdfe), TBL_ENTRY(0xdff), + TBL_ENTRY(0xe00), TBL_ENTRY(0xe01), TBL_ENTRY(0xe02), TBL_ENTRY(0xe03), + TBL_ENTRY(0xe04), TBL_ENTRY(0xe05), TBL_ENTRY(0xe06), TBL_ENTRY(0xe07), + TBL_ENTRY(0xe08), TBL_ENTRY(0xe09), TBL_ENTRY(0xe0a), TBL_ENTRY(0xe0b), + TBL_ENTRY(0xe0c), TBL_ENTRY(0xe0d), TBL_ENTRY(0xe0e), TBL_ENTRY(0xe0f), + TBL_ENTRY(0xe10), TBL_ENTRY(0xe11), TBL_ENTRY(0xe12), TBL_ENTRY(0xe13), + TBL_ENTRY(0xe14), TBL_ENTRY(0xe15), TBL_ENTRY(0xe16), TBL_ENTRY(0xe17), + TBL_ENTRY(0xe18), TBL_ENTRY(0xe19), TBL_ENTRY(0xe1a), TBL_ENTRY(0xe1b), + TBL_ENTRY(0xe1c), TBL_ENTRY(0xe1d), TBL_ENTRY(0xe1e), TBL_ENTRY(0xe1f), + TBL_ENTRY(0xe20), TBL_ENTRY(0xe21), TBL_ENTRY(0xe22), TBL_ENTRY(0xe23), + TBL_ENTRY(0xe24), TBL_ENTRY(0xe25), TBL_ENTRY(0xe26), TBL_ENTRY(0xe27), + TBL_ENTRY(0xe28), TBL_ENTRY(0xe29), TBL_ENTRY(0xe2a), TBL_ENTRY(0xe2b), + TBL_ENTRY(0xe2c), TBL_ENTRY(0xe2d), TBL_ENTRY(0xe2e), TBL_ENTRY(0xe2f), + TBL_ENTRY(0xe30), TBL_ENTRY(0xe31), TBL_ENTRY(0xe32), TBL_ENTRY(0xe33), + TBL_ENTRY(0xe34), TBL_ENTRY(0xe35), TBL_ENTRY(0xe36), TBL_ENTRY(0xe37), + TBL_ENTRY(0xe38), TBL_ENTRY(0xe39), TBL_ENTRY(0xe3a), TBL_ENTRY(0xe3b), + TBL_ENTRY(0xe3c), TBL_ENTRY(0xe3d), TBL_ENTRY(0xe3e), TBL_ENTRY(0xe3f), + TBL_ENTRY(0xe40), TBL_ENTRY(0xe41), TBL_ENTRY(0xe42), TBL_ENTRY(0xe43), + TBL_ENTRY(0xe44), TBL_ENTRY(0xe45), TBL_ENTRY(0xe46), TBL_ENTRY(0xe47), + TBL_ENTRY(0xe48), TBL_ENTRY(0xe49), TBL_ENTRY(0xe4a), TBL_ENTRY(0xe4b), + TBL_ENTRY(0xe4c), TBL_ENTRY(0xe4d), TBL_ENTRY(0xe4e), TBL_ENTRY(0xe4f), + TBL_ENTRY(0xe50), TBL_ENTRY(0xe51), TBL_ENTRY(0xe52), TBL_ENTRY(0xe53), + TBL_ENTRY(0xe54), TBL_ENTRY(0xe55), TBL_ENTRY(0xe56), TBL_ENTRY(0xe57), + TBL_ENTRY(0xe58), TBL_ENTRY(0xe59), TBL_ENTRY(0xe5a), TBL_ENTRY(0xe5b), + TBL_ENTRY(0xe5c), TBL_ENTRY(0xe5d), TBL_ENTRY(0xe5e), TBL_ENTRY(0xe5f), + TBL_ENTRY(0xe60), TBL_ENTRY(0xe61), TBL_ENTRY(0xe62), TBL_ENTRY(0xe63), + TBL_ENTRY(0xe64), TBL_ENTRY(0xe65), TBL_ENTRY(0xe66), TBL_ENTRY(0xe67), + TBL_ENTRY(0xe68), TBL_ENTRY(0xe69), TBL_ENTRY(0xe6a), TBL_ENTRY(0xe6b), + TBL_ENTRY(0xe6c), TBL_ENTRY(0xe6d), TBL_ENTRY(0xe6e), TBL_ENTRY(0xe6f), + TBL_ENTRY(0xe70), TBL_ENTRY(0xe71), TBL_ENTRY(0xe72), TBL_ENTRY(0xe73), + TBL_ENTRY(0xe74), TBL_ENTRY(0xe75), TBL_ENTRY(0xe76), TBL_ENTRY(0xe77), + TBL_ENTRY(0xe78), TBL_ENTRY(0xe79), TBL_ENTRY(0xe7a), TBL_ENTRY(0xe7b), + TBL_ENTRY(0xe7c), TBL_ENTRY(0xe7d), TBL_ENTRY(0xe7e), TBL_ENTRY(0xe7f), + TBL_ENTRY(0xe80), TBL_ENTRY(0xe81), TBL_ENTRY(0xe82), TBL_ENTRY(0xe83), + TBL_ENTRY(0xe84), TBL_ENTRY(0xe85), TBL_ENTRY(0xe86), TBL_ENTRY(0xe87), + TBL_ENTRY(0xe88), TBL_ENTRY(0xe89), TBL_ENTRY(0xe8a), TBL_ENTRY(0xe8b), + TBL_ENTRY(0xe8c), TBL_ENTRY(0xe8d), TBL_ENTRY(0xe8e), TBL_ENTRY(0xe8f), + TBL_ENTRY(0xe90), TBL_ENTRY(0xe91), TBL_ENTRY(0xe92), TBL_ENTRY(0xe93), + TBL_ENTRY(0xe94), TBL_ENTRY(0xe95), TBL_ENTRY(0xe96), TBL_ENTRY(0xe97), + TBL_ENTRY(0xe98), TBL_ENTRY(0xe99), TBL_ENTRY(0xe9a), TBL_ENTRY(0xe9b), + TBL_ENTRY(0xe9c), TBL_ENTRY(0xe9d), TBL_ENTRY(0xe9e), TBL_ENTRY(0xe9f), + TBL_ENTRY(0xea0), TBL_ENTRY(0xea1), TBL_ENTRY(0xea2), TBL_ENTRY(0xea3), + TBL_ENTRY(0xea4), TBL_ENTRY(0xea5), TBL_ENTRY(0xea6), TBL_ENTRY(0xea7), + TBL_ENTRY(0xea8), TBL_ENTRY(0xea9), TBL_ENTRY(0xeaa), TBL_ENTRY(0xeab), + TBL_ENTRY(0xeac), TBL_ENTRY(0xead), TBL_ENTRY(0xeae), TBL_ENTRY(0xeaf), + TBL_ENTRY(0xeb0), TBL_ENTRY(0xeb1), TBL_ENTRY(0xeb2), TBL_ENTRY(0xeb3), + TBL_ENTRY(0xeb4), TBL_ENTRY(0xeb5), TBL_ENTRY(0xeb6), TBL_ENTRY(0xeb7), + TBL_ENTRY(0xeb8), TBL_ENTRY(0xeb9), TBL_ENTRY(0xeba), TBL_ENTRY(0xebb), + TBL_ENTRY(0xebc), TBL_ENTRY(0xebd), TBL_ENTRY(0xebe), TBL_ENTRY(0xebf), + TBL_ENTRY(0xec0), TBL_ENTRY(0xec1), TBL_ENTRY(0xec2), TBL_ENTRY(0xec3), + TBL_ENTRY(0xec4), TBL_ENTRY(0xec5), TBL_ENTRY(0xec6), TBL_ENTRY(0xec7), + TBL_ENTRY(0xec8), TBL_ENTRY(0xec9), TBL_ENTRY(0xeca), TBL_ENTRY(0xecb), + TBL_ENTRY(0xecc), TBL_ENTRY(0xecd), TBL_ENTRY(0xece), TBL_ENTRY(0xecf), + TBL_ENTRY(0xed0), TBL_ENTRY(0xed1), TBL_ENTRY(0xed2), TBL_ENTRY(0xed3), + TBL_ENTRY(0xed4), TBL_ENTRY(0xed5), TBL_ENTRY(0xed6), TBL_ENTRY(0xed7), + TBL_ENTRY(0xed8), TBL_ENTRY(0xed9), TBL_ENTRY(0xeda), TBL_ENTRY(0xedb), + TBL_ENTRY(0xedc), TBL_ENTRY(0xedd), TBL_ENTRY(0xede), TBL_ENTRY(0xedf), + TBL_ENTRY(0xee0), TBL_ENTRY(0xee1), TBL_ENTRY(0xee2), TBL_ENTRY(0xee3), + TBL_ENTRY(0xee4), TBL_ENTRY(0xee5), TBL_ENTRY(0xee6), TBL_ENTRY(0xee7), + TBL_ENTRY(0xee8), TBL_ENTRY(0xee9), TBL_ENTRY(0xeea), TBL_ENTRY(0xeeb), + TBL_ENTRY(0xeec), TBL_ENTRY(0xeed), TBL_ENTRY(0xeee), TBL_ENTRY(0xeef), + TBL_ENTRY(0xef0), TBL_ENTRY(0xef1), TBL_ENTRY(0xef2), TBL_ENTRY(0xef3), + TBL_ENTRY(0xef4), TBL_ENTRY(0xef5), TBL_ENTRY(0xef6), TBL_ENTRY(0xef7), + TBL_ENTRY(0xef8), TBL_ENTRY(0xef9), TBL_ENTRY(0xefa), TBL_ENTRY(0xefb), + TBL_ENTRY(0xefc), TBL_ENTRY(0xefd), TBL_ENTRY(0xefe), TBL_ENTRY(0xeff), + TBL_ENTRY(0xf00), TBL_ENTRY(0xf01), TBL_ENTRY(0xf02), TBL_ENTRY(0xf03), + TBL_ENTRY(0xf04), TBL_ENTRY(0xf05), TBL_ENTRY(0xf06), TBL_ENTRY(0xf07), + TBL_ENTRY(0xf08), TBL_ENTRY(0xf09), TBL_ENTRY(0xf0a), TBL_ENTRY(0xf0b), + TBL_ENTRY(0xf0c), TBL_ENTRY(0xf0d), TBL_ENTRY(0xf0e), TBL_ENTRY(0xf0f), + TBL_ENTRY(0xf10), TBL_ENTRY(0xf11), TBL_ENTRY(0xf12), TBL_ENTRY(0xf13), + TBL_ENTRY(0xf14), TBL_ENTRY(0xf15), TBL_ENTRY(0xf16), TBL_ENTRY(0xf17), + TBL_ENTRY(0xf18), TBL_ENTRY(0xf19), TBL_ENTRY(0xf1a), TBL_ENTRY(0xf1b), + TBL_ENTRY(0xf1c), TBL_ENTRY(0xf1d), TBL_ENTRY(0xf1e), TBL_ENTRY(0xf1f), + TBL_ENTRY(0xf20), TBL_ENTRY(0xf21), TBL_ENTRY(0xf22), TBL_ENTRY(0xf23), + TBL_ENTRY(0xf24), TBL_ENTRY(0xf25), TBL_ENTRY(0xf26), TBL_ENTRY(0xf27), + TBL_ENTRY(0xf28), TBL_ENTRY(0xf29), TBL_ENTRY(0xf2a), TBL_ENTRY(0xf2b), + TBL_ENTRY(0xf2c), TBL_ENTRY(0xf2d), TBL_ENTRY(0xf2e), TBL_ENTRY(0xf2f), + TBL_ENTRY(0xf30), TBL_ENTRY(0xf31), TBL_ENTRY(0xf32), TBL_ENTRY(0xf33), + TBL_ENTRY(0xf34), TBL_ENTRY(0xf35), TBL_ENTRY(0xf36), TBL_ENTRY(0xf37), + TBL_ENTRY(0xf38), TBL_ENTRY(0xf39), TBL_ENTRY(0xf3a), TBL_ENTRY(0xf3b), + TBL_ENTRY(0xf3c), TBL_ENTRY(0xf3d), TBL_ENTRY(0xf3e), TBL_ENTRY(0xf3f), + TBL_ENTRY(0xf40), TBL_ENTRY(0xf41), TBL_ENTRY(0xf42), TBL_ENTRY(0xf43), + TBL_ENTRY(0xf44), TBL_ENTRY(0xf45), TBL_ENTRY(0xf46), TBL_ENTRY(0xf47), + TBL_ENTRY(0xf48), TBL_ENTRY(0xf49), TBL_ENTRY(0xf4a), TBL_ENTRY(0xf4b), + TBL_ENTRY(0xf4c), TBL_ENTRY(0xf4d), TBL_ENTRY(0xf4e), TBL_ENTRY(0xf4f), + TBL_ENTRY(0xf50), TBL_ENTRY(0xf51), TBL_ENTRY(0xf52), TBL_ENTRY(0xf53), + TBL_ENTRY(0xf54), TBL_ENTRY(0xf55), TBL_ENTRY(0xf56), TBL_ENTRY(0xf57), + TBL_ENTRY(0xf58), TBL_ENTRY(0xf59), TBL_ENTRY(0xf5a), TBL_ENTRY(0xf5b), + TBL_ENTRY(0xf5c), TBL_ENTRY(0xf5d), TBL_ENTRY(0xf5e), TBL_ENTRY(0xf5f), + TBL_ENTRY(0xf60), TBL_ENTRY(0xf61), TBL_ENTRY(0xf62), TBL_ENTRY(0xf63), + TBL_ENTRY(0xf64), TBL_ENTRY(0xf65), TBL_ENTRY(0xf66), TBL_ENTRY(0xf67), + TBL_ENTRY(0xf68), TBL_ENTRY(0xf69), TBL_ENTRY(0xf6a), TBL_ENTRY(0xf6b), + TBL_ENTRY(0xf6c), TBL_ENTRY(0xf6d), TBL_ENTRY(0xf6e), TBL_ENTRY(0xf6f), + TBL_ENTRY(0xf70), TBL_ENTRY(0xf71), TBL_ENTRY(0xf72), TBL_ENTRY(0xf73), + TBL_ENTRY(0xf74), TBL_ENTRY(0xf75), TBL_ENTRY(0xf76), TBL_ENTRY(0xf77), + TBL_ENTRY(0xf78), TBL_ENTRY(0xf79), TBL_ENTRY(0xf7a), TBL_ENTRY(0xf7b), + TBL_ENTRY(0xf7c), TBL_ENTRY(0xf7d), TBL_ENTRY(0xf7e), TBL_ENTRY(0xf7f), + TBL_ENTRY(0xf80), TBL_ENTRY(0xf81), TBL_ENTRY(0xf82), TBL_ENTRY(0xf83), + TBL_ENTRY(0xf84), TBL_ENTRY(0xf85), TBL_ENTRY(0xf86), TBL_ENTRY(0xf87), + TBL_ENTRY(0xf88), TBL_ENTRY(0xf89), TBL_ENTRY(0xf8a), TBL_ENTRY(0xf8b), + TBL_ENTRY(0xf8c), TBL_ENTRY(0xf8d), TBL_ENTRY(0xf8e), TBL_ENTRY(0xf8f), + TBL_ENTRY(0xf90), TBL_ENTRY(0xf91), TBL_ENTRY(0xf92), TBL_ENTRY(0xf93), + TBL_ENTRY(0xf94), TBL_ENTRY(0xf95), TBL_ENTRY(0xf96), TBL_ENTRY(0xf97), + TBL_ENTRY(0xf98), TBL_ENTRY(0xf99), TBL_ENTRY(0xf9a), TBL_ENTRY(0xf9b), + TBL_ENTRY(0xf9c), TBL_ENTRY(0xf9d), TBL_ENTRY(0xf9e), TBL_ENTRY(0xf9f), + TBL_ENTRY(0xfa0), TBL_ENTRY(0xfa1), TBL_ENTRY(0xfa2), TBL_ENTRY(0xfa3), + TBL_ENTRY(0xfa4), TBL_ENTRY(0xfa5), TBL_ENTRY(0xfa6), TBL_ENTRY(0xfa7), + TBL_ENTRY(0xfa8), TBL_ENTRY(0xfa9), TBL_ENTRY(0xfaa), TBL_ENTRY(0xfab), + TBL_ENTRY(0xfac), TBL_ENTRY(0xfad), TBL_ENTRY(0xfae), TBL_ENTRY(0xfaf), + TBL_ENTRY(0xfb0), TBL_ENTRY(0xfb1), TBL_ENTRY(0xfb2), TBL_ENTRY(0xfb3), + TBL_ENTRY(0xfb4), TBL_ENTRY(0xfb5), TBL_ENTRY(0xfb6), TBL_ENTRY(0xfb7), + TBL_ENTRY(0xfb8), TBL_ENTRY(0xfb9), TBL_ENTRY(0xfba), TBL_ENTRY(0xfbb), + TBL_ENTRY(0xfbc), TBL_ENTRY(0xfbd), TBL_ENTRY(0xfbe), TBL_ENTRY(0xfbf), + TBL_ENTRY(0xfc0), TBL_ENTRY(0xfc1), TBL_ENTRY(0xfc2), TBL_ENTRY(0xfc3), + TBL_ENTRY(0xfc4), TBL_ENTRY(0xfc5), TBL_ENTRY(0xfc6), TBL_ENTRY(0xfc7), + TBL_ENTRY(0xfc8), TBL_ENTRY(0xfc9), TBL_ENTRY(0xfca), TBL_ENTRY(0xfcb), + TBL_ENTRY(0xfcc), TBL_ENTRY(0xfcd), TBL_ENTRY(0xfce), TBL_ENTRY(0xfcf), + TBL_ENTRY(0xfd0), TBL_ENTRY(0xfd1), TBL_ENTRY(0xfd2), TBL_ENTRY(0xfd3), + TBL_ENTRY(0xfd4), TBL_ENTRY(0xfd5), TBL_ENTRY(0xfd6), TBL_ENTRY(0xfd7), + TBL_ENTRY(0xfd8), TBL_ENTRY(0xfd9), TBL_ENTRY(0xfda), TBL_ENTRY(0xfdb), + TBL_ENTRY(0xfdc), TBL_ENTRY(0xfdd), TBL_ENTRY(0xfde), TBL_ENTRY(0xfdf), + TBL_ENTRY(0xfe0), TBL_ENTRY(0xfe1), TBL_ENTRY(0xfe2), TBL_ENTRY(0xfe3), + TBL_ENTRY(0xfe4), TBL_ENTRY(0xfe5), TBL_ENTRY(0xfe6), TBL_ENTRY(0xfe7), + TBL_ENTRY(0xfe8), TBL_ENTRY(0xfe9), TBL_ENTRY(0xfea), TBL_ENTRY(0xfeb), + TBL_ENTRY(0xfec), TBL_ENTRY(0xfed), TBL_ENTRY(0xfee), TBL_ENTRY(0xfef), + TBL_ENTRY(0xff0), TBL_ENTRY(0xff1), TBL_ENTRY(0xff2), TBL_ENTRY(0xff3), + TBL_ENTRY(0xff4), TBL_ENTRY(0xff5), TBL_ENTRY(0xff6), TBL_ENTRY(0xff7), + TBL_ENTRY(0xff8), TBL_ENTRY(0xff9), TBL_ENTRY(0xffa), TBL_ENTRY(0xffb), + TBL_ENTRY(0xffc), TBL_ENTRY(0xffd), TBL_ENTRY(0xffe), TBL_ENTRY(0xfff), +}; diff --git a/arch/arm/cpu/armv7/uniphier/lowlevel_init.S b/arch/arm/cpu/armv7/uniphier/lowlevel_init.S new file mode 100644 index 0000000000..0ea12d3cfc --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/lowlevel_init.S @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +ENTRY(lowlevel_init) + mov r8, lr @ persevere link reg across call + + /* + * The UniPhier Boot ROM loads SPL code to the L2 cache. + * But CPUs can only do instruction fetch now because start.S has + * cleared C and M bits. + * First we need to turn on MMU and Dcache again to get back + * data access to L2. + */ + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache + mcr p15, 0, r0, c1, c0, 0 + + /* + * Now we are using the page table embedded in the Boot ROM. + * It is not handy since it is not a straight mapped table for sLD3. + * What we need to do next is to switch over to the page table in SPL. + */ + ldr r3, =init_page_table @ page table must be 16KB aligned + + /* Disable MMU and Dcache before switching Page Table */ + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache + mcr p15, 0, r0, c1, c0, 0 + + bl enable_mmu + +#ifdef CONFIG_UNIPHIER_SMP + /* + * ACTLR (Auxiliary Control Register) for Cortex-A9 + * bit[9] Parity on + * bit[8] Alloc in one way + * bit[7] EXCL (Exclusive cache bit) + * bit[6] SMP + * bit[3] Write full line of zeros mode + * bit[2] L1 Prefetch enable + * bit[1] L2 prefetch enable + * bit[0] FW (Cache and TLB maintenance broadcast) + */ + mrc p15, 0, r0, c1, c0, 1 @ ACTLR (Auxiliary Control Register) + orr r0, r0, #0x41 @ enable SMP, FW bit + mcr p15, 0, r0, c1, c0, 1 + + /* branch by CPU ID */ + mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register) + and r0, r0, #0x3 + cmp r0, #0x0 + beq primary_cpu + ldr r1, =ROM_BOOT_ROMRSV2 + mov r0, #0 + str r0, [r1] +0: wfe + ldr r0, [r1] + cmp r0, #0 + beq 0b + bx r0 @ r0: entry point of U-Boot main for the secondary CPU +primary_cpu: + ldr r1, =ROM_BOOT_ROMRSV2 + ldr r0, =_start @ entry for the secondary CPU + str r0, [r1] + ldr r0, [r1] @ make sure str is complete before sev + sev @ kick the sedoncary CPU + mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register + bfc r1, #0, #13 @ clear bit 12-0 + mov r0, #-1 + str r0, [r1, #SCU_INV_ALL] @ SCU Invalidate All Register + mov r0, #1 @ SCU enable + str r0, [r1, #SCU_CTRL] @ SCU Control Register +#endif + + bl setup_init_ram @ RAM area for temporary stack pointer + + mov lr, r8 @ restore link + mov pc, lr @ back to my caller +ENDPROC(lowlevel_init) + +ENTRY(enable_mmu) + mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register) + bic r0, r0, #0x37 + orr r0, r0, #0x20 @ disable TTBR1 + mcr p15, 0, r0, c2, c0, 2 + + orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA + mcr p15, 0, r0, c2, c0, 0 @ TTBR0 + + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs + + mov r0, #-1 @ manager for all domains (No permission check) + mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register) + + dsb + isb + /* + * MMU on: + * TLBs was already invalidated in "../start.S" + * So, we don't need to invalidate it here. + */ + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable + mcr p15, 0, r0, c1, c0, 0 + + mov pc, lr +ENDPROC(enable_mmu) + +#include + +#define BOOT_RAM_SIZE (SSC_WAY_SIZE) +#define BOOT_WAY_BITS (0x00000100) /* way 8 */ + +ENTRY(setup_init_ram) + /* + * Touch to zero for the boot way + */ +0: + /* + * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order + */ + ldr r0, = 0x00408006 @ touch to zero with address range + ldr r1, = SSCOQM + str r0, [r1] + ldr r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE) @ base address + ldr r1, = SSCOQAD + str r0, [r1] + ldr r0, = BOOT_RAM_SIZE + ldr r1, = SSCOQSZ + str r0, [r1] + ldr r0, = BOOT_WAY_BITS + ldr r1, = SSCOQWN + str r0, [r1] + ldr r1, = SSCOPPQSEF + ldr r0, [r1] + cmp r0, #0 @ check if the command is successfully set + bne 0b @ try again if an error occurres + + ldr r1, = SSCOLPQS +1: + ldr r0, [r1] + cmp r0, #0x4 + bne 1b @ wait until the operation is completed + str r0, [r1] @ clear the complete notification flag + + mov pc, lr +ENDPROC(setup_init_ram) diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile new file mode 100644 index 0000000000..b385e19544 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile @@ -0,0 +1,10 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-y += boot-mode.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ + sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o +obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ + umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c new file mode 100644 index 0000000000..85f37f299b --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) + +void bcu_init(void) +{ + int shift; + + writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */ + writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */ + + /* Specify DDR channel */ + shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4; + writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ + + shift -= 32; + writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ + + shift -= 32; + writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c new file mode 100644 index 0000000000..27d772e8cb --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int checkboard(void) +{ + puts("Board: PH1-LD4 Board\n"); + + return check_support_card(); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c new file mode 100644 index 0000000000..4302277dfc --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void bcu_init(void); +void sbc_init(void); +void sg_init(void); +void pll_init(void); +void pin_init(void); +void clkrst_init(void); + +int board_postclk_init(void) +{ + bcu_init(); + + sbc_init(); + + sg_init(); + + pll_init(); + + uniphier_board_init(); + + led_write(B, 1, , ); + + clkrst_init(); + + led_write(B, 2, , ); + + pin_init(); + + led_write(B, 3, , ); + + return 0; +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c new file mode 100644 index 0000000000..d359b56291 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c @@ -0,0 +1 @@ +#include "../ph1-pro4/boot-mode.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c new file mode 100644 index 0000000000..18965a94c5 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void clkrst_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); + tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1 + | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND; + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); + tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC + | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI; + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c new file mode 100644 index 0000000000..a7429402f3 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void pin_init(void) +{ + u32 tmp; + + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */ + sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */ + + sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */ + sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */ + + sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */ + sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */ + + sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ + sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ +#endif + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(158, 0); /* XNFRE -> XNFRE_GB */ + sg_set_pinsel(159, 0); /* XNFWE -> XNFWE_GB */ + sg_set_pinsel(160, 0); /* XFALE -> NFALE_GB */ + sg_set_pinsel(161, 0); /* XFCLE -> NFCLE_GB */ + sg_set_pinsel(162, 0); /* XNFWP -> XFNWP_GB */ + sg_set_pinsel(163, 0); /* XNFCE0 -> XNFCE0_GB */ + sg_set_pinsel(164, 0); /* NANDRYBY0 -> NANDRYBY0_GB */ + sg_set_pinsel(22, 0); /* MMCCLK -> XFNCE1_GB */ + sg_set_pinsel(23, 0); /* MMCCMD -> NANDRYBY1_GB */ + sg_set_pinsel(24, 0); /* MMCDAT0 -> NFD0_GB */ + sg_set_pinsel(25, 0); /* MMCDAT1 -> NFD1_GB */ + sg_set_pinsel(26, 0); /* MMCDAT2 -> NFD2_GB */ + sg_set_pinsel(27, 0); /* MMCDAT3 -> NFD3_GB */ + sg_set_pinsel(28, 0); /* MMCDAT4 -> NFD4_GB */ + sg_set_pinsel(29, 0); /* MMCDAT5 -> NFD5_GB */ + sg_set_pinsel(30, 0); /* MMCDAT6 -> NFD6_GB */ + sg_set_pinsel(31, 0); /* MMCDAT7 -> NFD7_GB */ +#endif + +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(53, 0); /* USB0VBUS -> USB0VBUS */ + sg_set_pinsel(54, 0); /* USB0OD -> USB0OD */ + sg_set_pinsel(55, 0); /* USB1VBUS -> USB1VBUS */ + sg_set_pinsel(56, 0); /* USB1OD -> USB1OD */ + /* sg_set_pinsel(67, 23); */ /* PCOE -> USB2VBUS */ + /* sg_set_pinsel(68, 23); */ /* PCWAIT -> USB2OD */ +#endif + + tmp = readl(SG_IECTRL); + tmp |= 0x41; + writel(tmp, SG_IECTRL); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c new file mode 100644 index 0000000000..68b9d5ff27 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#undef DPLL_SSC_RATE_1PER + +void dpll_init(void) +{ + u32 tmp; + + /* + * Set Frequency + * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) + * to FOUT (DPLLCTRL.bit[29:20]) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~0x000f0000; +#if CONFIG_DDR_FREQ == 1600 + tmp |= 0x000c0000; +#elif CONFIG_DDR_FREQ == 1333 + tmp |= 0x000d0000; +#else +# error "Unknown frequency" +#endif + +#if defined(DPLL_SSC_RATE_1PER) + tmp &= ~SC_DPLLCTRL_SSC_RATE; +#else + tmp |= SC_DPLLCTRL_SSC_RATE; +#endif + writel(tmp, SC_DPLLCTRL); + + tmp = readl(SC_DPLLCTRL2); + tmp |= SC_DPLLCTRL2_NRSTDS; + writel(tmp, SC_DPLLCTRL2); +} + +void upll_init(void) +{ + u32 tmp, clk_mode_upll, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ + tmp = readl(SC_UPLLCTRL); + tmp &= ~0x18000000; + writel(tmp, SC_UPLLCTRL); + + if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x0228f5c0; + } else { + /* AXO: default 24.576MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x02328000; + } + } + + writel(tmp, SC_UPLLCTRL); + + /* set 1 to K_LD(UPLLCTRL.bit[27]) */ + tmp |= 0x08000000; + writel(tmp, SC_UPLLCTRL); + + /* wait 10 usec */ + udelay(10); + + /* set 1 to SNRT(UPLLCTRL.bit[28]) */ + tmp |= 0x10000000; + writel(tmp, SC_UPLLCTRL); +} + +void vpll_init(void) +{ + u32 tmp, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 1 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27BCTRL); + + /* Set 0 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27BCTRL2); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27BCTRL3); + } else { + /* AXO: default 24.576MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27BCTRL3); + } + + /* Set 1 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* wait 10 usec */ + udelay(10); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* set 0 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= ~0x00000001; + writel(tmp, SC_VPLL27BCTRL); +} + +void pll_init(void) +{ + dpll_init(); + upll_init(); + vpll_init(); + + /* + * Wait 500 usec until dpll get stable + * We wait 10 usec in upll_init() and vpll_init() + * so 20 usec can be saved here. + */ + udelay(480); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c new file mode 100644 index 0000000000..837b2a891b --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c @@ -0,0 +1 @@ +#include "../ph1-pro4/pll_spectrum.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c new file mode 100644 index 0000000000..a37ed1674f --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +void sbc_init(void) +{ + /* XECS1: sub/boot memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); + +#if !defined(CONFIG_SPL_BUILD) + /* XECS0: boot/sub memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); +#endif + /* XECS3: peripherals */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); + + /* base address regsiters */ + writel(0x0000bc01, SBBASE0); + writel(0x0400bc01, SBBASE1); + writel(0x0800bf01, SBBASE3); + +#if !defined(CONFIG_SPL_BUILD) + /* enable access to sub memory when boot swap is on */ + sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */ +#endif + sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */ +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c new file mode 100644 index 0000000000..b4dd799a88 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void sg_init(void) +{ + u32 tmp; + + /* Set DDR size */ + tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); + tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); +#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE + tmp |= SG_MEMCONF_SPARSEMEM; +#endif + writel(tmp, SG_MEMCONF); + + /* Input ports must be enabled deasserting reset of cores */ + tmp = readl(SG_IECTRL); + tmp |= 0x1; + writel(tmp, SG_IECTRL); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c new file mode 100644 index 0000000000..1344ac1caa --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static inline void umc_start_ssif(void __iomem *ssif_base) +{ + writel(0x00000000, ssif_base + 0x0000b004); + writel(0xffffffff, ssif_base + 0x0000c004); + writel(0x000fffcf, ssif_base + 0x0000c008); + writel(0x00000001, ssif_base + 0x0000b000); + writel(0x00000001, ssif_base + 0x0000c000); + writel(0x03010101, ssif_base + UMC_MDMCHSEL); + writel(0x03010100, ssif_base + UMC_DMDCHSEL); + + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); + + writel(0x00000001, ssif_base + UMC_CPURST); + writel(0x00000001, ssif_base + UMC_IDSRST); + writel(0x00000001, ssif_base + UMC_IXMRST); + writel(0x00000001, ssif_base + UMC_MDMRST); + writel(0x00000001, ssif_base + UMC_MDDRST); + writel(0x00000001, ssif_base + UMC_SIORST); + writel(0x00000001, ssif_base + UMC_VIORST); + writel(0x00000001, ssif_base + UMC_FRCRST); + writel(0x00000001, ssif_base + UMC_RGLRST); + writel(0x00000001, ssif_base + UMC_AIORST); + writel(0x00000001, ssif_base + UMC_DMDRST); +} + +void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) +{ + if (freq == 1333) { + writel(0x45990b11, dramcont + UMC_CMDCTLA); + writel(0x16958924, dramcont + UMC_CMDCTLB); + writel(0x5101046A, dramcont + UMC_INITCTLA); + + if (size == 1) + writel(0x27028B0A, dramcont + UMC_INITCTLB); + else if (size == 2) + writel(0x38028B0A, dramcont + UMC_INITCTLB); + + writel(0x000FF0FF, dramcont + UMC_INITCTLC); + writel(0x00000b51, dramcont + UMC_DRMMR0); + } else if (freq == 1600) { + writel(0x36BB0F17, dramcont + UMC_CMDCTLA); + writel(0x18C6AA24, dramcont + UMC_CMDCTLB); + writel(0x5101387F, dramcont + UMC_INITCTLA); + + if (size == 1) + writel(0x2F030D3F, dramcont + UMC_INITCTLB); + else if (size == 2) + writel(0x43030D3F, dramcont + UMC_INITCTLB); + + writel(0x00FF00FF, dramcont + UMC_INITCTLC); + writel(0x00000d71, dramcont + UMC_DRMMR0); + } + + writel(0x00000006, dramcont + UMC_DRMMR1); + + if (freq == 1333) + writel(0x00000290, dramcont + UMC_DRMMR2); + else if (freq == 1600) + writel(0x00000298, dramcont + UMC_DRMMR2); + + writel(0x00000800, dramcont + UMC_DRMMR3); + + if (freq == 1333) { + if (size == 1) + writel(0x00240512, dramcont + UMC_SPCCTLA); + else if (size == 2) + writel(0x00350512, dramcont + UMC_SPCCTLA); + + writel(0x00ff0006, dramcont + UMC_SPCCTLB); + writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); + } else if (freq == 1600) { + if (size == 1) + writel(0x002B0617, dramcont + UMC_SPCCTLA); + else if (size == 2) + writel(0x003F0617, dramcont + UMC_SPCCTLA); + + writel(0x00ff0008, dramcont + UMC_SPCCTLB); + writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); + } + + writel(0x04060806, dramcont + UMC_WDATACTL_D0); + writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x00000000, ca_base + 0x2300); + writel(0x00400020, dramcont + UMC_DCCGCTL); + writel(0x00000003, dramcont + 0x7000); + writel(0x0000000f, dramcont + 0x8000); + writel(0x000000c3, dramcont + 0x8004); + writel(0x00000071, dramcont + 0x8008); + writel(0x0000003b, dramcont + UMC_DICGCTLA); + writel(0x020a0808, dramcont + UMC_DICGCTLB); + writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x80000201, ca_base + 0xc20); + writel(0x0801e01e, dramcont + UMC_FLOWCTLA); + writel(0x00200000, dramcont + UMC_FLOWCTLB); + writel(0x00004444, dramcont + UMC_FLOWCTLC); + writel(0x200a0a00, dramcont + UMC_SPCSETB); + writel(0x00000000, dramcont + UMC_SPCSETD); + writel(0x00000520, dramcont + UMC_DFICUPDCTLA); +} + +static inline int umc_init_sub(int freq, int size_ch0, int size_ch1) +{ + void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; + void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); + void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); + void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); + void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + + umc_dram_init_start(dramcont0); + umc_dram_init_start(dramcont1); + umc_dram_init_poll(dramcont0); + umc_dram_init_poll(dramcont1); + + writel(0x00000101, dramcont0 + UMC_DIOCTLA); + + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + + umc_start_ssif(ssif_base); + + return 0; +} + +int umc_init(void) +{ + return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000, + CONFIG_SDRAM1_SIZE / 0x08000000); +} + +#if CONFIG_DDR_FREQ != 1333 && CONFIG_DDR_FREQ != 1600 +#error Unsupported DDR Frequency. +#endif + +#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ + (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ + CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 +/* OK */ +#else +#error Unsupported DDR configuration. +#endif diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile new file mode 100644 index 0000000000..712afd1bee --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile @@ -0,0 +1,10 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-y += boot-mode.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \ + sg_init.o pll_init.o clkrst_init.o pinctrl.o +obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ + umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c new file mode 100644 index 0000000000..325a4f6160 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int checkboard(void) +{ + puts("Board: PH1-Pro4 Board\n"); + + return check_support_card(); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c new file mode 100644 index 0000000000..7198829988 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void sbc_init(void); +void sg_init(void); +void pll_init(void); +void pin_init(void); +void clkrst_init(void); + +int board_postclk_init(void) +{ + sbc_init(); + + sg_init(); + + pll_init(); + + uniphier_board_init(); + + led_write(B, 1, , ); + + clkrst_init(); + + led_write(B, 2, , ); + + pin_init(); + + led_write(B, 3, , ); + + return 0; +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c new file mode 100644 index 0000000000..33bccff2a5 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +struct boot_device_info boot_device_table[] = { + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"}, + {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, ""} +}; + +u32 get_boot_mode_sel(void) +{ + return (readl(SG_PINMON0) >> 1) & 0x1f; +} + +u32 spl_boot_device(void) +{ + u32 boot_mode; + + if (boot_is_swapped()) + return BOOT_DEVICE_NOR; + + boot_mode = get_boot_mode_sel(); + + return boot_device_table[boot_mode].type; +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c new file mode 100644 index 0000000000..18965a94c5 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void clkrst_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); + tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1 + | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND; + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); + tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC + | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI; + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c new file mode 100644 index 0000000000..503c247d6b --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */ + sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */ + sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */ + sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */ + sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */ + sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */ + sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */ + sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */ +#endif + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(40, 0); /* NFD0 -> NFD0 */ + sg_set_pinsel(41, 0); /* NFD1 -> NFD1 */ + sg_set_pinsel(42, 0); /* NFD2 -> NFD2 */ + sg_set_pinsel(43, 0); /* NFD3 -> NFD3 */ + sg_set_pinsel(44, 0); /* NFD4 -> NFD4 */ + sg_set_pinsel(45, 0); /* NFD5 -> NFD5 */ + sg_set_pinsel(46, 0); /* NFD6 -> NFD6 */ + sg_set_pinsel(47, 0); /* NFD7 -> NFD7 */ + sg_set_pinsel(48, 0); /* NFALE -> NFALE */ + sg_set_pinsel(49, 0); /* NFCLE -> NFCLE */ + sg_set_pinsel(50, 0); /* XNFRE -> XNFRE */ + sg_set_pinsel(51, 0); /* XNFWE -> XNFWE */ + sg_set_pinsel(52, 0); /* XNFWP -> XNFWP */ + sg_set_pinsel(53, 0); /* XNFCE0 -> XNFCE0 */ + sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */ +#endif + + writel(1, SG_LOADPINCTRL); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c new file mode 100644 index 0000000000..2dcc0892cc --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#undef DPLL_SSC_RATE_1PER + +void dpll_init(void) +{ + u32 tmp; + + /* + * Set Frequency + * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) + * to FOUT ( DPLLCTRL.bit[29:20] ) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~(0x000f0000); +#if CONFIG_DDR_FREQ == 1600 + tmp |= 0x000c0000; +#elif CONFIG_DDR_FREQ == 1333 + tmp |= 0x000d0000; +#else +# error "Unsupported frequency" +#endif + + /* + * Set Moduration rate + * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15]) + */ +#if defined(DPLL_SSC_RATE_1PER) + tmp &= ~0x00008000; +#else + tmp |= 0x00008000; +#endif + writel(tmp, SC_DPLLCTRL); + + tmp = readl(SC_DPLLCTRL2); + tmp |= SC_DPLLCTRL2_NRSTDS; + writel(tmp, SC_DPLLCTRL2); +} + +void stop_mpll(void) +{ + u32 tmp; + + tmp = readl(SC_MPLLOSCCTL); + + if (!(tmp & SC_MPLLOSCCTL_MPLLST)) + return; /* already stopped */ + + tmp &= ~SC_MPLLOSCCTL_MPLLEN; + writel(tmp, SC_MPLLOSCCTL); + + while (readl(SC_MPLLOSCCTL) & SC_MPLLOSCCTL_MPLLST) + ; +} + +void vpll_init(void) +{ + u32 tmp, clk_mode_axosel; + + /* Set VPLL27A & VPLL27B */ + tmp = readl(SG_PINMON0); + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + +#if defined(CONFIG_MACH_PH1_PRO4) + /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */ + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) + return; +#endif + + /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ + tmp = readl(SC_VPLL27ACTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27BCTRL); + + /* Unset VPLA_K_LD and VPLB_K_LD bit */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Set VPLA_M and VPLB_M to 0x20 */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27BCTRL2); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) { + /* Set VPLA_K and VPLB_K for AXO: 25MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066666; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066666; + writel(tmp, SC_VPLL27BCTRL3); + } else { + /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27BCTRL3); + } + + /* wait 1 usec */ + udelay(1); + + /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */ + tmp = readl(SC_VPLL27ACTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Unset VPLA_SNRST and VPLB_SNRST bit */ + tmp = readl(SC_VPLL27ACTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ + tmp = readl(SC_VPLL27ACTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27BCTRL); +} + +void pll_init(void) +{ + dpll_init(); + stop_mpll(); + vpll_init(); + + /* + * Wait 500 usec until dpll get stable + * We wait 1 usec in vpll_init() so 1 usec can be saved here. + */ + udelay(499); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c new file mode 100644 index 0000000000..4538d1af44 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void enable_dpll_ssc(void) +{ + u32 tmp; + + tmp = readl(SC_DPLLCTRL); + tmp |= SC_DPLLCTRL_SSC_EN; + writel(tmp, SC_DPLLCTRL); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c new file mode 100644 index 0000000000..f113db54d1 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +void sbc_init(void) +{ +#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) + /* + * Only CS1 is connected to support card. + * BKSZ[1:0] should be set to "01". + */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); + + if (readl(SBBASE0) & 0x1) { + /* + * Boot Swap Off: boot from mask ROM + * 0x00000000-0x01ffffff: mask ROM + * 0x02000000-0x3effffff: memory bank (31MB) + * 0x03f00000-0x3fffffff: peripherals (1MB) + */ + writel(0x0000be01, SBBASE0); /* dummy */ + writel(0x0200be01, SBBASE1); + } else { + /* + * Boot Swap On: boot from external NOR/SRAM + * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. + * + * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank + * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals + */ + writel(0x0000bc01, SBBASE0); + } +#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD) +#if !defined(CONFIG_SPL_BUILD) + /* XECS0: boot/sub memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); +#endif + /* XECS1: sub/boot memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); + + /* XECS3: peripherals */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); + + writel(0x0000bc01, SBBASE0); /* boot memory */ + writel(0x0400bc01, SBBASE1); /* sub memory */ + writel(0x0800bf01, SBBASE3); /* peripherals */ + +#if !defined(CONFIG_SPL_BUILD) + sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */ +#endif + sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */ + writel(0x00000001, SG_LOADPINCTRL); + +#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */ +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c new file mode 100644 index 0000000000..b4dd799a88 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void sg_init(void) +{ + u32 tmp; + + /* Set DDR size */ + tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); + tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); +#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE + tmp |= SG_MEMCONF_SPARSEMEM; +#endif + writel(tmp, SG_MEMCONF); + + /* Input ports must be enabled deasserting reset of cores */ + tmp = readl(SG_IECTRL); + tmp |= 0x1; + writel(tmp, SG_IECTRL); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c new file mode 100644 index 0000000000..dd462875bb --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static inline void umc_start_ssif(void __iomem *ssif_base) +{ + writel(0x00000001, ssif_base + 0x0000b004); + writel(0xffffffff, ssif_base + 0x0000c004); + writel(0x07ffffff, ssif_base + 0x0000c008); + writel(0x00000001, ssif_base + 0x0000b000); + writel(0x00000001, ssif_base + 0x0000c000); + + writel(0x03010100, ssif_base + UMC_HDMCHSEL); + writel(0x03010101, ssif_base + UMC_MDMCHSEL); + writel(0x03010100, ssif_base + UMC_DVCCHSEL); + writel(0x03010100, ssif_base + UMC_DMDCHSEL); + + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); + writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */ + + writel(0x00000001, ssif_base + UMC_CPURST); + writel(0x00000001, ssif_base + UMC_IDSRST); + writel(0x00000001, ssif_base + UMC_IXMRST); + writel(0x00000001, ssif_base + UMC_HDMRST); + writel(0x00000001, ssif_base + UMC_MDMRST); + writel(0x00000001, ssif_base + UMC_HDDRST); + writel(0x00000001, ssif_base + UMC_MDDRST); + writel(0x00000001, ssif_base + UMC_SIORST); + writel(0x00000001, ssif_base + UMC_GIORST); + writel(0x00000001, ssif_base + UMC_HD2RST); + writel(0x00000001, ssif_base + UMC_VIORST); + writel(0x00000001, ssif_base + UMC_DVCRST); + writel(0x00000001, ssif_base + UMC_RGLRST); + writel(0x00000001, ssif_base + UMC_VPERST); + writel(0x00000001, ssif_base + UMC_AIORST); + writel(0x00000001, ssif_base + UMC_DMDRST); +} + +void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) +{ + writel(0x66bb0f17, dramcont + UMC_CMDCTLA); + writel(0x18c6aa44, dramcont + UMC_CMDCTLB); + writel(0x5101387f, dramcont + UMC_INITCTLA); + writel(0x43030d3f, dramcont + UMC_INITCTLB); + writel(0x00ff00ff, dramcont + UMC_INITCTLC); + writel(0x00000d71, dramcont + UMC_DRMMR0); + writel(0x00000006, dramcont + UMC_DRMMR1); + writel(0x00000298, dramcont + UMC_DRMMR2); + writel(0x00000000, dramcont + UMC_DRMMR3); + writel(0x003f0617, dramcont + UMC_SPCCTLA); + writel(0x00ff0008, dramcont + UMC_SPCCTLB); + writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); + writel(0x000c00ae, dramcont + UMC_RDATACTL_D1); + writel(0x04060802, dramcont + UMC_WDATACTL_D0); + writel(0x04060802, dramcont + UMC_WDATACTL_D1); + writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x00000000, ca_base + 0x2300); + writel(0x00400020, dramcont + UMC_DCCGCTL); + writel(0x0000000f, dramcont + 0x7000); + writel(0x0000000f, dramcont + 0x8000); + writel(0x000000c3, dramcont + 0x8004); + writel(0x00000071, dramcont + 0x8008); + writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x00000000, dramcont + 0x0060); + writel(0x80000201, ca_base + 0xc20); + writel(0x0801e01e, dramcont + UMC_FLOWCTLA); + writel(0x00200000, dramcont + UMC_FLOWCTLB); + writel(0x00004444, dramcont + UMC_FLOWCTLC); + writel(0x200a0a00, dramcont + UMC_SPCSETB); + writel(0x00010000, dramcont + UMC_SPCSETD); + writel(0x80000020, dramcont + UMC_DFICUPDCTLA); +} + +static inline int umc_init_sub(int freq, int size_ch0, int size_ch1) +{ + void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; + void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); + void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); + void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); + void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + + umc_dram_init_start(dramcont0); + umc_dram_init_start(dramcont1); + umc_dram_init_poll(dramcont0); + umc_dram_init_poll(dramcont1); + + writel(0x00000101, dramcont0 + UMC_DIOCTLA); + + writel(0x00000103, dramcont0 + UMC_DIOCTLA); + + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + + writel(0x00000103, dramcont1 + UMC_DIOCTLA); + + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + + umc_start_ssif(ssif_base); + + return 0; +} + +int umc_init(void) +{ + return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000, + CONFIG_SDRAM1_SIZE / 0x08000000); +} + +#if CONFIG_DDR_FREQ != 1600 +#error Unsupported DDR frequency. +#endif + +#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \ + (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \ + ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \ + (CONFIG_SDRAM1_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH1 == 1)) +/* OK */ +#else + #error Unsupported DDR configuration. +#endif diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile new file mode 100644 index 0000000000..b385e19544 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile @@ -0,0 +1,10 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-y += boot-mode.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ + sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o +obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ + umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c new file mode 100644 index 0000000000..69b172e4e7 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c @@ -0,0 +1 @@ +#include "../ph1-ld4/bcu_init.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c new file mode 100644 index 0000000000..15dc289c01 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int checkboard(void) +{ + puts("Board: PH1-sLD8 Board\n"); + + return check_support_card(); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c new file mode 100644 index 0000000000..287b33c21d --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c @@ -0,0 +1 @@ +#include "../ph1-ld4/board_postclk_init.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c new file mode 100644 index 0000000000..d359b56291 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c @@ -0,0 +1 @@ +#include "../ph1-pro4/boot-mode.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c new file mode 100644 index 0000000000..18965a94c5 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void clkrst_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); + tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1 + | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND; + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); + tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC + | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI; + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c new file mode 100644 index 0000000000..2b6403f88f --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */ + sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */ + + sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */ + sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */ + + sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */ + sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */ + + sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ + sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ +#endif + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(15, 0); /* XNFRE_GB -> XNFRE_GB */ + sg_set_pinsel(16, 0); /* XNFWE_GB -> XNFWE_GB */ + sg_set_pinsel(17, 0); /* XFALE_GB -> NFALE_GB */ + sg_set_pinsel(18, 0); /* XFCLE_GB -> NFCLE_GB */ + sg_set_pinsel(19, 0); /* XNFWP_GB -> XFNWP_GB */ + sg_set_pinsel(20, 0); /* XNFCE0_GB -> XNFCE0_GB */ + sg_set_pinsel(21, 0); /* NANDRYBY0_GB -> NANDRYBY0_GB */ + sg_set_pinsel(22, 0); /* XFNCE1_GB -> XFNCE1_GB */ + sg_set_pinsel(23, 0); /* NANDRYBY1_GB -> NANDRYBY1_GB */ + sg_set_pinsel(24, 0); /* NFD0_GB -> NFD0_GB */ + sg_set_pinsel(25, 0); /* NFD1_GB -> NFD1_GB */ + sg_set_pinsel(26, 0); /* NFD2_GB -> NFD2_GB */ + sg_set_pinsel(27, 0); /* NFD3_GB -> NFD3_GB */ + sg_set_pinsel(28, 0); /* NFD4_GB -> NFD4_GB */ + sg_set_pinsel(29, 0); /* NFD5_GB -> NFD5_GB */ + sg_set_pinsel(30, 0); /* NFD6_GB -> NFD6_GB */ + sg_set_pinsel(31, 0); /* NFD7_GB -> NFD7_GB */ +#endif + +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(41, 0); /* USB0VBUS -> USB0VBUS */ + sg_set_pinsel(42, 0); /* USB0OD -> USB0OD */ + sg_set_pinsel(43, 0); /* USB1VBUS -> USB1VBUS */ + sg_set_pinsel(44, 0); /* USB1OD -> USB1OD */ + /* sg_set_pinsel(114, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */ + /* sg_set_pinsel(115, 4); */ /* RXD1 -> USB2OD */ +#endif +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c new file mode 100644 index 0000000000..4d87053430 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c @@ -0,0 +1,201 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +void dpll_init(void) +{ + u32 tmp; + /* + * Set DPLL SSC parameters for DPLLCTRL3 + * [23] DIVN_TEST 0x1 + * [22:16] DIVN 0x50 + * [10] FREFSEL_TEST 0x1 + * [9:8] FREFSEL 0x2 + * [4] ICPD_TEST 0x1 + * [3:0] ICPD 0xb + */ + tmp = readl(SC_DPLLCTRL3); + tmp &= ~0x00ff0717; + tmp |= 0x00d0061b; + writel(tmp, SC_DPLLCTRL3); + + /* + * Set DPLL SSC parameters for DPLLCTRL + * <-1%> <-2%> + * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) + * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~0x3ff07fff; +#ifdef CONFIG_DPLL_SSC_RATE_1PER + tmp |= 0x084018bf; +#else + tmp |= 0x084031a6; +#endif + writel(tmp, SC_DPLLCTRL); + + /* + * Set DPLL SSC parameters for DPLLCTRL2 + * [31:29] SSC_STEP 0 + * [27] SSC_REG_REF 1 + * [26:20] SSC_M 79 (0x4f) + * [19:0] SSC_K 964689 (0xeb851) + */ + tmp = readl(SC_DPLLCTRL2); + tmp &= ~0xefffffff; + tmp |= 0x0cfeb851; + writel(tmp, SC_DPLLCTRL2); +} + +void upll_init(void) +{ + u32 tmp, clk_mode_upll, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ + tmp = readl(SC_UPLLCTRL); + tmp &= ~0x18000000; + writel(tmp, SC_UPLLCTRL); + + if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x0228f5c0; + } else { + /* AXO: default 24.576MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x02328000; + } + } + + writel(tmp, SC_UPLLCTRL); + + /* set 1 to K_LD(UPLLCTRL.bit[27]) */ + tmp |= 0x08000000; + writel(tmp, SC_UPLLCTRL); + + /* wait 10 usec */ + udelay(10); + + /* set 1 to SNRT(UPLLCTRL.bit[28]) */ + tmp |= 0x10000000; + writel(tmp, SC_UPLLCTRL); +} + +void vpll_init(void) +{ + u32 tmp, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 1 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27BCTRL); + + /* Set 0 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27BCTRL2); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27BCTRL3); + } else { + /* AXO: default 24.576MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27BCTRL3); + } + + /* Set 1 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* wait 10 usec */ + udelay(10); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* set 0 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= ~0x00000001; + writel(tmp, SC_VPLL27BCTRL); +} + +void pll_init(void) +{ + dpll_init(); + upll_init(); + vpll_init(); + + /* + * Wait 500 usec until dpll get stable + * We wait 10 usec in upll_init() and vpll_init() + * so 20 usec can be saved here. + */ + udelay(480); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c new file mode 100644 index 0000000000..9b8c4855e5 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c @@ -0,0 +1 @@ +#include "../ph1-ld4/pll_spectrum.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c new file mode 100644 index 0000000000..af44dee4f6 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +void sbc_init(void) +{ +#if !defined(CONFIG_SPL_BUILD) + /* XECS0 : dummy */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); +#endif + /* XECS1 : boot memory (always boot swap = on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); + + /* XECS4 : sub memory */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44); + + /* XECS5 : peripherals */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54); + + /* base address regsiters */ + writel(0x0000bc01, SBBASE0); /* boot memory */ + writel(0x0900bfff, SBBASE1); /* dummy */ + writel(0x0400bc01, SBBASE4); /* sub memory */ + writel(0x0800bf01, SBBASE5); /* peripherals */ + + sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */ + sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */ + + /* dummy read to assure write process */ + readl(SG_PINCTRL(33)); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c new file mode 100644 index 0000000000..a808289a56 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c @@ -0,0 +1 @@ +#include "../ph1-ld4/sg_init.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c new file mode 100644 index 0000000000..ff2dcb1640 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static inline void umc_start_ssif(void __iomem *ssif_base) +{ + writel(0x00000000, ssif_base + 0x0000b004); + writel(0xffffffff, ssif_base + 0x0000c004); + writel(0x000fffcf, ssif_base + 0x0000c008); + writel(0x00000001, ssif_base + 0x0000b000); + writel(0x00000001, ssif_base + 0x0000c000); + writel(0x03010101, ssif_base + UMC_MDMCHSEL); + writel(0x03010100, ssif_base + UMC_DMDCHSEL); + + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); + + writel(0x00000001, ssif_base + UMC_CPURST); + writel(0x00000001, ssif_base + UMC_IDSRST); + writel(0x00000001, ssif_base + UMC_IXMRST); + writel(0x00000001, ssif_base + UMC_MDMRST); + writel(0x00000001, ssif_base + UMC_MDDRST); + writel(0x00000001, ssif_base + UMC_SIORST); + writel(0x00000001, ssif_base + UMC_VIORST); + writel(0x00000001, ssif_base + UMC_FRCRST); + writel(0x00000001, ssif_base + UMC_RGLRST); + writel(0x00000001, ssif_base + UMC_AIORST); + writel(0x00000001, ssif_base + UMC_DMDRST); +} + +void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) +{ +#ifdef CONFIG_DDR_STANDARD + writel(0x55990b11, dramcont + UMC_CMDCTLA); + writel(0x16958944, dramcont + UMC_CMDCTLB); +#else + writel(0x45990b11, dramcont + UMC_CMDCTLA); + writel(0x16958924, dramcont + UMC_CMDCTLB); +#endif + + writel(0x5101046A, dramcont + UMC_INITCTLA); + + if (size == 1) + writel(0x27028B0A, dramcont + UMC_INITCTLB); + else if (size == 2) + writel(0x38028B0A, dramcont + UMC_INITCTLB); + + writel(0x00FF00FF, dramcont + UMC_INITCTLC); + writel(0x00000b51, dramcont + UMC_DRMMR0); + writel(0x00000006, dramcont + UMC_DRMMR1); + writel(0x00000290, dramcont + UMC_DRMMR2); + +#ifdef CONFIG_DDR_STANDARD + writel(0x00000000, dramcont + UMC_DRMMR3); +#else + writel(0x00000800, dramcont + UMC_DRMMR3); +#endif + + if (size == 1) + writel(0x00240512, dramcont + UMC_SPCCTLA); + else if (size == 2) + writel(0x00350512, dramcont + UMC_SPCCTLA); + + writel(0x00ff0006, dramcont + UMC_SPCCTLB); + writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); + writel(0x04060806, dramcont + UMC_WDATACTL_D0); + writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x00000000, ca_base + 0x2300); + writel(0x00400020, dramcont + UMC_DCCGCTL); + writel(0x00000003, dramcont + 0x7000); + writel(0x0000004f, dramcont + 0x8000); + writel(0x000000c3, dramcont + 0x8004); + writel(0x00000077, dramcont + 0x8008); + writel(0x0000003b, dramcont + UMC_DICGCTLA); + writel(0x020a0808, dramcont + UMC_DICGCTLB); + writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x80000201, ca_base + 0xc20); + writel(0x0801e01e, dramcont + UMC_FLOWCTLA); + writel(0x00200000, dramcont + UMC_FLOWCTLB); + writel(0x00004444, dramcont + UMC_FLOWCTLC); + writel(0x200a0a00, dramcont + UMC_SPCSETB); + writel(0x00000000, dramcont + UMC_SPCSETD); + writel(0x00000520, dramcont + UMC_DFICUPDCTLA); +} + +static inline int umc_init_sub(int freq, int size_ch0, int size_ch1) +{ + void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; + void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); + void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); + void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); + void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + + umc_dram_init_start(dramcont0); + umc_dram_init_start(dramcont1); + umc_dram_init_poll(dramcont0); + umc_dram_init_poll(dramcont1); + + writel(0x00000101, dramcont0 + UMC_DIOCTLA); + + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + + umc_start_ssif(ssif_base); + + return 0; +} + +int umc_init(void) +{ + return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000, + CONFIG_SDRAM1_SIZE / 0x08000000); +} + +#if CONFIG_DDR_FREQ != 1333 +#error Unsupported DDR frequency. +#endif + +#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ + (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ + CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 +/* OK */ +#else +#error Unsupported DDR configuration. +#endif diff --git a/arch/arm/cpu/armv7/uniphier/reset.c b/arch/arm/cpu/armv7/uniphier/reset.c new file mode 100644 index 0000000000..b0dc9673b4 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/reset.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +void reset_cpu(unsigned long ignored) +{ + u32 tmp; + + uniphier_board_reset(); + + writel(5, SC_IRQTIMSET); /* default value */ + + tmp = readl(SC_SLFRSTSEL); + tmp &= ~0x3; /* mask [1:0] */ + tmp |= 0x0; /* XRST reboot */ + writel(tmp, SC_SLFRSTSEL); + + tmp = readl(SC_SLFRSTCTL); + tmp |= 0x1; + writel(tmp, SC_SLFRSTCTL); +} diff --git a/arch/arm/cpu/armv7/uniphier/smp.S b/arch/arm/cpu/armv7/uniphier/smp.S new file mode 100644 index 0000000000..25ba981cea --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/smp.S @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2013 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* Entry point of U-Boot main program for the secondary CPU */ +LENTRY(secondary_entry) + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache disable + mcr p15, 0, r0, c1, c0, 0 + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs + mcr p15, 0, r0, c7, c5, 0 @ invalidate icache + dsb + led_write(C,0,,) + ldr r1, =ROM_BOOT_ROMRSV2 + mov r0, #0 + str r0, [r1] +0: wfe + ldr r4, [r1] @ r4: entry point for secondary CPUs + cmp r4, #0 + beq 0b + led_write(C, P, U, 1) + bx r4 @ secondary CPUs jump to linux +ENDPROC(secondary_entry) + +ENTRY(wakeup_secondary) + ldr r1, =ROM_BOOT_ROMRSV2 +0: ldr r0, [r1] + cmp r0, #0 + bne 0b + + /* set entry address and send event to the secondary CPU */ + ldr r0, =secondary_entry + str r0, [r1] + ldr r0, [r1] @ make sure store is complete + mov r0, #0x100 +0: subs r0, r0, #1 @ I don't know the reason, but without this wait + bne 0b @ fails to wake up the secondary CPU + sev + + /* wait until the secondary CPU reach to secondary_entry */ +0: ldr r0, [r1] + cmp r0, #0 + bne 0b + bx lr +ENDPROC(wakeup_secondary) diff --git a/arch/arm/cpu/armv7/uniphier/spl.c b/arch/arm/cpu/armv7/uniphier/spl.c new file mode 100644 index 0000000000..40d28adaf3 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/spl.c @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2013-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +void spl_board_init(void) +{ +#if defined(CONFIG_BOARD_POSTCLK_INIT) + board_postclk_init(); +#endif + dram_init(); +} diff --git a/arch/arm/cpu/armv7/uniphier/support_card.c b/arch/arm/cpu/armv7/uniphier/support_card.c new file mode 100644 index 0000000000..40d49409c2 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/support_card.c @@ -0,0 +1,180 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) + +#define PFC_MICRO_SUPPORT_CARD_RESET \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034) +#define PFC_MICRO_SUPPORT_CARD_REVISION \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0) +/* + * 0: reset deassert, 1: reset + * + * bit[0]: LAN, I2C, LED + * bit[1]: UART + */ +void support_card_reset_deassert(void) +{ + writel(0, PFC_MICRO_SUPPORT_CARD_RESET); +} + +void support_card_reset(void) +{ + writel(3, PFC_MICRO_SUPPORT_CARD_RESET); +} + +static int support_card_show_revision(void) +{ + u32 revision; + + revision = readl(PFC_MICRO_SUPPORT_CARD_REVISION); + printf("(PFC CPLD version %d.%d)\n", revision >> 4, revision & 0xf); + return 0; +} +#endif + +#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) + +#define DCC_MICRO_SUPPORT_CARD_RESET_LAN \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x00401300) +#define DCC_MICRO_SUPPORT_CARD_RESET_UART \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x00401304) +#define DCC_MICRO_SUPPORT_CARD_RESET_I2C \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x00401308) +#define DCC_MICRO_SUPPORT_CARD_REVISION \ + ((CONFIG_SUPPORT_CARD_BASE) + 0x005000E0) + +void support_card_reset_deassert(void) +{ + writel(1, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */ + writel(1, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */ + writel(1, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */ +} + +void support_card_reset(void) +{ + writel(0, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */ + writel(0, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */ + writel(0, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */ +} + +static int support_card_show_revision(void) +{ + u32 revision; + + revision = readl(DCC_MICRO_SUPPORT_CARD_REVISION); + + if (revision >= 0x67) { + printf("(DCC CPLD version 3.%d.%d)\n", + revision >> 4, revision & 0xf); + return 0; + } else { + printf("(DCC CPLD unknown version)\n"); + return -1; + } +} +#endif + +void support_card_init(void) +{ + /* + * After power on, we need to keep the LAN controller in reset state + * for a while. (200 usec) + * Fortunatelly, enough wait time is already inserted in pll_init() + * function. So we do not have to wait here. + */ + support_card_reset_deassert(); +} + +int check_support_card(void) +{ + printf("SC: Micro Support Card "); + return support_card_show_revision(); +} + +#if defined(CONFIG_SMC911X) +#include + +int board_eth_init(bd_t *bis) +{ + return smc911x_initialize(0, CONFIG_SMC911X_BASE); +} +#endif + +#if !defined(CONFIG_SYS_NO_FLASH) + +#include + +#if CONFIG_SYS_MAX_FLASH_BANKS > 1 +static phys_addr_t flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS] = + CONFIG_SYS_FLASH_BANKS_LIST; + +phys_addr_t cfi_flash_bank_addr(int i) +{ + return flash_banks_list[i]; +} +#endif + +int mem_is_flash(phys_addr_t base) +{ + const int loop = 128; + u32 *scratch_addr; + u32 saved_value; + int ret = 1; + int i; + + scratch_addr = map_physmem(base + 0x01e00000, + sizeof(u32) * loop, MAP_NOCACHE); + + for (i = 0; i < loop; i++, scratch_addr++) { + saved_value = readl(scratch_addr); + writel(~saved_value, scratch_addr); + if (readl(scratch_addr) != saved_value) { + /* We assume no memory or SRAM here. */ + writel(saved_value, scratch_addr); + ret = 0; + break; + } + } + + unmap_physmem(scratch_addr, MAP_NOCACHE); + + return ret; +} + +int board_flash_wp_on(void) +{ + int i; + int ret = 1; + + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { + if (mem_is_flash(cfi_flash_bank_addr(i))) { + /* + * We found at least one flash. + * We need to return 0 and call flash_init(). + */ + ret = 0; + } +#if CONFIG_SYS_MAX_FLASH_BANKS > 1 + else { + /* + * We might have a SRAM here. + * To prevent SRAM data from being destroyed, + * we set dummy address (SDRAM). + */ + flash_banks_list[i] = 0x80000000 + 0x10000 * i; + } +#endif + } + + return ret; +} +#endif diff --git a/arch/arm/cpu/armv7/uniphier/timer.c b/arch/arm/cpu/armv7/uniphier/timer.c new file mode 100644 index 0000000000..6edc0842a9 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/timer.c @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */ +#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1) + +static void *get_global_timer_base(void) +{ + void *val; + + asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (val) : : "memory"); + + return val + GLOBAL_TIMER_OFFSET; +} + +unsigned long timer_read_counter(void) +{ + /* + * ARM 64bit Global Timer is too much for our purpose. + * We use only lower 32 bit of the timer counter. + */ + return readl(get_global_timer_base() + GTIMER_CNT_L); +} + +int timer_init(void) +{ + /* enable timer */ + writel(PRESCALER << 8 | 1, get_global_timer_base() + GTIMER_CTRL); + + return 0; +} diff --git a/arch/arm/include/asm/arch-uniphier/arm-mpcore.h b/arch/arm/include/asm/arch-uniphier/arm-mpcore.h new file mode 100644 index 0000000000..cf7cd46c10 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/arm-mpcore.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_ARM_MPCORE_H +#define ARCH_ARM_MPCORE_H + +/* Snoop Control Unit */ +#define SCU_OFFSET 0x00 + +/* SCU Control Register */ +#define SCU_CTRL 0x00 +/* SCU Configuration Register */ +#define SCU_CONF 0x04 +/* SCU CPU Power Status Register */ +#define SCU_PWR_STATUS 0x08 +/* SCU Invalidate All Registers in Secure State */ +#define SCU_INV_ALL 0x0C +/* SCU Filtering Start Address Register */ +#define SCU_FILTER_START 0x40 +/* SCU Filtering End Address Register */ +#define SCU_FILTER_END 0x44 +/* SCU Access Control Register */ +#define SCU_SAC 0x50 +/* SCU Non-secure Access Control Register */ +#define SCU_SNSAC 0x54 + +/* Global Timer */ +#define GLOBAL_TIMER_OFFSET 0x200 + +/* Global Timer Counter Registers */ +#define GTIMER_CNT_L 0x00 +#define GTIMER_CNT_H 0x04 +/* Global Timer Control Register */ +#define GTIMER_CTRL 0x08 +/* Global Timer Interrupt Status Register */ +#define GTIMER_STAT 0x0C +/* Comparator Value Registers */ +#define GTIMER_CMP_L 0x10 +#define GTIMER_CMP_H 0x14 +/* Auto-increment Register */ +#define GTIMER_INC 0x18 + +#endif /* ARCH_ARM_MPCORE_H */ diff --git a/arch/arm/include/asm/arch-uniphier/bcu-regs.h b/arch/arm/include/asm/arch-uniphier/bcu-regs.h new file mode 100644 index 0000000000..0dfd94e5d7 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/bcu-regs.h @@ -0,0 +1,30 @@ +/* + * UniPhier BCU (Bus Control Unit) registers + * + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_BCU_REGS_H +#define ARCH_BCU_REGS_H + +#define BCU_BASE 0x50080000 + +#define BCSCR(x) (BCU_BASE + 0x180 + (x) * 4) +#define BCSCR0 (BCSCR(0)) +#define BCSCR1 (BCSCR(1)) +#define BCSCR2 (BCSCR(2)) +#define BCSCR3 (BCSCR(3)) +#define BCSCR4 (BCSCR(4)) +#define BCSCR5 (BCSCR(5)) + +#define BCIPPCCHR(x) (BCU_BASE + 0x0280 + (x) * 4) +#define BCIPPCCHR0 (BCIPPCCHR(0)) +#define BCIPPCCHR1 (BCIPPCCHR(1)) +#define BCIPPCCHR2 (BCIPPCCHR(2)) +#define BCIPPCCHR3 (BCIPPCCHR(3)) +#define BCIPPCCHR4 (BCIPPCCHR(4)) +#define BCIPPCCHR5 (BCIPPCCHR(5)) + +#endif /* ARCH_BCU_REGS_H */ diff --git a/arch/arm/include/asm/arch-uniphier/board.h b/arch/arm/include/asm/arch-uniphier/board.h new file mode 100644 index 0000000000..e6ba4e4ee4 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/board.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_BOARD_H +#define ARCH_BOARD_H + +#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) || \ + defined(CONFIG_DCC_MICRO_SUPPORT_CARD) +void support_card_reset(void); +void support_card_init(void); +int check_support_card(void); +#else +#define support_card_reset() do {} while (0) +#define support_card_init() do {} while (0) +static inline int check_support_card(void) +{ + return 0; +} +#endif + +static inline void uniphier_board_reset(void) +{ + support_card_reset(); +} + +static inline void uniphier_board_init(void) +{ + support_card_init(); +} + +#endif /* ARCH_BOARD_H */ diff --git a/arch/arm/include/asm/arch-uniphier/boot-device.h b/arch/arm/include/asm/arch-uniphier/boot-device.h new file mode 100644 index 0000000000..6987f57669 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/boot-device.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_BOOT_DEVICE_H_ +#define _ASM_BOOT_DEVICE_H_ + +u32 get_boot_mode_sel(void); + +struct boot_device_info { + u32 type; + char *info; +}; + +extern struct boot_device_info boot_device_table[]; + +#endif /* _ASM_BOOT_DEVICE_H_ */ diff --git a/arch/arm/include/asm/arch-uniphier/led.h b/arch/arm/include/asm/arch-uniphier/led.h new file mode 100644 index 0000000000..21277dac76 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/led.h @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_LED_H +#define ARCH_LED_H + +#include + +#define LED_CHAR_0 0x7e +#define LED_CHAR_1 0x0c +#define LED_CHAR_2 0xb6 +#define LED_CHAR_3 0x9e +#define LED_CHAR_4 0xcc +#define LED_CHAR_5 0xda +#define LED_CHAR_6 0xfa +#define LED_CHAR_7 0x4e +#define LED_CHAR_8 0xfe +#define LED_CHAR_9 0xde + +#define LED_CHAR_A 0xee +#define LED_CHAR_B 0xf8 +#define LED_CHAR_C 0x72 +#define LED_CHAR_D 0xbc +#define LED_CHAR_E 0xf2 +#define LED_CHAR_F 0xe2 +#define LED_CHAR_G 0x7a +#define LED_CHAR_H 0xe8 +#define LED_CHAR_I 0x08 +#define LED_CHAR_J 0x3c +#define LED_CHAR_K 0xea +#define LED_CHAR_L 0x70 +#define LED_CHAR_M 0x6e +#define LED_CHAR_N 0xa8 +#define LED_CHAR_O 0xb8 +#define LED_CHAR_P 0xe6 +#define LED_CHAR_Q 0xce +#define LED_CHAR_R 0xa0 +#define LED_CHAR_S 0xc8 +#define LED_CHAR_T 0x8c +#define LED_CHAR_U 0x7c +#define LED_CHAR_V 0x54 +#define LED_CHAR_W 0xfc +#define LED_CHAR_X 0xec +#define LED_CHAR_Y 0xdc +#define LED_CHAR_Z 0xa4 + +#define LED_CHAR_SPACE 0x00 +#define LED_CHAR_DOT 0x01 + +#define LED_CHAR_ (LED_CHAR_SPACE) + +/** Macro to translate 4 characters into integer to display led */ +#define LED_C2I(C0, C1, C2, C3) \ + (~( \ + (LED_CHAR_##C0 << 24) | \ + (LED_CHAR_##C1 << 16) | \ + (LED_CHAR_##C2 << 8) | \ + (LED_CHAR_##C3) \ + )) + +#if defined(CONFIG_SUPPORT_CARD_LED_BASE) + +#define LED_ADDR CONFIG_SUPPORT_CARD_LED_BASE + +#ifdef __ASSEMBLY__ + +#define led_write(C0, C1, C2, C3) raw_led_write LED_C2I(C0, C1, C2, C3) +.macro raw_led_write data + ldr r0, =\data + ldr r1, =LED_ADDR + str r0, [r1] +.endm + +#else /* __ASSEMBLY__ */ + +#include + +#define led_write(C0, C1, C2, C3) \ +do { \ + raw_led_write(LED_C2I(C0, C1, C2, C3)); \ +} while (0) + +static inline void raw_led_write(u32 data) +{ + writel(data, LED_ADDR); +} + +#endif /* __ASSEMBLY__ */ + +#else /* CONFIG_SUPPORT_CARD_LED_BASE */ + +#define led_write(C0, C1, C2, C3) +#define raw_led_write(x) + +#endif /* CONFIG_SUPPORT_CARD_LED_BASE */ + +#endif /* ARCH_LED_H */ diff --git a/arch/arm/include/asm/arch-uniphier/sbc-regs.h b/arch/arm/include/asm/arch-uniphier/sbc-regs.h new file mode 100644 index 0000000000..8e410788ef --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/sbc-regs.h @@ -0,0 +1,108 @@ +/* + * UniPhier SBC (System Bus Controller) registers + * + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_SBC_REGS_H +#define ARCH_SBC_REGS_H + +#define SBBASE_BASE 0x58c00100 +#define SBBASE(x) (SBBASE_BASE + (x) * 0x10) + +#define SBBASE0 (SBBASE(0)) +#define SBBASE1 (SBBASE(1)) +#define SBBASE2 (SBBASE(2)) +#define SBBASE3 (SBBASE(3)) +#define SBBASE4 (SBBASE(4)) +#define SBBASE5 (SBBASE(5)) +#define SBBASE6 (SBBASE(6)) +#define SBBASE7 (SBBASE(7)) + +#define SBBASE_BANK_ENABLE (0x00000001) + +#define SBCTRL_BASE 0x58c00200 +#define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4) + +#define SBCTRL00 SBCTRL(0, 0) +#define SBCTRL01 SBCTRL(0, 1) +#define SBCTRL02 SBCTRL(0, 2) +#define SBCTRL03 SBCTRL(0, 3) +#define SBCTRL04 (SBCTRL_BASE + 0x100) + +#define SBCTRL10 SBCTRL(1, 0) +#define SBCTRL11 SBCTRL(1, 1) +#define SBCTRL12 SBCTRL(1, 2) +#define SBCTRL13 SBCTRL(1, 3) +#define SBCTRL14 (SBCTRL_BASE + 0x110) + +#define SBCTRL20 SBCTRL(2, 0) +#define SBCTRL21 SBCTRL(2, 1) +#define SBCTRL22 SBCTRL(2, 2) +#define SBCTRL23 SBCTRL(2, 3) +#define SBCTRL24 (SBCTRL_BASE + 0x120) + +#define SBCTRL30 SBCTRL(3, 0) +#define SBCTRL31 SBCTRL(3, 1) +#define SBCTRL32 SBCTRL(3, 2) +#define SBCTRL33 SBCTRL(3, 3) +#define SBCTRL34 (SBCTRL_BASE + 0x130) + +#define SBCTRL40 SBCTRL(4, 0) +#define SBCTRL41 SBCTRL(4, 1) +#define SBCTRL42 SBCTRL(4, 2) +#define SBCTRL43 SBCTRL(4, 3) +#define SBCTRL44 (SBCTRL_BASE + 0x140) + +#define SBCTRL50 SBCTRL(5, 0) +#define SBCTRL51 SBCTRL(5, 1) +#define SBCTRL52 SBCTRL(5, 2) +#define SBCTRL53 SBCTRL(5, 3) +#define SBCTRL54 (SBCTRL_BASE + 0x150) + +#define SBCTRL60 SBCTRL(6, 0) +#define SBCTRL61 SBCTRL(6, 1) +#define SBCTRL62 SBCTRL(6, 2) +#define SBCTRL63 SBCTRL(6, 3) +#define SBCTRL64 (SBCTRL_BASE + 0x160) + +#define SBCTRL70 SBCTRL(7, 0) +#define SBCTRL71 SBCTRL(7, 1) +#define SBCTRL72 SBCTRL(7, 2) +#define SBCTRL73 SBCTRL(7, 3) +#define SBCTRL74 (SBCTRL_BASE + 0x170) + +/* slower but LED works */ +#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000 +#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00 +#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009 +#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110 + +/* faster but LED does not work */ +#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000 +#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700 +/* NOR flash needs more wait counts than SRAM */ +#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009 +#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210 + +#define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000 +#define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500 +#define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020 + +#define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000 +#define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500 +#define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010 + +#define ROM_BOOT_ROMRSV2 0x59801208 + +#ifndef __ASSEMBLY__ +#include +static inline int boot_is_swapped(void) +{ + return !(readl(SBBASE0) & SBBASE_BANK_ENABLE); +} +#endif + +#endif /* ARCH_SBC_REGS_H */ diff --git a/arch/arm/include/asm/arch-uniphier/sc-regs.h b/arch/arm/include/asm/arch-uniphier/sc-regs.h new file mode 100644 index 0000000000..1197bb52d4 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/sc-regs.h @@ -0,0 +1,62 @@ +/* + * UniPhier SC (System Control) block registers + * + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_SC_REGS_H +#define ARCH_SC_REGS_H + +#define SC_BASE_ADDR 0x61840000 + +#define SC_MPLLOSCCTL (SC_BASE_ADDR | 0x1184) +#define SC_MPLLOSCCTL_MPLLEN (0x1 << 0) +#define SC_MPLLOSCCTL_MPLLST (0x1 << 1) + +#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200) +#define SC_DPLLCTRL_SSC_EN (0x1 << 31) +#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16) +#define SC_DPLLCTRL_SSC_RATE (0x1 << 15) + +#define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204) +#define SC_DPLLCTRL2_NRSTDS (0x1 << 28) + +#define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208) +#define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31) +#define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31) + +#define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210) + +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270) +#define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274) +#define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278) + +#define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290) +#define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294) +#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298) + +#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) +#define SC_RSTCTRL_NRST_ETHER (0x1 << 12) +#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5) +#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4) +#define SC_RSTCTRL_NRST_NAND (0x1 << 2) + +#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004) +#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) + +#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) +#define SC_CLKCTRL_CLK_ETHER (0x1 << 12) +#define SC_CLKCTRL_CLK_MIO (0x1 << 11) +#define SC_CLKCTRL_CLK_UMC (0x1 << 4) +#define SC_CLKCTRL_CLK_NAND (0x1 << 2) +#define SC_CLKCTRL_CLK_SBC (0x1 << 1) +#define SC_CLKCTRL_CLK_PERI (0x1 << 0) + +/* System reset control register */ +#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000) +#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010) +#define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014) + +#endif /* ARCH_SC_REGS_H */ diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h new file mode 100644 index 0000000000..79d7ec7148 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h @@ -0,0 +1,182 @@ +/* + * UniPhier SG (SoC Glue) block registers + * + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_SG_REGS_H +#define ARCH_SG_REGS_H + +/* Base Address */ +#define SG_CTRL_BASE 0x5f800000 +#define SG_DBG_BASE 0x5f900000 + +/* Revision */ +#define SG_REVISION (SG_CTRL_BASE | 0x0000) +#define SG_REVISION_TYPE_SHIFT 16 +#define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT) +#define SG_REVISION_MODEL_SHIFT 8 +#define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT) +#define SG_REVISION_REV_SHIFT 0 +#define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT) + +/* Memory Configuration */ +#define SG_MEMCONF (SG_CTRL_BASE | 0x0400) + +#define SG_MEMCONF_CH0_SIZE_64MB ((0x0 << 10) | (0x01 << 0)) +#define SG_MEMCONF_CH0_SIZE_128MB ((0x0 << 10) | (0x02 << 0)) +#define SG_MEMCONF_CH0_SIZE_256MB ((0x0 << 10) | (0x03 << 0)) +#define SG_MEMCONF_CH0_SIZE_512MB ((0x1 << 10) | (0x00 << 0)) +#define SG_MEMCONF_CH0_SIZE_1024MB ((0x1 << 10) | (0x01 << 0)) +#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8) +#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8) + +#define SG_MEMCONF_CH1_SIZE_64MB ((0x0 << 11) | (0x01 << 2)) +#define SG_MEMCONF_CH1_SIZE_128MB ((0x0 << 11) | (0x02 << 2)) +#define SG_MEMCONF_CH1_SIZE_256MB ((0x0 << 11) | (0x03 << 2)) +#define SG_MEMCONF_CH1_SIZE_512MB ((0x1 << 11) | (0x00 << 2)) +#define SG_MEMCONF_CH1_SIZE_1024MB ((0x1 << 11) | (0x01 << 2)) +#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9) +#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9) + +#define SG_MEMCONF_SPARSEMEM (0x1 << 4) + +/* Pin Control */ +#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000) + +#if defined(CONFIG_MACH_PH1_PRO4) +# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8) +#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) +# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4) +#endif + +#if defined(CONFIG_MACH_PH1_PRO4) +#define SG_PINSELBITS 4 +#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) +#define SG_PINSELBITS 8 +#endif + +#define SG_PINSEL_ADDR(n) (SG_PINCTRL((n) * (SG_PINSELBITS) / 32)) +#define SG_PINSEL_MASK(n) (~(((1 << (SG_PINSELBITS)) - 1) << \ + ((n) * (SG_PINSELBITS) % 32))) +#define SG_PINSEL_MODE(n, mode) ((mode) << ((n) * (SG_PINSELBITS) % 32)) + +/* Only for PH1-Pro4 */ +#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700) + +/* Input Enable */ +#define SG_IECTRL (SG_CTRL_BASE | 0x1d00) + +/* Pin Monitor */ +#define SG_PINMON0 (SG_DBG_BASE | 0x0100) + +#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19) +#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19) +#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19) +#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19) + +#define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16) + +#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16) +#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16) + +#ifndef __ASSEMBLY__ +#include +#include + +static inline void sg_set_pinsel(int n, int value) +{ + writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n)) + | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n)); +} + +static inline u32 sg_memconf_val_ch0(unsigned long size, int num) +{ + int size_mb = (size >> 20) / num; + u32 ret; + + switch (size_mb) { + case 64: + ret = SG_MEMCONF_CH0_SIZE_64MB; + break; + case 128: + ret = SG_MEMCONF_CH0_SIZE_128MB; + break; + case 256: + ret = SG_MEMCONF_CH0_SIZE_256MB; + break; + case 512: + ret = SG_MEMCONF_CH0_SIZE_512MB; + break; + case 1024: + ret = SG_MEMCONF_CH0_SIZE_1024MB; + break; + default: + BUG(); + break; + } + + switch (num) { + case 1: + ret |= SG_MEMCONF_CH0_NUM_1; + break; + case 2: + ret |= SG_MEMCONF_CH0_NUM_2; + break; + default: + BUG(); + break; + } + return ret; +} + +static inline u32 sg_memconf_val_ch1(unsigned long size, int num) +{ + int size_mb = (size >> 20) / num; + u32 ret; + + switch (size_mb) { + case 64: + ret = SG_MEMCONF_CH1_SIZE_64MB; + break; + case 128: + ret = SG_MEMCONF_CH1_SIZE_128MB; + break; + case 256: + ret = SG_MEMCONF_CH1_SIZE_256MB; + break; + case 512: + ret = SG_MEMCONF_CH1_SIZE_512MB; + break; + case 1024: + ret = SG_MEMCONF_CH1_SIZE_1024MB; + break; + default: + BUG(); + break; + } + + switch (num) { + case 1: + ret |= SG_MEMCONF_CH1_NUM_1; + break; + case 2: + ret |= SG_MEMCONF_CH1_NUM_2; + break; + default: + BUG(); + break; + } + return ret; +} +#endif /* __ASSEMBLY__ */ + +#endif /* ARCH_SG_REGS_H */ diff --git a/arch/arm/include/asm/arch-uniphier/ssc-regs.h b/arch/arm/include/asm/arch-uniphier/ssc-regs.h new file mode 100644 index 0000000000..77b3470c6d --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/ssc-regs.h @@ -0,0 +1,67 @@ +/* + * UniPhier System Cache (L2 Cache) registers + * + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_SSC_REGS_H +#define ARCH_SSC_REGS_H + +#define SSCC 0x500c0000 +#define SSCC_BST (0x1 << 20) +#define SSCC_ACT (0x1 << 19) +#define SSCC_WTG (0x1 << 18) +#define SSCC_PRD (0x1 << 17) +#define SSCC_WBWA (0x1 << 16) +#define SSCC_EX (0x1 << 13) +#define SSCC_ON (0x1 << 0) + +#define SSCLPDAWCR 0x500c0030 + +#define SSCOPE 0x506c0244 +#define SSCOPE_CM_SYNC 0x00000008 + +#define SSCOQM 0x506c0248 +#define SSCOQM_TID_MASK (0x3 << 21) +#define SSCOQM_TID_BY_WAY (0x2 << 21) +#define SSCOQM_TID_BY_INST_WAY (0x1 << 21) +#define SSCOQM_TID_BY_DATA_WAY (0x0 << 21) +#define SSCOQM_S_MASK (0x3 << 17) +#define SSCOQM_S_WAY (0x2 << 17) +#define SSCOQM_S_ALL (0x1 << 17) +#define SSCOQM_S_ADDRESS (0x0 << 17) +#define SSCOQM_CE (0x1 << 15) +#define SSCOQM_CW (0x1 << 14) +#define SSCOQM_CM_MASK (0x7) +#define SSCOQM_CM_DIRT_TOUCH (0x7) +#define SSCOQM_CM_ZERO_TOUCH (0x6) +#define SSCOQM_CM_NORM_TOUCH (0x5) +#define SSCOQM_CM_PREF_FETCH (0x4) +#define SSCOQM_CM_SSC_FETCH (0x3) +#define SSCOQM_CM_WB_INV (0x2) +#define SSCOQM_CM_WB (0x1) +#define SSCOQM_CM_INV (0x0) + +#define SSCOQAD 0x506c024c +#define SSCOQSZ 0x506c0250 +#define SSCOQWN 0x506c0258 + +#define SSCOPPQSEF 0x506c025c +#define SSCOPPQSEF_FE (0x1 << 1) +#define SSCOPPQSEF_OE (0x1 << 0) + +#define SSCOLPQS 0x506c0260 +#define SSCOLPQS_EF (0x1 << 2) +#define SSCOLPQS_EST (0x1 << 1) +#define SSCOLPQS_QST (0x1 << 0) + +#define SSCOQCE0 0x506c0270 + +#define SSC_LINE_SIZE 128 +#define SSC_NUM_ENTRIES 256 +#define SSC_WAY_SIZE ((SSC_LINE_SIZE) * (SSC_NUM_ENTRIES)) +#define SSC_RANGE_OP_MAX_SIZE (0x00400000 - (SSC_LINE_SIZE)) + +#endif /* ARCH_SSC_REGS_H */ diff --git a/arch/arm/include/asm/arch-uniphier/umc-regs.h b/arch/arm/include/asm/arch-uniphier/umc-regs.h new file mode 100644 index 0000000000..6159281fd3 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/umc-regs.h @@ -0,0 +1,119 @@ +/* + * UniPhier UMC (Universal Memory Controller) registers + * + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_UMC_REGS_H +#define ARCH_UMC_REGS_H + +#define UMC_BASE 0x5b800000 + +/* SSIF registers */ +#define UMC_SSIF_BASE UMC_BASE + +#define UMC_CPURST 0x00000700 +#define UMC_IDSRST 0x0000070C +#define UMC_IXMRST 0x00000714 +#define UMC_HDMRST 0x00000718 +#define UMC_MDMRST 0x0000071C +#define UMC_HDDRST 0x00000720 +#define UMC_MDDRST 0x00000724 +#define UMC_SIORST 0x00000728 +#define UMC_GIORST 0x0000072C +#define UMC_HD2RST 0x00000734 +#define UMC_VIORST 0x0000073C +#define UMC_FRCRST 0x00000748 /* LD4/sLD8 */ +#define UMC_DVCRST 0x00000748 /* Pro4 */ +#define UMC_RGLRST 0x00000750 +#define UMC_VPERST 0x00000758 +#define UMC_AIORST 0x00000764 +#define UMC_DMDRST 0x00000770 + +#define UMC_HDMCHSEL 0x00000898 +#define UMC_MDMCHSEL 0x0000089C +#define UMC_DVCCHSEL 0x000008C8 +#define UMC_DMDCHSEL 0x000008F0 + +#define UMC_CLKEN_SSIF_FETCH 0x0000C060 +#define UMC_CLKEN_SSIF_COMQUE0 0x0000C064 +#define UMC_CLKEN_SSIF_COMWC0 0x0000C068 +#define UMC_CLKEN_SSIF_COMRC0 0x0000C06C +#define UMC_CLKEN_SSIF_COMQUE1 0x0000C070 +#define UMC_CLKEN_SSIF_COMWC1 0x0000C074 +#define UMC_CLKEN_SSIF_COMRC1 0x0000C078 +#define UMC_CLKEN_SSIF_WC 0x0000C07C +#define UMC_CLKEN_SSIF_RC 0x0000C080 +#define UMC_CLKEN_SSIF_DST 0x0000C084 + +/* CA registers */ +#define UMC_CA_BASE(ch) (UMC_BASE + 0x00001000 + 0x00001000 * (ch)) + +/* DRAM controller registers */ +#define UMC_DRAMCONT_BASE(ch) (UMC_BASE + 0x00400000 + 0x00200000 * (ch)) + +#define UMC_CMDCTLA 0x00000000 +#define UMC_CMDCTLB 0x00000004 +#define UMC_INITCTLA 0x00000008 +#define UMC_INITCTLB 0x0000000C +#define UMC_INITCTLC 0x00000010 +#define UMC_INITSET 0x00000014 +#define UMC_INITSTAT 0x00000018 +#define UMC_DRMMR0 0x0000001C +#define UMC_DRMMR1 0x00000020 +#define UMC_DRMMR2 0x00000024 +#define UMC_DRMMR3 0x00000028 +#define UMC_SPCCTLA 0x00000030 +#define UMC_SPCCTLB 0x00000034 +#define UMC_SPCSETA 0x00000038 +#define UMC_SPCSETB 0x0000003C +#define UMC_SPCSETC 0x00000040 +#define UMC_SPCSETD 0x00000044 +#define UMC_SPCSTATA 0x00000050 +#define UMC_SPCSTATB 0x00000054 +#define UMC_SPCSTATC 0x00000058 +#define UMC_ACSSETA 0x00000060 +#define UMC_FLOWCTLA 0x00000400 +#define UMC_FLOWCTLB 0x00000404 +#define UMC_FLOWCTLC 0x00000408 +#define UMC_FLOWCTLG 0x00000508 +#define UMC_RDATACTL_D0 0x00000600 +#define UMC_WDATACTL_D0 0x00000604 +#define UMC_RDATACTL_D1 0x00000608 +#define UMC_WDATACTL_D1 0x0000060C +#define UMC_DATASET 0x00000610 +#define UMC_DCCGCTL 0x00000720 +#define UMC_DICGCTLA 0x00000724 +#define UMC_DICGCTLB 0x00000728 +#define UMC_DIOCTLA 0x00000C00 +#define UMC_DFICUPDCTLA 0x00000C20 + +#ifndef __ASSEMBLY__ + +#include + +static inline void umc_polling(u32 address, u32 expval, u32 mask) +{ + u32 nmask = ~mask; + u32 data; + do { + data = readl(address) & nmask; + } while (data != expval); +} + +static inline void umc_dram_init_start(void __iomem *dramcont) +{ + writel(0x00000002, dramcont + UMC_INITSET); +} + +static inline void umc_dram_init_poll(void __iomem *dramcont) +{ + while ((readl(dramcont + UMC_INITSTAT) & 0x00000002)) + ; +} + +#endif + +#endif diff --git a/include/configs/ph1_ld4.h b/include/configs/ph1_ld4.h new file mode 100644 index 0000000000..a28d7b579a --- /dev/null +++ b/include/configs/ph1_ld4.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PH1_XXX_H +#define __PH1_XXX_H + +/* + * Support Card Select + * + * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC. + * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card. + * CPLD is re-programmed for ARIMA board compatibility. + * No define - No support card. + */ + +#if 0 +#define CONFIG_PFC_MICRO_SUPPORT_CARD +#else +#define CONFIG_DCC_MICRO_SUPPORT_CARD +#endif + +/* + * Serial Configuration + * SoC UART : enable CONFIG_UNIPHIER_SERIAL + * On-board UART: enable CONFIG_SYS_NS16550_SERIAL + */ +#if 1 +#define CONFIG_UNIPHIER_SERIAL +#else +#define CONFIG_SYS_NS16550_SERIAL +#endif + +#define CONFIG_SYS_UNIPHIER_UART_CLK 36864000 + +#define CONFIG_SMC911X + +#define CONFIG_DDR_NUM_CH0 1 +#define CONFIG_DDR_NUM_CH1 1 + +#define CONFIG_DDR_FREQ 1600 + +/* + * Memory Size & Mapping + */ +/* Physical start address of SDRAM */ +#define CONFIG_SDRAM0_BASE 0x80000000 +#define CONFIG_SDRAM0_SIZE 0x10000000 +#define CONFIG_SDRAM1_BASE 0x90000000 +#define CONFIG_SDRAM1_SIZE 0x10000000 + +#define CONFIG_SPL_TEXT_BASE 0x40000 + +#include "uniphier-common.h" + +#endif /* __PH1_XXX_H */ diff --git a/include/configs/ph1_pro4.h b/include/configs/ph1_pro4.h new file mode 100644 index 0000000000..b79967f7da --- /dev/null +++ b/include/configs/ph1_pro4.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PH1_XXX_H +#define __PH1_XXX_H + +/* + * Support Card Select + * + * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC. + * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card. + * CPLD is re-programmed for ARIMA board compatibility. + * No define - No support card. + */ + +#if 0 +#define CONFIG_PFC_MICRO_SUPPORT_CARD +#else +#define CONFIG_DCC_MICRO_SUPPORT_CARD +#endif + +/* + * Serial Configuration + * SoC UART : enable CONFIG_UNIPHIER_SERIAL + * On-board UART: enable CONFIG_SYS_NS16550_SERIAL + */ +#if 1 +#define CONFIG_UNIPHIER_SERIAL +#else +#define CONFIG_SYS_NS16550_SERIAL +#endif + +#define CONFIG_SYS_UNIPHIER_UART_CLK 73728000 + +#define CONFIG_SMC911X + +#define CONFIG_DDR_NUM_CH0 2 +#define CONFIG_DDR_NUM_CH1 2 + +#define CONFIG_DDR_FREQ 1600 + +#define CONFIG_UNIPHIER_SMP + +/* + * Memory Size & Mapping + */ +/* Physical start address of SDRAM */ +#define CONFIG_SDRAM0_BASE 0x80000000 +#define CONFIG_SDRAM0_SIZE 0x20000000 +#define CONFIG_SDRAM1_BASE 0xa0000000 +#define CONFIG_SDRAM1_SIZE 0x20000000 + +#define CONFIG_SPL_TEXT_BASE 0x100000 + +#include "uniphier-common.h" + +#endif /* __PH1_XXX_H */ diff --git a/include/configs/ph1_sld8.h b/include/configs/ph1_sld8.h new file mode 100644 index 0000000000..9d391f1d74 --- /dev/null +++ b/include/configs/ph1_sld8.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PH1_XXX_H +#define __PH1_XXX_H + +/* + * Support Card Select + * + * CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC. + * CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card. + * CPLD is re-programmed for ARIMA board compatibility. + * No define - No support card. + */ + +#if 0 +#define CONFIG_PFC_MICRO_SUPPORT_CARD +#else +#define CONFIG_DCC_MICRO_SUPPORT_CARD +#endif + +/* + * Serial Configuration + * SoC UART : enable CONFIG_UNIPHIER_SERIAL + * On-board UART: enable CONFIG_SYS_NS16550_SERIAL + */ +#if 1 +#define CONFIG_UNIPHIER_SERIAL +#else +#define CONFIG_SYS_NS16550_SERIAL +#endif + +#define CONFIG_SYS_UNIPHIER_UART_CLK 80000000 + +#define CONFIG_SMC911X + +#define CONFIG_DDR_NUM_CH0 1 +#define CONFIG_DDR_NUM_CH1 1 + +#define CONFIG_DDR_FREQ 1333 + +/* #define CONFIG_DDR_STANDARD */ + +/* + * Memory Size & Mapping + */ +/* Physical start address of SDRAM */ +#define CONFIG_SDRAM0_BASE 0x80000000 +#define CONFIG_SDRAM0_SIZE 0x10000000 +#define CONFIG_SDRAM1_BASE 0x90000000 +#define CONFIG_SDRAM1_SIZE 0x10000000 + +#define CONFIG_SPL_TEXT_BASE 0x40000 + +#include "uniphier-common.h" + +#endif /* __PH1_XXX_H */ diff --git a/include/configs/uniphier-common.h b/include/configs/uniphier-common.h new file mode 100644 index 0000000000..18fe277cad --- /dev/null +++ b/include/configs/uniphier-common.h @@ -0,0 +1,266 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* U-boot - Common settings for UniPhier Family */ + +#ifndef __CONFIG_UNIPHIER_COMMON_H__ +#define __CONFIG_UNIPHIER_COMMON_H__ + +#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) && \ + defined(CONFIG_DCC_MICRO_SUPPORT_CARD) +# error "Both CONFIG_PFC_MICRO_SUPPORT_CARD and CONFIG_DCC_MICRO_SUPPORT_CARD \ +are defined. Select only one of them." +#endif + +/* + * Support card address map + */ +#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) +# define CONFIG_SUPPORT_CARD_BASE 0x03f00000 +# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) +# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000) +# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000) +#endif + +#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) +# define CONFIG_SUPPORT_CARD_BASE 0x08000000 +# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) +# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630) +# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000) +#endif + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE +#define CONFIG_SYS_NS16550_CLK 12288000 +#define CONFIG_SYS_NS16550_REG_SIZE -2 + +#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE +#define CONFIG_SMC911X_32_BIT + +#define CONFIG_SYS_UNIPHIER_SERIAL_BASE0 0x54006800 +#define CONFIG_SYS_UNIPHIER_SERIAL_BASE1 0x54006900 +#define CONFIG_SYS_UNIPHIER_SERIAL_BASE2 0x54006a00 +#define CONFIG_SYS_UNIPHIER_SERIAL_BASE3 0x54006b00 + +/*----------------------------------------------------------------------- + * MMU and Cache Setting + *----------------------------------------------------------------------*/ + +/* Comment out the following to enable L1 cache */ +/* #define CONFIG_SYS_ICACHE_OFF */ +/* #define CONFIG_SYS_DCACHE_OFF */ + +/* Comment out the following to enable L2 cache */ +#define CONFIG_UNIPHIER_L2CACHE_ON + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#define CONFIG_TIMESTAMP + +/* FLASH related */ +#define CONFIG_MTD_DEVICE + +/* + * uncomment the following to disable FLASH related code. + */ +/* #define CONFIG_SYS_NO_FLASH */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI + +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MONITOR_BASE 0 +#define CONFIG_SYS_FLASH_BASE 0 + +/* + * flash_toggle does not work for out supoort card. + * We need to use flash_status_poll. + */ +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL + +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) +# define CONFIG_SYS_MAX_FLASH_BANKS 1 +# define CONFIG_SYS_FLASH_BANKS_LIST {0x00000000} +# define CONFIG_SYS_FLASH_BANKS_SIZES {0x02000000} +#endif + +#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) +# define CONFIG_SYS_MAX_FLASH_BANKS 1 +# define CONFIG_SYS_FLASH_BANKS_LIST {0x04000000} +# define CONFIG_SYS_FLASH_BANKS_SIZES {0x04000000} +#endif + +/* serial console configuration */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_GENERIC_BOARD + +#if !defined(CONFIG_SPL_BUILD) +#define CONFIG_USE_ARCH_MEMSET +#define CONFIG_USE_ARCH_MEMCPY +#endif + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ + +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_CONS_INDEX 1 + +/* + * For NAND booting the environment is embedded in the U-Boot image. Please take + * look at the file board/amcc/canyonlands/u-boot-nand.lds for details. + */ +/* #define CONFIG_ENV_IS_IN_NAND */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x0 +/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ + +/* Time clock 1MHz */ +#define CONFIG_SYS_TIMER_RATE 1000000 + +/* + * By default, ARP timeout is 5 sec. + * The first ARP request does not seem to work. + * So we need to retry ARP request anyway. + * We want to shrink the interval until the second ARP request. + */ +#define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_TIME +#define CONFIG_CMD_NAND /* NAND flash suppport */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 2 +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_NAND_DENALI_ECC_SIZE 1024 + +#define CONFIG_SYS_NAND_REGS_BASE 0x68100000 +#define CONFIG_SYS_NAND_DATA_BASE 0x68000000 + +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) + +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * Network Configuration + */ +#define CONFIG_ETHADDR 00:21:83:24:00:00 +#define CONFIG_SERVERIP 192.168.11.1 +#define CONFIG_IPADDR 192.168.11.10 +#define CONFIG_GATEWAYIP 192.168.11.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 0x84000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_BOOTFILE "fit.itb" + +#define CONFIG_CMDLINE_EDITING /* add command line history */ + +#define CONFIG_BOOTCOMMAND "run $bootmode" + +#define CONFIG_ROOTPATH "/nfs/root/path" +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs $bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ + "tftpboot; bootm;" + +#define CONFIG_BOOTARGS " user_debug=0x1f init=/sbin/init" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "image_offset=0x00080000\0" \ + "image_size=0x00f00000\0" \ + "verify=n\0" \ + "autostart=yes\0" \ + "norboot=run add_default_bootargs;" \ + "bootm $image_offset\0" \ + "nandboot=run add_default_bootargs;" \ + "nand read $loadaddr $image_offset $image_size;" \ + "bootm\0" \ + "add_default_bootargs=setenv bootargs $bootargs" \ + " console=ttyS0,$baudrate\0" \ + +/* FIT support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ + +/* Open Firmware flat tree */ +#define CONFIG_OF_LIBFDT + +#define CONFIG_HAVE_ARM_SECURE + +/* Memory Size & Mapping */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE + +#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE +/* Thre is no memory hole */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE) +#else +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE) +#endif + +#define CONFIG_SYS_TEXT_BASE 0x84000000 + +#if defined(CONFIG_SPL_BUILD) +#define CONFIG_BOARD_POSTCLK_INIT +#else +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_SYS_SPL_MALLOC_START (0x0ff00000) +#define CONFIG_SYS_SPL_MALLOC_SIZE (0x00004000) + +#define CONFIG_SYS_INIT_SP_ADDR (0x0ff08000) + +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_NAND_SUPPORT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */ +#define CONFIG_SPL_LIBGENERIC_SUPPORT + +#define CONFIG_SPL_BOARD_INIT + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 + +#endif /* __CONFIG_UNIPHIER_COMMON_H__ */ -- cgit v1.2.3 From 66cba041fe8fe4cdc3d8252974021257e736572a Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 3 Oct 2014 19:21:07 +0900 Subject: ARM: UniPhier: add Kconfig and defconfig This commit allows to build Panasonic UniPhier family: PH1-LD4, PH1-Pro4, PH1-sLD8 Signed-off-by: Masahiro Yamada --- arch/arm/Kconfig | 5 +++++ arch/arm/cpu/armv7/uniphier/Kconfig | 32 ++++++++++++++++++++++++++++++++ configs/ph1_ld4_defconfig | 8 ++++++++ configs/ph1_pro4_defconfig | 8 ++++++++ configs/ph1_sld8_defconfig | 8 ++++++++ 5 files changed, 61 insertions(+) create mode 100644 arch/arm/cpu/armv7/uniphier/Kconfig create mode 100644 configs/ph1_ld4_defconfig create mode 100644 configs/ph1_pro4_defconfig create mode 100644 configs/ph1_sld8_defconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3efede2c55..43ba33a2af 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -521,6 +521,9 @@ config TARGET_COLIBRI_PXA270 config TARGET_JORNADA bool "Support jornada" +config ARCH_UNIPHIER + bool "Panasonic UniPhier platform" + endchoice source "arch/arm/cpu/armv8/Kconfig" @@ -549,6 +552,8 @@ source "arch/arm/cpu/armv7/rmobile/Kconfig" source "arch/arm/cpu/armv7/tegra-common/Kconfig" +source "arch/arm/cpu/armv7/uniphier/Kconfig" + source "arch/arm/cpu/arm926ejs/versatile/Kconfig" source "arch/arm/cpu/armv7/zynq/Kconfig" diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig new file mode 100644 index 0000000000..34f5496c8c --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -0,0 +1,32 @@ +menu "Panasonic UniPhier platform" + depends on ARCH_UNIPHIER + +config SYS_CPU + string + default "armv7" + +config SYS_SOC + string + default "uniphier" + +config SYS_CONFIG_NAME + string + default "ph1_pro4" if MACH_PH1_PRO4 + default "ph1_ld4" if MACH_PH1_LD4 + default "ph1_sld8" if MACH_PH1_SLD8 + +choice + prompt "UniPhier SoC select" + +config MACH_PH1_PRO4 + bool "PH1-Pro4" + +config MACH_PH1_LD4 + bool "PH1-LD4" + +config MACH_PH1_SLD8 + bool "PH1-sLD8" + +endchoice + +endmenu diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig new file mode 100644 index 0000000000..53f3126e71 --- /dev/null +++ b/configs/ph1_ld4_defconfig @@ -0,0 +1,8 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_UNIPHIER=y ++S:CONFIG_MACH_PH1_LD4=y +CONFIG_NAND_DENALI=y +CONFIG_SYS_NAND_DENALI_64BIT=y +CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 +S:CONFIG_SPL_NAND_DENALI=y diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig new file mode 100644 index 0000000000..209466ebcb --- /dev/null +++ b/configs/ph1_pro4_defconfig @@ -0,0 +1,8 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_UNIPHIER=y ++S:CONFIG_MACH_PH1_PRO4=y +CONFIG_NAND_DENALI=y +CONFIG_SYS_NAND_DENALI_64BIT=y +CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 +S:CONFIG_SPL_NAND_DENALI=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig new file mode 100644 index 0000000000..658977bcf6 --- /dev/null +++ b/configs/ph1_sld8_defconfig @@ -0,0 +1,8 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_UNIPHIER=y ++S:CONFIG_MACH_PH1_SLD8=y +CONFIG_NAND_DENALI=y +CONFIG_SYS_NAND_DENALI_64BIT=y +CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 +S:CONFIG_SPL_NAND_DENALI=y -- cgit v1.2.3 From 0fb63aa63c35888dface83b44c1401be097277eb Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 3 Oct 2014 19:21:08 +0900 Subject: MAINTAINERS: add me as a maintainer of UniPhier platform Signed-off-by: Masahiro Yamada Acked-by: Albert ARIBAUD Acked-by: Michal Simek --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index af194ca755..aafa061ed8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -149,6 +149,15 @@ F: arch/arm/include/asm/arch-davinci/ F: arch/arm/include/asm/arch-omap*/ F: arch/arm/include/asm/ti-common/ +ARM UNIPHIER +M: Masahiro Yamada +S: Maintained +T: git git://git.denx.de/u-boot-uniphier.git +F: arch/arm/cpu/armv7/uniphier/ +F: arch/arm/include/asm/arch-uniphier/ +F: configs/ph1_*_defconfig +F: drivers/serial/serial_uniphier.c + ARM ZYNQ M: Michal Simek S: Maintained -- cgit v1.2.3 From 6dd0e7c00bfa5ce861a72b8e4a3ef9e787306125 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 3 Oct 2014 19:21:09 +0900 Subject: git-mailrc: add me as a maintainer of UniPhier platform Signed-off-by: Masahiro Yamada --- doc/git-mailrc | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/git-mailrc b/doc/git-mailrc index 0fba1003c4..35f2eb2fc1 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -63,6 +63,7 @@ alias sunxi uboot, ijc, jwrdegoede alias tegra uboot, sjg, Tom Warren , Stephen Warren alias tegra2 tegra alias ti uboot, trini +alias uniphier uboot, masahiro alias zynq uboot, monstr alias avr32 uboot, abiessmann -- cgit v1.2.3 From 45e60c25b54f0443265ee49909c70af90d5cbad9 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 28 Sep 2014 00:05:23 +0200 Subject: lsxl: convert to generic board and fix typo Besides converting the LS-XHL and LS-CHLv2 to generic board, fix a typo which accidentally reverted the bootsource to 'hdd' although the default bootsource should be 'legacy'. Cc: Tom Rini Cc: Prafulla Wadaskar Signed-off-by: Michael Walle Signed-off-by: Prafulla Wadaskar --- include/configs/lsxl.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index bf5c1a1298..a14bfe3a85 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -8,6 +8,8 @@ #ifndef _CONFIG_LSXL_H #define _CONFIG_LSXL_H +#define CONFIG_SYS_GENERIC_BOARD + /* * Version number information */ @@ -157,7 +159,7 @@ "standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \ "setenv ncip; setenv gatewayip; setenv ethact; " \ "setenv bootfile; setenv dnsip; " \ - "setenv bootsource hdd; run ser\0" \ + "setenv bootsource legacy; run ser\0" \ "restore_env=run standard_env; saveenv; reset\0" \ "ser=setenv stdin serial; setenv stdout serial; " \ "setenv stderr serial\0" \ -- cgit v1.2.3 From fb6f86c4116252bbae2fb8773a614b8c790d25d4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 30 Sep 2014 14:05:39 -0300 Subject: mx6sxsabresd: Fix PCI reset and power GPIO assignments PERST_GPIO and POWER_GPIO are currently swapped. Fix the GPIO assignments as per the board schematics. Signed-off-by: Fabio Estevam --- include/configs/mx6sxsabresd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index fd74c6980d..e02ea18a64 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -204,8 +204,8 @@ #define CONFIG_PCI_PNP #define CONFIG_PCI_SCAN_SHOW #define CONFIG_PCIE_IMX -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 1) -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 0) +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif /* FLASH and environment organization */ -- cgit v1.2.3 From ba743ac5c123d4a3491a995e20b930989d485795 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Wed, 1 Oct 2014 18:33:48 -0700 Subject: nitrogen6x: Update DDR timings for 2G memory arrangement Update DDR calibration settings based on a larger test set. The initial values were gathered on a small number of boards, and have been found to fail on some boards under load. Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg index bb5716e88d..1096f777ec 100644 --- a/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg +++ b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg @@ -24,18 +24,18 @@ DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43040319 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03040279 -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43040321 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03030251 -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4d434248 -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c4d -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x34424543 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x49324933 -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001a0017 -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00170027 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000a001f +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42740304 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026e0265 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x02750306 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02720244 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x463d4041 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c47 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x37414441 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4633473b +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0025001f +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00290027 +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f002b +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000f0029 DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 -- cgit v1.2.3 From 46f8a4b7e6cbf9cd86ad09f2a679fe1d78b79bb1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 25 Sep 2014 21:14:16 +0200 Subject: arm: m28evk: Zap superfluous tab in env Remove this tab from env, since it's useless, just use spaces. Signed-off-by: Marek Vasut Cc: Stefano Babic --- include/configs/m28evk.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 322b45fd99..efe770b81b 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -282,9 +282,9 @@ "mmc rescan;" \ "if test -e mmc 0:2 ${bootscript} ; then " \ "if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \ - "then;" \ - "\techo Running bootscript...;" \ - "\tsource ${kernel_addr_r};" \ + "then ; " \ + "echo Running bootscript... ; " \ + "source ${kernel_addr_r} ; " \ "fi ; " \ "fi\0" -- cgit v1.2.3 From 252499e603aa342368cb8a02c6d0641435e676c0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 25 Sep 2014 21:14:17 +0200 Subject: arm: m53evk: Zap superfluous tab in env Remove this tab from env, since it's useless, just use spaces. Signed-off-by: Marek Vasut Cc: Stefano Babic --- include/configs/m53evk.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index ee4eb10e46..c133ba9d03 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -351,9 +351,9 @@ "mmc rescan;" \ "if test -e mmc 0:1 ${bootscript} ; then " \ "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \ - "then;" \ - "\techo Running bootscript...;" \ - "\tsource ${kernel_addr_r};" \ + "then ; " \ + "echo Running bootscript... ; " \ + "source ${kernel_addr_r} ; " \ "fi ; " \ "fi\0" -- cgit v1.2.3 From 39d0973300b83c08f3f5047245ebf1de883b31f2 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Thu, 2 Oct 2014 13:33:46 +0200 Subject: imx6: add Bachmann OT1200 board This patch adds support for the OT1200 series of devices. Following components are used in u-boot: + ethernet + i2c + emmc + gpio For more details see README. Changes v1 > v2 - make use of enable_cspi_clock(..) - fix usage of OUTPUT_40OHM define - added README Changes v2 > v3 - improve spelling in README - added own copy of mx6q_4x_mt41j128.cfg Signed-off-by: Christian Gmeiner --- arch/arm/Kconfig | 4 + board/bachmann/ot1200/Kconfig | 23 +++ board/bachmann/ot1200/MAINTAINERS | 6 + board/bachmann/ot1200/Makefile | 9 ++ board/bachmann/ot1200/README | 20 +++ board/bachmann/ot1200/mx6q_4x_mt41j128.cfg | 169 +++++++++++++++++++ board/bachmann/ot1200/ot1200.c | 251 +++++++++++++++++++++++++++++ configs/ot1200_defconfig | 3 + include/configs/ot1200.h | 197 ++++++++++++++++++++++ 9 files changed, 682 insertions(+) create mode 100644 board/bachmann/ot1200/Kconfig create mode 100644 board/bachmann/ot1200/MAINTAINERS create mode 100644 board/bachmann/ot1200/Makefile create mode 100644 board/bachmann/ot1200/README create mode 100644 board/bachmann/ot1200/mx6q_4x_mt41j128.cfg create mode 100644 board/bachmann/ot1200/ot1200.c create mode 100644 configs/ot1200_defconfig create mode 100644 include/configs/ot1200.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 106aed985f..8face21d56 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -414,6 +414,9 @@ config TARGET_HUMMINGBOARD config TARGET_TQMA6 bool "TQ Systems TQMa6 board" +config TARGET_OT1200 + bool "Bachmann OT1200" + config OMAP34XX bool "OMAP34XX SoC" @@ -577,6 +580,7 @@ source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" source "board/atmel/sama5d3xek/Kconfig" +source "board/bachmann/ot1200/Kconfig" source "board/balloon3/Kconfig" source "board/barco/titanium/Kconfig" source "board/bluegiga/apx4devkit/Kconfig" diff --git a/board/bachmann/ot1200/Kconfig b/board/bachmann/ot1200/Kconfig new file mode 100644 index 0000000000..55a825d8aa --- /dev/null +++ b/board/bachmann/ot1200/Kconfig @@ -0,0 +1,23 @@ +if TARGET_OT1200 + +config SYS_CPU + string + default "armv7" + +config SYS_BOARD + string + default "ot1200" + +config SYS_VENDOR + string + default "bachmann" + +config SYS_SOC + string + default "mx6" + +config SYS_CONFIG_NAME + string + default "ot1200" + +endif diff --git a/board/bachmann/ot1200/MAINTAINERS b/board/bachmann/ot1200/MAINTAINERS new file mode 100644 index 0000000000..ad75c24ee4 --- /dev/null +++ b/board/bachmann/ot1200/MAINTAINERS @@ -0,0 +1,6 @@ +BACHMANN ELECTRONIC OT1200 BOARD +M: Christian Gmeiner +S: Maintained +F: board/bachmann/ot1200 +F: include/configs/ot1200.h +F: configs/ot1200*_defconfig diff --git a/board/bachmann/ot1200/Makefile b/board/bachmann/ot1200/Makefile new file mode 100644 index 0000000000..1bd42e8321 --- /dev/null +++ b/board/bachmann/ot1200/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2012-2013, Guennadi Liakhovetski +# (C) Copyright 2012-2013 Freescale Semiconductor, Inc. +# Copyright (C) 2013, Boundary Devices +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := ot1200.o diff --git a/board/bachmann/ot1200/README b/board/bachmann/ot1200/README new file mode 100644 index 0000000000..c03d44e458 --- /dev/null +++ b/board/bachmann/ot1200/README @@ -0,0 +1,20 @@ +U-Boot for the Bachmann electronic GmbH OT1200 devices + +There are two different versions of the base board, which differ +in the way ethernet is done. The variant detection is done during +runtime based on the address of the found phy. + +- "mr" variant +FEC is connected directly to an ethernet switch (KSZ8895). The ethernet +port is always up and auto-negotiation is not possible. + +- normal variant +FEC is connected to a normal phy and auto-negotiation is possible. + + +The variant name is part of the dtb file name loaded by u-boot. This +make is possible to boot the linux kernel and make use variant specific +devicetree (fixed-phy link). + +In order to support different display resoltuions/sizes the OT1200 devices +are making use of EDID data stored in an i2c EEPROM. diff --git a/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg b/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg new file mode 100644 index 0000000000..bb6c60b4c3 --- /dev/null +++ b/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 + +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 + +DATA 4 0x020e05ac 0x00020030 +DATA 4 0x020e05b4 0x00020030 +DATA 4 0x020e0528 0x00020030 +DATA 4 0x020e0520 0x00020030 + +DATA 4 0x020e0514 0x00020030 +DATA 4 0x020e0510 0x00020030 +DATA 4 0x020e05bc 0x00020030 +DATA 4 0x020e05c4 0x00020030 + +DATA 4 0x020e056c 0x00020030 +DATA 4 0x020e0578 0x00020030 +DATA 4 0x020e0588 0x00020030 +DATA 4 0x020e0594 0x00020030 + +DATA 4 0x020e057c 0x00020030 +DATA 4 0x020e0590 0x00003000 +DATA 4 0x020e0598 0x00003000 +DATA 4 0x020e058c 0x00000000 + +DATA 4 0x020e059c 0x00003030 +DATA 4 0x020e05a0 0x00003030 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 + +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 + +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e0750 0x00020000 + +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0798 0x000C0000 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +DATA 4 0x021b0018 0x00081740 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b000c 0x555A7974 +DATA 4 0x021b0010 0xDB538F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b002c 0x000026D2 + +DATA 4 0x021b0030 0x005A1023 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x831A0000 + +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x0408803A +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x0000803B +DATA 4 0x021b001c 0x00428031 +DATA 4 0x021b001c 0x00428039 +DATA 4 0x021b001c 0x19308030 +DATA 4 0x021b001c 0x19308038 + +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b001c 0x04008048 +DATA 4 0x021b0800 0xA1380003 +DATA 4 0x021b4800 0xA1380003 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b4818 0x00022227 + +DATA 4 0x021b083c 0x434B0350 +DATA 4 0x021b0840 0x034C0359 +DATA 4 0x021b483c 0x434B0350 +DATA 4 0x021b4840 0x03650348 +DATA 4 0x021b0848 0x4436383B +DATA 4 0x021b4848 0x39393341 +DATA 4 0x021b0850 0x35373933 +DATA 4 0x021b4850 0x48254A36 + +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F + +DATA 4 0x021b480c 0x00440044 +DATA 4 0x021b4810 0x00440044 + +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +DATA 4 0x021b001c 0x00000000 +DATA 4 0x021b0404 0x00011006 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x000000fb diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c new file mode 100644 index 0000000000..0d5ede5ca8 --- /dev/null +++ b/board/bachmann/ot1200/ot1200.c @@ -0,0 +1,251 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2014, Bachmann electronic GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \ + PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \ + PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \ + PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); +} + +static iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; + +static void setup_iomux_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_iomux_spi(); + + return 0; +} + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +struct fsl_esdhc_cfg usdhc_cfg[] = { + {USDHC3_BASE_ADDR}, +}; + +int board_mmc_init(bd_t *bis) +{ + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 8; + + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* I2C3 - IO expander */ +static struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, + .gp = IMX_GPIO_NR(3, 17) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, + .gp = IMX_GPIO_NR(3, 18) + } +}; + +static iomux_v3_cfg_t const pwm_pad[] = { + MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM), +}; + +static void leds_on(void) +{ + /* turn on all possible leds connected via GPIO expander */ + i2c_set_bus_num(2); + pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT); + pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0); +} + +static void backlight_lcd_off(void) +{ + unsigned gpio = IMX_GPIO_NR(2, 0); + gpio_direction_output(gpio, 0); + + gpio = IMX_GPIO_NR(2, 3); + gpio_direction_output(gpio, 0); +} + +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + setup_iomux_enet(); + + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + + /* scan phy 0 and 5 */ + phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + free(bus); + return 0; + } + + /* depending on the phy address we can detect our board version */ + if (phydev->addr == 0) + setenv("boardver", ""); + else + setenv("boardver", "mr"); + + printf("using phy at %d\n", phydev->addr); + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + free(phydev); + free(bus); + } + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + backlight_lcd_off(); + + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + leds_on(); + + /* enable ecspi3 clocks */ + enable_cspi_clock(1, 2); + + return 0; +} + +int checkboard(void) +{ + puts("Board: "CONFIG_SYS_BOARD"\n"); + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + return 0; +} diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig new file mode 100644 index 0000000000..c516038697 --- /dev/null +++ b/configs/ot1200_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q" +CONFIG_ARM=y +CONFIG_TARGET_OT1200=y diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h new file mode 100644 index 0000000000..071880fe75 --- /dev/null +++ b/include/configs/ot1200.h @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2014 Bachmann electronic GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" +#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#include +#include + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_GENERIC_BOARD + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R +#define CONFIG_MXC_GPIO + +/* FUSE Configs */ +#define CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP + +/* UART Configs */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* SF Configs */ +#define CONFIG_CMD_SF +#define CONFIG_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_SST +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 2 +#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(1, 3)<<8)) +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) + +/* IO expander */ +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* OCOTP Configs */ +#define CONFIG_CMD_IMXOTP +#define CONFIG_IMX_OTP +#define IMX_OTP_BASE OCOTP_BASE_ADDR +#define IMX_OTP_ADDR_MAX 0x7F +#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA +#define IMX_OTPWRITE_ENABLED + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER + +#ifdef CONFIG_MX6Q +#define CONFIG_CMD_SATA +#endif + +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE MII100 +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0x5 +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC + +/* Miscellaneous commands */ +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_SETEXPR + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 2 + +#define CONFIG_PREBOOT "" + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_CBSIZE 1024 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */ +#define CONFIG_ENV_OFFSET (1024 * 1024) +/* M25P16 has an erase size of 64 KiB */ +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD + +/* FS Configs */ +#define CONFIG_CMD_EXT3 +#define CONFIG_CMD_EXT4 +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FS_GENERIC + +#define CONFIG_BOOTP_SERVERIP +#define CONFIG_BOOTP_BOOTFILE + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From c9c86bde3d8d24a9eee06f64eaa2e14206c76d77 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:22 -0700 Subject: nitrogen6x: implement board_cfb_skip() to disable text output Several customers have asked to leave the display quiet during boot, so allow the user to express this request by the presence of environment variable "novideo". Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 60a09f4bb3..1a6edac02b 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -558,6 +558,11 @@ struct display_info_t const displays[] = {{ } } }; size_t display_count = ARRAY_SIZE(displays); +int board_cfb_skip(void) +{ + return NULL != getenv("novideo"); +} + static void setup_display(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; -- cgit v1.2.3 From 213e9e334822ba6a08d8d222d392dc30db8aa381 Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Thu, 2 Oct 2014 12:16:23 -0700 Subject: nitrogen6x: simplify board_mmc_getcd The same logic applies to both SD card slots, only with different GPIOs and the code should make that easier to see. Signed-off-by: Troy Kisky --- board/boundary/nitrogen6x/nitrogen6x.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 1a6edac02b..e8cc243774 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -279,17 +279,11 @@ struct fsl_esdhc_cfg usdhc_cfg[2] = { int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; - - if (cfg->esdhc_base == USDHC3_BASE_ADDR) { - gpio_direction_input(IMX_GPIO_NR(7, 0)); - ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); - } else { - gpio_direction_input(IMX_GPIO_NR(2, 6)); - ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); - } + int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) : + IMX_GPIO_NR(2, 6); - return ret; + gpio_direction_input(gp_cd); + return !gpio_get_value(gp_cd); } int board_mmc_init(bd_t *bis) -- cgit v1.2.3 From 41612472b6de135598d0dcf24da783a9802badc8 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:24 -0700 Subject: nitrogen6x: configure SD2 pads for SDIO on USDHC2 Pads SD2_CLK/CMD/DAT0-3 are connected to an SDIO WiFi device on Nitrogen and unconnected on BD-SL-i.MX6 (sabre lite). Configure them as SDIO pins to prevent them from being in a state that confuses the WiFi part. Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index e8cc243774..bde299f55d 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -124,6 +124,15 @@ struct i2c_pads_info i2c_pad_info2 = { } }; +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -657,6 +666,8 @@ int board_init(void) #ifdef CONFIG_MXC_SPI setup_spi(); #endif + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); -- cgit v1.2.3 From a3b527a947f6f71b2673bb7943854b4459f4142e Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:25 -0700 Subject: nitrogen6x: power-down miscellanous peripherals Ensure that cameras and USB OTG power are in a stable (reset) state at reset by configuring their pads and toggling GPIOs. Signed-off-by: Troy Kisky Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 47 +++++++++++++++++++++++++++++++--- 1 file changed, 43 insertions(+), 4 deletions(-) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index bde299f55d..38f0df8fdd 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -622,17 +622,56 @@ static void setup_display(void) } #endif +/* wl1271 pads on nitrogen6x */ +static iomux_v3_cfg_t const init_pads[] = { + /* WL12XX_WL_IRQ_GP */ + NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN), + /* WL12XX_WL_ENABLE_GP */ + NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM), + /* WL12XX_BT_ENABLE_GP */ + NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM), + /* USB otg power */ + NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM), + NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM), + NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM), + NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM), + NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM), +}; + +#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) + +static unsigned gpios_out_low[] = { + /* Disable wl1271 */ + IMX_GPIO_NR(6, 15), /* disable wireless */ + IMX_GPIO_NR(6, 16), /* disable bluetooth */ + IMX_GPIO_NR(3, 22), /* disable USB otg power */ + IMX_GPIO_NR(2, 5), /* ov5640 mipi camera reset */ + IMX_GPIO_NR(1, 8), /* ov5642 reset */ +}; + +static unsigned gpios_out_high[] = { + IMX_GPIO_NR(1, 6), /* ov5642 powerdown */ + IMX_GPIO_NR(6, 9), /* ov5640 mipi camera power down */ +}; + +static void set_gpios(unsigned *p, int cnt, int val) +{ + int i; + + for (i = 0; i < cnt; i++) + gpio_direction_output(*p++, val); +} + int board_early_init_f(void) { setup_iomux_uart(); - /* Disable wl1271 For Nitrogen6w */ + set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1); + set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0); gpio_direction_input(WL12XX_WL_IRQ_GP); - gpio_direction_output(WL12XX_WL_ENABLE_GP, 0); - gpio_direction_output(WL12XX_BT_ENABLE_GP, 0); - gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */ imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads)); + imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads)); setup_buttons(); #if defined(CONFIG_VIDEO_IPUV3) -- cgit v1.2.3 From 693cccf412b14b69cd6c81e10f150302ebfdd696 Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Thu, 2 Oct 2014 12:16:26 -0700 Subject: nitrogen6x: configure SGTL5000, CSI camera clock outputs Configure CLKO outputs for SGTL5000, CSI camera. The sys_mclk output for the SGTL500 in particular prevents Windows CE from properly driving audio. Signed-off-by: Troy Kisky Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 38f0df8fdd..96e2b7430c 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -622,8 +622,14 @@ static void setup_display(void) } #endif -/* wl1271 pads on nitrogen6x */ static iomux_v3_cfg_t const init_pads[] = { + /* SGTL5000 sys_mclk */ + NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM), + + /* J5 - Camera MCLK */ + NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM), + + /* wl1271 pads on nitrogen6x */ /* WL12XX_WL_IRQ_GP */ NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN), /* WL12XX_WL_ENABLE_GP */ -- cgit v1.2.3 From 9fc425278b333f481d1bbf1efd98813dcd4d57d4 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:27 -0700 Subject: nitrogen6x: staticize board file Declare locally-used data structures and functions as static and pull in header files to prevent compiler warnings of "Should it be static?" when building with "make C=1". Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 96e2b7430c..e795492046 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -28,6 +28,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) @@ -70,12 +72,12 @@ int dram_init(void) return 0; } -iomux_v3_cfg_t const uart1_pads[] = { +static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -iomux_v3_cfg_t const uart2_pads[] = { +static iomux_v3_cfg_t const uart2_pads[] = { MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; @@ -83,7 +85,7 @@ iomux_v3_cfg_t const uart2_pads[] = { #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) /* I2C1, SGTL5000 */ -struct i2c_pads_info i2c_pad_info0 = { +static struct i2c_pads_info i2c_pad_info0 = { .scl = { .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, @@ -97,7 +99,7 @@ struct i2c_pads_info i2c_pad_info0 = { }; /* I2C2 Camera, MIPI */ -struct i2c_pads_info i2c_pad_info1 = { +static struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, @@ -111,7 +113,7 @@ struct i2c_pads_info i2c_pad_info1 = { }; /* I2C3, J15 - RGB connector */ -struct i2c_pads_info i2c_pad_info2 = { +static struct i2c_pads_info i2c_pad_info2 = { .scl = { .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC, @@ -133,7 +135,7 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; -iomux_v3_cfg_t const usdhc3_pads[] = { +static iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -143,7 +145,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; -iomux_v3_cfg_t const usdhc4_pads[] = { +static iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -153,7 +155,7 @@ iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; -iomux_v3_cfg_t const enet_pads1[] = { +static iomux_v3_cfg_t const enet_pads1[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -180,7 +182,7 @@ iomux_v3_cfg_t const enet_pads1[] = { MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -iomux_v3_cfg_t const enet_pads2[] = { +static iomux_v3_cfg_t const enet_pads2[] = { MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -198,7 +200,7 @@ static iomux_v3_cfg_t const misc_pads[] = { }; /* wl1271 pads on nitrogen6x */ -iomux_v3_cfg_t const wl12xx_pads[] = { +static iomux_v3_cfg_t const wl12xx_pads[] = { (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(WEAK_PULLDOWN), (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK) @@ -246,7 +248,7 @@ static void setup_iomux_enet(void) imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); } -iomux_v3_cfg_t const usb_pads[] = { +static iomux_v3_cfg_t const usb_pads[] = { MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), }; @@ -280,7 +282,7 @@ int board_ehci_power(int port, int on) #endif #ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg[2] = { +static struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR}, {USDHC4_BASE_ADDR}, }; @@ -331,7 +333,7 @@ int board_mmc_init(bd_t *bis) #endif #ifdef CONFIG_MXC_SPI -iomux_v3_cfg_t const ecspi1_pads[] = { +static iomux_v3_cfg_t const ecspi1_pads[] = { /* SS1 */ MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -339,7 +341,7 @@ iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), }; -void setup_spi(void) +static void setup_spi(void) { imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); -- cgit v1.2.3 From adc4a2bd03ad6ab4cc7f73609d60ab740c8126e6 Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Thu, 2 Oct 2014 12:16:29 -0700 Subject: nitrogen6x: phy: add 100 us delay after phy reset Testing shows that the Micrel PHY may not be completely out of reset if accessed immediately. Signed-off-by: Troy Kisky Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index e795492046..a89a15ca74 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -246,6 +246,7 @@ static void setup_iomux_enet(void) gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); + udelay(100); /* Wait 100 us before using mii interface */ } static iomux_v3_cfg_t const usb_pads[] = { -- cgit v1.2.3 From 84caf0b26b513df0a0f45832d053a623963e5c6f Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:30 -0700 Subject: nitrogen6x: prevent warnings about board_ehci* callbacks Include declarations of board_ehci callbacks to prevent compiler warnings and enforce function prototypes. Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index a89a15ca74..67d4154480 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -30,6 +30,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) -- cgit v1.2.3 From 4328fb05bf8c90e96afa023d39395efa5fb2fda5 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Thu, 2 Oct 2014 12:16:31 -0700 Subject: nitrogen6x: display: add support lvds jeida screen Add support for Boundary Devices 7" and 10.1" 1280x800 displays with integrated FocalTech ft5x06 10-point touch controller. Because they share the touch controller with the 1024x600 displays, auto-detection is disabled and you must explicitly set the 'panel' environment variable: U-Boot > setenv panel LDB-WXGA U-Boot > saveenv && reset Signed-off-by: Robert Winkler Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 67d4154480..39e8013480 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -474,6 +474,17 @@ static void enable_lvds(struct display_info_t const *dev) gpio_direction_output(LVDS_BACKLIGHT_GP, 1); } +static void enable_lvds_jeida(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + u32 reg = readl(&iomux->gpr[2]); + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA; + writel(reg, &iomux->gpr[2]); + gpio_direction_output(LVDS_BACKLIGHT_GP, 1); +} + static void enable_rgb(struct display_info_t const *dev) { imx_iomux_v3_setup_multiple_pads( @@ -502,6 +513,26 @@ struct display_info_t const displays[] = {{ .vsync_len = 10, .sync = FB_SYNC_EXT, .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 0, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_lvds_jeida, + .mode = { + .name = "LDB-WXGA", + .refresh = 60, + .xres = 1280, + .yres = 800, + .pixclock = 14065, + .left_margin = 40, + .right_margin = 40, + .upper_margin = 3, + .lower_margin = 80, + .hsync_len = 10, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED } }, { .bus = 2, .addr = 0x4, -- cgit v1.2.3 From 443d4d15d7bd2f2bd5a58a6a6dd8da2a8dd23de4 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:32 -0700 Subject: nitrogen6x: display: add qvga panel Add support for a 1/4 VGA panel with a 24-bit RGB interface. No auto-detection is enabled, so you must configure the 'panel' environment variable to use this display: U-Boot > setenv panel qvga U-Boot > saveenv && reset Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 39e8013480..5e0461c54c 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -593,6 +593,26 @@ struct display_info_t const displays[] = {{ .vsync_len = 10, .sync = 0, .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 0, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_rgb, + .mode = { + .name = "qvga", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = 37037, + .left_margin = 38, + .right_margin = 37, + .upper_margin = 16, + .lower_margin = 15, + .hsync_len = 30, + .vsync_len = 3, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED } } }; size_t display_count = ARRAY_SIZE(displays); -- cgit v1.2.3 From 4adc1127f8c50c4361d0024e098a91e7050e7400 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:33 -0700 Subject: nitrogen6x: display: add support for LG-9.7 LVDS display Add support for LG 9.7" LVDS panel (1024x768) with integrated eGalax touch screen. Note that this panel differs only slightly from the Hannstar XGA panel (margins). No auto-detection is available because it shares the same touch controller as the Hannstar-XGA display, so you'll need to configure it through the 'panel' environment variable: U-Boot > setenv panel LG-9.7 U-Boot > saveenv && reset Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 5e0461c54c..2200bc7c3b 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -553,6 +553,26 @@ struct display_info_t const displays[] = {{ .vsync_len = 10, .sync = FB_SYNC_EXT, .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 0, + .addr = 0, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "LG-9.7", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, /* ~65MHz */ + .left_margin = 480, + .right_margin = 260, + .upper_margin = 16, + .lower_margin = 6, + .hsync_len = 250, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED } }, { .bus = 2, .addr = 0x38, -- cgit v1.2.3 From d6949e3f9dc6f2bbc63b1614601291091d1f0347 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:34 -0700 Subject: nitrogen6x: display: add LDB-WXGA-S for SPWG 1280x800 displays This patch adds support for LVDS WXGA displays that use the SPWG encoding standard instead of JEIDA. No auto-detection is enabled and you must explicitly set the 'panel' environment variable: U-Boot > setenv panel LDB-WXGA-S U-Boot > saveenv && reset Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 2200bc7c3b..045f81ecb7 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -533,6 +533,26 @@ struct display_info_t const displays[] = {{ .vsync_len = 10, .sync = FB_SYNC_EXT, .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 0, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "LDB-WXGA-S", + .refresh = 60, + .xres = 1280, + .yres = 800, + .pixclock = 14065, + .left_margin = 40, + .right_margin = 40, + .upper_margin = 3, + .lower_margin = 80, + .hsync_len = 10, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED } }, { .bus = 2, .addr = 0x4, -- cgit v1.2.3 From 04edda266d333af5fe8cd5775f49071e8098082a Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:35 -0700 Subject: nitrogen6x: display: add support for fusion 7 display Add support for the Touch Revolution Fusion7 display: 800x480 RGB with a custom F0710A resistive touch controller. Auto-detection of this panel is supported so no configuration is required. Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 045f81ecb7..be2a41f1a4 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -613,6 +613,26 @@ struct display_info_t const displays[] = {{ .vsync_len = 10, .sync = FB_SYNC_EXT, .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x10, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = detect_i2c, + .enable = enable_rgb, + .mode = { + .name = "fusion7", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 33898, + .left_margin = 96, + .right_margin = 24, + .upper_margin = 3, + .lower_margin = 10, + .hsync_len = 72, + .vsync_len = 7, + .sync = 0x40000002, + .vmode = FB_VMODE_NONINTERLACED } }, { .bus = 2, .addr = 0x48, -- cgit v1.2.3 From 135663061ffa78c391dd502674bb50823555b675 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:36 -0700 Subject: nitrogen6x: display: add svga display (800x600) Add support for 800x600 18-bit RGB displays using VESA GTF timings. No auto-detection is supported, so you must configure this panel manually through the 'panel' environment variable: U-Boot > setenv panel svga U-Boot > saveenv && reset Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index be2a41f1a4..ccbb9b7e29 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -633,6 +633,26 @@ struct display_info_t const displays[] = {{ .vsync_len = 7, .sync = 0x40000002, .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 0, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = NULL, + .enable = enable_rgb, + .mode = { + .name = "svga", + .refresh = 60, + .xres = 800, + .yres = 600, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED } }, { .bus = 2, .addr = 0x48, -- cgit v1.2.3 From 865aa30bb30fb1675ea516bfab8850f91da69a29 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:37 -0700 Subject: nitrogen6x: display: add Ampire 1024x600 panel Add support for an Ampire 1024x600 LVDS panel with integrated Ilitek capacitive touch screen. Auto-detection is enabled, so no explicit configuration is needed. Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index ccbb9b7e29..38d0b529de 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -653,6 +653,26 @@ struct display_info_t const displays[] = {{ .vsync_len = 10, .sync = 0, .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x41, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "amp1024x600", + .refresh = 60, + .xres = 1024, + .yres = 600, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED } }, { .bus = 2, .addr = 0x48, -- cgit v1.2.3 From c745de7174e9f59f68ec281bf094259ada46d2a8 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:38 -0700 Subject: nitrogen6x: display: add wvga-lvds panel Add support for WVGA (800x480) panels using VESA GTF timings over LVDS. No auto-detection is supported, so you must configure this panel manually through the 'panel' environment variable: U-Boot > setenv panel svga U-Boot > saveenv && reset Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 38d0b529de..a82ec45b0f 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -673,6 +673,26 @@ struct display_info_t const displays[] = {{ .vsync_len = 10, .sync = FB_SYNC_EXT, .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 0, + .addr = 0, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = 0, + .enable = enable_lvds, + .mode = { + .name = "wvga-lvds", + .refresh = 57, + .xres = 800, + .yres = 480, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED } }, { .bus = 2, .addr = 0x48, -- cgit v1.2.3 From ce9507b793a0755b37b3612657a12f4d19ee0b61 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:39 -0700 Subject: nitrogen6x: display use I2C detect for HDMI The HPD pin and RX_SENSE registers have proven to be less reliable than using I2C on the EDID pins for detection of an HDMI monitor. In particular, when the HDMI output is reset through a "reboot" cycle, the detect_hdmi() routine often bounces, resulting in a failure to detect a connected monitor. Signed-off-by: Eric Nelson --- board/boundary/nitrogen6x/nitrogen6x.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index a82ec45b0f..2762fcffae 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -494,10 +494,10 @@ static void enable_rgb(struct display_info_t const *dev) } struct display_info_t const displays[] = {{ - .bus = -1, - .addr = 0, + .bus = 1, + .addr = 0x50, .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, + .detect = detect_i2c, .enable = do_enable_hdmi, .mode = { .name = "HDMI", -- cgit v1.2.3 From 84e2dc0c89dc5c70ae17224141a745edcd36402c Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:40 -0700 Subject: nitrogen6x: config: add USB Mass Storage (ums) support Add support for the USB mass storage to enable access to on-board storage (especially eMMC and SATA). Details at: http://boundarydevices.com/u-boot-usb-mass-storage-gadget/ Signed-off-by: Eric Nelson --- include/configs/nitrogen6x.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 2a1eb3b773..5e9b7437d9 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -368,4 +368,17 @@ #define CONFIG_PCIE_IMX #endif +#define CONFIG_CMD_ELF + +#define CONFIG_USB_GADGET +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +/* Netchip IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 +#define CONFIG_G_DNL_MANUFACTURER "Boundary" + #endif /* __CONFIG_H */ -- cgit v1.2.3 From 5b7103e0af5435d68489b2b579e9e46226782e64 Mon Sep 17 00:00:00 2001 From: Diego Rondini Date: Thu, 2 Oct 2014 12:16:41 -0700 Subject: nitrogen6x: config: allow boot to USB stick This patch enables boot to USB storage devices by expanding on the list of boot devices. Because the USB startup currently takes a long time, it places USB at the end of the list of supported devices. You can over-ride the boot order using the bootdevs environment variable. For instance, this will make USB the first (highest priority) device: U-Boot > setenv bootdevs usb mmc sata U-Boot > saveenv Signed-off-by: Diego Rondini Signed-off-by: Eric Nelson --- include/configs/nitrogen6x.h | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 5e9b7437d9..21a25e0734 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -173,7 +173,13 @@ #define CONFIG_DRIVE_MMC #endif -#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC +#ifdef CONFIG_USB_STORAGE +#define CONFIG_DRIVE_USB "usb " +#else +#define CONFIG_DRIVE_USB +#endif + +#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC CONFIG_DRIVE_USB #if defined(CONFIG_SABRELITE) #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -253,12 +259,16 @@ "run netboot; " #else #define CONFIG_EXTRA_ENV_SETTINGS \ + "bootdevs=" CONFIG_DRIVE_TYPES "\0" \ "console=ttymxc1\0" \ "clearenv=if sf probe || sf probe || sf probe 1 ; then " \ "sf erase 0xc0000 0x2000 && " \ "echo restored environment to factory default ; fi\0" \ - "bootcmd=for dtype in " CONFIG_DRIVE_TYPES \ + "bootcmd=for dtype in ${bootdevs}" \ "; do " \ + "if itest.s \"xusb\" == \"x${dtype}\" ; then " \ + "usb start ;" \ + "fi; " \ "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \ "for fs in fat ext2 ; do " \ "${fs}load " \ @@ -274,7 +284,7 @@ "echo ; echo serial console at 115200, 8N1 ; echo ; " \ "echo details at http://boundarydevices.com/6q_bootscript ; " \ "setenv stdout serial\0" \ - "upgradeu=for dtype in " CONFIG_DRIVE_TYPES \ + "upgradeu=for dtype in ${bootdevs}" \ "; do " \ "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \ "for fs in fat ext2 ; do " \ -- cgit v1.2.3 From 43a3431c2602ba7949c3bbb7a541396caa772c2c Mon Sep 17 00:00:00 2001 From: Kevin Mihelich Date: Thu, 2 Oct 2014 12:16:42 -0700 Subject: nitrogen6x: config: use FS_GENERIC load command Remove the individual attempts to load using ext2 and fat, replace with the generic load command supporting available filesystem types. Signed-off-by: Kevin Mihelich --- include/configs/nitrogen6x.h | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 21a25e0734..2167d77a38 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -270,13 +270,11 @@ "usb start ;" \ "fi; " \ "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \ - "for fs in fat ext2 ; do " \ - "${fs}load " \ - "${dtype} ${disk}:1 " \ - "10008000 " \ - "/6x_bootscript" \ - "&& source 10008000 ; " \ - "done ; " \ + "load " \ + "${dtype} ${disk}:1 " \ + "10008000 " \ + "/6x_bootscript" \ + "&& source 10008000 ; " \ "done ; " \ "done; " \ "setenv stdout serial,vga ; " \ @@ -287,11 +285,9 @@ "upgradeu=for dtype in ${bootdevs}" \ "; do " \ "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \ - "for fs in fat ext2 ; do " \ - "${fs}load ${dtype} ${disk}:1 10008000 " \ - "/6x_upgrade " \ - "&& source 10008000 ; " \ - "done ; " \ + "load ${dtype} ${disk}:1 10008000 " \ + "/6x_upgrade " \ + "&& source 10008000 ; " \ "done ; " \ "done\0" \ -- cgit v1.2.3 From 8145ccc3be91f4909884cb80735e33ee930baa15 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:43 -0700 Subject: nitrogen6x: config: add initrd_high Support RAM disks by setting initrd_high. See commit 7e9603e Signed-off-by: Eric Nelson --- include/configs/nitrogen6x.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 2167d77a38..3c24443592 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -282,6 +282,7 @@ "echo ; echo serial console at 115200, 8N1 ; echo ; " \ "echo details at http://boundarydevices.com/6q_bootscript ; " \ "setenv stdout serial\0" \ + "initrd_high=0xffffffff\0" \ "upgradeu=for dtype in ${bootdevs}" \ "; do " \ "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \ -- cgit v1.2.3 From 8d97b3ad95a2584aa31e281cfe2d6977f790803a Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:44 -0700 Subject: nitrogen6x: config: expose SATA, then MMC over USB If no boot script was found, expose internal storage over the USB mass storage gadget to allow easy programming. This is especially useful when SD cards are inaccessible or when loading SATA drives. More details are available in this blog post: http://boundarydevices.com/u-boot-usb-mass-storage-gadget/ Signed-off-by: Eric Nelson --- include/configs/nitrogen6x.h | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 3c24443592..b31b92291d 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -180,6 +180,7 @@ #endif #define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC CONFIG_DRIVE_USB +#define CONFIG_UMSDEVS CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC #if defined(CONFIG_SABRELITE) #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -260,6 +261,7 @@ #else #define CONFIG_EXTRA_ENV_SETTINGS \ "bootdevs=" CONFIG_DRIVE_TYPES "\0" \ + "umsdevs=" CONFIG_UMSDEVS "\0" \ "console=ttymxc1\0" \ "clearenv=if sf probe || sf probe || sf probe 1 ; then " \ "sf erase 0xc0000 0x2000 && " \ @@ -281,7 +283,26 @@ "echo ; echo 6x_bootscript not found ; " \ "echo ; echo serial console at 115200, 8N1 ; echo ; " \ "echo details at http://boundarydevices.com/6q_bootscript ; " \ - "setenv stdout serial\0" \ + "setenv stdout serial;" \ + "setenv stdin serial,usbkbd;" \ + "for dtype in ${umsdevs} ; do " \ + "if itest.s sata == ${dtype}; then " \ + "initcmd='sata init' ;" \ + "else " \ + "initcmd='mmc rescan' ;" \ + "fi; " \ + "for disk in 0 1 ; do " \ + "if $initcmd && $dtype dev $disk ; then " \ + "setenv stdout serial,vga; " \ + "echo expose ${dtype} ${disk} " \ + "over USB; " \ + "ums 0 $dtype $disk ;" \ + "fi; " \ + " done; " \ + "done ;" \ + "setenv stdout serial,vga; " \ + "echo no block devices found;" \ + "\0" \ "initrd_high=0xffffffff\0" \ "upgradeu=for dtype in ${bootdevs}" \ "; do " \ -- cgit v1.2.3 From c36c0008285ebc5b3c56b4c0fcc654d2b55fef66 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:45 -0700 Subject: nitrogen6x: config: enable USB keyboard support Enable the use of USB keyboards on SABRE Lite and Nitrogen6x boards. Signed-off-by: Eric Nelson --- include/configs/nitrogen6x.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index b31b92291d..d505191d20 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -122,6 +122,8 @@ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP /* Miscellaneous commands */ #define CONFIG_CMD_BMODE -- cgit v1.2.3 From d3d70e6f9b450ca37c005abe0a8ed5cd2869d71b Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:46 -0700 Subject: nitrogen6x: config: add CONFIG_CMD_MEMTEST Enable the 'mtest' command on Nitrogen6x and SABRE Lite boards. Signed-off-by: Eric Nelson --- include/configs/nitrogen6x.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index d505191d20..82dc0fc975 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -382,6 +382,7 @@ #define CONFIG_CMD_BMP #define CONFIG_CMD_TIME +#define CONFIG_CMD_MEMTEST #define CONFIG_SYS_ALT_MEMTEST #define CONFIG_CMD_BOOTZ -- cgit v1.2.3 From 5dbdc3cf3cd870ef799fd8e412f8b82915c98b65 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:47 -0700 Subject: nitrogen6x: config: enable "i2c edid" Enable the "i2c edid" command to query data from an attached HDMI monitor. Usage is typically this: U-Boot > i2c dev 1 U-Boot > i2c edid 0x50 ... Signed-off-by: Eric Nelson --- include/configs/nitrogen6x.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 82dc0fc975..b911d06da7 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -63,6 +63,7 @@ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_I2C_EDID /* MMC Configs */ #define CONFIG_FSL_ESDHC -- cgit v1.2.3 From 3f5d964ea082049c9616e4dc827cd4aa3972a281 Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Thu, 2 Oct 2014 12:16:48 -0700 Subject: nitrogen6x: config: allow more bootargs parameters Increase the maximum number of arguments allowed by the Hush parser. This prevents errors when users or scripts aren't quoting parameters when setting the "bootargs" variable et al. Signed-off-by: Troy Kisky Signed-off-by: Eric Nelson --- include/configs/nitrogen6x.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index b911d06da7..50b6c5a19a 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -326,7 +326,7 @@ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MAXARGS 48 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_MEMTEST_START 0x10000000 -- cgit v1.2.3 From 54950e8215c819e6a8e46752255b8347b00eb81f Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:49 -0700 Subject: nitrogen6x: config: disable logo Some users (QNX and Windows CE users in particular) have asked to disable the Penguin shown on the display at boot time. Signed-off-by: Eric Nelson Acked-by: Stefano Babic --- include/configs/nitrogen6x.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 50b6c5a19a..60c942f0d2 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -140,7 +140,6 @@ #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO #define CONFIG_IPUV3_CLK 260000000 #define CONFIG_CMD_HDMIDETECT #define CONFIG_CONSOLE_MUX -- cgit v1.2.3 From c0e7bd6661ee2c117d9543b674c968d711a9aed9 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:51 -0700 Subject: nitrogen6x: config: add gpio command Enable the 'gpio' command to allow reading and toggling of GPIO pins. Signed-off-by: Eric Nelson --- include/configs/nitrogen6x.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 60c942f0d2..21013bc23a 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -32,6 +32,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MISC_INIT_R #define CONFIG_MXC_GPIO +#define CONFIG_CMD_GPIO #define CONFIG_CI_UDC #define CONFIG_USBD_HS #define CONFIG_USB_GADGET_DUALSPEED -- cgit v1.2.3 From e9feee63705c1d380e229a381f9a7d696044ff76 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 2 Oct 2014 12:16:52 -0700 Subject: nitrogen6x: config: enable Android fastboot Enable 'fastboot' command. This is currently enabled but not yet functional. Including it in the configuration will ease further testing and development as discussed on the mailing list. Signed-off-by: Eric Nelson --- include/configs/nitrogen6x.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 21013bc23a..17559d8f8c 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -413,4 +413,9 @@ #define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 #define CONFIG_G_DNL_MANUFACTURER "Boundary" +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000 + #endif /* __CONFIG_H */ -- cgit v1.2.3 From 5e3a388cddce1685ccd9bc1b58ddb89a191ed88f Mon Sep 17 00:00:00 2001 From: Kevin Mihelich Date: Thu, 2 Oct 2014 12:16:53 -0700 Subject: nitrogen6x: config: enable EXT4 filesystem Support reading/writing ext4 partitions. Signed-off-by: Kevin Mihelich Signed-off-by: Eric Nelson --- include/configs/nitrogen6x.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 17559d8f8c..469591fe88 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -77,6 +77,8 @@ #define CONFIG_GENERIC_MMC #define CONFIG_BOUNCE_BUFFER #define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION -- cgit v1.2.3 From c19a8bc5711ec63e905ef91f045a1489f0aa3cb0 Mon Sep 17 00:00:00 2001 From: Anthony Felice Date: Sat, 6 Sep 2014 19:47:06 +0200 Subject: vf610twr: Tune DDR initialization settings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: Anthony Felice [rebased on v2014.10-rc2] Signed-off-by: Stefan Agner --- arch/arm/include/asm/arch-vf610/imx-regs.h | 49 +++++++++++--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 44 +++++++------ arch/arm/include/asm/imx-common/iomux-v3.h | 2 + board/freescale/vf610twr/vf610twr.c | 94 +++++++++++++++++---------- 4 files changed, 127 insertions(+), 62 deletions(-) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index bb002172c9..9d797dbe1f 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -103,9 +103,11 @@ /* DDRMC */ #define DDRMC_PHY_DQ_TIMING 0x00002613 #define DDRMC_PHY_DQS_TIMING 0x00002615 -#define DDRMC_PHY_CTRL 0x01210080 +#define DDRMC_PHY_CTRL 0x00210000 #define DDRMC_PHY_MASTER_CTRL 0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00012020 +#define DDRMC_PHY_SLAVE_CTRL 0x00002000 +#define DDRMC_PHY_OFF 0x00000000 +#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 #define DDRMC_PHY50_DDR3_MODE (1 << 12) #define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8) @@ -138,7 +140,7 @@ #define DDRMC_CR21_CCMAP_EN 1 #define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) #define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24) -#define DDRMC_CR23_TDLL(v) ((v) & 0xff) +#define DDRMC_CR23_TDLL(v) ((v) & 0xffff) #define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f) #define DDRMC_CR25_TREF_EN (1 << 16) #define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16) @@ -151,7 +153,7 @@ #define DDRMC_CR33_EN_QK_SREF (1 << 16) #define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16) #define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8) -#define DDRMC_CR38_FREQ_CHG_EN (1 << 8) +#define DDRMC_CR38_FREQ_CHG_EN(v) (((v) & 0x1) << 8) #define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16) #define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8) #define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3) @@ -163,7 +165,7 @@ #define DDRMC_CR67_ZQCS(v) ((v) & 0xfff) #define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8) #define DDRMC_CR70_REF_PER_ZQ(v) (v) -#define DDRMC_CR72_ZQCS_ROTATE (1 << 24) +#define DDRMC_CR72_ZQCS_ROTATE(v) (((v) & 0x1) << 24) #define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24) #define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16) #define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8) @@ -182,9 +184,10 @@ #define DDRMC_CR77_CS_MAP (1 << 24) #define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8) #define DDRMC_CR77_SWAP_EN 1 +#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24) #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) -#define DDRMC_CR79_CTLUPD_AREF (1 << 24) -#define DDRMC_CR82_INT_MASK 0x1fffffff +#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24) +#define DDRMC_CR82_INT_MASK 0x10000000 #define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24) #define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16) #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) @@ -192,9 +195,17 @@ #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) +#define DDRMC_CR97_WRLVL_EN (1 << 24) +#define DDRMC_CR98_WRLVL_DL_0 (0) +#define DDRMC_CR99_WRLVL_DL_1 (0) +#define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) +#define DDRMC_CR102_RDLVL_REG_EN (1 << 8) #define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8) +#define DDRMC_CR106_RDLVL_GTDL_0(v) ((v) & 0xff) #define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff) +#define DDRMC_CR110_RDLVL_GTDL_1(v) (((v) & 0xff) << 16) #define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8) +#define DDRMC_CR115_RDLVL_GTDL_2(v) ((v) & 0xff) #define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8) #define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3) #define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24) @@ -208,20 +219,42 @@ #define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff) #define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8) #define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf) +#define DDRMC_CR123_AXI1_P_ODR_EN (1 << 16) #define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff) #define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8) #define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8) #define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f) +#define DDRMC_CR137_PHYCTL_DL(v) (((v) & 0xf) << 16) +#define DDRMC_CR138_PHY_WRLV_MXDL(v) (((v) & 0xffff) << 16) +#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x8) << 8) #define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24) #define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16) #define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8) #define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff) +#define DDRMC_CR140_PHY_WRLV_WW(v) ((v) & 0x3ff) +#define DDRMC_CR143_RDLV_GAT_MXDL(v) (((v) & 0xffff) << 16) +#define DDRMC_CR143_RDLV_MXDL(v) ((v) & 0xffff) +#define DDRMC_CR144_PHY_RDLVL_RES(v) (((v) & 0xff) << 24) +#define DDRMC_CR144_PHY_RDLV_LOAD(v) (((v) & 0xff) << 16) +#define DDRMC_CR144_PHY_RDLV_DLL(v) (((v) & 0xff) << 8) +#define DDRMC_CR144_PHY_RDLV_EN(v) ((v) & 0xff) +#define DDRMC_CR145_PHY_RDLV_RR(v) ((v) & 0x3ff) +#define DDRMC_CR146_PHY_RDLVL_RESP(v) (v) +#define DDRMC_CR147_RDLV_RESP_MASK(v) ((v) & 0xfffff) +#define DDRMC_CR148_RDLV_GATE_RESP_MASK(v) ((v) & 0xfffff) +#define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(v) (((v) & 0xf) << 8) +#define DDRMC_CR151_RDLVL_DQ_ZERO_CNT(v) ((v) & 0xf) #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27) #define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21) #define DDRMC_CR154_DDR_SEL_PAD_CONTR(v) (((v) & 0x3) << 18) +#define DDRMC_CR154_PAD_ZQ_HW_FOR(v) (((v) & 0x1) << 14) #define DDRMC_CR155_AXI0_AWCACHE (1 << 10) -#define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7) +#define DDRMC_CR155_PAD_ODT_BYTE1(v) (((v) & 0x7) << 3) +#define DDRMC_CR155_PAD_ODT_BYTE0(v) ((v) & 0x7) #define DDRMC_CR158_TWR(v) ((v) & 0x3f) +#define DDRMC_CR161_ODT_EN(v) (((v) & 0x1) << 16) +#define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8) +#define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf) #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 7464da80cf..9226e69fec 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -17,6 +17,8 @@ #define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ PAD_CTL_OBE_IBE_ENABLE) #define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm +#define VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_25ohm | \ + PAD_CTL_INPUT_DIFFERENTIAL) #define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE) #define VF610_NFC_IO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ @@ -102,6 +104,7 @@ enum { VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), + VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL), @@ -117,6 +120,7 @@ enum { VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, 0x025c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL), @@ -124,26 +128,26 @@ enum { VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), + VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), + VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index 70ee86c432..a8ca49c343 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -120,6 +120,8 @@ typedef u64 iomux_v3_cfg_t; #define PAD_MUX_MODE_SHIFT 20 +#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16) + #define PAD_CTL_SPEED_MED (1 << 12) #define PAD_CTL_SPEED_HIGH (3 << 12) diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 54a9f2c7c3..21f49fdb32 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -45,6 +45,7 @@ void setup_iomux_ddr(void) VF610_PAD_DDR_A3__DDR_A_3, VF610_PAD_DDR_A2__DDR_A_2, VF610_PAD_DDR_A1__DDR_A_1, + VF610_PAD_DDR_A0__DDR_A_0, VF610_PAD_DDR_BA2__DDR_BA_2, VF610_PAD_DDR_BA1__DDR_BA_1, VF610_PAD_DDR_BA0__DDR_BA_0, @@ -76,6 +77,7 @@ void setup_iomux_ddr(void) VF610_PAD_DDR_WE__DDR_WE_B, VF610_PAD_DDR_ODT1__DDR_ODT_0, VF610_PAD_DDR_ODT0__DDR_ODT_1, + VF610_PAD_DDR_RESETB, }; imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); @@ -88,30 +90,30 @@ void ddr_phy_init(void) writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]); writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]); writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]); - writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]); writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]); writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]); - writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]); - writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]); - writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]); - writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]); - writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]); + + /* LPDDR2 only parameter */ + writel(DDRMC_PHY_OFF, &ddrmr->phy[49]); writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]); + + /* Processor Pad ODT settings */ + writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]); } void ddr_ctrl_init(void) @@ -120,12 +122,12 @@ void ddr_ctrl_init(void) writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]); - writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]); + writel(DDRMC_CR10_TRST_PWRON(80000), &ddrmr->cr[10]); - writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]); + writel(DDRMC_CR11_CKE_INACTIVE(200000), &ddrmr->cr[11]); writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]); - writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) | - DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]); + writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4), + &ddrmr->cr[13]); writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) | DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]); writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]); @@ -134,24 +136,23 @@ void ddr_ctrl_init(void) writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]); writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]); - writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT | - DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]); + writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]); - writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]); + writel(DDRMC_CR22_TDAL(12), &ddrmr->cr[22]); writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]); writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]); writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]); - writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]); - writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]); + writel(DDRMC_CR26_TREF(3120) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]); + writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]); writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]); writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]); - writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]); + writel(DDRMC_CR31_TXSNR(48) | DDRMC_CR31_TXSR(468), &ddrmr->cr[31]); writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]); writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]); - writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]); + writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]); writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) | DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]); @@ -164,37 +165,45 @@ void ddr_ctrl_init(void) writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]); writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]); - writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]); + writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]); writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) | DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]); writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN | - DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255), + DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64), &ddrmr->cr[74]); writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN | DDRMC_CR75_PLEN, &ddrmr->cr[75]); writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) | - DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]); + DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]); writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE | DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]); - writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]); - writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]); + writel(DDRMC_CR78_Q_FULLNESS(7) | DDRMC_CR78_BUR_ON_FLY_BIT(12), + &ddrmr->cr[78]); + writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]); writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]); - writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0, - &ddrmr->cr[87]); + writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]); writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]); writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]); writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]); writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]); + writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]); + writel(DDRMC_CR98_WRLVL_DL_0, &ddrmr->cr[98]); + writel(DDRMC_CR99_WRLVL_DL_1, &ddrmr->cr[99]); + + writel(DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, + &ddrmr->cr[102]); - writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]); - writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]); - writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]); + writel(DDRMC_CR105_RDLVL_DL_0(0), &ddrmr->cr[105]); + writel(DDRMC_CR106_RDLVL_GTDL_0(4), &ddrmr->cr[106]); + writel(DDRMC_CR110_RDLVL_GTDL_1(4), &ddrmr->cr[110]); + writel(DDRMC_CR114_RDLVL_GTDL_2(0), &ddrmr->cr[114]); + writel(DDRMC_CR115_RDLVL_GTDL_2(0), &ddrmr->cr[115]); - writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), + writel(DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]); writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]); @@ -205,23 +214,40 @@ void ddr_ctrl_init(void) &ddrmr->cr[121]); writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]); - writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1), - &ddrmr->cr[123]); + writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | + DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]); writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]); - writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]); + writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]); writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]); + writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]); + writel(DDRMC_CR138_PHY_WRLV_MXDL(256) | DDRMC_CR138_PHYDRAM_CK_EN(1), + &ddrmr->cr[138]); writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]); + writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]); + writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) | DDRMC_CR143_RDLV_MXDL(128), + &ddrmr->cr[143]); + writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) | + DDRMC_CR144_PHY_RDLV_DLL(3) | DDRMC_CR144_PHY_RDLV_EN(3), + &ddrmr->cr[144]); + writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]); + writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]); + writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]); + writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]); + writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) | + DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]); writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | - DDRMC_CR154_PAD_ZQ_MODE(1) | - DDRMC_CR154_DDR_SEL_PAD_CONTR(3), &ddrmr->cr[154]); - writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2), + DDRMC_CR154_PAD_ZQ_MODE(1) | DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | + DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]); + writel(DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]); writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]); + writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | + DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]); ddr_phy_init(); -- cgit v1.2.3 From e4d761000a50447a2afca2447088dbf282edda64 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:38 -0600 Subject: Exynos: Use 900MHz ARM frequency in SPL for peach_pit The device seems to hang in SPL if the full speed is used when booting from USB, perhaps because the PMIC has not been set to the maximum ARM core voltage yet. Slow it down to a reliable speed. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/dts/exynos5420-peach-pit.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index 3ed70a8a92..207782effb 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -32,7 +32,7 @@ mem-manuf = "samsung"; mem-type = "ddr3"; clock-frequency = <800000000>; - arm-frequency = <1700000000>; + arm-frequency = <900000000>; }; tmu@10060000 { -- cgit v1.2.3 From 83d937803ad344234da8abdf616d4c1563a12e04 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:39 -0600 Subject: exynos5: Enable data cache Things run faster when the data cache is enabled, so turn it on along with the 'dcache' command. Signed-off-by: Simon Glass Tested-by: Ajay Kumar Signed-off-by: Minkyu Kang --- include/configs/exynos5-dt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index 1dc3002523..68f3a41cc1 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -33,8 +33,8 @@ #define CONFIG_TRACE_EARLY_ADDR 0x50000000 /* Keep L2 Cache Disabled */ -#define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_CMD_CACHE /* Enable ACE acceleration for SHA1 and SHA256 */ #define CONFIG_EXYNOS_ACE_SHA -- cgit v1.2.3 From 2c94611d5f6dc5b49c02806dfdaacf6b27a5da83 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:40 -0600 Subject: cros_ec: power: Add a tunnelled version of the tps65090 driver Unfortunately on Pit the AP has no direct access to the tps65090 but must talk through the EC (over SPI) to the EC's I2C bus. When driver model supports PMICs this will be relatively easy. In the meantime the best approach is to duplicate the driver. It will be refactored once driver model support is expanded. Signed-off-by: Simon Glass Tested-by: Ajay Kumar Signed-off-by: Minkyu Kang --- drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps65090_ec.c | 218 ++++++++++++++++++++++++++++++++++ 2 files changed, 219 insertions(+) create mode 100644 drivers/power/pmic/pmic_tps65090_ec.c diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index a472f61f88..0b766112c0 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o +obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pmic_tps65090_ec.c b/drivers/power/pmic/pmic_tps65090_ec.c new file mode 100644 index 0000000000..ac0d44fec8 --- /dev/null +++ b/drivers/power/pmic/pmic_tps65090_ec.c @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2013 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define TPS65090_ADDR 0x48 + +static struct tps65090 { + struct cros_ec_dev *dev; /* The CROS_EC device */ +} config; + +/* TPS65090 register addresses */ +enum { + REG_IRQ1 = 0, + REG_CG_CTRL0 = 4, + REG_CG_STATUS1 = 0xa, + REG_FET1_CTRL = 0x0f, + REG_FET2_CTRL, + REG_FET3_CTRL, + REG_FET4_CTRL, + REG_FET5_CTRL, + REG_FET6_CTRL, + REG_FET7_CTRL, + TPS65090_NUM_REGS, +}; + +enum { + IRQ1_VBATG = 1 << 3, + CG_CTRL0_ENC_MASK = 0x01, + + MAX_FET_NUM = 7, + MAX_CTRL_READ_TRIES = 5, + + /* TPS65090 FET_CTRL register values */ + FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */ + FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */ + FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */ + FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */ + FET_CTRL_ENFET = 1 << 0, /* Enable FET */ +}; + +/** + * tps65090_read - read a byte from tps6090 + * + * @param reg The register address to read from. + * @param val We'll return value value read here. + * @return 0 if ok; error if EC returns failure. + */ +static int tps65090_read(u32 reg, u8 *val) +{ + return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1, + val, 1, true); +} + +/** + * tps65090_write - write a byte to tps6090 + * + * @param reg The register address to write to. + * @param val The value to write. + * @return 0 if ok; error if EC returns failure. + */ +static int tps65090_write(u32 reg, u8 val) +{ + return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1, + &val, 1, false); +} + +/** + * Checks for a valid FET number + * + * @param fet_id FET number to check + * @return 0 if ok, -EINVAL if FET value is out of range + */ +static int tps65090_check_fet(unsigned int fet_id) +{ + if (fet_id == 0 || fet_id > MAX_FET_NUM) { + debug("parameter fet_id is out of range, %u not in 1 ~ %u\n", + fet_id, MAX_FET_NUM); + return -EINVAL; + } + + return 0; +} + +/** + * Set the power state for a FET + * + * @param fet_id Fet number to set (1..MAX_FET_NUM) + * @param set 1 to power on FET, 0 to power off + * @return -EIO if we got a comms error, -EAGAIN if the FET failed to + * change state. If all is ok, returns 0. + */ +static int tps65090_fet_set(int fet_id, bool set) +{ + int retry; + u8 reg, value; + + value = FET_CTRL_ADENFET | FET_CTRL_WAIT; + if (set) + value |= FET_CTRL_ENFET; + + if (tps65090_write(REG_FET1_CTRL + fet_id - 1, value)) + return -EIO; + + /* Try reading until we get a result */ + for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) { + if (tps65090_read(REG_FET1_CTRL + fet_id - 1, ®)) + return -EIO; + + /* Check that the fet went into the expected state */ + if (!!(reg & FET_CTRL_PGFET) == set) + return 0; + + /* If we got a timeout, there is no point in waiting longer */ + if (reg & FET_CTRL_TOFET) + break; + + mdelay(1); + } + + debug("FET %d: Power good should have set to %d but reg=%#02x\n", + fet_id, set, reg); + return -EAGAIN; +} + +int tps65090_fet_enable(unsigned int fet_id) +{ + ulong start; + int loops; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + start = get_timer(0); + for (loops = 0;; loops++) { + ret = tps65090_fet_set(fet_id, true); + if (!ret) + break; + + if (get_timer(start) > 100) + break; + + /* Turn it off and try again until we time out */ + tps65090_fet_set(fet_id, false); + } + + if (ret) { + debug("%s: FET%d failed to power on: time=%lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + } else if (loops) { + debug("%s: FET%d powered on after %lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + } + /* + * Unfortunately, there are some conditions where the power + * good bit will be 0, but the fet still comes up. One such + * case occurs with the lcd backlight. We'll just return 0 here + * and assume that the fet will eventually come up. + */ + if (ret == -EAGAIN) + ret = 0; + + return ret; +} + +int tps65090_fet_disable(unsigned int fet_id) +{ + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + ret = tps65090_fet_set(fet_id, false); + + return ret; +} + +int tps65090_fet_is_enabled(unsigned int fet_id) +{ + u8 reg = 0; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + ret = tps65090_read(REG_FET1_CTRL + fet_id - 1, ®); + if (ret) { + debug("fail to read FET%u_CTRL register over I2C", fet_id); + return -EIO; + } + + return reg & FET_CTRL_ENFET; +} + +int tps65090_init(void) +{ + puts("TPS65090 PMIC EC init\n"); + + config.dev = board_get_cros_ec_dev(); + if (!config.dev) { + debug("%s: no cros_ec device: cannot init tps65090\n", + __func__); + return -ENODEV; + } + + return 0; +} -- cgit v1.2.3 From 5b9c8cb6cbb822594b9e5171a7ee2839f497352e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:41 -0600 Subject: cros_ec: exynos: Use the correct tps65090 driver in each case Exynos 5250 boards (snow, spring) use the I2C driver but Exynos 5420 boards cannot due to a hardware design decision. Select the correct driver to use in each case. Signed-off-by: Simon Glass Tested-by: Ajay Kumar Signed-off-by: Minkyu Kang --- drivers/power/pmic/Makefile | 2 +- include/configs/exynos5250-dt.h | 1 + include/configs/peach-pit.h | 2 ++ 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 0b766112c0..e7b07ebab4 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -11,7 +11,7 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o -obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o +obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index c24984bd2b..5504515ab1 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -42,6 +42,7 @@ /* PMIC */ #define CONFIG_POWER_MAX77686 +#define CONFIG_POWER_TPS65090_I2C /* Sound */ #define CONFIG_CMD_SOUND diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 987cef504c..34734ada21 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -30,4 +30,6 @@ #define LCD_BPP LCD_COLOR16 #endif +#define CONFIG_POWER_TPS65090_EC + #endif /* __CONFIG_PEACH_PIT_H */ -- cgit v1.2.3 From 98149d72f36f5543854568cb2d48277b0e7a88ba Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:42 -0600 Subject: dm: exynos: Split out the cros_ec drivers With the driver model conversion we are going to be using driver model for SPI and not for I2C. This works OK so long as a board doesn't need both dm and non-dm versions of the cros_ec driver. Since pit uses SPI and snow uses I2C we need to split the configs so that only one driver is compiled for each platform. We can fix this later when driver model supports I2C. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- include/configs/exynos5-dt.h | 2 -- include/configs/exynos5250-dt.h | 2 ++ include/configs/peach-pit.h | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index 68f3a41cc1..0c400b16fa 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -69,8 +69,6 @@ /* Enable keyboard */ #define CONFIG_CROS_EC /* CROS_EC protocol */ -#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ -#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ #define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ #define CONFIG_CMD_CROS_EC #define CONFIG_KEYBOARD diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 5504515ab1..05d33a7285 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -22,6 +22,8 @@ #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) +#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ + /* USB */ #define CONFIG_CMD_USB #define CONFIG_USB_XHCI diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 34734ada21..8db889c2ce 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -31,5 +31,6 @@ #endif #define CONFIG_POWER_TPS65090_EC +#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ #endif /* __CONFIG_PEACH_PIT_H */ -- cgit v1.2.3 From f0d80fbcd70e3ab56dc460bc5f5325176161f5a8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:43 -0600 Subject: exynos: dts: Add device tree node for cros_ec keyboard Add a keyboard definition so that the keyboard can be used on pit. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/dts/exynos5420-peach-pit.dts | 55 +++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index 207782effb..995e62b337 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -28,6 +28,61 @@ pmic = "/i2c@12ca0000"; }; + cros-ec-keyb { + compatible = "google,cros-ec-keyb"; + google,key-rows = <8>; + google,key-columns = <13>; + google,repeat-delay-ms = <240>; + google,repeat-rate-ms = <30>; + google,ghost-filter; + /* + * Keymap entries take the form of 0xRRCCKKKK where + * RR=Row CC=Column KKKK=Key Code + * The values below are for a US keyboard layout and + * are taken from the Linux driver. Note that the + * 102ND key is not used for US keyboards. + */ + linux,keymap = < + /* CAPSLCK F1 B F10 */ + 0x0001003a 0x0002003b 0x00030030 0x00040044 + /* N = R_ALT ESC */ + 0x00060031 0x0008000d 0x000a0064 0x01010001 + /* F4 G F7 H */ + 0x0102003e 0x01030022 0x01040041 0x01060023 + /* ' F9 BKSPACE L_CTRL */ + 0x01080028 0x01090043 0x010b000e 0x0200001d + /* TAB F3 T F6 */ + 0x0201000f 0x0202003d 0x02030014 0x02040040 + /* ] Y 102ND [ */ + 0x0205001b 0x02060015 0x02070056 0x0208001a + /* F8 GRAVE F2 5 */ + 0x02090042 0x03010029 0x0302003c 0x03030006 + /* F5 6 - \ */ + 0x0304003f 0x03060007 0x0308000c 0x030b002b + /* R_CTRL A D F */ + 0x04000061 0x0401001e 0x04020020 0x04030021 + /* S K J ; */ + 0x0404001f 0x04050025 0x04060024 0x04080027 + /* L ENTER Z C */ + 0x04090026 0x040b001c 0x0501002c 0x0502002e + /* V X , M */ + 0x0503002f 0x0504002d 0x05050033 0x05060032 + /* L_SHIFT / . SPACE */ + 0x0507002a 0x05080035 0x05090034 0x050B0039 + /* 1 3 4 2 */ + 0x06010002 0x06020004 0x06030005 0x06040003 + /* 8 7 0 9 */ + 0x06050009 0x06060008 0x0608000b 0x0609000a + /* L_ALT DOWN RIGHT Q */ + 0x060a0038 0x060b006c 0x060c006a 0x07010010 + /* E R W I */ + 0x07020012 0x07030013 0x07040011 0x07050017 + /* U R_SHIFT P O */ + 0x07060016 0x07070036 0x07080019 0x07090018 + /* UP LEFT */ + 0x070b0067 0x070c0069>; + }; + dmc { mem-manuf = "samsung"; mem-type = "ddr3"; -- cgit v1.2.3 From 4c7bb1d2e0526d26972969d4c01fd6c760d4d865 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:44 -0600 Subject: exynos: Rename -dt config files to -common We want exynos5250-dt.h to be a board which can support any exynos5250 device. This matches the naming used by Linux. As a first step, rename the existing -dt files to -common to make it clear they are common files, and not specific boards. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- include/configs/exynos4-common.h | 139 +++++++++++++++++ include/configs/exynos4-dt.h | 139 ----------------- include/configs/exynos5-common.h | 292 ++++++++++++++++++++++++++++++++++++ include/configs/exynos5-dt.h | 292 ------------------------------------ include/configs/exynos5250-common.h | 74 +++++++++ include/configs/exynos5250-dt.h | 74 --------- include/configs/odroid.h | 2 +- include/configs/origen.h | 2 +- include/configs/peach-pit.h | 2 +- include/configs/s5pc210_universal.h | 2 +- include/configs/smdk5250.h | 2 +- include/configs/smdk5420.h | 2 +- include/configs/snow.h | 2 +- include/configs/trats.h | 2 +- include/configs/trats2.h | 2 +- 15 files changed, 514 insertions(+), 514 deletions(-) create mode 100644 include/configs/exynos4-common.h delete mode 100644 include/configs/exynos4-dt.h create mode 100644 include/configs/exynos5-common.h delete mode 100644 include/configs/exynos5-dt.h create mode 100644 include/configs/exynos5250-common.h delete mode 100644 include/configs/exynos5250-dt.h diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h new file mode 100644 index 0000000000..38b8961a50 --- /dev/null +++ b/include/configs/exynos4-common.h @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS4_COMMON_H +#define __CONFIG_EXYNOS4_COMMON_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ +#define CONFIG_EXYNOS4 /* which is in a Exynos4 Family */ + +#include /* get chip and board defs */ + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_COMMON +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING + +#include + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_S5P_SDHCI +#define CONFIG_SDHCI +#define CONFIG_MMC_SDMA +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_MMC_DEFAULT_DEV 0 + +/* PWM */ +#define CONFIG_PWM + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command definition*/ +#include + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_XIMG +#undef CONFIG_CMD_CACHE +#undef CONFIG_CMD_ONENAND +#undef CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_MMC +#define CONFIG_CMD_DFU +#define CONFIG_CMD_GPT +#define CONFIG_CMD_PMIC +#define CONFIG_CMD_SETEXPR + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +/* FAT */ +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE + +/* EXT4 */ +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE + +/* USB Composite download gadget - g_dnl */ +#define CONFIG_USBDOWNLOAD_GADGET + +/* TIZEN THOR downloader support */ +#define CONFIG_CMD_THOR_DOWNLOAD +#define CONFIG_THOR_FUNCTION + +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* USB Samsung's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 +#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 +#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM +#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D +#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 +#define CONFIG_G_DNL_MANUFACTURER "Samsung" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_PART +#define CONFIG_PARTITION_UUIDS + +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE + +/* Enable devicetree support */ +#define CONFIG_OF_LIBFDT + +#endif /* __CONFIG_EXYNOS4_COMMON_H */ diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos4-dt.h deleted file mode 100644 index 99472acd0c..0000000000 --- a/include/configs/exynos4-dt.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (C) 2014 Samsung Electronics - * - * Configuration settings for the SAMSUNG EXYNOS5 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS4 /* which is in a Exynos4 Family */ - -#include /* get chip and board defs */ - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_COMMON -#define CONFIG_SYS_GENERIC_BOARD - -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - -#include - -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_S5P_SDHCI -#define CONFIG_SDHCI -#define CONFIG_MMC_SDMA -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_MMC_DEFAULT_DEV 0 - -/* PWM */ -#define CONFIG_PWM - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition*/ -#include - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG -#undef CONFIG_CMD_CACHE -#undef CONFIG_CMD_ONENAND -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_MMC -#define CONFIG_CMD_DFU -#define CONFIG_CMD_GPT -#define CONFIG_CMD_PMIC -#define CONFIG_CMD_SETEXPR - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -/* FAT */ -#define CONFIG_CMD_FAT -#define CONFIG_FAT_WRITE - -/* EXT4 */ -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE - -/* USB Composite download gadget - g_dnl */ -#define CONFIG_USBDOWNLOAD_GADGET - -/* TIZEN THOR downloader support */ -#define CONFIG_CMD_THOR_DOWNLOAD -#define CONFIG_THOR_FUNCTION - -#define CONFIG_DFU_FUNCTION -#define CONFIG_DFU_MMC -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M -#define DFU_DEFAULT_POLL_TIMEOUT 300 - -/* USB Samsung's IDs */ -#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 -#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 -#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 -#define CONFIG_G_DNL_MANUFACTURER "Samsung" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - -#define CONFIG_USB_GADGET -#define CONFIG_USB_GADGET_S3C_UDC_OTG -#define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET_VBUS_DRAW 2 - -#define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USB_GADGET_MASS_STORAGE - -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - -#endif /* __CONFIG_H */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h new file mode 100644 index 0000000000..fede0e8cbf --- /dev/null +++ b/include/configs/exynos5-common.h @@ -0,0 +1,292 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS5_COMMON_H +#define __CONFIG_EXYNOS5_COMMON_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ +#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ + +#include /* get chip and board defs */ + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_COMMON +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_EXYNOS_SPL + +/* Allow tracing to be enabled */ +#define CONFIG_TRACE +#define CONFIG_CMD_TRACE +#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) +#define CONFIG_TRACE_EARLY_SIZE (8 << 20) +#define CONFIG_TRACE_EARLY +#define CONFIG_TRACE_EARLY_ADDR 0x50000000 + +/* Keep L2 Cache Disabled */ +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_CMD_CACHE + +/* Enable ACE acceleration for SHA1 and SHA256 */ +#define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_SHA_HW_ACCEL + +/* input clock of PLL: SMDK5250 has 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING + +/* Power Down Modes */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +/* Offset for inform registers */ +#define INFORM0_OFFSET 0x800 +#define INFORM1_OFFSET 0x804 +#define INFORM2_OFFSET 0x808 +#define INFORM3_OFFSET 0x80c + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) + +/* select serial console configuration */ +#define CONFIG_BAUDRATE 115200 +#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 +#define CONFIG_SILENT_CONSOLE + +/* Enable keyboard */ +#define CONFIG_CROS_EC /* CROS_EC protocol */ +#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ +#define CONFIG_CMD_CROS_EC +#define CONFIG_KEYBOARD + +/* Console configuration */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define EXYNOS_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_S5P_SDHCI +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC +#define CONFIG_SUPPORT_EMMC_BOOT +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* PWM */ +#define CONFIG_PWM + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command definition*/ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_NET +#define CONFIG_CMD_HASH + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +/* Thermal Management Unit */ +#define CONFIG_EXYNOS_TMU +#define CONFIG_CMD_DTT +#define CONFIG_TMU_CMD_DTT + +/* TPM */ +#define CONFIG_TPM +#define CONFIG_CMD_TPM +#define CONFIG_TPM_TIS_I2C +#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 +#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 + +/* MMC SPL */ +#define COPY_BL2_FNPTR_ADDR 0x02020030 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT + +/* specific .lds file */ +#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + +#define CONFIG_RD_LVL + +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS + +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_SECURE_BL1_ONLY + +/* Secure FW size configuration */ +#ifdef CONFIG_SECURE_BL1_ONLY +#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ +#else +#define CONFIG_SEC_FW_SIZE 0 +#endif + +/* Configuration of BL1, BL2, ENV Blocks on mmc */ +#define CONFIG_RES_BLOCK_SIZE (512) +#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ +#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ + +#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) +#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) + +/* Store environment at the end of a 4 MB SPI flash */ +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) + +/* U-boot copy size from boot Media to DRAM.*/ +#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) +#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) + +#define CONFIG_SPI_BOOTING +#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 +#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_PART +#define CONFIG_PARTITION_UUIDS + +/* I2C */ +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_SYS_I2C +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ +#define CONFIG_SYS_I2C_S3C24X0 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 +#define CONFIG_I2C_EDID + +/* SPI */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 + +#ifdef CONFIG_SPI_FLASH +#define CONFIG_EXYNOS_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 50000000 +#define EXYNOS5_SPI_NUM_CONTROLLERS 5 +#define CONFIG_OF_SPI +#endif + +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +#define CONFIG_ENV_SPI_BUS 1 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 +#endif + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_TPS65090 + +/* Ethernet Controllor Driver */ +#ifdef CONFIG_CMD_NET +#define CONFIG_SMC911X +#define CONFIG_SMC911X_BASE 0x5000000 +#define CONFIG_SMC911X_16_BIT +#define CONFIG_ENV_SROM_BANK 1 +#endif /*CONFIG_CMD_NET*/ + +/* Enable PXE Support */ +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_PXE +#define CONFIG_MENU +#endif + +/* Enable devicetree support */ +#define CONFIG_OF_LIBFDT + +/* SHA hashing */ +#define CONFIG_CMD_HASH +#define CONFIG_HASH_VERIFY +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +/* Enable Time Command */ +#define CONFIG_CMD_TIME + +#define CONFIG_CMD_BOOTZ + +#define CONFIG_CMD_GPIO + +/* USB boot mode */ +#define CONFIG_USB_BOOTING +#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 +#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 +#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 + +#endif /* __CONFIG_EXYNOS5_COMMON_H */ diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h deleted file mode 100644 index 0c400b16fa..0000000000 --- a/include/configs/exynos5-dt.h +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright (C) 2013 Samsung Electronics - * - * Configuration settings for the SAMSUNG EXYNOS5 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ - -#include /* get chip and board defs */ - -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_COMMON -#define CONFIG_ARCH_EARLY_INIT_R -#define CONFIG_EXYNOS_SPL - -/* Allow tracing to be enabled */ -#define CONFIG_TRACE -#define CONFIG_CMD_TRACE -#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) -#define CONFIG_TRACE_EARLY_SIZE (8 << 20) -#define CONFIG_TRACE_EARLY -#define CONFIG_TRACE_EARLY_ADDR 0x50000000 - -/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_CMD_CACHE - -/* Enable ACE acceleration for SHA1 and SHA256 */ -#define CONFIG_EXYNOS_ACE_SHA -#define CONFIG_SHA_HW_ACCEL - -/* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - -/* Power Down Modes */ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - -/* Offset for inform registers */ -#define INFORM0_OFFSET 0x800 -#define INFORM1_OFFSET 0x804 -#define INFORM2_OFFSET 0x808 -#define INFORM3_OFFSET 0x80c - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) - -/* select serial console configuration */ -#define CONFIG_BAUDRATE 115200 -#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 -#define CONFIG_SILENT_CONSOLE - -/* Enable keyboard */ -#define CONFIG_CROS_EC /* CROS_EC protocol */ -#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ -#define CONFIG_CMD_CROS_EC -#define CONFIG_KEYBOARD - -/* Console configuration */ -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial,cros-ec-keyb\0" \ - "stdout=serial,lcd\0" \ - "stderr=serial,lcd\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXYNOS_DEVICE_SETTINGS - -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC -#define CONFIG_SUPPORT_EMMC_BOOT -#define CONFIG_BOUNCE_BUFFER - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* PWM */ -#define CONFIG_PWM - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition*/ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_NET -#define CONFIG_CMD_HASH - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -/* Thermal Management Unit */ -#define CONFIG_EXYNOS_TMU -#define CONFIG_CMD_DTT -#define CONFIG_TMU_CMD_DTT - -/* TPM */ -#define CONFIG_TPM -#define CONFIG_CMD_TPM -#define CONFIG_TPM_TIS_I2C -#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 -#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 - -/* MMC SPL */ -#define COPY_BL2_FNPTR_ADDR 0x02020030 - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT - -/* specific .lds file */ -#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -#define CONFIG_RD_LVL - -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_SECURE_BL1_ONLY - -/* Secure FW size configuration */ -#ifdef CONFIG_SECURE_BL1_ONLY -#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ -#else -#define CONFIG_SEC_FW_SIZE 0 -#endif - -/* Configuration of BL1, BL2, ENV Blocks on mmc */ -#define CONFIG_RES_BLOCK_SIZE (512) -#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ -#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ - -#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) -#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) - -/* Store environment at the end of a 4 MB SPI flash */ -#define FLASH_SIZE (0x4 << 20) -#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) - -/* U-boot copy size from boot Media to DRAM.*/ -#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) -#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) - -#define CONFIG_SPI_BOOTING -#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 -#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) - -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - -/* I2C */ -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C -#define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ -#define CONFIG_SYS_I2C_S3C24X0 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 -#define CONFIG_I2C_EDID - -/* SPI */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SPI_FLASH -#define CONFIG_ENV_SPI_BASE 0x12D30000 - -#ifdef CONFIG_SPI_FLASH -#define CONFIG_EXYNOS_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SPI_FLASH_GIGADEVICE -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SF_DEFAULT_SPEED 50000000 -#define EXYNOS5_SPI_NUM_CONTROLLERS 5 -#define CONFIG_OF_SPI -#endif - -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -#define CONFIG_ENV_SPI_BUS 1 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 -#endif - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_TPS65090 - -/* Ethernet Controllor Driver */ -#ifdef CONFIG_CMD_NET -#define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE 0x5000000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_ENV_SROM_BANK 1 -#endif /*CONFIG_CMD_NET*/ - -/* Enable PXE Support */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PXE -#define CONFIG_MENU -#endif - -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - -/* SHA hashing */ -#define CONFIG_CMD_HASH -#define CONFIG_HASH_VERIFY -#define CONFIG_SHA1 -#define CONFIG_SHA256 - -/* Enable Time Command */ -#define CONFIG_CMD_TIME - -#define CONFIG_CMD_BOOTZ - -#define CONFIG_CMD_GPIO - -/* USB boot mode */ -#define CONFIG_USB_BOOTING -#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 -#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 -#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 - -#endif /* __CONFIG_H */ diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h new file mode 100644 index 0000000000..b4c1ccffe3 --- /dev/null +++ b/include/configs/exynos5250-common.h @@ -0,0 +1,74 @@ + +/* + * Copyright (C) 2012 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5250 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_5250_H +#define __CONFIG_5250_H + +#include +#define CONFIG_EXYNOS5250 + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000 + +/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */ +#define MACH_TYPE_SMDK5250 3774 +#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 + +#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) + +#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ + +/* USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE + +#define CONFIG_SPL_TEXT_BASE 0x02023400 + +#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" + +#define CONFIG_SYS_PROMPT "SMDK5250 # " +#define CONFIG_IDENT_STRING " for SMDK5250" + +#define CONFIG_IRAM_STACK 0x02050000 + +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK + +/* PMIC */ +#define CONFIG_POWER_MAX77686 +#define CONFIG_POWER_TPS65090_I2C + +/* Sound */ +#define CONFIG_CMD_SOUND +#ifdef CONFIG_CMD_SOUND +#define CONFIG_SOUND +#define CONFIG_I2S_SAMSUNG +#define CONFIG_I2S +#define CONFIG_SOUND_MAX98095 +#define CONFIG_SOUND_WM8994 +#endif + +/* I2C */ +#define CONFIG_MAX_I2C_NUM 8 + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPP LCD_COLOR16 +#endif + +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 8 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ + +#endif /* __CONFIG_5250_H */ diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h deleted file mode 100644 index 05d33a7285..0000000000 --- a/include/configs/exynos5250-dt.h +++ /dev/null @@ -1,74 +0,0 @@ - -/* - * Copyright (C) 2012 Samsung Electronics - * - * Configuration settings for the SAMSUNG EXYNOS5250 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_5250_H -#define __CONFIG_5250_H - -#include -#define CONFIG_EXYNOS5250 - -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_TEXT_BASE 0x43E00000 - -/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */ -#define MACH_TYPE_SMDK5250 3774 -#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 - -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - -#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ - -/* USB */ -#define CONFIG_CMD_USB -#define CONFIG_USB_XHCI -#define CONFIG_USB_XHCI_EXYNOS -#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE - -#define CONFIG_SPL_TEXT_BASE 0x02023400 - -#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" - -#define CONFIG_SYS_PROMPT "SMDK5250 # " -#define CONFIG_IDENT_STRING " for SMDK5250" - -#define CONFIG_IRAM_STACK 0x02050000 - -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK - -/* PMIC */ -#define CONFIG_POWER_MAX77686 -#define CONFIG_POWER_TPS65090_I2C - -/* Sound */ -#define CONFIG_CMD_SOUND -#ifdef CONFIG_CMD_SOUND -#define CONFIG_SOUND -#define CONFIG_I2S_SAMSUNG -#define CONFIG_I2S -#define CONFIG_SOUND_MAX98095 -#define CONFIG_SOUND_WM8994 -#endif - -/* I2C */ -#define CONFIG_MAX_I2C_NUM 8 - -/* Display */ -#define CONFIG_LCD -#ifdef CONFIG_LCD -#define CONFIG_EXYNOS_FB -#define CONFIG_EXYNOS_DP -#define LCD_BPP LCD_COLOR16 -#endif - -/* DRAM Memory Banks */ -#define CONFIG_NR_DRAM_BANKS 8 -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ - -#endif /* __CONFIG_5250_H */ diff --git a/include/configs/odroid.h b/include/configs/odroid.h index b616ac2fbd..07a2ff69ca 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -12,7 +12,7 @@ #ifndef __CONFIG_ODROID_U3_H #define __CONFIG_ODROID_U3_H -#include +#include #define CONFIG_SYS_PROMPT "Odroid # " /* Monitor Command Prompt */ diff --git a/include/configs/origen.h b/include/configs/origen.h index fb1536c62c..fc8a202a93 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_ORIGEN_H #define __CONFIG_ORIGEN_H -#include +#include #define CONFIG_SYS_PROMPT "ORIGEN # " diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 8db889c2ce..5e428cc8ff 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_PEACH_PIT_H #define __CONFIG_PEACH_PIT_H -#include +#include #include diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 082d51c52b..e26522d17d 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_UNIVERSAL_H #define __CONFIG_UNIVERSAL_H -#include +#include #define CONFIG_SYS_PROMPT "Universal # " /* Monitor Command Prompt */ diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 61170941c1..56d41e69e6 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_SMDK_H #define __CONFIG_SMDK_H -#include +#include /* Enable FIT support and comparison */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 36a156f7a7..abda141770 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_SMDK5420_H #define __CONFIG_SMDK5420_H -#include +#include #include diff --git a/include/configs/snow.h b/include/configs/snow.h index fbaaa593cc..2942fdfda0 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_SNOW_H #define __CONFIG_SNOW_H -#include +#include /* Enable FIT support and comparison */ diff --git a/include/configs/trats.h b/include/configs/trats.h index 43751e7938..c7edd07937 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_TRATS_H #define __CONFIG_TRATS_H -#include +#include #define CONFIG_SYS_PROMPT "Trats # " /* Monitor Command Prompt */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index e9a04f7af3..de72651828 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -11,7 +11,7 @@ #ifndef __CONFIG_TRATS2_H #define __CONFIG_TRATS2_H -#include +#include #define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */ -- cgit v1.2.3 From 5ea01ab10dcdab41d1bfb1972b4b2298d5a26fcf Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:45 -0600 Subject: exynos: Move common exynos settings into a common file Since exynos4 and exyno5 share many settings, we should move these into a common file to avoid duplication. In effect the changes are that all exynos boards now have EXT4 and FAT write support. This affects exynos5250 and exynos5420 which previously did not. This also disables the ext2 commands which are equivalent to ext4 anyway. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- include/configs/exynos-common.h | 91 +++++++++++++++++++++++++++++++++++++ include/configs/exynos4-common.h | 77 +------------------------------ include/configs/exynos5-common.h | 86 +++++------------------------------ include/configs/origen.h | 3 -- include/configs/s5pc210_universal.h | 3 -- include/configs/smdk5250.h | 4 -- include/configs/snow.h | 4 -- include/configs/trats.h | 4 -- include/configs/trats2.h | 4 -- 9 files changed, 105 insertions(+), 171 deletions(-) create mode 100644 include/configs/exynos-common.h diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h new file mode 100644 index 0000000000..7b9eda4aef --- /dev/null +++ b/include/configs/exynos-common.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Common configuration settings for the SAMSUNG EXYNOS boards. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EXYNOS_COMMON_H +#define __EXYNOS_COMMON_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ + +#include /* get chip and board defs */ +#include + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_COMMON +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F + +/* Enable fdt support */ +#define CONFIG_OF_LIBFDT + +/* Keep L2 Cache Disabled */ +#define CONFIG_CMD_CACHE + +/* input clock of PLL: 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING +#define CONFIG_ENV_OVERWRITE + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) + +/* select serial console configuration */ +#define CONFIG_BAUDRATE 115200 + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_S5P_SDHCI +#define CONFIG_SDHCI +#define CONFIG_DWMMC +#define CONFIG_EXYNOS_DWMMC +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +/* PWM */ +#define CONFIG_PWM + +/* Command definition*/ +#include + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_PART +#define CONFIG_PARTITION_UUIDS + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS + +#endif /* __CONFIG_H */ diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 38b8961a50..972add458c 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -9,81 +9,29 @@ #ifndef __CONFIG_EXYNOS4_COMMON_H #define __CONFIG_EXYNOS4_COMMON_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS4 /* which is in a Exynos4 Family */ +#define CONFIG_EXYNOS4 /* Exynos4 Family */ -#include /* get chip and board defs */ - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_COMMON -#define CONFIG_SYS_GENERIC_BOARD +#include "exynos-common.h" #define CONFIG_SYS_CACHELINE_SIZE 32 - -/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG #define CONFIG_REVISION_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - -#include /* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_S5P_SDHCI -#define CONFIG_SDHCI #define CONFIG_MMC_SDMA -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC -#define CONFIG_BOUNCE_BUFFER #define CONFIG_MMC_DEFAULT_DEV 0 -/* PWM */ -#define CONFIG_PWM - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition*/ -#include - #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_MISC #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS #undef CONFIG_CMD_XIMG -#undef CONFIG_CMD_CACHE #undef CONFIG_CMD_ONENAND #undef CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_MMC #define CONFIG_CMD_DFU #define CONFIG_CMD_GPT #define CONFIG_CMD_PMIC #define CONFIG_CMD_SETEXPR -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -/* FAT */ -#define CONFIG_CMD_FAT -#define CONFIG_FAT_WRITE - -/* EXT4 */ -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE - /* USB Composite download gadget - g_dnl */ #define CONFIG_USBDOWNLOAD_GADGET @@ -105,26 +53,8 @@ #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 #define CONFIG_G_DNL_MANUFACTURER "Samsung" -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_S3C_UDC_OTG #define CONFIG_USB_GADGET_DUALSPEED @@ -133,7 +63,4 @@ #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_GADGET_MASS_STORAGE -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - #endif /* __CONFIG_EXYNOS4_COMMON_H */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index fede0e8cbf..380a46feb8 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -9,18 +9,11 @@ #ifndef __CONFIG_EXYNOS5_COMMON_H #define __CONFIG_EXYNOS5_COMMON_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ - -#include /* get chip and board defs */ - -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_COMMON +#define CONFIG_EXYNOS5 /* Exynos5 Family */ + +#include "exynos-common.h" + +#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_EXYNOS_SPL @@ -32,22 +25,11 @@ #define CONFIG_TRACE_EARLY #define CONFIG_TRACE_EARLY_ADDR 0x50000000 -/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_CMD_CACHE /* Enable ACE acceleration for SHA1 and SHA256 */ #define CONFIG_EXYNOS_ACE_SHA #define CONFIG_SHA_HW_ACCEL -/* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - /* Power Down Modes */ #define S5P_CHECK_SLEEP 0x00000BAD #define S5P_CHECK_DIDLE 0xBAD00000 @@ -59,13 +41,12 @@ #define INFORM2_OFFSET 0x808 #define INFORM3_OFFSET 0x80c -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) - /* select serial console configuration */ #define CONFIG_BAUDRATE 115200 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 #define CONFIG_SILENT_CONSOLE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_CONSOLE_MUX /* Enable keyboard */ #define CONFIG_CROS_EC /* CROS_EC protocol */ @@ -74,8 +55,6 @@ #define CONFIG_KEYBOARD /* Console configuration */ -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define EXYNOS_DEVICE_SETTINGS \ "stdin=serial,cros-ec-keyb\0" \ "stdout=serial,lcd\0" \ @@ -84,39 +63,11 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ EXYNOS_DEVICE_SETTINGS -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC -#define CONFIG_SUPPORT_EMMC_BOOT -#define CONFIG_BOUNCE_BUFFER - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* PWM */ -#define CONFIG_PWM - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition*/ -#include - #define CONFIG_CMD_PING #define CONFIG_CMD_ELF -#define CONFIG_CMD_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT #define CONFIG_CMD_NET #define CONFIG_CMD_HASH -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - /* Thermal Management Unit */ #define CONFIG_EXYNOS_TMU #define CONFIG_CMD_DTT @@ -131,6 +82,7 @@ /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 +#define CONFIG_SUPPORT_EMMC_BOOT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT @@ -139,14 +91,8 @@ #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" /* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) @@ -173,10 +119,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS - #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SECURE_BL1_ONLY @@ -209,11 +151,6 @@ #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - /* I2C */ #define CONFIG_SYS_I2C_INIT_BOARD #define CONFIG_SYS_I2C @@ -267,9 +204,6 @@ #define CONFIG_MENU #endif -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - /* SHA hashing */ #define CONFIG_CMD_HASH #define CONFIG_HASH_VERIFY @@ -289,4 +223,8 @@ #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 +/* Enable FIT support and comparison */ +#define CONFIG_FIT +#define CONFIG_FIT_BEST_MATCH + #endif /* __CONFIG_EXYNOS5_COMMON_H */ diff --git a/include/configs/origen.h b/include/configs/origen.h index fc8a202a93..da9d6a1ee1 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -35,9 +35,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - /* select serial console configuration */ #define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index e26522d17d..27f3d0af47 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -27,9 +27,6 @@ #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - /* select serial console configuration */ #define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 56d41e69e6..7673bae446 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -12,8 +12,4 @@ #include -/* Enable FIT support and comparison */ -#define CONFIG_FIT -#define CONFIG_FIT_BEST_MATCH - #endif /* __CONFIG_SMDK_H */ diff --git a/include/configs/snow.h b/include/configs/snow.h index 2942fdfda0..0834cc9223 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -12,8 +12,4 @@ #include -/* Enable FIT support and comparison */ -#define CONFIG_FIT -#define CONFIG_FIT_BEST_MATCH - #endif /* __CONFIG_SNOW_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h index c7edd07937..b21ea2de5f 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -39,10 +39,6 @@ #define CONFIG_SYS_TEXT_BASE 0x63300000 -#include -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - /* select serial console configuration */ #define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/trats2.h b/include/configs/trats2.h index de72651828..42481ab6e1 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -36,10 +36,6 @@ #define CONFIG_SYS_TEXT_BASE 0x43e00000 -#include -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - /* select serial console configuration */ #define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 -- cgit v1.2.3 From 87033d4d97e0cc569c59efef7ce4ce940c48e71b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:46 -0600 Subject: exynos: Move common smdk5420 things to common file A few things are common but are not in the common file. Fix this and rename the file to fit with the other exynos*-common files. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- include/configs/exynos5420-common.h | 50 +++++++++++++++++++++++++++++++++++ include/configs/exynos5420.h | 52 ------------------------------------- include/configs/peach-pit.h | 4 +-- include/configs/smdk5420.h | 4 +-- 4 files changed, 52 insertions(+), 58 deletions(-) create mode 100644 include/configs/exynos5420-common.h delete mode 100644 include/configs/exynos5420.h diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h new file mode 100644 index 0000000000..27e7edc577 --- /dev/null +++ b/include/configs/exynos5420-common.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5420 SoC + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS5420_H +#define __CONFIG_EXYNOS5420_H + +#define CONFIG_EXYNOS5420 + +#include + +#define MACH_TYPE_SMDK5420 8002 +#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 + +#define CONFIG_VAR_SIZE_SPL + +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_TEXT_BASE 0x23E00000 +#ifdef CONFIG_VAR_SIZE_SPL +#define CONFIG_SPL_TEXT_BASE 0x02024410 +#else +#define CONFIG_SPL_TEXT_BASE 0x02024400 +#endif +#define CONFIG_IRAM_TOP 0x02074000 + +#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024) + +#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420" + +#define CONFIG_MAX_I2C_NUM 11 + +#define CONFIG_BOARD_REV_GPIO_COUNT 2 + +#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000" + +/* + * Put the initial stack pointer 1KB below this to allow room for the + * SPL marker. This value is arbitrary, but gd_t is placed starting here. + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) + +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ + +#endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h deleted file mode 100644 index d2a95567a8..0000000000 --- a/include/configs/exynos5420.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2013 Samsung Electronics - * - * Configuration settings for the SAMSUNG EXYNOS5420 SoC - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_EXYNOS5420_H -#define __CONFIG_EXYNOS5420_H - -#define CONFIG_EXYNOS5420 /* which is in a Exynos5 Family */ - -#define MACH_TYPE_SMDK5420 8002 -#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 - -#define CONFIG_VAR_SIZE_SPL - -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_TEXT_BASE 0x23E00000 -#ifdef CONFIG_VAR_SIZE_SPL -#define CONFIG_SPL_TEXT_BASE 0x02024410 -#else -#define CONFIG_SPL_TEXT_BASE 0x02024400 -#endif -#define CONFIG_IRAM_TOP 0x02074000 - -#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024) - -#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420" - -#define CONFIG_MAX_I2C_NUM 11 - -/* Enable FIT support and comparison */ -#define CONFIG_FIT -#define CONFIG_FIT_BEST_MATCH - -#define CONFIG_BOARD_REV_GPIO_COUNT 2 - -#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000" - -/* - * Put the initial stack pointer 1KB below this to allow room for the - * SPL marker. This value is arbitrary, but gd_t is placed starting here. - */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) - -/* DRAM Memory Banks */ -#define CONFIG_NR_DRAM_BANKS 7 -#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ - -#endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 5e428cc8ff..e9736fc449 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -9,9 +9,7 @@ #ifndef __CONFIG_PEACH_PIT_H #define __CONFIG_PEACH_PIT_H -#include - -#include +#include /* select serial console configuration */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index abda141770..894ed115d6 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -9,9 +9,7 @@ #ifndef __CONFIG_SMDK5420_H #define __CONFIG_SMDK5420_H -#include - -#include +#include #define CONFIG_SMDK5420 /* which is in a SMDK5420 */ -- cgit v1.2.3 From 7d159536192323d65765211e7e7f56efcf3509ac Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:47 -0600 Subject: exynos: config: Move cros_ec and tps65090 out of smdk boards These boards do not in fact have a Chrome OS EC, nor a TPS565090 PMIC, so move the settings into a separate common file to be used by those that need it. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- include/configs/exynos5-common.h | 18 +++--------------- include/configs/exynos5-dt-common.h | 35 +++++++++++++++++++++++++++++++++++ include/configs/exynos5250-common.h | 3 --- include/configs/peach-pit.h | 1 + include/configs/snow.h | 4 ++++ 5 files changed, 43 insertions(+), 18 deletions(-) create mode 100644 include/configs/exynos5-dt-common.h diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 380a46feb8..3581a3878c 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -48,17 +48,10 @@ #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_CONSOLE_MUX -/* Enable keyboard */ -#define CONFIG_CROS_EC /* CROS_EC protocol */ -#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ -#define CONFIG_CMD_CROS_EC -#define CONFIG_KEYBOARD - -/* Console configuration */ #define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial,cros-ec-keyb\0" \ - "stdout=serial,lcd\0" \ - "stderr=serial,lcd\0" + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" #define CONFIG_EXTRA_ENV_SETTINGS \ EXYNOS_DEVICE_SETTINGS @@ -185,11 +178,6 @@ #define CONFIG_ENV_SPI_MAX_HZ 50000000 #endif -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_TPS65090 - /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET #define CONFIG_SMC911X diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h new file mode 100644 index 0000000000..66547fa34e --- /dev/null +++ b/include/configs/exynos5-dt-common.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * Configuration settings for generic Exynos 5 board + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS5_DT_COMMON_H +#define __CONFIG_EXYNOS5_DT_COMMON_H + +#include "exynos5-common.h" + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_TPS65090 + +/* Enable keyboard */ +#define CONFIG_CROS_EC /* CROS_EC protocol */ +#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ +#define CONFIG_CMD_CROS_EC +#define CONFIG_KEYBOARD + +/* Console configuration */ +#undef EXYNOS_DEVICE_SETTINGS +#define EXYNOS_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS + +#endif diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index b4c1ccffe3..987eb15fd9 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -22,8 +22,6 @@ #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) -#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ - /* USB */ #define CONFIG_CMD_USB #define CONFIG_USB_XHCI @@ -44,7 +42,6 @@ /* PMIC */ #define CONFIG_POWER_MAX77686 -#define CONFIG_POWER_TPS65090_I2C /* Sound */ #define CONFIG_CMD_SOUND diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index e9736fc449..046813d1b6 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -10,6 +10,7 @@ #define __CONFIG_PEACH_PIT_H #include +#include /* select serial console configuration */ diff --git a/include/configs/snow.h b/include/configs/snow.h index 0834cc9223..dc09c66543 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -10,6 +10,10 @@ #define __CONFIG_SNOW_H #include +#include +#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ +#define CONFIG_POWER_TPS65090_I2C + #endif /* __CONFIG_SNOW_H */ -- cgit v1.2.3 From f94de733df8a3a6e28a9acbfc00871319f567775 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:48 -0600 Subject: config: Move arndale to use common exynos5250 file Most of the arndale features are common with other exynos5250 boards. To permit easier addition of driver model support, use the common file. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- include/configs/arndale.h | 195 +----------------------------------- include/configs/exynos-common.h | 1 - include/configs/exynos4-common.h | 2 + include/configs/exynos5-common.h | 12 --- include/configs/exynos5250-common.h | 5 - include/configs/exynos5420-common.h | 14 +++ include/configs/peach-pit.h | 10 ++ include/configs/smdk5250.h | 19 ++++ include/configs/smdk5420.h | 3 + include/configs/snow.h | 17 ++++ 10 files changed, 66 insertions(+), 212 deletions(-) diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 43077cf851..f9ee40fa7e 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -9,109 +9,19 @@ #ifndef __CONFIG_ARNDALE_H #define __CONFIG_ARNDALE_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ -#define CONFIG_EXYNOS5250 - -#include /* get chip and board defs */ - -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - - -/* Allow tracing to be enabled */ -#define CONFIG_TRACE -#define CONFIG_CMD_TRACE -#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) -#define CONFIG_TRACE_EARLY_SIZE (8 << 20) -#define CONFIG_TRACE_EARLY -#define CONFIG_TRACE_EARLY_ADDR 0x50000000 - -/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_DCACHE_OFF - -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_TEXT_BASE 0x43E00000 - -/* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - -/* Power Down Modes */ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - -/* Offset for inform registers */ -#define INFORM0_OFFSET 0x800 -#define INFORM1_OFFSET 0x804 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) - -/* select serial console configuration */ -#define CONFIG_BAUDRATE 115200 -#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 -#define CONFIG_SILENT_CONSOLE - -/* Console configuration */ -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXYNOS_DEVICE_SETTINGS +#include "exynos5250-common.h" /* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC #define CONFIG_SUPPORT_EMMC_BOOT -#define CONFIG_BOUNCE_BUFFER - - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* PWM */ -#define CONFIG_PWM /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -/* Command definition*/ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MMC #define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_NET -#define CONFIG_CMD_HASH - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* USB */ -#define CONFIG_CMD_USB #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_EXYNOS -#define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_USB_HOST_ETHER @@ -119,106 +29,23 @@ /* MMC SPL */ #define CONFIG_EXYNOS_SPL -#define COPY_BL2_FNPTR_ADDR 0x02020030 - -#define CONFIG_SPL_LIBCOMMON_SUPPORT - -/* specific .lds file */ -#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" -#define CONFIG_SPL_TEXT_BASE 0x02023400 -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - -#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" /* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "ARNDALE # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -#define CONFIG_RD_LVL #define CONFIG_NR_DRAM_BANKS 8 #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS #define CONFIG_IDENT_STRING " for ARNDALE" -#define CONFIG_SYS_MMC_ENV_DEV 0 - #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SECURE_BL1_ONLY - -/* Secure FW size configuration */ -#ifdef CONFIG_SECURE_BL1_ONLY -#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ -#else -#define CONFIG_SEC_FW_SIZE 0 -#endif - -/* Configuration of BL1, BL2, ENV Blocks on mmc */ -#define CONFIG_RES_BLOCK_SIZE (512) -#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ -#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ - -#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) -#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) #define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) -/* U-boot copy size from boot Media to DRAM.*/ -#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) -#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) - -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - - #define CONFIG_IRAM_STACK 0x02050000 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK -/* I2C */ -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C -#define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ -#define CONFIG_SYS_I2C_S3C24X0 -#define CONFIG_MAX_I2C_NUM 8 -#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 -#define CONFIG_I2C_EDID - /* PMIC */ #define CONFIG_PMIC #define CONFIG_POWER_I2C @@ -227,26 +54,6 @@ #define CONFIG_PREBOOT -/* Ethernet Controllor Driver */ -#ifdef CONFIG_CMD_NET -#define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE 0x5000000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_ENV_SROM_BANK 1 -#endif /*CONFIG_CMD_NET*/ - -/* Enable PXE Support */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PXE -#define CONFIG_MENU -#endif - -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - -/* Enable Time Command */ -#define CONFIG_CMD_TIME - #define CONFIG_S5P_PA_SYSRAM 0x02020000 #define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 7b9eda4aef..54b61d71a5 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -20,7 +20,6 @@ #define CONFIG_ARCH_CPU_INIT #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_COMMON #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 972add458c..89ba14e05d 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -13,6 +13,8 @@ #include "exynos-common.h" +#define CONFIG_BOARD_COMMON + #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_REVISION_TAG diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 3581a3878c..ba591e7c1e 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -14,7 +14,6 @@ #include "exynos-common.h" #define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_EXYNOS_SPL /* Allow tracing to be enabled */ @@ -83,8 +82,6 @@ /* specific .lds file */ #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" -/* Miscellaneous configurable options */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" /* Boot Argument Buffer Size */ /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE @@ -132,15 +129,10 @@ #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) -/* Store environment at the end of a 4 MB SPI flash */ -#define FLASH_SIZE (0x4 << 20) -#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) - /* U-boot copy size from boot Media to DRAM.*/ #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) -#define CONFIG_SPI_BOOTING #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) @@ -155,10 +147,6 @@ #define CONFIG_I2C_EDID /* SPI */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SPI_FLASH -#define CONFIG_ENV_SPI_BASE 0x12D30000 - #ifdef CONFIG_SPI_FLASH #define CONFIG_EXYNOS_SPI #define CONFIG_CMD_SF diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 987eb15fd9..713614f3ad 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -24,8 +24,6 @@ /* USB */ #define CONFIG_CMD_USB -#define CONFIG_USB_XHCI -#define CONFIG_USB_XHCI_EXYNOS #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE @@ -33,9 +31,6 @@ #define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" -#define CONFIG_SYS_PROMPT "SMDK5250 # " -#define CONFIG_IDENT_STRING " for SMDK5250" - #define CONFIG_IRAM_STACK 0x02050000 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 27e7edc577..b0f940cd16 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -11,8 +11,17 @@ #define CONFIG_EXYNOS5420 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING + #include +#define CONFIG_ARCH_EARLY_INIT_R + #define MACH_TYPE_SMDK5420 8002 #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 @@ -37,6 +46,8 @@ #define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000" +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 + /* * Put the initial stack pointer 1KB below this to allow room for the * SPL marker. This value is arbitrary, but gd_t is placed starting here. @@ -47,4 +58,7 @@ #define CONFIG_NR_DRAM_BANKS 7 #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ +/* Miscellaneous configurable options */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + #endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 046813d1b6..ab8ac60df2 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -9,9 +9,16 @@ #ifndef __CONFIG_PEACH_PIT_H #define __CONFIG_PEACH_PIT_H +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) + #include #include +#define CONFIG_BOARD_COMMON /* select serial console configuration */ #define CONFIG_SERIAL3 /* use SERIAL 3 */ @@ -32,4 +39,7 @@ #define CONFIG_POWER_TPS65090_EC #define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + #endif /* __CONFIG_PEACH_PIT_H */ diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 7673bae446..83953728dd 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -9,7 +9,26 @@ #ifndef __CONFIG_SMDK_H #define __CONFIG_SMDK_H +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING + #include +#define CONFIG_BOARD_COMMON +#define CONFIG_ARCH_EARLY_INIT_R + +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + +#define CONFIG_SYS_PROMPT "SMDK5250 # " +#define CONFIG_IDENT_STRING " for SMDK5250" + +/* Miscellaneous configurable options */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + #endif /* __CONFIG_SMDK_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 894ed115d6..fd2d482e4a 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -11,6 +11,8 @@ #include +#define CONFIG_BOARD_COMMON + #define CONFIG_SMDK5420 /* which is in a SMDK5420 */ @@ -19,5 +21,6 @@ #define CONFIG_SYS_PROMPT "SMDK5420 # " #define CONFIG_IDENT_STRING " for SMDK5420" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" #endif /* __CONFIG_SMDK5420_H */ diff --git a/include/configs/snow.h b/include/configs/snow.h index dc09c66543..7eaa58697e 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -9,6 +9,13 @@ #ifndef __CONFIG_SNOW_H #define __CONFIG_SNOW_H +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING + #include #include @@ -16,4 +23,14 @@ #define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ #define CONFIG_POWER_TPS65090_I2C +#define CONFIG_BOARD_COMMON +#define CONFIG_ARCH_EARLY_INIT_R + +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + +#define CONFIG_SYS_PROMPT "snow # " +#define CONFIG_IDENT_STRING " for snow" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + #endif /* __CONFIG_SNOW_H */ -- cgit v1.2.3 From 1d5511000367e94d5edce7d9c3720bd9097912a7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:49 -0600 Subject: config: Move smdkv310 to use common exynos4 file Most of the smdkv310 features are common with other exynos4 boards. To permit easier addition of driver model support, use the common file and add a device tree file. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/Kconfig | 1 + arch/arm/dts/Makefile | 1 + arch/arm/dts/exynos4210-smdkv310.dts | 21 +++++++++++++ configs/smdkv310_defconfig | 1 + include/configs/smdkv310.h | 61 ++++++------------------------------ 5 files changed, 34 insertions(+), 51 deletions(-) create mode 100644 arch/arm/dts/exynos4210-smdkv310.dts diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index e7c93d8c1f..7a0d182e5f 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -5,6 +5,7 @@ choice config TARGET_SMDKV310 bool "Exynos4210 SMDKV310 board" + select OF_CONTROL if !SPL_BUILD config TARGET_TRATS bool "Exynos4210 Trats board" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5f2b946fdd..43a70e455f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ + exynos4210-smdkv310.dtb \ exynos4210-universal_c210.dtb \ exynos4210-trats.dtb \ exynos4412-trats2.dtb \ diff --git a/arch/arm/dts/exynos4210-smdkv310.dts b/arch/arm/dts/exynos4210-smdkv310.dts new file mode 100644 index 0000000000..c390c8f0c8 --- /dev/null +++ b/arch/arm/dts/exynos4210-smdkv310.dts @@ -0,0 +1,21 @@ +/* + * Samsung's Exynos4210-based SMDKV310 board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos4.dtsi" + +/ { + model = "Samsung SMDKV310 on Exynos4210"; + compatible = "samsung,smdkv310", "samsung,exynos4210"; + + aliases { + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + }; + +}; diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig index 44da2732b6..0d1a24f99f 100644 --- a/configs/smdkv310_defconfig +++ b/configs/smdkv310_defconfig @@ -2,3 +2,4 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_ARCH_EXYNOS=y +S:CONFIG_TARGET_SMDKV310=y +CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310" diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 048c178692..a2469eb60c 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -9,71 +9,42 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include "exynos4-common.h" + +#undef CONFIG_BOARD_COMMON +#undef CONFIG_USB_GADGET +#undef CONFIG_USB_GADGET_S3C_UDC_OTG +#undef CONFIG_CMD_USB_MASS_STORAGE +#undef CONFIG_REVISION_TAG +#undef CONFIG_CMD_THOR_DOWNLOAD +#undef CONFIG_CMD_DFU + /* High Level Configuration Options */ -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5P 1 /* S5P Family */ -#define CONFIG_EXYNOS4 /* EXYNOS4 Family */ #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ #define CONFIG_SMDKV310 1 /* working with SMDKV310*/ -#include /* get chip and board defs */ - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F - /* Mach Type */ #define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310 #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_TEXT_BASE 0x43E00000 -/* input clock of PLL: SMDKV310 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - /* Handling Sleep Mode*/ #define S5P_CHECK_SLEEP 0x00000BAD #define S5P_CHECK_DIDLE 0xBAD00000 #define S5P_CHECK_LPA 0xABAD0000 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) - /* select serial console configuration */ #define CONFIG_SERIAL1 1 /* use SERIAL 1 */ -#define CONFIG_BAUDRATE 115200 #define EXYNOS4_DEFAULT_UART_OFFSET 0x010000 -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI - -/* PWM */ -#define CONFIG_PWM 1 - /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -/* Command definition*/ -#include - #define CONFIG_CMD_PING #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP -#define CONFIG_CMD_MMC #define CONFIG_CMD_NET -#define CONFIG_CMD_FAT - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* MMC SPL */ #define CONFIG_SKIP_LOWLEVEL_INIT @@ -84,15 +55,8 @@ #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" /* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "SMDKV310 # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) @@ -111,8 +75,6 @@ #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE /* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH 1 -#undef CONFIG_CMD_IMLS #define CONFIG_IDENT_STRING " for SMDKC210/V310" #define CONFIG_CLK_1000_400_200 @@ -126,7 +88,6 @@ #define RESERVE_BLOCK_SIZE (512) #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) -#define CONFIG_DOS_PARTITION 1 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) @@ -146,6 +107,4 @@ #define CONFIG_ENV_SROM_BANK 1 #endif /*CONFIG_CMD_NET*/ -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT #endif /* __CONFIG_H */ -- cgit v1.2.3 From 311757be275c1d592ff357e9faedca4c967a3064 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:50 -0600 Subject: samsung: Enable device tree for s5p_goni Change this board to add a device tree. This also adds a pinmux header file although it is not used as yet. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/Kconfig | 9 +++-- arch/arm/cpu/armv7/s5pc1xx/Kconfig | 20 ++++++++++ arch/arm/dts/Makefile | 1 + arch/arm/dts/s5pc1xx-goni.dts | 28 ++++++++++++++ arch/arm/include/asm/arch-s5pc1xx/periph.h | 61 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-s5pc1xx/pinmux.h | 50 ++++++++++++++++++++++++ configs/s5p_goni_defconfig | 2 + drivers/mmc/s5p_sdhci.c | 2 - include/configs/s5p_goni.h | 4 +- 9 files changed, 170 insertions(+), 7 deletions(-) create mode 100644 arch/arm/cpu/armv7/s5pc1xx/Kconfig create mode 100644 arch/arm/dts/s5pc1xx-goni.dts create mode 100644 arch/arm/include/asm/arch-s5pc1xx/periph.h create mode 100644 arch/arm/include/asm/arch-s5pc1xx/pinmux.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 43ba33a2af..22ceb9dbb9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -336,6 +336,9 @@ config TARGET_BCM958622HR config ARCH_EXYNOS bool "Samsung EXYNOS" +config ARCH_S5PC1XX + bool "Samsung S5PC1XX" + config ARCH_HIGHBANK bool "Calxeda Highbank" @@ -429,9 +432,6 @@ config RMOBILE config TARGET_CM_FX6 bool "Support cm_fx6" -config TARGET_S5P_GONI - bool "Support s5p_goni" - config TARGET_SMDKC100 bool "Support smdkc100" @@ -550,6 +550,8 @@ source "arch/arm/cpu/arm926ejs/orion5x/Kconfig" source "arch/arm/cpu/armv7/rmobile/Kconfig" +source "arch/arm/cpu/armv7/s5pc1xx/Kconfig" + source "arch/arm/cpu/armv7/tegra-common/Kconfig" source "arch/arm/cpu/armv7/uniphier/Kconfig" @@ -657,7 +659,6 @@ source "board/raspberrypi/rpi_b/Kconfig" source "board/ronetix/pm9261/Kconfig" source "board/ronetix/pm9263/Kconfig" source "board/ronetix/pm9g45/Kconfig" -source "board/samsung/goni/Kconfig" source "board/samsung/smdk2410/Kconfig" source "board/samsung/smdkc100/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig new file mode 100644 index 0000000000..1a8941dd9a --- /dev/null +++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig @@ -0,0 +1,20 @@ +if ARCH_S5PC1XX + +choice + prompt "S5PC1XX board select" + +config TARGET_S5P_GONI + bool "S5P Goni board" + select OF_CONTROL if !SPL_BUILD + +endchoice + +config SYS_CPU + default "armv7" + +config SYS_SOC + default "s5pc1xx" + +source "board/samsung/goni/Kconfig" + +endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 43a70e455f..076e0f7bf2 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,3 +1,4 @@ +dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-universal_c210.dtb \ diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts new file mode 100644 index 0000000000..2e671bbf7e --- /dev/null +++ b/arch/arm/dts/s5pc1xx-goni.dts @@ -0,0 +1,28 @@ +/* + * Samsung's S5PC110-based Goni board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + model = "Samsung Goni based on S5PC110"; + compatible = "samsung,goni", "samsung,s5pc110"; + + aliases { + serial2 = "/serial@e2900800"; + console = "/serial@e2900800"; + }; + + serial@e2900800 { + compatible = "samsung,exynos4210-uart"; + reg = <0xe2900800 0x400>; + id = <2>; + }; + +}; diff --git a/arch/arm/include/asm/arch-s5pc1xx/periph.h b/arch/arm/include/asm/arch-s5pc1xx/periph.h new file mode 100644 index 0000000000..5c1c3d4a93 --- /dev/null +++ b/arch/arm/include/asm/arch-s5pc1xx/periph.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Rajeshwari Shinde + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals required for pinmux configuration. List will + * grow with support for more devices getting added. + * Numbering based on interrupt table. + * + */ +enum periph_id { + PERIPH_ID_UART0 = 51, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + PERIPH_ID_I2C0 = 56, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, + PERIPH_ID_SPI0 = 68, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SDMMC0 = 75, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC2, + PERIPH_ID_SDMMC3, + PERIPH_ID_I2C8 = 87, + PERIPH_ID_I2C9, + PERIPH_ID_I2S0 = 98, + PERIPH_ID_I2S1 = 99, + + /* Since following peripherals do + * not have shared peripheral interrupts (SPIs) + * they are numbered arbitiraly after the maximum + * SPIs Exynos has (128) + */ + PERIPH_ID_SROMC = 128, + PERIPH_ID_SPI3, + PERIPH_ID_SPI4, + PERIPH_ID_SDMMC4, + PERIPH_ID_PWM0, + PERIPH_ID_PWM1, + PERIPH_ID_PWM2, + PERIPH_ID_PWM3, + PERIPH_ID_PWM4, + PERIPH_ID_I2C10 = 203, + + PERIPH_ID_NONE = -1, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/pinmux.h b/arch/arm/include/asm/arch-s5pc1xx/pinmux.h new file mode 100644 index 0000000000..0b91ef658c --- /dev/null +++ b/arch/arm/include/asm/arch-s5pc1xx/pinmux.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Abhilash Kesavan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_PINMUX_H +#define __ASM_ARM_ARCH_PINMUX_H + +#include "periph.h" + +/* + * Flags for setting specific configarations of peripherals. + * List will grow with support for more devices getting added. + */ +enum { + PINMUX_FLAG_NONE = 0x00000000, + + /* Flags for eMMC */ + PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */ + + /* Flags for SROM controller */ + PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */ + PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */ +}; + +/** + * Configures the pinmux for a particular peripheral. + * + * Each gpio can be configured in many different ways (4 bits on exynos) + * such as "input", "output", "special function", "external interrupt" + * etc. This function will configure the peripheral pinmux along with + * pull-up/down and drive strength. + * + * @param peripheral peripheral to be configured + * @param flags configure flags + * @return 0 if ok, -1 on error (e.g. unsupported peripheral) + */ +int exynos_pinmux_config(int peripheral, int flags); + +/** + * Decode the peripheral id using the interrpt numbers. + * + * @param blob Device tree blob + * @param node FDT I2C node to find + * @return peripheral id if ok, PERIPH_ID_NONE on error + */ +int pinmux_decode_periph_id(const void *blob, int node); +#endif diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig index c0c35090cf..618e590802 100644 --- a/configs/s5p_goni_defconfig +++ b/configs/s5p_goni_defconfig @@ -1,2 +1,4 @@ CONFIG_ARM=y +CONFIG_ARCH_S5PC1XX=y CONFIG_TARGET_S5P_GONI=y +CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni" diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 2ff0ec2a42..637dd972a5 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -14,9 +14,7 @@ #include #include #include -#ifdef CONFIG_OF_CONTROL #include -#endif static char *S5P_NAME = "SAMSUNG SDHCI"; static void s5p_sdhci_set_control_reg(struct sdhci_host *host) diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index a51215d9ae..feb4d7670b 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -53,6 +53,7 @@ #define CONFIG_MMC #define CONFIG_SDHCI #define CONFIG_S5P_SDHCI +#define SDHCI_MAX_HOSTS 4 /* PWM */ #define CONFIG_PWM 1 @@ -106,7 +107,6 @@ ",12m(modem)"\ ",60m(qboot)\0" -#define CONFIG_BOOTDELAY 1 #define CONFIG_ZERO_BOOTDELAY_CHECK /* partitions definitions */ @@ -283,4 +283,6 @@ #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_OF_LIBFDT + #endif /* __CONFIG_H */ -- cgit v1.2.3 From 93327f69769d9fe09ef25efd6ca9182f1095a417 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:51 -0600 Subject: samsung: Enable device tree for smdkc100 Change this board to add a device tree. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/Kconfig | 4 ---- arch/arm/cpu/armv7/s5pc1xx/Kconfig | 5 +++++ arch/arm/dts/Makefile | 1 + arch/arm/dts/s5pc1xx-smdkc100.dts | 29 +++++++++++++++++++++++++++++ configs/smdkc100_defconfig | 2 ++ include/configs/smdkc100.h | 2 ++ 6 files changed, 39 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/s5pc1xx-smdkc100.dts diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 22ceb9dbb9..6c5ecd2b2c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -432,9 +432,6 @@ config RMOBILE config TARGET_CM_FX6 bool "Support cm_fx6" -config TARGET_SMDKC100 - bool "Support smdkc100" - config TARGET_SOCFPGA_CYCLONE5 bool "Support socfpga_cyclone5" @@ -660,7 +657,6 @@ source "board/ronetix/pm9261/Kconfig" source "board/ronetix/pm9263/Kconfig" source "board/ronetix/pm9g45/Kconfig" source "board/samsung/smdk2410/Kconfig" -source "board/samsung/smdkc100/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" source "board/scb9328/Kconfig" source "board/schulercontrol/sc_sps_1/Kconfig" diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig index 1a8941dd9a..2fbbc18203 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/Kconfig +++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig @@ -7,6 +7,10 @@ config TARGET_S5P_GONI bool "S5P Goni board" select OF_CONTROL if !SPL_BUILD +config TARGET_SMDKC100 + bool "Support smdkc100 board" + select OF_CONTROL if !SPL_BUILD + endchoice config SYS_CPU @@ -16,5 +20,6 @@ config SYS_SOC default "s5pc1xx" source "board/samsung/goni/Kconfig" +source "board/samsung/smdkc100/Kconfig" endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 076e0f7bf2..c37580ed84 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,3 +1,4 @@ +dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ diff --git a/arch/arm/dts/s5pc1xx-smdkc100.dts b/arch/arm/dts/s5pc1xx-smdkc100.dts new file mode 100644 index 0000000000..42754ce811 --- /dev/null +++ b/arch/arm/dts/s5pc1xx-smdkc100.dts @@ -0,0 +1,29 @@ +/* + * Samsung's Exynos4210-based SMDKV310 board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + model = "Samsung SMDKC100 based on S5PC100"; + compatible = "samsung,smdkc100", "samsung,s5pc100"; + + aliases { + serial0 = "/serial@ec000000"; + console = "/serial@ec000000"; + }; + + serial@ec000000 { + compatible = "samsung,exynos4210-uart"; + reg = <0xec000000 0x100>; + interrupts = <0 51 0>; + id = <0>; + }; + +}; diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig index 7455235f23..041030f942 100644 --- a/configs/smdkc100_defconfig +++ b/configs/smdkc100_defconfig @@ -1,2 +1,4 @@ CONFIG_ARM=y CONFIG_TARGET_SMDKC100=y +CONFIG_ARCH_S5PC1XX=y +CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100" diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index c9a2e1568f..566028dd25 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -217,4 +217,6 @@ #define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/ #endif /* CONFIG_CMD_NET */ +#define CONFIG_OF_LIBFDT + #endif /* __CONFIG_H */ -- cgit v1.2.3 From 2ecd779742e3eda5b8d1355b56ddc1ea836c8407 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 7 Oct 2014 22:01:52 -0600 Subject: exynos: Enable pre-relocation malloc() Enable this feature to support driver model before relocation. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- include/configs/exynos-common.h | 5 +++-- include/configs/odroid.h | 2 -- include/configs/s5p_goni.h | 5 +++-- include/configs/smdkc100.h | 4 ++++ 4 files changed, 10 insertions(+), 6 deletions(-) diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 54b61d71a5..371f32d840 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -38,8 +38,9 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_ENV_OVERWRITE -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) +/* Size of malloc() pool before and after relocation */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) /* select serial console configuration */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 07a2ff69ca..b928af839e 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -37,8 +37,6 @@ #define CONFIG_SYS_TEXT_BASE 0x43e00000 #include -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) /* select serial console configuration */ #define CONFIG_SERIAL1 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index feb4d7670b..0c6e9c7878 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -39,8 +39,9 @@ #define CONFIG_INITRD_TAG #define CONFIG_CMDLINE_EDITING -/* Size of malloc() pool.*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 80 * SZ_1M) +/* Size of malloc() pool before and after relocation */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) /* * select serial console configuration diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 566028dd25..22835ffd64 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -47,6 +47,10 @@ * 1MB = 0x100000, 0x100000 = 1024 * 1024 */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) + +/* Small malloc pool before relocation */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) + /* * select serial console configuration */ -- cgit v1.2.3 From dab067c32307d7f78ab00ef19690fecbc3ad607a Mon Sep 17 00:00:00 2001 From: Robert Baldyga Date: Fri, 19 Sep 2014 12:17:55 +0200 Subject: armv7: s5pc1xx: improve cache handling Move cache handling code to C file, and add enable_caches() and disable_caches() functions. Signed-off-by: Robert Baldyga Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/s5pc1xx/cache.S | 30 ------------------------ arch/arm/cpu/armv7/s5pc1xx/cache.c | 47 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 30 deletions(-) delete mode 100644 arch/arm/cpu/armv7/s5pc1xx/cache.S create mode 100644 arch/arm/cpu/armv7/s5pc1xx/cache.c diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S deleted file mode 100644 index 3089592eb1..0000000000 --- a/arch/arm/cpu/armv7/s5pc1xx/cache.S +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electronics - * Minkyu Kang - * - * based on arch/arm/cpu/armv7/omap3/cache.S - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -.align 5 - -#include - -#ifndef CONFIG_SYS_L2CACHE_OFF -ENTRY(v7_outer_cache_enable) - push {r0, r1, r2, lr} - mrc 15, 0, r3, cr1, cr0, 1 - orr r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - pop {r1, r2, r3, pc} -ENDPROC(v7_outer_cache_enable) - -ENTRY(v7_outer_cache_disable) - push {r0, r1, r2, lr} - mrc 15, 0, r3, cr1, cr0, 1 - bic r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - pop {r1, r2, r3, pc} -ENDPROC(v7_outer_cache_disable) -#endif diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.c b/arch/arm/cpu/armv7/s5pc1xx/cache.c new file mode 100644 index 0000000000..51af2990c2 --- /dev/null +++ b/arch/arm/cpu/armv7/s5pc1xx/cache.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Minkyu Kang + * Robert Baldyga + * + * based on arch/arm/cpu/armv7/omap3/cache.S + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + dcache_enable(); +} + +void disable_caches(void) +{ + dcache_disable(); +} +#endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +void v7_outer_cache_enable(void) +{ + __asm( + "push {r0, r1, r2, lr}\n\t" + "mrc 15, 0, r3, cr1, cr0, 1\n\t" + "orr r3, r3, #2\n\t" + "mcr 15, 0, r3, cr1, cr0, 1\n\t" + "pop {r1, r2, r3, pc}" + ); +} + +void v7_outer_cache_disable(void) +{ + __asm( + "push {r0, r1, r2, lr}\n\t" + "mrc 15, 0, r3, cr1, cr0, 1\n\t" + "bic r3, r3, #2\n\t" + "mcr 15, 0, r3, cr1, cr0, 1\n\t" + "pop {r1, r2, r3, pc}" + ); +} +#endif -- cgit v1.2.3 From de8f7705aa8f39f2f959299d8d6b290674ab27b3 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 26 Sep 2014 18:54:43 +0900 Subject: exynos: update maintainer of Snow and SMDK5420 board The email address of Rajeshwari Shinde is not working. This commit gives Akshay the maintainership of Snow and SMDK5420 boards. Signed-off-by: Masahiro Yamada Cc: Akshay Saraswat Cc: Minkyu Kang Signed-off-by: Minkyu Kang --- board/samsung/smdk5250/MAINTAINERS | 2 +- board/samsung/smdk5420/MAINTAINERS | 4 ---- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/board/samsung/smdk5250/MAINTAINERS b/board/samsung/smdk5250/MAINTAINERS index 8a2a4aa63c..070593e266 100644 --- a/board/samsung/smdk5250/MAINTAINERS +++ b/board/samsung/smdk5250/MAINTAINERS @@ -6,7 +6,7 @@ F: include/configs/smdk5250.h F: configs/smdk5250_defconfig SNOW BOARD -M: Rajeshwari Shinde +M: Akshay Saraswat S: Maintained F: include/configs/snow.h F: configs/snow_defconfig diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS index c8241a82f5..e0f5c7a530 100644 --- a/board/samsung/smdk5420/MAINTAINERS +++ b/board/samsung/smdk5420/MAINTAINERS @@ -4,9 +4,5 @@ S: Maintained F: board/samsung/smdk5420/ F: include/configs/peach-pit.h F: configs/peach-pit_defconfig - -SMDK5420 BOARD -M: Rajeshwari Shinde -S: Maintained F: include/configs/smdk5420.h F: configs/smdk5420_defconfig -- cgit v1.2.3 From b219773957d2ee8fedb56f0fcb19288eb72d4867 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Tue, 23 Sep 2014 12:46:43 +0200 Subject: odroid: clock: set aclk_cores to 200MHz This change fixes suspend/resume issue in the kernel caused by the wrong 'aclk_cores' clock value expected by the kernel. Signed-off-by: Przemyslaw Marczak Cc: Minkyu Kang Signed-off-by: Minkyu Kang --- board/samsung/odroid/odroid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index ac19527a90..5edb250f06 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -158,10 +158,10 @@ static void board_clock_init(void) * For MOUThpm = 1000 MHz (MOUTapll) * doutcopy = MOUThpm / (ratio + 1) = 200 (4) * sclkhpm = doutcopy / (ratio + 1) = 200 (4) - * cores_out = armclk / (ratio + 1) = 1000 (0) + * cores_out = armclk / (ratio + 1) = 200 (4) */ clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); - set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(0); + set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4); clrsetbits_le32(&clk->div_cpu1, clr, set); -- cgit v1.2.3 From f885b849681ce0f15c2df313f38ae06a601be506 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 30 Sep 2014 18:45:32 +0200 Subject: sunxi: Fix gmac not working reliable on the Bananapi In order for the gmac nic to work reliable on the Bananapi, we need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" of the GMAC clk register (0x01c20164) to 3. Without this about 9 out of 10 ethernet packets get lost, with this setting there is no packet loss. So far setting these bits is only necessary on the Bananapi, so this commit solves this with a bit of #ifdef CONFIG_BANANAPI code. If in the future we need to do something similar for other boards, we can create a specific CONFIG_FOO option for this then. Reported-by: Karsten Merker Signed-off-by: Hans de Goede Tested-by: Karsten Merker Tested-by: Zoltan HERPAI Tested-by: Tony Zhang Acked-by: Ian Campbell --- board/sunxi/gmac.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index e7ff95285c..6348d27282 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -24,6 +24,15 @@ int sunxi_gmac_initialize(bd_t *bis) CCM_GMAC_CTRL_GPIT_MII); #endif + /* + * In order for the gmac nic to work reliable on the Bananapi, we + * need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" + * of the GMAC clk register to 3. + */ +#ifdef CONFIG_BANANAPI + setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10); +#endif + /* Configure pin mux settings for GMAC */ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { #ifdef CONFIG_RGMII -- cgit v1.2.3 From c33e4f11821420018e6d41fda8e554607d54e94f Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 28 Jul 2014 08:11:21 +0900 Subject: arm: rmobile: lager: Fix value of CONFIG_SH_SCIF_CLK_FREQ The clock of SCIF (serial port) of lager is supplied from External Clock. And value of clock is 14.7456MHz. Signed-off-by: Nobuhiro Iwamatsu --- include/configs/lager.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/lager.h b/include/configs/lager.h index 6e9d67d690..6bd1ce8710 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -167,7 +167,7 @@ #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) #define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ #define CONFIG_SYS_TMU_CLK_DIV 4 -- cgit v1.2.3 From c252d64bdd2db80ee6894437c56fc31ceb5d7a7e Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 28 Jul 2014 08:35:05 +0900 Subject: arm: rmobile: lager: Add CONFIG_SCIF_USE_EXT_CLK SCIF of lager use external clock mode. This enables external clock mode on lager board. Signed-off-by: Nobuhiro Iwamatsu --- include/configs/lager.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/lager.h b/include/configs/lager.h index 6bd1ce8710..699135fc0e 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -90,6 +90,7 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF0 +#define CONFIG_SCIF_USE_EXT_CLK #undef CONFIG_SYS_CONSOLE_INFO_QUIET #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE -- cgit v1.2.3 From cc45a610b6027b35444bad283f016491cee14bd2 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 28 Jul 2014 08:35:05 +0900 Subject: arm: rmobile: koelsch: Add CONFIG_SCIF_USE_EXT_CLK SCIF of koelsch use external clock mode. This enables external clock mode on koelsch board. Signed-off-by: Nobuhiro Iwamatsu --- include/configs/koelsch.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 21667d1f78..e015e9091b 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -89,6 +89,7 @@ /* SCIF */ #define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF0 +#define CONFIG_SCIF_USE_EXT_CLK #undef CONFIG_SYS_CONSOLE_INFO_QUIET #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE -- cgit v1.2.3 From 83335bdc0c3249cfe66df36b6826e29ffab6aa7f Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 24 Jul 2014 15:28:04 +0900 Subject: arm: rmobile: koelsch: Update QoS initialization to version 0.334 This update QoS version 0.334 for ES2 of R8A7791. Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/koelsch/qos.c | 41 +++++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/board/renesas/koelsch/qos.c b/board/renesas/koelsch/qos.c index 55a04202c1..ecf3eeddd7 100644 --- a/board/renesas/koelsch/qos.c +++ b/board/renesas/koelsch/qos.c @@ -13,7 +13,7 @@ #include #include -/* QoS version 0.240 for ES1 and version 0.310 for ES2 */ +/* QoS version 0.240 for ES1 and version 0.334 for ES2 */ enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, @@ -116,10 +116,16 @@ void qos_init(void) /* S3C -QoS */ s3c = (struct rcar_s3c *)S3C_BASE; if (IS_R8A7791_ES2()) { - writel(0x00FF1B0D, &s3c->s3cadsplcr); - writel(0x1F0D0B0A, &s3c->s3crorr); - writel(0x1F0D0B09, &s3c->s3cworr); - writel(0x00200808, &s3c->s3carcr11); + /* Linear All mode */ + /* writel(0x00000000, &s3c->s3cadsplcr); */ + /* Linear Linear 0x7000 to 0x7800 mode */ + writel(0x00BF1B0C, &s3c->s3cadsplcr); + /* Split Linear 0x6800 t 0x7000 mode */ + /* writel(0x00DF1B0C, &s3c->s3cadsplcr); */ + /* Ssplit All mode */ + /* writel(0x00FF1B0C, &s3c->s3cadsplcr); */ + writel(0x1F0B0908, &s3c->s3crorr); + writel(0x1F0C0A08, &s3c->s3cworr); } else { writel(0x00FF1B1D, &s3c->s3cadsplcr); writel(0x1F0D0C0C, &s3c->s3crorr); @@ -149,10 +155,7 @@ void qos_init(void) writel(0x00002032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; - if (IS_R8A7791_ES2()) - writel(0x80928092, &s3c_qos->s3cqos0); - else - writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x00820082, &s3c_qos->s3cqos0); writel(0x20960020, &s3c_qos->s3cqos1); writel(0x20302030, &s3c_qos->s3cqos2); writel(0x20AA20DC, &s3c_qos->s3cqos3); @@ -185,7 +188,7 @@ void qos_init(void) writel(0x00000001, &qos_addr->dbrqctr); writel(0x00002078, &qos_addr->dbthres0); writel(0x0000204B, &qos_addr->dbthres1); - writel(0x00001FE7, &qos_addr->dbthres2); + writel(0x0000201E, &qos_addr->dbthres2); writel(0x00000001, &qos_addr->dblgqon); } @@ -193,13 +196,13 @@ void qos_init(void) for (i = DBSC3_00; i < DBSC3_NR; i++) { qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; writel(0x00000002, &qos_addr->dblgcnt); - writel(0x000020EB, &qos_addr->dbtmval0); - writel(0x0000206E, &qos_addr->dbtmval1); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); writel(0x00002050, &qos_addr->dbtmval2); writel(0x0000203A, &qos_addr->dbtmval3); writel(0x00000001, &qos_addr->dbrqctr); writel(0x00002078, &qos_addr->dbthres0); - writel(0x0000205A, &qos_addr->dbthres1); + writel(0x0000204B, &qos_addr->dbthres1); writel(0x0000203C, &qos_addr->dbthres2); writel(0x00000001, &qos_addr->dblgqon); } @@ -215,7 +218,7 @@ void qos_init(void) writel(0x00000001, &qos_addr->dbrqctr); writel(0x00002078, &qos_addr->dbthres0); writel(0x0000204B, &qos_addr->dbthres1); - writel(0x00001FE7, &qos_addr->dbthres2); + writel(0x0000201E, &qos_addr->dbthres2); writel(0x00000001, &qos_addr->dblgqon); } @@ -223,13 +226,13 @@ void qos_init(void) for (i = DBSC3_00; i < DBSC3_NR; i++) { qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_w_qos_addr[i]; writel(0x00000002, &qos_addr->dblgcnt); - writel(0x000020EB, &qos_addr->dbtmval0); - writel(0x0000206E, &qos_addr->dbtmval1); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); writel(0x00002050, &qos_addr->dbtmval2); writel(0x0000203A, &qos_addr->dbtmval3); writel(0x00000001, &qos_addr->dbrqctr); writel(0x00002078, &qos_addr->dbthres0); - writel(0x0000205A, &qos_addr->dbthres1); + writel(0x0000204B, &qos_addr->dbthres1); writel(0x0000203C, &qos_addr->dbthres2); writel(0x00000001, &qos_addr->dblgqon); } @@ -245,14 +248,12 @@ void qos_init(void) mxi = (struct rcar_mxi *)MXI_BASE; writel(0x00000013, &mxi->mxrtcr); writel(0x00000013, &mxi->mxwtcr); - writel(0x00780080, &mxi->mxsaar0); - writel(0x02000800, &mxi->mxsaar1); /* QoS Control (MXI) */ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; writel(0x0000000C, &mxi_qos->vspdu0); writel(0x0000000C, &mxi_qos->vspdu1); - writel(0x0000000D, &mxi_qos->du0); + writel(0x0000000E, &mxi_qos->du0); writel(0x0000000D, &mxi_qos->du1); /* AXI -QoS */ -- cgit v1.2.3 From 4c216f556c4f909799e5608d937ed1c0f93c2bd9 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 24 Jul 2014 15:30:32 +0900 Subject: arm: rmobile: alt: Update QoS initialization to version 0.11 Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/alt/qos.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/renesas/alt/qos.c b/board/renesas/alt/qos.c index ea51f3f532..d788aa0ffb 100644 --- a/board/renesas/alt/qos.c +++ b/board/renesas/alt/qos.c @@ -13,7 +13,7 @@ #include #include -/* QoS version 0.10 */ +/* QoS version 0.11 */ enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, @@ -156,8 +156,8 @@ void qos_init(void) } /* CCI-400 -QoS */ - writel(0x20001000, CCI_400_MAXOT_1); - writel(0x20001000, CCI_400_MAXOT_2); + writel(0x20000800, CCI_400_MAXOT_1); + writel(0x20000800, CCI_400_MAXOT_2); writel(0x0000000C, CCI_400_QOSCNTL_1); writel(0x0000000C, CCI_400_QOSCNTL_2); -- cgit v1.2.3 From 96c434b17d292d44a7163afdcdac0b0e7b446c3a Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 29 Jul 2014 12:13:16 +0900 Subject: arm: rmobile: lager: Update Qos setting to version 0.955 This updates QoS version 0.955 for ES1 of lager board. Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/lager/qos.c | 107 ++++++++++++++++++++++++++-------------------- 1 file changed, 61 insertions(+), 46 deletions(-) diff --git a/board/renesas/lager/qos.c b/board/renesas/lager/qos.c index 374275747d..930fe8d99b 100644 --- a/board/renesas/lager/qos.c +++ b/board/renesas/lager/qos.c @@ -12,55 +12,55 @@ #include #include -/* QoS version 0.955 */ +/* QoS version 0.955 for ES1 enum { - DBSC3_R00, DBSC3_R01, DBSC3_R02, DBSC3_R03, DBSC3_R04, - DBSC3_R05, DBSC3_R06, DBSC3_R07, DBSC3_R08, DBSC3_R09, - DBSC3_R10, DBSC3_R11, DBSC3_R12, DBSC3_R13, DBSC3_R14, - DBSC3_R15, - DBSC3_W00, DBSC3_W01, DBSC3_W02, DBSC3_W03, DBSC3_W04, - DBSC3_W05, DBSC3_W06, DBSC3_W07, DBSC3_W08, DBSC3_W09, - DBSC3_W10, DBSC3_W11, DBSC3_W12, DBSC3_W13, DBSC3_W14, - DBSC3_W15, + DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, + DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, + DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, + DBSC3_15, DBSC3_NR, }; -static const u32 dbsc3_qos_addr[DBSC3_NR] = { - [DBSC3_R00] = DBSC3_0_QOS_R0_BASE, - [DBSC3_R01] = DBSC3_0_QOS_R1_BASE, - [DBSC3_R02] = DBSC3_0_QOS_R2_BASE, - [DBSC3_R03] = DBSC3_0_QOS_R3_BASE, - [DBSC3_R04] = DBSC3_0_QOS_R4_BASE, - [DBSC3_R05] = DBSC3_0_QOS_R5_BASE, - [DBSC3_R06] = DBSC3_0_QOS_R6_BASE, - [DBSC3_R07] = DBSC3_0_QOS_R7_BASE, - [DBSC3_R08] = DBSC3_0_QOS_R8_BASE, - [DBSC3_R09] = DBSC3_0_QOS_R9_BASE, - [DBSC3_R10] = DBSC3_0_QOS_R10_BASE, - [DBSC3_R11] = DBSC3_0_QOS_R11_BASE, - [DBSC3_R12] = DBSC3_0_QOS_R12_BASE, - [DBSC3_R13] = DBSC3_0_QOS_R13_BASE, - [DBSC3_R14] = DBSC3_0_QOS_R14_BASE, - [DBSC3_R15] = DBSC3_0_QOS_R15_BASE, - [DBSC3_W00] = DBSC3_0_QOS_W0_BASE, - [DBSC3_W01] = DBSC3_0_QOS_W1_BASE, - [DBSC3_W02] = DBSC3_0_QOS_W2_BASE, - [DBSC3_W03] = DBSC3_0_QOS_W3_BASE, - [DBSC3_W04] = DBSC3_0_QOS_W4_BASE, - [DBSC3_W05] = DBSC3_0_QOS_W5_BASE, - [DBSC3_W06] = DBSC3_0_QOS_W6_BASE, - [DBSC3_W07] = DBSC3_0_QOS_W7_BASE, - [DBSC3_W08] = DBSC3_0_QOS_W8_BASE, - [DBSC3_W09] = DBSC3_0_QOS_W9_BASE, - [DBSC3_W10] = DBSC3_0_QOS_W10_BASE, - [DBSC3_W11] = DBSC3_0_QOS_W11_BASE, - [DBSC3_W12] = DBSC3_0_QOS_W12_BASE, - [DBSC3_W13] = DBSC3_0_QOS_W13_BASE, - [DBSC3_W14] = DBSC3_0_QOS_W14_BASE, - [DBSC3_W15] = DBSC3_0_QOS_W15_BASE, +static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_R0_BASE, + [DBSC3_01] = DBSC3_0_QOS_R1_BASE, + [DBSC3_02] = DBSC3_0_QOS_R2_BASE, + [DBSC3_03] = DBSC3_0_QOS_R3_BASE, + [DBSC3_04] = DBSC3_0_QOS_R4_BASE, + [DBSC3_05] = DBSC3_0_QOS_R5_BASE, + [DBSC3_06] = DBSC3_0_QOS_R6_BASE, + [DBSC3_07] = DBSC3_0_QOS_R7_BASE, + [DBSC3_08] = DBSC3_0_QOS_R8_BASE, + [DBSC3_09] = DBSC3_0_QOS_R9_BASE, + [DBSC3_10] = DBSC3_0_QOS_R10_BASE, + [DBSC3_11] = DBSC3_0_QOS_R11_BASE, + [DBSC3_12] = DBSC3_0_QOS_R12_BASE, + [DBSC3_13] = DBSC3_0_QOS_R13_BASE, + [DBSC3_14] = DBSC3_0_QOS_R14_BASE, + [DBSC3_15] = DBSC3_0_QOS_R15_BASE, }; +static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_W0_BASE, + [DBSC3_01] = DBSC3_0_QOS_W1_BASE, + [DBSC3_02] = DBSC3_0_QOS_W2_BASE, + [DBSC3_03] = DBSC3_0_QOS_W3_BASE, + [DBSC3_04] = DBSC3_0_QOS_W4_BASE, + [DBSC3_05] = DBSC3_0_QOS_W5_BASE, + [DBSC3_06] = DBSC3_0_QOS_W6_BASE, + [DBSC3_07] = DBSC3_0_QOS_W7_BASE, + [DBSC3_08] = DBSC3_0_QOS_W8_BASE, + [DBSC3_09] = DBSC3_0_QOS_W9_BASE, + [DBSC3_10] = DBSC3_0_QOS_W10_BASE, + [DBSC3_11] = DBSC3_0_QOS_W11_BASE, + [DBSC3_12] = DBSC3_0_QOS_W12_BASE, + [DBSC3_13] = DBSC3_0_QOS_W13_BASE, + [DBSC3_14] = DBSC3_0_QOS_W14_BASE, + [DBSC3_15] = DBSC3_0_QOS_W15_BASE, +}; + +/* QoS version 0.955 for ES1 */ void qos_init(void) { int i; @@ -115,7 +115,6 @@ void qos_init(void) writel(0x20142032, &s3c_qos->s3cqos8); s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; - writel(0x00810089, &s3c_qos->s3cqos0); writel(0x20410001, &s3c_qos->s3cqos1); writel(0x200A2023, &s3c_qos->s3cqos2); @@ -129,9 +128,24 @@ void qos_init(void) writel(0x00200808, &s3c->s3carcr11); /* DBSC -QoS */ - /* DBSC0 - Read/Write */ - for (i = DBSC3_R00; i < DBSC3_NR; i++) { - qos_addr = (struct rcar_dbsc3_qos *)dbsc3_qos_addr[i]; + /* DBSC0 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; + writel(0x00000203, &qos_addr->dblgcnt); + writel(0x00002064, &qos_addr->dbtmval0); + writel(0x00002048, &qos_addr->dbtmval1); + writel(0x00002032, &qos_addr->dbtmval2); + writel(0x00002019, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002019, &qos_addr->dbthres0); + writel(0x00002019, &qos_addr->dbthres1); + writel(0x00002019, &qos_addr->dbthres2); + writel(0x00000000, &qos_addr->dblgqon); + } + + /* DBSC0 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; writel(0x00000203, &qos_addr->dblgcnt); writel(0x00002064, &qos_addr->dbtmval0); writel(0x00002048, &qos_addr->dbtmval1); @@ -143,6 +157,7 @@ void qos_init(void) writel(0x00002019, &qos_addr->dbthres2); writel(0x00000000, &qos_addr->dblgqon); } + /* CCI-400 -QoS */ writel(0x20001000, CCI_400_MAXOT_1); writel(0x20001000, CCI_400_MAXOT_2); -- cgit v1.2.3 From 9f1c3beada5a3b70318def14b6b04355d41baa82 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 29 Jul 2014 12:14:05 +0900 Subject: arm: rmobile: lager: Add Qos setting for ES2 This adds support version 0.963 for ES2 of lager board. Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/lager/qos.c | 1253 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 1251 insertions(+), 2 deletions(-) diff --git a/board/renesas/lager/qos.c b/board/renesas/lager/qos.c index 930fe8d99b..ce7f8ba10c 100644 --- a/board/renesas/lager/qos.c +++ b/board/renesas/lager/qos.c @@ -12,7 +12,7 @@ #include #include -/* QoS version 0.955 for ES1 +/* QoS version 0.955 for ES1 and version 0.963 for ES2 */ enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, @@ -61,7 +61,7 @@ static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { }; /* QoS version 0.955 for ES1 */ -void qos_init(void) +static void qos_init_es1(void) { int i; struct rcar_s3c *s3c; @@ -1132,3 +1132,1252 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000000, &axi_qos->qosqon); } + +/* QoS version 0.963 for ES2 */ +static void qos_init_es2(void) +{ + int i; + struct rcar_s3c *s3c; + struct rcar_s3c_qos *s3c_qos; + struct rcar_dbsc3_qos *qos_addr; + struct rcar_mxi *mxi; + struct rcar_mxi_qos *mxi_qos; + struct rcar_axi_qos *axi_qos; + + /* DBSC DBADJ2 */ + writel(0x20042004, DBSC3_0_DBADJ2); + + /* S3C -QoS */ + s3c = (struct rcar_s3c *)S3C_BASE; + writel(0x80000000, &s3c->s3cadsplcr); + writel(0x1F060504, &s3c->s3crorr); + writel(0x1F060503, &s3c->s3cworr); + + /* QoS Control Registers */ + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; + writel(0x80928092, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20DC, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20DC, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20FA, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20FA, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + writel(0x00200808, &s3c->s3carcr11); + + /* DBSC -QoS */ + /* DBSC0 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002032, &qos_addr->dbtmval2); + writel(0x00001FB0, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000201E, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC0 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002050, &qos_addr->dbtmval2); + writel(0x0000203A, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000203C, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* MXI -QoS */ + /* Transaction Control (MXI) */ + mxi = (struct rcar_mxi *)MXI_BASE; + writel(0x00000013, &mxi->mxrtcr); + writel(0x00000013, &mxi->mxwtcr); + writel(0x00B800C0, &mxi->mxsaar0); + writel(0x02000800, &mxi->mxsaar1); + + /* QoS Control (MXI) */ + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; + writel(0x0000000C, &mxi_qos->vspdu0); + writel(0x0000000C, &mxi_qos->vspdu1); + writel(0x0000000E, &mxi_qos->du0); + writel(0x0000000E, &mxi_qos->du1); + + /* AXI -QoS */ + /* Transaction Control (MXI) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (RT-AXI) */ + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002299, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (MP-AXI) */ + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000206E, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (SYS-AXI256) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (CCI-AXI) */ + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (Media-AXI) */ + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020dc, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020dc, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002004, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); +} + +void qos_init(void) +{ + if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) + qos_init_es2(); + else + qos_init_es1(); +} -- cgit v1.2.3 From f212a8abf3dc3715b95ce3c187c7402ee40788e6 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Wed, 30 Jul 2014 12:28:00 +0900 Subject: arm: rmobile: lager: Fix CPU frequency setting Setting to change the CPU frequency is only used version2. Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/lager/lager.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index a5a0474cd7..5302839b33 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -29,15 +29,17 @@ void s_init(void) { struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; - u32 stc; /* Watchdog init */ writel(0xA5A5A500, &rwdt->rwtcsra); writel(0xA5A5A500, &swdt->swtcsra); /* CPU frequency setting. Set to 1.4GHz */ - stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; - clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); + if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { + u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) + << PLL0_STC_BIT; + clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); + } /* QoS(Quality-of-Service) Init */ qos_init(); -- cgit v1.2.3 From 7d835803640e743a60572b49a736370c75f9cb44 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 7 Aug 2014 09:10:45 +0900 Subject: arm: rmobile: Remove unnecessary initialization for l2ctlr This removes duplicate initialization of l2ctlr. Signed-off-by: Nobuhiro Iwamatsu --- arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S index 287f8d74af..dbb96ed194 100644 --- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S @@ -42,11 +42,6 @@ do_lowlevel_init: mcreq p15, 0, r0, c1, c0, 1 /* and set l2 latency */ - mrceq p15, 1, r0, c9, c0, 2 /* l2ctlr */ - orreq r0, r0, #0x00000800 - orreq r0, r0, #0x00000003 - mcreq p15, 1, r0, c9, c0, 2 - mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */ and r0, r0, #0xf00 lsr r0, r0, #8 -- cgit v1.2.3 From 237faf095fb43abbed6e40266ef7efccc8b9308b Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 8 Aug 2014 08:41:15 +0900 Subject: arm: rmobile: r8a7791: Fix initialize L2 cache rmobile/lowlevel_init_ca15.S are common in r8a7790 and r8a7791 of rmobile SoC. But L2 cache of r8a7791 does not use L2CTLR[5]. This adds fix to set L2CTLR [5] only when the r8a7790. Signed-off-by: Nobuhiro Iwamatsu --- arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S index dbb96ed194..5820e1a37a 100644 --- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S @@ -53,7 +53,15 @@ do_lowlevel_init: cmp r1, #3 /* has already been set up */ bicne r0, r0, #0xe7 orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */ - orrne r0, r0, #0x20 /* L2CTLR[5] */ + + ldr r2, =0xFF000044 /* PRR */ + ldr r1, [r2] + and r1, r1, #0x7F00 + lsrs r1, r1, #8 + cmp r1, #0x45 /* 0x45 is ID of r8a7790 */ + bne L2CTLR_5_SKIP + orrne r0, r0, #0x20 /* L2CTLR[5] */ +L2CTLR_5_SKIP: mcrne p15, 1, r0, c9, c0, 2 _exit_init_l2_a15: -- cgit v1.2.3 From 88982893c4d50692b80a2155146cda9e42266c6b Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 8 Aug 2014 08:44:02 +0900 Subject: arm: rmobile: r8a7794: Skip initialize L2 cache rmobile/lowlevel_init_ca15.S are common in r8a7790, r8a7791 and r8a7794 of rmobile SoCs. The initialize L2 cache in lowlevel_init_ca15.S only needed for Cortex-A15. The r8a7794 is Cortex-A7, not Cortex-A15. This adds Skip to initialize L2 cache when r8a7794. Signed-off-by: Nobuhiro Iwamatsu --- arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S index 5820e1a37a..879e0e097f 100644 --- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S @@ -35,6 +35,13 @@ do_cpu_waiting: */ .align 4 do_lowlevel_init: + ldr r2, =0xFF000044 /* PRR */ + ldr r1, [r2] + and r1, r1, #0x7F00 + lsrs r1, r1, #8 + cmp r1, #0x4C /* 0x4C is ID of r8a7794 */ + beq _exit_init_l2_a15 + /* surpress wfe if ca15 */ tst r4, #4 mrceq p15, 0, r0, c1, c0, 1 /* actlr */ -- cgit v1.2.3 From 7d2f669b94aa42579b5d5775dfb076bce0102e3f Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 17 Sep 2014 15:59:25 +0300 Subject: compulab: eeprom: add default eeprom bus Add default eeprom bus setting. This addresses the trimslice compile error that was introduced with the addition of this setting. Cc: Albert ARIBAUD Cc: Igor Grinberg Signed-off-by: Nikita Kiryanov Acked-by: Igor Grinberg --- board/compulab/common/eeprom.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index 85442cd103..2df3adabf8 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -15,6 +15,10 @@ # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #endif +#ifndef CONFIG_SYS_I2C_EEPROM_BUS +#define CONFIG_SYS_I2C_EEPROM_BUS 0 +#endif + #define EEPROM_LAYOUT_VER_OFFSET 44 #define BOARD_SERIAL_OFFSET 20 #define BOARD_SERIAL_OFFSET_LEGACY 8 -- cgit v1.2.3 From 05968e7cfd5dcc50cfe51d03d119a5e9d77bd07c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 3 Oct 2014 20:03:03 +0900 Subject: mtd: denali: fix NAND_CMD_PARAM command NAND_CMD_PARAM (0xEC) command is not working on the Denali NAND controller driver. Unlike NAND_CMD_READID (0x90), when the NAND_CMD_PARAM command is followed by an address cycle, the target device goes busy. (R/B# is deasserted) Wait until the parameter data are ready. In addition, unnecessary clear_interrupts() should be removed. Signed-off-by: Masahiro Yamada Acked-by: Chin Liang See --- drivers/mtd/nand/denali.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index ba3de1a635..d9abc7e1d6 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1059,9 +1059,8 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, addr = MODE_11 | BANK(denali->flash_bank); index_addr(denali, addr | 0, cmd); break; - case NAND_CMD_PARAM: - clear_interrupts(denali); case NAND_CMD_READID: + case NAND_CMD_PARAM: reset_buf(denali); /* sometimes ManufactureId read from register is not right * e.g. some of Micron MT29F32G08QAA MLC NAND chips @@ -1070,6 +1069,8 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, addr = MODE_11 | BANK(denali->flash_bank); index_addr(denali, addr | 0, cmd); index_addr(denali, addr | 1, col & 0xFF); + if (cmd == NAND_CMD_PARAM) + udelay(50); break; case NAND_CMD_READ0: case NAND_CMD_SEQIN: -- cgit v1.2.3 From ed3c980bee74dc1bd599dd44b41b2c32ee78c0a8 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 3 Oct 2014 20:03:04 +0900 Subject: mtd: denali: support NAND_CMD_RNDOUT command The function nand_flash_detect_ext_param_page() requires NAND_CMD_RNDOUT command supported. It is necessary to detect some types of ONFi-compliant devices. Without it, the error message "unsupported command received 0x5" is shown. Let's support this command on the Denali NAND controller driver. Signed-off-by: Masahiro Yamada Acked-by: Chin Liang See --- drivers/mtd/nand/denali.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index d9abc7e1d6..308b7845f1 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1072,6 +1072,13 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, if (cmd == NAND_CMD_PARAM) udelay(50); break; + case NAND_CMD_RNDOUT: + addr = MODE_11 | BANK(denali->flash_bank); + index_addr(denali, addr | 0, cmd); + index_addr(denali, addr | 1, col & 0xFF); + index_addr(denali, addr | 1, col >> 8); + index_addr(denali, addr | 0, NAND_CMD_RNDOUTSTART); + break; case NAND_CMD_READ0: case NAND_CMD_SEQIN: denali->page = page; -- cgit v1.2.3 From 64a0c24726530696bf0c2cdaa75d171d957a7ee0 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Fri, 3 Oct 2014 14:29:01 +0100 Subject: pxe: Ensure we don't overflow bootargs On a couple of platforms I've tripped over long PXE append lines overflowing this array, due to having CONFIG_SYS_CBSIZE == 256. When doing preseeded Debian installs it's pretty trivial to exceed that. Since the symptom can be a silent hang or a crash add a check. Of course the affected boards would also need an increased CBSIZE to actually work. Note that due to the printing of the final bootargs string CONFIG_SYS_PBSIZE also needs to be sufficiently large. Signed-off-by: Ian Campbell [trini: Use %zd not %d in printf for all args] Signed-off-by: Tom Rini --- common/cmd_pxe.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c index 0ab1e0aaa6..7e32c95df3 100644 --- a/common/cmd_pxe.c +++ b/common/cmd_pxe.c @@ -674,6 +674,15 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label) char bootargs[CONFIG_SYS_CBSIZE] = ""; char finalbootargs[CONFIG_SYS_CBSIZE]; + if (strlen(label->append ?: "") + + strlen(ip_str) + strlen(mac_str) + 1 > sizeof(bootargs)) { + printf("bootarg overflow %zd+%zd+%zd+1 > %zd\n", + strlen(label->append ?: ""), + strlen(ip_str), strlen(mac_str), + sizeof(bootargs)); + return 1; + } + if (label->append) strcpy(bootargs, label->append); strcat(bootargs, ip_str); -- cgit v1.2.3 From fef3e25fc3f59da6410878614e8717020a7d7f74 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 2 Oct 2014 15:20:10 -0700 Subject: common/board_r: Fix booting issue on T4240QDS Commit 294b91a5817147d4b7f47be2ac69bac2a1f26491 moved initr_malloc earlier than initr_unlock_ram_in_cache. This causes issue on T4240. It may be related to locked L1 d-cache and unlocked L2 cache. D- cache could and should be unlock earlier for normal operation. This patch moves initr_unlock_ram_in_cache before initr_malloc. It has been verified on the following boards, in which only T4240QDS suffered and has been since fixed: T4240QDS, T2080QDS, P5040DS, P4080DS, MPC8572DS, MPC8536DS, MPC8641HPCN, B4860QDS. Signed-off-by: York Sun CC: Scott Wood CC: Simon Glass Acked-by: Simon Glass --- common/board_r.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/board_r.c b/common/board_r.c index 231c6d6711..c339aad7f5 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -717,6 +717,9 @@ init_fnc_t init_sequence_r[] = { initr_caches, #endif initr_reloc_global_data, +#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) + initr_unlock_ram_in_cache, +#endif initr_barrier, initr_malloc, bootstage_relocate, @@ -759,9 +762,6 @@ init_fnc_t init_sequence_r[] = { #ifdef CONFIG_SYS_DELAYED_ICACHE initr_icache_enable, #endif -#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) - initr_unlock_ram_in_cache, -#endif #if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT) /* * Do early PCI configuration _before_ the flash gets initialised, -- cgit v1.2.3 From 115e71f7da1f6fd96c20793842f5751897d9fdee Mon Sep 17 00:00:00 2001 From: Stefan Herbrechtsmeier Date: Tue, 16 Sep 2014 17:51:05 +0200 Subject: omap3: overo: Fix fdtfile test Commit 12cc54376768461533b55ada1b0b6d4979f40579 'omap3: overo: Select fdtfile for expansion board' wrongly missed the operator in the fdtfile test. Update the test to only overwrite an empty fdtfile environment variable. Signed-off-by: Stefan Herbrechtsmeier --- include/configs/omap3_overo.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index e66f30655d..b17e495f5f 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -151,7 +151,7 @@ "run mmcboot;" \ "fi;" \ "if run loadzimage; then " \ - "if test $fdtfile; then " \ + "if test -z \"${fdtfile}\"; then " \ "setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \ "fi;" \ "if run loadfdt; then " \ -- cgit v1.2.3 From 02590aa31cc282cffafac559032981094f716fa9 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 23 Sep 2014 18:07:01 +0300 Subject: ahci: Don't start command DMA engine before buffers are set The DMA/FIS buffers are set in ahci_port_start() which is called after ahci_host_init(). So don't start the DMA engine here (i.e. don't set FIS_RX) This fixes the following error at kernel boot on OMAP platforms (e.g. DRA7x) WARNING: CPU: 0 PID: 0 at drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x260/0x358() 44000000.ocp:L3 Custom Error: MASTER SATA TARGET GPMC (Idle): Data Access in User mode during Functional access Signed-off-by: Roger Quadros --- drivers/block/ahci.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index dce99adc6b..a93a8e1c04 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -229,7 +229,6 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) * already be on in the command register. */ cmd = readl(port_mmio + PORT_CMD); - cmd |= PORT_CMD_FIS_RX; cmd |= PORT_CMD_SPIN_UP; writel_with_flush(cmd, port_mmio + PORT_CMD); -- cgit v1.2.3 From 3160b1b98603cba3c480f70e153b259171d3e4a6 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 23 Sep 2014 18:07:02 +0300 Subject: OMAP5+: sata/scsi: Implement scsi_init() On OMAP platforms, SATA controller provides the SCSI subsystem so implement scsi_init(). Get rid of the unnecessary sata_init() call from dra7xx-evm and omap5-uevm board files. Signed-off-by: Roger Quadros --- arch/arm/cpu/armv7/omap-common/sata.c | 6 ++++++ board/ti/dra7xx/evm.c | 1 - board/ti/omap5_uevm/evm.c | 6 ------ include/configs/omap5_uevm.h | 1 - 4 files changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c index cad4feed00..131d082bc8 100644 --- a/arch/arm/cpu/armv7/omap-common/sata.c +++ b/arch/arm/cpu/armv7/omap-common/sata.c @@ -74,3 +74,9 @@ int init_sata(int dev) return ret; } + +/* On OMAP platforms SATA provides the SCSI subsystem */ +void scsi_init(void) +{ + init_sata(0); +} diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 5592fc5def..37df7b2cad 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -93,7 +93,6 @@ int board_late_init(void) else setenv("board_name", "dra7xx"); #endif - init_sata(0); return 0; } diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index 4666b38a71..833ffe9943 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -69,12 +69,6 @@ int board_init(void) return 0; } -int board_late_init(void) -{ - init_sata(0); - return 0; -} - int board_eth_init(bd_t *bis) { return 0; diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 7e2ecd53f5..e8dc462f14 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -72,7 +72,6 @@ /* Max time to hold reset on this board, see doc/README.omap-reset-time */ #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 -#define CONFIG_BOARD_LATE_INIT #define CONFIG_CMD_SCSI #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI -- cgit v1.2.3 From d59baeb76f911d0391e73e5f6068e55ea48514f8 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 23 Sep 2014 18:07:03 +0300 Subject: ARM: OMAP5+: sata: Move scsi_scan() to the right place scsi_scan() must be called as part of scsi_init() and not as part of sata_init(). Signed-off-by: Roger Quadros --- arch/arm/cpu/armv7/omap-common/sata.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c index 131d082bc8..3b4dd3f5d7 100644 --- a/arch/arm/cpu/armv7/omap-common/sata.c +++ b/arch/arm/cpu/armv7/omap-common/sata.c @@ -70,7 +70,6 @@ int init_sata(int dev) writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG); ret = ahci_init(DWC_AHSATA_BASE); - scsi_scan(1); return ret; } @@ -79,4 +78,5 @@ int init_sata(int dev) void scsi_init(void) { init_sata(0); + scsi_scan(1); } -- cgit v1.2.3 From 76300c0d2d63bb7cb02679bf749f30ae4a1ca969 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 23 Sep 2014 18:07:04 +0300 Subject: common: spl_sata: perform SCSI scan before getting device At least on OMAP, init_sata() no longer performs scsi_scan() so we must do it explicitly here. Cc: Dan Murphy Signed-off-by: Roger Quadros --- common/spl/spl_sata.c | 1 + 1 file changed, 1 insertion(+) diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c index 2e7adca0ca..12e16d9603 100644 --- a/common/spl/spl_sata.c +++ b/common/spl/spl_sata.c @@ -32,6 +32,7 @@ void spl_sata_load_image(void) hang(); } else { /* try to recognize storage devices immediately */ + scsi_scan(0); stor_dev = scsi_get_dev(0); } -- cgit v1.2.3 From 026330af41842e7752a291012428a5ddf2c06449 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Tue, 23 Sep 2014 21:10:26 +0300 Subject: ARM: keystone: clock: fix main pll ratio div definitions The definitions for div ratio supposed to be in hex and were added in dec by mistake. Signed-off-by: Ivan Khoronzhuk --- arch/arm/include/asm/arch-keystone/clock_defs.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/arch-keystone/clock_defs.h b/arch/arm/include/asm/arch-keystone/clock_defs.h index e545341ca7..85a046b89a 100644 --- a/arch/arm/include/asm/arch-keystone/clock_defs.h +++ b/arch/arm/include/asm/arch-keystone/clock_defs.h @@ -102,10 +102,10 @@ static struct pllctl_regs *pllctl_regs[] = { #define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT) #define PLL_BWADJ_HI_MASK 0xf -#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0) -#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0) -#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 1) -#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 4) -#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 17) +#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0x0) +#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0x0) +#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 0x1) +#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 0x4) +#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 0x17) #endif /* _CLOCK_DEFS_H_ */ -- cgit v1.2.3 From 717a23b871d1563bc3a063ebceccf13a2ca2d10b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 26 Sep 2014 18:42:36 +0900 Subject: kconfig: fix another bug of "make savedefconfig" In some cases, the last lines of SPL or TPL are not output to a file. The entries remaining in the "unmatched" variable must be flushed. Signed-off-by: Masahiro Yamada Acked-by: Simon Glass --- scripts/multiconfig.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh index 4a8737f352..b5185a84cf 100644 --- a/scripts/multiconfig.sh +++ b/scripts/multiconfig.sh @@ -229,6 +229,8 @@ do_savedefconfig () { unmatched="$unmatched%$symbol:$line" fi done < defconfig + + output_lines="$output_lines%$unmatched" done rm -f defconfig -- cgit v1.2.3 From dc9617e0cee28808863cbb21f4528f89bc383923 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:37:57 +0900 Subject: powerpc: ppc4xx: remove board support for KAREF and METROBOX These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/ppc4xx/Kconfig | 8 - board/sandburst/common/flash.c | 493 ---------------- board/sandburst/common/sb_common.c | 349 ------------ board/sandburst/common/sb_common.h | 60 -- board/sandburst/karef/Kconfig | 12 - board/sandburst/karef/MAINTAINERS | 6 - board/sandburst/karef/Makefile | 16 - board/sandburst/karef/config.mk | 21 - board/sandburst/karef/hal_ka_of_auto.h | 324 ----------- board/sandburst/karef/hal_ka_sc_auto.h | 836 ---------------------------- board/sandburst/karef/init.S | 39 -- board/sandburst/karef/karef.c | 595 -------------------- board/sandburst/karef/karef.h | 60 -- board/sandburst/karef/karef_version.h | 10 - board/sandburst/karef/u-boot.lds.debug | 130 ----- board/sandburst/metrobox/Kconfig | 12 - board/sandburst/metrobox/MAINTAINERS | 6 - board/sandburst/metrobox/Makefile | 15 - board/sandburst/metrobox/config.mk | 16 - board/sandburst/metrobox/hal_xc_auto.h | 553 ------------------ board/sandburst/metrobox/init.S | 37 -- board/sandburst/metrobox/metrobox.c | 561 ------------------- board/sandburst/metrobox/metrobox.h | 29 - board/sandburst/metrobox/metrobox_version.h | 11 - board/sandburst/metrobox/u-boot.lds.debug | 130 ----- configs/KAREF_defconfig | 3 - configs/METROBOX_defconfig | 3 - doc/README.scrapyard | 2 + include/configs/KAREF.h | 284 ---------- include/configs/METROBOX.h | 349 ------------ 30 files changed, 2 insertions(+), 4968 deletions(-) delete mode 100644 board/sandburst/common/flash.c delete mode 100644 board/sandburst/common/sb_common.c delete mode 100644 board/sandburst/common/sb_common.h delete mode 100644 board/sandburst/karef/Kconfig delete mode 100644 board/sandburst/karef/MAINTAINERS delete mode 100644 board/sandburst/karef/Makefile delete mode 100644 board/sandburst/karef/config.mk delete mode 100644 board/sandburst/karef/hal_ka_of_auto.h delete mode 100644 board/sandburst/karef/hal_ka_sc_auto.h delete mode 100644 board/sandburst/karef/init.S delete mode 100644 board/sandburst/karef/karef.c delete mode 100644 board/sandburst/karef/karef.h delete mode 100644 board/sandburst/karef/karef_version.h delete mode 100644 board/sandburst/karef/u-boot.lds.debug delete mode 100644 board/sandburst/metrobox/Kconfig delete mode 100644 board/sandburst/metrobox/MAINTAINERS delete mode 100644 board/sandburst/metrobox/Makefile delete mode 100644 board/sandburst/metrobox/config.mk delete mode 100644 board/sandburst/metrobox/hal_xc_auto.h delete mode 100644 board/sandburst/metrobox/init.S delete mode 100644 board/sandburst/metrobox/metrobox.c delete mode 100644 board/sandburst/metrobox/metrobox.h delete mode 100644 board/sandburst/metrobox/metrobox_version.h delete mode 100644 board/sandburst/metrobox/u-boot.lds.debug delete mode 100644 configs/KAREF_defconfig delete mode 100644 configs/METROBOX_defconfig delete mode 100644 include/configs/KAREF.h delete mode 100644 include/configs/METROBOX.h diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 41b525c16d..7c645f1cdb 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -226,12 +226,6 @@ config TARGET_ALPR config TARGET_P3P440 bool "Support p3p440" -config TARGET_KAREF - bool "Support KAREF" - -config TARGET_METROBOX - bool "Support METROBOX" - config TARGET_XPEDITE1000 bool "Support xpedite1000" @@ -306,8 +300,6 @@ source "board/mpl/pip405/Kconfig" source "board/pcs440ep/Kconfig" source "board/prodrive/alpr/Kconfig" source "board/prodrive/p3p440/Kconfig" -source "board/sandburst/karef/Kconfig" -source "board/sandburst/metrobox/Kconfig" source "board/sbc405/Kconfig" source "board/sc3/Kconfig" source "board/t3corp/Kconfig" diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c deleted file mode 100644 index ad046bed69..0000000000 --- a/board/sandburst/common/flash.c +++ /dev/null @@ -1,493 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * Ported from Ebony flash support - * Travis B. Sawyer - * Sandburst Corporation - */ -#include -#include -#include - - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { - {0xfff80000} /* Boot Flash */ -}; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i=0; iflash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); - return; - } - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr ); - - /* Write auto select command: read Manufacturer ID */ - udelay(10000); - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - udelay(1000); - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - udelay(1000); - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - udelay(1000); - - value = addr2[0]; - - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; /* => 512 kb */ - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (info->flash_id == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* reset to return to reading data */ - addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7(flash_info_t *info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - DEBUGF("Erasing sector %p\n", addr2); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - for (i=0; i<50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c deleted file mode 100644 index c23ef50547..0000000000 --- a/board/sandburst/common/sb_common.c +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Copyright (C) 2005 Sandburst Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include -#include "sb_common.h" - -DECLARE_GLOBAL_DATA_PTR; - -long int fixed_sdram (void); - -/************************************************************************* - * metrobox_get_master - * - * PRI_N - active low signal. If the GPIO pin is low we are the master - * - ************************************************************************/ -int sbcommon_get_master(void) -{ - ppc440_gpio_regs_t *gpio_regs; - - gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; - - if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) { - return 0; - } - else { - return 1; - } -} - -/************************************************************************* - * metrobox_secondary_present - * - * Figure out if secondary/slave board is present - * - ************************************************************************/ -int sbcommon_secondary_present(void) -{ - ppc440_gpio_regs_t *gpio_regs; - - gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; - - if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES) - return 0; - else - return 1; -} - -/************************************************************************* - * sbcommon_get_serial_number - * - * Retrieve the board serial number via the mac address in eeprom - * - ************************************************************************/ -unsigned short sbcommon_get_serial_number(void) -{ - unsigned char buff[0x100]; - unsigned short sernum; - - /* Get the board serial number from eeprom */ - /* Initialize I2C */ - i2c_set_bus_num(0); - - /* Read 256 bytes in EEPROM */ - i2c_read (0x50, 0, 1, buff, 0x100); - - memcpy(&sernum, &buff[0xF4], 2); - sernum /= 32; - - return (sernum); -} - -/************************************************************************* - * sbcommon_fans - * - * Spin up fans 2 & 3 to get some air moving. OS will take care - * of the rest. This is mostly a precaution... - * - * Assumes i2c bus 1 is ready. - * - ************************************************************************/ -void sbcommon_fans(void) -{ - /* - * Attempt to turn on 2 of the fans... - * Need to go through the bridge - */ - i2c_set_bus_num(1); - puts ("FANS: "); - - /* select fan4 through the bridge */ - i2c_reg_write(0x73, /* addr */ - 0x00, /* reg */ - 0x08); /* val = bus 4 */ - - /* Turn on FAN 4 */ - i2c_reg_write(0x2e, - 1, - 0x80); - - i2c_reg_write(0x2e, - 0, - 0x19); - - /* Deselect bus 4 on the bridge */ - i2c_reg_write(0x73, - 0x00, - 0x00); - - /* select fan3 through the bridge */ - i2c_reg_write(0x73, /* addr */ - 0x00, /* reg */ - 0x04); /* val = bus 3 */ - - /* Turn on FAN 3 */ - i2c_reg_write(0x2e, - 1, - 0x80); - - i2c_reg_write(0x2e, - 0, - 0x19); - - /* Deselect bus 3 on the bridge */ - i2c_reg_write(0x73, - 0x00, - 0x00); - - /* select fan2 through the bridge */ - i2c_reg_write(0x73, /* addr */ - 0x00, /* reg */ - 0x02); /* val = bus 4 */ - - /* Turn on FAN 2 */ - i2c_reg_write(0x2e, - 1, - 0x80); - - i2c_reg_write(0x2e, - 0, - 0x19); - - /* Deselect bus 2 on the bridge */ - i2c_reg_write(0x73, - 0x00, - 0x00); - - /* select fan1 through the bridge */ - i2c_reg_write(0x73, /* addr */ - 0x00, /* reg */ - 0x01); /* val = bus 0 */ - - /* Turn on FAN 1 */ - i2c_reg_write(0x2e, - 1, - 0x80); - - i2c_reg_write(0x2e, - 0, - 0x19); - - /* Deselect bus 1 on the bridge */ - i2c_reg_write(0x73, - 0x00, - 0x00); - - puts ("on\n"); - i2c_set_bus_num(0); - - return; - -} - -/************************************************************************* - * initdram - * - * Initialize sdram - * - ************************************************************************/ -phys_size_t initdram (int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); -#else - dram_size = fixed_sdram (); -#endif - return dram_size; -} - - -/************************************************************************* - * testdram - * - * - ************************************************************************/ -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("Testing SDRAM: "); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("OK\n"); - return 0; -} -#endif - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - * - * Assumes: 128 MB, non-ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -long int fixed_sdram (void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ - mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ - /* RA=10 RD=3 */ - mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ - udelay (400); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ - for (;;) { - mfsdram (SDRAM0_MCSTS, reg); - if (reg & 0x80000000) - break; - } - - return (128 * 1024 * 1024); /* 128 MB */ -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - -/************************************************************************* - * board_get_enetaddr - * - * Get the ethernet MAC address for the management ethernet from the - * strap EEPROM. Note that is the BASE address for the range of - * external ethernet MACs on the board. The base + 31 is the actual - * mgmt mac address. - * - ************************************************************************/ - -void board_get_enetaddr(int macaddr_idx, uchar *enet) -{ - int i; - unsigned short tmp; - unsigned char buff[0x100], *cp; - - if (0 == macaddr_idx) { - - /* Initialize I2C */ - i2c_set_bus_num(0); - - /* Read 256 bytes in EEPROM */ - i2c_read (0x50, 0, 1, buff, 0x100); - - cp = &buff[0xF0]; - - for (i = 0; i < 6; i++,cp++) - enet[i] = *cp; - - memcpy(&tmp, &enet[4], 2); - tmp += 31; - memcpy(&enet[4], &tmp, 2); - - } else { - enet[0] = 0x02; - enet[1] = 0x00; - enet[2] = 0x00; - enet[3] = 0x00; - enet[4] = 0x00; - if (1 == sbcommon_get_master() ) { - /* Master/Primary card */ - enet[5] = 0x01; - } else { - /* Slave/Secondary card */ - enet [5] = 0x02; - } - } - - return; -} - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - - return (ctrlc()); -} -#endif diff --git a/board/sandburst/common/sb_common.h b/board/sandburst/common/sb_common.h deleted file mode 100644 index 57406335bf..0000000000 --- a/board/sandburst/common/sb_common.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef __SBCOMMON_H__ -#define __SBCOMMON_H__ -/* - * Copyright (C) 2005 Sandburst Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include -#include -#include - -/* - * GPIO Settings - */ -/* Chassis settings */ -#define SBCOMMON_GPIO_PRI_N 0x00001000 /* 0 = Chassis Master, 1 = Slave */ -#define SBCOMMON_GPIO_SEC_PRES 0x00000800 /* 1 = Other board present */ - -/* Debug LEDs */ -#define SBCOMMON_GPIO_DBGLED_0 0x00000400 -#define SBCOMMON_GPIO_DBGLED_1 0x00000200 -#define SBCOMMON_GPIO_DBGLED_2 0x00100000 -#define SBCOMMON_GPIO_DBGLED_3 0x00000100 - -#define SBCOMMON_GPIO_DBGLEDS (SBCOMMON_GPIO_DBGLED_0 | \ - SBCOMMON_GPIO_DBGLED_1 | \ - SBCOMMON_GPIO_DBGLED_2 | \ - SBCOMMON_GPIO_DBGLED_3) - -#define SBCOMMON_GPIO_SYS_FAULT 0x00000080 -#define SBCOMMON_GPIO_SYS_OTEMP 0x00000040 -#define SBCOMMON_GPIO_SYS_STATUS 0x00000020 - -#define SBCOMMON_GPIO_SYS_LEDS (SBCOMMON_GPIO_SYS_STATUS) - -#define SBCOMMON_GPIO_LEDS (SBCOMMON_GPIO_DBGLED_0 | \ - SBCOMMON_GPIO_DBGLED_1 | \ - SBCOMMON_GPIO_DBGLED_2 | \ - SBCOMMON_GPIO_DBGLED_3 | \ - SBCOMMON_GPIO_SYS_STATUS) - -typedef struct ppc440_gpio_regs { - volatile unsigned long out; - volatile unsigned long tri_state; - volatile unsigned long dummy[4]; - volatile unsigned long open_drain; - volatile unsigned long in; -} __attribute__((packed)) ppc440_gpio_regs_t; - -int sbcommon_get_master(void); -int sbcommon_secondary_present(void); -unsigned short sbcommon_get_serial_number(void); -void sbcommon_fans(void); -void board_get_enetaddr(int macaddr_idx, uchar *enet); - -#endif /* __SBCOMMON_H__ */ diff --git a/board/sandburst/karef/Kconfig b/board/sandburst/karef/Kconfig deleted file mode 100644 index 1b04576b9c..0000000000 --- a/board/sandburst/karef/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KAREF - -config SYS_BOARD - default "karef" - -config SYS_VENDOR - default "sandburst" - -config SYS_CONFIG_NAME - default "KAREF" - -endif diff --git a/board/sandburst/karef/MAINTAINERS b/board/sandburst/karef/MAINTAINERS deleted file mode 100644 index 21510e85c0..0000000000 --- a/board/sandburst/karef/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -KAREF BOARD -#M: Travis Sawyer -S: Orphan (since 2014-03) -F: board/sandburst/karef/ -F: include/configs/KAREF.h -F: configs/KAREF_defconfig diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile deleted file mode 100644 index ce29b4100e..0000000000 --- a/board/sandburst/karef/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2005 -# Sandburst Corporation -# Travis B. Sawyer -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# TBS: add for debugging purposes -ccflags-y += -DBUILDUSER='"$(shell whoami)"' - -obj-y = karef.o ../common/flash.o ../common/sb_common.o -extra-y += init.o diff --git a/board/sandburst/karef/config.mk b/board/sandburst/karef/config.mk deleted file mode 100644 index b73986d3f2..0000000000 --- a/board/sandburst/karef/config.mk +++ /dev/null @@ -1,21 +0,0 @@ -# -# (C) Copyright 2005 -# Sandburst Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# Sandburst Corporation Metrobox Reference Design -# Travis B. Sawyer -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/sandburst/karef/hal_ka_of_auto.h b/board/sandburst/karef/hal_ka_of_auto.h deleted file mode 100644 index cc501c99d9..0000000000 --- a/board/sandburst/karef/hal_ka_of_auto.h +++ /dev/null @@ -1,324 +0,0 @@ -/* **************************************************************** - * Common defs for reg spec for chip ka_of - * Auto-generated by trex2: DO NOT HAND-EDIT!! - * **************************************************************** - */ - -#ifndef HAL_KA_OF_AUTO_H -#define HAL_KA_OF_AUTO_H - - -/* ---------------------------------------------------------------- - * For block: 'ofem' - */ - -/* ---- Block instance addressing (for block-select) */ -#define OFEM_BLOCK_ADDR_BIT_L 6 -#define OFEM_BLOCK_ADDR_BIT_H 9 -#define OFEM_BLOCK_ADDR_WIDTH 4 - -#define OFEM_ADDR 0x0 - -/* ---- Reg addressing (within block) */ -#define OFEM_REG_ADDR_BIT_L 2 -#define OFEM_REG_ADDR_BIT_H 5 -#define OFEM_REG_ADDR_WIDTH 4 - - -/* ================================================================ - * ---- Register KA_OF_OFEM_REVISION */ -#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET 0x000 -#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_REVISION_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_REVISION_MSB 31 -#define SAND_HAL_KA_OF_OFEM_REVISION_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_RESET */ -#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET 0x004 -#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_RESET_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_RESET_MSB 31 -#define SAND_HAL_KA_OF_OFEM_RESET_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_CNTL */ -#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET 0x018 -#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_CNTL_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_CNTL_MSB 31 -#define SAND_HAL_KA_OF_OFEM_CNTL_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_MAC_FLOW_CTL */ -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET 0x01c -#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB 31 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_INTERRUPT */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET 0x008 -#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB 31 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_INTERRUPT_MASK */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET 0x00c -#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB 31 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_SCRATCH */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET 0x010 -#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB 0 - -/* ================================================================ - * ---- Register KA_OF_OFEM_SCRATCH_MASK */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET 0x014 -#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB 0 - -/* ================================================================ - * Field info for register KA_OF_OFEM_REVISION */ -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK 0x0000ff00 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB 15 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB 8 -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT 0x00000024 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK 0x000000ff -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB 7 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB 0 -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_RESET */ -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK 0x00000004 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB 2 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB 2 -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK 0x00000002 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT 1 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB 1 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB 1 -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK 0x00000001 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB 0 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB 0 -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_CNTL */ -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK 0x000000c0 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT 6 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB 7 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB 6 -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK 0x00000030 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB 5 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB 4 -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK 0x0000000c -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB 3 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB 2 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK 0x00000003 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB 1 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB 0 -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_MAC_FLOW_CTL */ -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK 0x00000100 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB 8 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB 8 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0 -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_INTERRUPT */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK 0x00000100 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000080 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000040 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK 0x00000020 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK 0x00000010 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK 0x00000008 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK 0x00000004 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK 0x00000002 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_INTERRUPT_MASK */ -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00000100 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 8 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000080 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 7 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000040 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 6 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000020 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 5 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000010 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 4 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000008 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 3 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000004 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 2 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0 -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register KA_OF_OFEM_SCRATCH */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_OF_OFEM_SCRATCH_MASK */ -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff - -#endif /* matches #ifndef HAL_KA_OF_AUTO_H */ diff --git a/board/sandburst/karef/hal_ka_sc_auto.h b/board/sandburst/karef/hal_ka_sc_auto.h deleted file mode 100644 index db1cec246a..0000000000 --- a/board/sandburst/karef/hal_ka_sc_auto.h +++ /dev/null @@ -1,836 +0,0 @@ -/* **************************************************************** - * Common defs for reg spec for chip ka_sc - * Auto-generated by trex2: DO NOT HAND-EDIT!! - * **************************************************************** - */ - -#ifndef HAL_KA_SC_AUTO_H -#define HAL_KA_SC_AUTO_H - - -/* ---------------------------------------------------------------- - * For block: 'scan' - */ - -/* ---- Block instance addressing (for block-select) */ -#define SCAN_BLOCK_ADDR_BIT_L 7 -#define SCAN_BLOCK_ADDR_BIT_H 9 -#define SCAN_BLOCK_ADDR_WIDTH 3 - -#define SCAN_ADDR 0x0 - -/* ---- Reg addressing (within block) */ -#define SCAN_REG_ADDR_BIT_L 2 -#define SCAN_REG_ADDR_BIT_H 6 -#define SCAN_REG_ADDR_WIDTH 5 - - -/* ================================================================ - * ---- Register KA_SC_SCAN_REVISION */ -#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET 0x000 -#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_REVISION_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_REVISION_MSB 31 -#define SAND_HAL_KA_SC_SCAN_REVISION_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_RESET */ -#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET 0x004 -#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_RESET_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_RESET_MSB 31 -#define SAND_HAL_KA_SC_SCAN_RESET_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_STATUS */ -#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET 0x008 -#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_STATUS_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_STATUS_MSB 31 -#define SAND_HAL_KA_SC_SCAN_STATUS_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_CNTL */ -#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET 0x01c -#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_CNTL_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_CNTL_MSB 31 -#define SAND_HAL_KA_SC_SCAN_CNTL_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_INFO */ -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET 0x020 -#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_FROM_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET 0x024 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_FROM_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET 0x028 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_TO_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET 0x02c -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_TO_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET 0x030 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCAN_CTRL */ -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET 0x034 -#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_PLL_CTRL */ -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET 0x038 -#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB 31 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_CORE_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET 0x03c -#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_DR_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET 0x040 -#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SPI_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET 0x044 -#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET 0x048 -#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET 0x04c -#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_BRD_BRD_IN */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET 0x050 -#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB 31 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_MISC */ -#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET 0x054 -#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_MISC_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_MISC_MSB 31 -#define SAND_HAL_KA_SC_SCAN_MISC_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_INTERRUPT */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET 0x00c -#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_INTERRUPT_MASK */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET 0x010 -#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB 31 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCRATCH */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET 0x014 -#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB 0 - -/* ================================================================ - * ---- Register KA_SC_SCAN_SCRATCH_MASK */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET 0x018 -#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB 0 - -/* ================================================================ - * Field info for register KA_SC_SCAN_REVISION */ -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK 0x0000ff00 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB 15 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB 8 -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT 0x00000023 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK 0x000000ff -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB 7 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB 0 -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_RESET */ -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB 9 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB 9 -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB 8 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB 8 -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK 0x00000080 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT 7 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB 7 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB 7 -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK 0x00000040 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB 6 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB 6 -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK 0x00000020 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT 5 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB 5 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB 5 -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB 4 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB 4 -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB 3 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB 3 -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB 1 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB 1 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB 0 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB 0 -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_STATUS */ -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK 0x00000040 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB 6 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB 6 -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK 0x00000020 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT 5 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB 5 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB 5 -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB 4 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB 4 -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB 3 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB 3 -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB 2 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB 2 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB 1 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB 1 -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB 0 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB 0 -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_CNTL */ -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK 0x00000400 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT 10 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB 10 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB 10 -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB 9 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB 9 -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB 8 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB 8 -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK 0x000000c0 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB 7 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB 6 -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK 0x00000030 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB 5 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB 4 -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK 0x0000000c -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB 3 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB 2 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK 0x00000003 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB 1 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB 0 -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_INFO */ -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK 0x0000f000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT 12 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB 15 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB 12 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK 0x00000300 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB 9 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB 8 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK 0x000000f0 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB 7 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB 4 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK 0x00000003 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB 1 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_FROM_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_FROM_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_TO_0 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_TO_1 */ -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCAN_CTRL */ -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK 0x04000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT 26 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB 26 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB 26 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK 0x03000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB 25 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB 24 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK 0x00100000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT 20 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB 20 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB 20 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK 0x00080000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT 19 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB 19 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB 19 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK 0x00040000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT 18 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB 18 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB 18 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK 0x00020000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT 17 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB 17 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB 17 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK 0x00010000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT 16 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB 16 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB 16 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK 0x00001000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT 12 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB 12 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB 12 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK 0x00000800 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT 11 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB 11 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB 11 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK 0x00000400 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT 10 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB 10 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB 10 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB 9 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB 9 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB 8 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB 8 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK 0x00000018 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB 4 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB 3 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB 2 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB 2 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB 1 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB 1 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_PLL_CTRL */ -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK 0x00002000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT 13 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB 13 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB 13 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK 0x00001000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT 12 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB 12 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB 12 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK 0x00000800 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT 11 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB 11 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB 11 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK 0x00000400 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT 10 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB 10 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB 10 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK 0x00000200 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT 9 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB 9 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB 9 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK 0x00000100 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT 8 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB 8 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB 8 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK 0x00000080 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT 7 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB 7 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB 7 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK 0x00000040 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT 6 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB 6 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB 6 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK 0x00000020 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT 5 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB 5 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB 5 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB 4 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB 4 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB 3 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB 3 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK 0x00000007 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB 2 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB 0 -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_CORE_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB 23 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_DR_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB 23 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SPI_CLK_COUNT */ -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB 23 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK 0x001fffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB 20 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK 0x001fffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB 20 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_BRD_BRD_IN */ -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK 0x001fffff -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB 20 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB 0 -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_MISC */ -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB 1 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB 1 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB 0 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB 0 -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_INTERRUPT */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_INTERRUPT_MASK */ -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00000010 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 4 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000008 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 3 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000004 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 2 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000002 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 1 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000001 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCRATCH */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register KA_SC_SCAN_SCRATCH_MASK */ -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff - -#endif /* matches #ifndef HAL_KA_SC_AUTO_H */ diff --git a/board/sandburst/karef/init.S b/board/sandburst/karef/init.S deleted file mode 100644 index 61c5d07964..0000000000 --- a/board/sandburst/karef/init.S +++ /dev/null @@ -1,39 +0,0 @@ -/* -* Copyright (C) 2005 Sandburst Corporation - * SPDX-License-Identifier: GPL-2.0+ -*/ -/* - * Ported from Ebony init.S by Travis B. Sawyer - */ - -#include -#include -#include -#include - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) - tlbtab_end diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c deleted file mode 100644 index 96d7dcd8fd..0000000000 --- a/board/sandburst/karef/karef.c +++ /dev/null @@ -1,595 +0,0 @@ -/* - * Copyright (C) 2005 Sandburst Corporation - * Travis B. Sawyer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "karef.h" -#include "karef_version.h" -#include -#include -#include -#include -#include -#include "../common/sb_common.h" -#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \ - defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) -#include -#endif - -void fpga_init (void); - -KAREF_BOARD_ID_ST board_id_as[] = -{ - {"Undefined"}, /* Not specified */ - {"Kamino Reference Design"}, - {"Reserved"}, /* Reserved for future use */ - {"Reserved"}, /* Reserved for future use */ -}; - -KAREF_BOARD_ID_ST ofem_board_id_as[] = -{ - {"Undefined"}, - {"1x10 + 10x2"}, - {"Reserved"}, - {"Reserved"}, -}; - -/************************************************************************* - * board_early_init_f - * - * Setup chip selects, initialize the Opto-FPGA, initialize - * interrupt polarity and triggers. - ************************************************************************/ -int board_early_init_f (void) -{ - ppc440_gpio_regs_t *gpio_regs; - - /* Enable GPIO interrupts */ - mtsdr(SDR0_PFC0, 0x00103E00); - - /* Setup access for LEDs, and system topology info */ - gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; - gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; - gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; - - /* Turn on all the leds for now */ - gpio_regs->out = SBCOMMON_GPIO_LEDS; - - /*--------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------*/ - mtebc(EBC0_CFG, - EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | - EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | - EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | - EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | - EBC_CFG_PR_32); - - /*--------------------------------------------------------------------+ - | 1/2 MB FLASH. Initialize bank 0 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB0AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - /*--------------------------------------------------------------------+ - | 8KB NVRAM/RTC. Initialize bank 1 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB1AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(PB2AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | KaRef Scan FPGA. Initialize bank 3 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB5AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48200000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | MAC A & B for Kamino. OFEM FPGA decodes the addresses - | Initialize bank 4 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB4AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) | - EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | OFEM FPGA Initialize bank 5 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB3AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - - mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48400000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(PB6AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | BME-32. Initialize bank 7 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB7AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - * Setup the interrupt controller polarities, triggers, etc. - +-------------------------------------------------------------------*/ - /* - * Because of the interrupt handling rework to handle 440GX interrupts - * with the common code, we needed to change names of the UIC registers. - * Here the new relationship: - * - * U-Boot name 440GX name - * ----------------------- - * UIC0 UICB0 - * UIC1 UIC0 - * UIC2 UIC1 - * UIC3 UIC2 - */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (UIC1ER, 0x00000000); /* disable all */ - mtdcr (UIC1CR, 0x00000000); /* all non- critical */ - mtdcr (UIC1PR, 0xfffffe03); /* polarity */ - mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */ - mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (UIC2ER, 0x00000000); /* disable all */ - mtdcr (UIC2CR, 0x00000000); /* all non-critical */ - mtdcr (UIC2PR, 0xffffc8ff); /* polarity */ - mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */ - mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (UIC3ER, 0x00000000); /* disable all */ - mtdcr (UIC3CR, 0x00000000); /* all non-critical */ - mtdcr (UIC3PR, 0xffff83ff); /* polarity */ - mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */ - mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - - mtdcr (UIC0SR, 0xfc000000); /* clear all */ - mtdcr (UIC0ER, 0x00000000); /* disable all */ - mtdcr (UIC0CR, 0x00000000); /* all non-critical */ - mtdcr (UIC0PR, 0xfc000000); - mtdcr (UIC0TR, 0x00000000); - mtdcr (UIC0VR, 0x00000001); - - fpga_init(); - - return 0; -} - - -/************************************************************************* - * checkboard - * - * Dump pertinent info to the console - ************************************************************************/ -int checkboard (void) -{ - sys_info_t sysinfo; - unsigned char brd_rev, brd_id; - unsigned short sernum; - unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0; - unsigned char ofem_brd_rev, ofem_brd_id; - KAREF_FPGA_REGS_ST *karef_ps; - OFEM_FPGA_REGS_ST *ofem_ps; - - karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; - ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; - - scan_id = (unsigned char)((karef_ps->revision_ul & - SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK) - >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT); - - scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK) - >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT); - - brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT); - - brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT); - - ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT); - - ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT); - - if (0xF != ofem_brd_id) { - ofem_id = (unsigned char)((ofem_ps->revision_ul & - SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK) - >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT); - - ofem_rev = (unsigned char)((ofem_ps->revision_ul & - SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK) - >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT); - } - - get_sys_info (&sysinfo); - - sernum = sbcommon_get_serial_number(); - - printf ("Board: Sandburst Corporation Kamino Reference Design " - "Serial Number: %d\n", sernum); - printf ("%s\n", KAREF_U_BOOT_REL_STR); - - printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); - if (sbcommon_get_master()) { - printf("Slot 0 - Master\nSlave board"); - if (sbcommon_secondary_present()) - printf(" present\n"); - else - printf(" not detected\n"); - } else { - printf("Slot 1 - Slave\n\n"); - } - - printf ("ScanFPGA ID:\t0x%02X\tRev: 0x%02X\n", scan_id, scan_rev); - printf ("Board Rev:\t0x%02X\tID: 0x%02X\n", brd_rev, brd_id); - if(0xF != ofem_brd_id) { - printf("OFemFPGA ID:\t0x%02X\tRev: 0x%02X\n", ofem_id, ofem_rev); - printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev); - } - - /* Fix the ack in the bme 32 */ - udelay(5000); - out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001); - asm("eieio"); - - - return (0); -} - -/************************************************************************* - * misc_init_f - * - * Initialize I2C bus one to gain access to the fans - ************************************************************************/ -int misc_init_f (void) -{ - /* Turn on fans 3 & 4 */ - sbcommon_fans(); - - return (0); -} - -/************************************************************************* - * misc_init_r - * - * Do nothing. - ************************************************************************/ -int misc_init_r (void) -{ - unsigned short sernum; - char envstr[255]; - uchar enetaddr[6]; - KAREF_FPGA_REGS_ST *karef_ps; - OFEM_FPGA_REGS_ST *ofem_ps; - - if(NULL != getenv("secondserial")) { - puts("secondserial is set, switching to second serial port\n"); - setenv("stderr", "serial1"); - setenv("stdout", "serial1"); - setenv("stdin", "serial1"); - } - - setenv("ubrelver", KAREF_U_BOOT_REL_STR); - - memset(envstr, 0, 255); - sprintf (envstr, "Built %s %s by %s", - U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); - setenv("bldstr", envstr); - saveenv(); - - if( getenv("autorecover")) { - setenv("autorecover", NULL); - saveenv(); - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for automatic filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33", - sernum, sernum); - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type allow the system to continue to boot\n"); - } - - if( getenv("fakeled")) { - karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; - ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; - ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK; - karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK; - setenv("bootdelay", "-1"); - saveenv(); - printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); - } - -#ifdef CONFIG_HAS_ETH0 - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(0, enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH1 - if (!eth_getenv_enetaddr("eth1addr", enetaddr)) { - board_get_enetaddr(1, enetaddr); - eth_setenv_enetaddr("eth1addr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH2 - if (!eth_getenv_enetaddr("eth2addr", enetaddr)) { - board_get_enetaddr(2, enetaddr); - eth_setenv_enetaddr("eth2addr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH3 - if (!eth_getenv_enetaddr("eth3addr", enetaddr)) { - board_get_enetaddr(3, enetaddr); - eth_setenv_enetaddr("eth3addr", enetaddr); - } -#endif - - return (0); -} - -/************************************************************************* - * ide_set_reset - ************************************************************************/ -#ifdef CONFIG_IDE_RESET -void ide_set_reset(int on) -{ - KAREF_FPGA_REGS_ST *karef_ps; - /* TODO: ide reset */ - karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; - - if (on) { - karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; - } else { - karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; - } -} -#endif /* CONFIG_IDE_RESET */ - -/************************************************************************* - * fpga_init - ************************************************************************/ -void fpga_init(void) -{ - KAREF_FPGA_REGS_ST *karef_ps; - OFEM_FPGA_REGS_ST *ofem_ps; - unsigned char ofem_id; - unsigned long tmp; - - /* Ensure we have power all around */ - udelay(500); - - karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; - tmp = - SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK | - SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK; - - karef_ps->reset_ul = tmp; - - /* - * Wait a bit to allow the ofem fpga to get its brains - */ - udelay(5000); - - /* - * Check to see if the ofem is there - */ - ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK) - >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT); - if(0xF != ofem_id) { - tmp = - SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK | - SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK | - SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK; - - ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; - ofem_ps->reset_ul = tmp; - - ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT; - } - - karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT; - - asm("eieio"); - - return; -} - -int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - memset(envstr, 0, 255); - /* - * Setup our ip address - */ - sprintf(envstr, "10.100.70.%d", sernum); - - setenv("ipaddr", envstr); - /* - * Setup the host ip address - */ - setenv("serverip", "10.100.17.10"); - - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs " - "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d " - "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:" - "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33", - sernum, sernum, sernum); - - setenv("bootargs_nfs", envstr); - setenv("bootargs", envstr); - - /* - * Setup CF bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 " - "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33", - sernum, sernum); - - setenv("bootargs_cf", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000"); - setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000"); - - /* - * Setup compact flash boot command - */ - setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000"); - - saveenv(); - - return(1); -} - -int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none", - sernum, sernum); - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - - setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type boot.\nWhen the kernel has booted" - " please type fsrecover.sh\n"); - - return(1); -} - -U_BOOT_CMD(kasetup, 1, 1, karefSetupVars, - "Set environment to factory defaults", ""); - -U_BOOT_CMD(karecover, 1, 1, karefRecover, - "Set environment to allow for fs recovery", ""); diff --git a/board/sandburst/karef/karef.h b/board/sandburst/karef/karef.h deleted file mode 100644 index eb9c314aa9..0000000000 --- a/board/sandburst/karef/karef.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef __KAREF_H__ -#define __KAREF_H__ -/* - * (C) Copyright 2005 - * Sandburst Corporation - * Travis B. Sawyer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Ka Reference Design OFEM FPGA Registers & definitions */ -#include "hal_ka_sc_auto.h" -#include "hal_ka_of_auto.h" - -typedef struct karef_board_id_s { - const char name[40]; -} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST; - -/* SCAN FPGA */ -typedef struct karef_fpga_regs_s -{ - volatile unsigned long revision_ul; /* Read Only */ - volatile unsigned long reset_ul; /* Read/Write */ - volatile unsigned long interrupt_ul; /* Read Only */ - volatile unsigned long mask_ul; /* Read/Write */ - volatile unsigned long scratch_ul; /* Read/Write */ - volatile unsigned long scrmask_ul; /* Read/Write */ - volatile unsigned long status_ul; /* Read Only */ - volatile unsigned long control_ul; /* Read/Write */ - volatile unsigned long boardinfo_ul; /* Read Only */ - volatile unsigned long scan_from0_ul; /* Read Only */ - volatile unsigned long scan_from1_ul; /* Read Only */ - volatile unsigned long scan_to0_ul; /* Read/Write */ - volatile unsigned long scan_to1_ul; /* Read/Write */ - volatile unsigned long scan_control_ul; /* Read/Write */ - volatile unsigned long pll_control_ul; /* Read/Write */ - volatile unsigned long core_clock_cnt_ul; /* Read/Write */ - volatile unsigned long dr_clock_cnt_ul; /* Read/Write */ - volatile unsigned long spi_clock_cnt_ul; /* Read/Write */ - volatile unsigned long brdout_data_ul; /* Read/Write */ - volatile unsigned long brdout_enable_ul; /* Read/Write */ - volatile unsigned long brdin_data_ul; /* Read Only */ - volatile unsigned long misc_ul; /* Read/Write */ -} __attribute__((packed)) KAREF_FPGA_REGS_ST , * KAREF_FPGA_REGS_PST; - -/* OFEM FPGA */ -typedef struct ofem_fpga_regs_s -{ - volatile unsigned long revision_ul; /* Read Only */ - volatile unsigned long reset_ul; /* Read/Write */ - volatile unsigned long interrupt_ul; /* Read Only */ - volatile unsigned long mask_ul; /* Read/Write */ - volatile unsigned long scratch_ul; /* Read/Write */ - volatile unsigned long scrmask_ul; /* Read/Write */ - volatile unsigned long control_ul; /* Read/Write */ - volatile unsigned long mac_flow_ctrl_ul; /* Read/Write */ -} __attribute__((packed)) OFEM_FPGA_REGS_ST , * OFEM_FPGA_REGS_PST; - - -#endif /* __KAREF_H__ */ diff --git a/board/sandburst/karef/karef_version.h b/board/sandburst/karef/karef_version.h deleted file mode 100644 index 6c6baee015..0000000000 --- a/board/sandburst/karef/karef_version.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _KAREF_VERSION_H_ -#define _KAREF_VERSION_H_ -/* - * Copyright (C) 2005 Sandburst Corporation - * Travis B. Sawyer - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#define KAREF_U_BOOT_REL_STR "Release 0.0.7" -#endif diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug deleted file mode 100644 index c17c8b939b..0000000000 --- a/board/sandburst/karef/u-boot.lds.debug +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text) - board/sandburst/karef/init.o (.text) - arch/powerpc/cpu/ppc4xx/kgdb.o (.text) - arch/powerpc/cpu/ppc4xx/traps.o (.text) - arch/powerpc/cpu/ppc4xx/interrupts.o (.text) - arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text) - arch/powerpc/cpu/ppc4xx/cpu_init.o (.text) - arch/powerpc/cpu/ppc4xx/speed.o (.text) - drivers/net/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - lib/zlib.o (.text) - -/* common/env_embedded.o(.text) */ - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/sandburst/metrobox/Kconfig b/board/sandburst/metrobox/Kconfig deleted file mode 100644 index 4a771efef4..0000000000 --- a/board/sandburst/metrobox/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_METROBOX - -config SYS_BOARD - default "metrobox" - -config SYS_VENDOR - default "sandburst" - -config SYS_CONFIG_NAME - default "METROBOX" - -endif diff --git a/board/sandburst/metrobox/MAINTAINERS b/board/sandburst/metrobox/MAINTAINERS deleted file mode 100644 index 71d18f9186..0000000000 --- a/board/sandburst/metrobox/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -METROBOX BOARD -#M: Travis Sawyer -S: Orphan (since 2014-03) -F: board/sandburst/metrobox/ -F: include/configs/METROBOX.h -F: configs/METROBOX_defconfig diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile deleted file mode 100644 index 2c1028bd2b..0000000000 --- a/board/sandburst/metrobox/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2005 -# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# TBS: add for debugging purposes -ccflags-y += -DBUILDUSER='"$(shell whoami)"' - -obj-y = metrobox.o ../common/flash.o ../common/sb_common.o -extra-y += init.o diff --git a/board/sandburst/metrobox/config.mk b/board/sandburst/metrobox/config.mk deleted file mode 100644 index 23190c8673..0000000000 --- a/board/sandburst/metrobox/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2005 -# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/sandburst/metrobox/hal_xc_auto.h b/board/sandburst/metrobox/hal_xc_auto.h deleted file mode 100644 index c99b38ca06..0000000000 --- a/board/sandburst/metrobox/hal_xc_auto.h +++ /dev/null @@ -1,553 +0,0 @@ -/* **************************************************************** - * Common defs for reg spec for chip xc - * Auto-generated by trex2: DO NOT HAND-EDIT!! - * **************************************************************** - */ - -#ifndef HAL_XC_AUTO_H -#define HAL_XC_AUTO_H - -/* ---------------------------------------------------------------- - * For block: 'xcvr_cntl' - */ - -/* ---- Block instance addressing (for block-select) */ -#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6 -#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9 -#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4 - -#define XCVR_CNTL_ADDR 0x0 - -/* ---- Reg addressing (within block) */ -#define XCVR_CNTL_REG_ADDR_BIT_L 2 -#define XCVR_CNTL_REG_ADDR_BIT_H 5 -#define XCVR_CNTL_REG_ADDR_WIDTH 4 - - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_REVISION */ -#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET 0x000 -#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_RESET */ -#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET 0x004 -#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_STATUS */ -#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET 0x008 -#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_CNTL */ -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET 0x01c -#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_BRD_INFO */ -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET 0x020 -#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */ -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET 0x024 -#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_INTERRUPT */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET 0x00c -#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET 0x010 -#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_SCRATCH */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET 0x014 -#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB 0 - -/* ================================================================ - * ---- Register XC_XCVR_CNTL_SCRATCH_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET 0x018 -#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK 0x000 -#endif -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB 0 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_REVISION */ -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK 0x0000ff00 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB 15 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK 0x000000ff -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_RESET */ -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK 0x00020000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT 17 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB 17 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB 17 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK 0x00010000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT 16 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB 16 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB 16 -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK 0x00008000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT 15 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB 15 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB 15 -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK 0x00004000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT 14 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB 14 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB 14 -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK 0x00002000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT 13 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB 13 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB 13 -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK 0x00000800 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT 11 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB 11 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK 0x00000200 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_SHIFT 9 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_LSB 9 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK 0x00000100 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MSB 8 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK 0x00000080 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_SHIFT 7 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_LSB 7 -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK 0x00000040 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MSB 6 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK 0x00000020 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_SHIFT 5 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_LSB 5 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_SHIFT 3 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_LSB 3 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_STATUS */ -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_CNTL */ -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MASK 0x00000300 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK 0x000000c0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MASK 0x00000030 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MASK 0x0000000c -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_BRD_INFO */ -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK 0x000000f0 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK 0x00000003 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_MAC_FLOW_CTL */ -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MASK 0x00000f00 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_INTERRUPT */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MASK 0x00002000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_SHIFT 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_LSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000800 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK 0x00000200 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK 0x00000100 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK 0x00000080 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK 0x00000040 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK 0x00000020 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK 0x00000008 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00002000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 13 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00001000 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 12 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000800 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 11 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000400 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 10 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000200 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 9 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000100 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 8 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000080 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 7 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000040 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 6 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000020 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 5 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000010 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 4 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000008 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 3 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000004 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 2 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_SCRATCH */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT 0x00000000 - -/* ================================================================ - * Field info for register XC_XCVR_CNTL_SCRATCH_MASK */ -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) -#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff - -#endif /* matches #ifndef HAL_XC_AUTO_H */ diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S deleted file mode 100644 index 13e340eece..0000000000 --- a/board/sandburst/metrobox/init.S +++ /dev/null @@ -1,37 +0,0 @@ -/* -* Copyright (C) 2005 -* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include -#include -#include -#include - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) - tlbtab_end diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c deleted file mode 100644 index 290fa020f8..0000000000 --- a/board/sandburst/metrobox/metrobox.c +++ /dev/null @@ -1,561 +0,0 @@ -/* - * Copyright (c) 2005 - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include "metrobox.h" -#include "metrobox_version.h" -#include -#include -#include -#include -#include -#include "../common/sb_common.h" -#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \ - defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) -#include -#endif - -void fpga_init (void); - -METROBOX_BOARD_ID_ST board_id_as[] = -{ {"Undefined"}, /* Not specified */ - {"2x10Gb"}, /* 2 ports, 10 GbE */ - {"20x1Gb"}, /* 20 ports, 1 GbE */ - {"Reserved"}, /* Reserved for future use */ -}; - -/************************************************************************* - * board_early_init_f - * - * Setup chip selects, initialize the Opto-FPGA, initialize - * interrupt polarity and triggers. - ************************************************************************/ -int board_early_init_f (void) -{ - ppc440_gpio_regs_t *gpio_regs; - - /* Enable GPIO interrupts */ - mtsdr(SDR0_PFC0, 0x00103E00); - - /* Setup access for LEDs, and system topology info */ - gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; - gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; - gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; - - /* Turn on all the leds for now */ - gpio_regs->out = SBCOMMON_GPIO_LEDS; - - /*--------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------*/ - mtebc(EBC0_CFG, - EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | - EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | - EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | - EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | - EBC_CFG_PR_32); - - /*--------------------------------------------------------------------+ - | 1/2 MB FLASH. Initialize bank 0 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB0AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - /*--------------------------------------------------------------------+ - | 8KB NVRAM/RTC. Initialize bank 1 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB1AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(PB2AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | OPTO & OFEM FPGA. Initialize bank 3 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB3AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48200000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | MAC A for metrobox - | MAC A & B for Kamino. OFEM FPGA decodes the addresses - | Initialize bank 4 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB4AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | Metrobox MAC B Initialize bank 5 with default values. - | KA REF FPGA Initialize bank 5 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB5AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48700000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - | Compact Flash, uses 2 Chip Selects (2 & 6) - +-------------------------------------------------------------------*/ - mtebc(PB6AP, - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | - EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | - EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | - EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - - mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /*--------------------------------------------------------------------+ - | BME-32. Initialize bank 7 with default values. - +-------------------------------------------------------------------*/ - mtebc(PB7AP, - EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | - EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - - mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*--------------------------------------------------------------------+ - * Setup the interrupt controller polarities, triggers, etc. - +-------------------------------------------------------------------*/ - /* - * Because of the interrupt handling rework to handle 440GX interrupts - * with the common code, we needed to change names of the UIC registers. - * Here the new relationship: - * - * U-Boot name 440GX name - * ----------------------- - * UIC0 UICB0 - * UIC1 UIC0 - * UIC2 UIC1 - * UIC3 UIC2 - */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (UIC1ER, 0x00000000); /* disable all */ - mtdcr (UIC1CR, 0x00000000); /* all non- critical */ - mtdcr (UIC1PR, 0xfffffe03); /* polarity */ - mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */ - mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (UIC2ER, 0x00000000); /* disable all */ - mtdcr (UIC2CR, 0x00000000); /* all non-critical */ - mtdcr (UIC2PR, 0xffffc8ff); /* polarity */ - mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */ - mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (UIC3ER, 0x00000000); /* disable all */ - mtdcr (UIC3CR, 0x00000000); /* all non-critical */ - mtdcr (UIC3PR, 0xffff83ff); /* polarity */ - mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */ - mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - - mtdcr (UIC0SR, 0xfc000000); /* clear all */ - mtdcr (UIC0ER, 0x00000000); /* disable all */ - mtdcr (UIC0CR, 0x00000000); /* all non-critical */ - mtdcr (UIC0PR, 0xfc000000); - mtdcr (UIC0TR, 0x00000000); - mtdcr (UIC0VR, 0x00000001); - - fpga_init(); - - return 0; -} - -/************************************************************************* - * checkboard - * - * Dump pertinent info to the console - ************************************************************************/ -int checkboard (void) -{ - sys_info_t sysinfo; - unsigned char brd_rev, brd_id; - unsigned short sernum; - unsigned char opto_rev, opto_id; - OPTO_FPGA_REGS_ST *opto_ps; - - opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; - - opto_rev = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); - - opto_id = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT); - - brd_rev = (unsigned char)((opto_ps->boardinfo_ul & - SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK) - >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT); - - brd_id = (unsigned char)((opto_ps->boardinfo_ul & - SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK) - >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT); - - get_sys_info (&sysinfo); - - sernum = sbcommon_get_serial_number(); - printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum); - printf ("%s\n", METROBOX_U_BOOT_REL_STR); - - printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); - if (sbcommon_get_master()) { - printf("Slot 0 - Master\nSlave board"); - if (sbcommon_secondary_present()) - printf(" present\n"); - else - printf(" not detected\n"); - } else { - printf("Slot 1 - Slave\n\n"); - } - - printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev); - printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id].name); - - /* Fix the ack in the bme 32 */ - udelay(5000); - out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001); - asm("eieio"); - - - return (0); -} - -/************************************************************************* - * misc_init_f - * - * Initialize I2C bus one to gain access to the fans - ************************************************************************/ -int misc_init_f (void) -{ - /* Turn on fans */ - sbcommon_fans(); - - return (0); -} - -/************************************************************************* - * misc_init_r - * - * Do nothing. - ************************************************************************/ -int misc_init_r (void) -{ - unsigned short sernum; - char envstr[255]; - uchar enetaddr[6]; - unsigned char opto_rev; - OPTO_FPGA_REGS_ST *opto_ps; - - opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; - - if(NULL != getenv("secondserial")) { - puts("secondserial is set, switching to second serial port\n"); - setenv("stderr", "serial1"); - setenv("stdout", "serial1"); - setenv("stdin", "serial1"); - } - - setenv("ubrelver", METROBOX_U_BOOT_REL_STR); - - memset(envstr, 0, 255); - sprintf (envstr, "Built %s %s by %s", - U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); - setenv("bldstr", envstr); - saveenv(); - - if( getenv("autorecover")) { - setenv("autorecover", NULL); - saveenv(); - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for automatic filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33", - sernum, sernum); - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type allow the system to continue to boot\n"); - } - - if( getenv("fakeled")) { - setenv("bootdelay", "-1"); - saveenv(); - printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); - opto_rev = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); - - if(0x12 <= opto_rev) { - opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK; - } - } - -#ifdef CONFIG_HAS_ETH0 - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(0, enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH1 - if (!eth_getenv_enetaddr("eth1addr", enetaddr)) { - board_get_enetaddr(1, enetaddr); - eth_setenv_enetaddr("eth1addr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH2 - if (!eth_getenv_enetaddr("eth2addr", enetaddr)) { - board_get_enetaddr(2, enetaddr); - eth_setenv_enetaddr("eth2addr", enetaddr); - } -#endif - -#ifdef CONFIG_HAS_ETH3 - if (!eth_getenv_enetaddr("eth3addr", enetaddr)) { - board_get_enetaddr(3, enetaddr); - eth_setenv_enetaddr("eth3addr", enetaddr); - } -#endif - - return (0); -} - -/************************************************************************* - * ide_set_reset - ************************************************************************/ -#ifdef CONFIG_IDE_RESET -void ide_set_reset(int on) -{ - OPTO_FPGA_REGS_ST *opto_ps; - opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; - - if (on) { /* assert RESET */ - opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; - } else { /* release RESET */ - opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; - } -} -#endif /* CONFIG_IDE_RESET */ - -/************************************************************************* - * fpga_init - ************************************************************************/ -void fpga_init(void) -{ - OPTO_FPGA_REGS_ST *opto_ps; - unsigned char opto_rev; - unsigned long tmp; - - /* Ensure we have power all around */ - udelay(500); - - /* - * Take appropriate hw bits out of reset - */ - opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; - - tmp = - SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK | - SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK; - opto_ps->reset_ul = tmp; - /* - * Turn on the 'Slow Blink' for the System Error Led. - * Ensure FPGA rev is up to at least rev 0x12 - */ - opto_rev = (unsigned char)((opto_ps->revision_ul & - SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) - >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); - if(0x12 <= opto_rev) { - opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT; - } - - asm("eieio"); - - return; -} - -int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - memset(envstr, 0, 255); - /* - * Setup our ip address - */ - sprintf(envstr, "10.100.60.%d", sernum); - - setenv("ipaddr", envstr); - /* - * Setup the host ip address - */ - setenv("serverip", "10.100.17.10"); - - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - - sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs " - "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d " - "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1" - ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33", - sernum, sernum, sernum); - - setenv("bootargs_nfs", envstr); - setenv("bootargs", envstr); - - /* - * Setup CF bootargs - */ - memset(envstr, 0, 255); - sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 " - "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33", - sernum, sernum); - - setenv("bootargs_cf", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000"); - setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000"); - - /* - * Setup compact flash boot command - */ - setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000"); - - saveenv(); - - - return(1); -} - -int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned short sernum; - char envstr[255]; - - sernum = sbcommon_get_serial_number(); - - printf("\nSetting up environment for filesystem recovery\n"); - /* - * Setup default bootargs - */ - memset(envstr, 0, 255); - sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " - "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none", - sernum, sernum); - - setenv("bootargs", envstr); - - /* - * Setup Default boot command - */ - setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;" - "fatload ide 0 8100000 pramdisk;" - "bootm 8000000 8100000"); - - printf("Done. Please type boot.\nWhen the kernel has booted" - " please type fsrecover.sh\n"); - - return(1); -} - -U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars, - "Set environment to factory defaults", ""); - -U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover, - "Set environment to allow for fs recovery", ""); diff --git a/board/sandburst/metrobox/metrobox.h b/board/sandburst/metrobox/metrobox.h deleted file mode 100644 index d64f496c9a..0000000000 --- a/board/sandburst/metrobox/metrobox.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef __METROBOX_H__ -#define __METROBOX_H__ -/* - * (C) Copyright 2005 - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -typedef struct metrobox_board_id_s { - const char name[40]; -} METROBOX_BOARD_ID_ST, *METROBOX_BOARD_ID_PST; - - -/* Metrobox Opto-FPGA registers and definitions */ -#include "hal_xc_auto.h" -typedef struct opto_fpga_regs_s { - volatile unsigned long revision_ul; /* Read Only */ - volatile unsigned long reset_ul; /* Read/Write */ - volatile unsigned long status_ul; /* Read Only */ - volatile unsigned long interrupt_ul; /* Read Only */ - volatile unsigned long mask_ul; /* Read/Write */ - volatile unsigned long scratch_ul; /* Read/Write */ - volatile unsigned long scrmask_ul; /* Read/Write */ - volatile unsigned long control_ul; /* Read/Write */ - volatile unsigned long boardinfo_ul; /* Read Only */ -} __attribute__ ((packed)) OPTO_FPGA_REGS_ST , *OPTO_FPGA_REGS_PST; - -#endif /* __METROBOX_H__ */ diff --git a/board/sandburst/metrobox/metrobox_version.h b/board/sandburst/metrobox/metrobox_version.h deleted file mode 100644 index 8264f56d6e..0000000000 --- a/board/sandburst/metrobox/metrobox_version.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _METROBOX_VERSION_H_ -#define _METROBOX_VERSION_H_ -/* - * (C) Copyright 2005 - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#define METROBOX_U_BOOT_REL_STR "Release 2.0.3" - -#endif diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug deleted file mode 100644 index 7ff09c0671..0000000000 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text) - board/sandburst/metrobox/init.o (.text) - arch/powerpc/cpu/ppc4xx/kgdb.o (.text) - arch/powerpc/cpu/ppc4xx/traps.o (.text) - arch/powerpc/cpu/ppc4xx/interrupts.o (.text) - arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text) - arch/powerpc/cpu/ppc4xx/cpu_init.o (.text) - arch/powerpc/cpu/ppc4xx/speed.o (.text) - drivers/net/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - lib/zlib.o (.text) - -/* common/env_embedded.o(.text) */ - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/configs/KAREF_defconfig b/configs/KAREF_defconfig deleted file mode 100644 index fcca3c980a..0000000000 --- a/configs/KAREF_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_KAREF=y diff --git a/configs/METROBOX_defconfig b/configs/METROBOX_defconfig deleted file mode 100644 index 14b471a0e9..0000000000 --- a/configs/METROBOX_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_METROBOX=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 2f5034f362..92ba1e411a 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +KAREF powerpc ppc4xx - - Travis Sawyer +METROBOX powerpc ppc4xx - - Travis Sawyer PK1C20 nios2 - 70fbc461 2014-08-24 Scott McNutt PCI5441 nios2 - 70fbc461 2014-08-24 Scott McNutt flagadm powerpc mpc8xx aec6f8c5 2014-08-22 Kári Davíðsson diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h deleted file mode 100644 index 546b725317..0000000000 --- a/include/configs/KAREF.h +++ /dev/null @@ -1,284 +0,0 @@ -/* - * (C) Copyright 2004 Sandburst Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference - * design. - ***********************************************************************/ - -/* - * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $ - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */ -#define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 - -#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/ -#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ - -#define CONFIG_VERY_BIG_RAM 1 -#define CONFIG_VERSION_VARIABLE - -#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design" - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) -#define CONFIG_SYS_KAREF_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000) -#define CONFIG_SYS_OFEM_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000) -#define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000) -#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) - -/* Here for completeness */ -#define CONFIG_SYS_OFEMAC_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/ -#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_PPC4XX_CH1 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */ -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F -#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */ - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ -#undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */ -#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ -#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */ - -#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR) - -#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/*----------------------------------------------------------------------- - * Networking - *----------------------------------------------------------------------*/ -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ -#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ -#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */ -#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */ -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ -#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ -#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ -#define CONFIG_PHY_RESET_DELAY 1000 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */ -#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */ -#define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_PING -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT - - -/* Include NetConsole support */ -#define CONFIG_NETCONSOLE - -/* Include auto complete with tabs */ -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "KaRefDes=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */ - - -/*----------------------------------------------------------------------- - * Console Buffer - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ - -/*----------------------------------------------------------------------- - * Memory Test - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Compact Flash (in true IDE mode) - *----------------------------------------------------------------------*/ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */ - -#define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride - to get to the correct offset */ -#define CONFIG_DOS_PARTITION 1 /* Include dos partition */ - -/*----------------------------------------------------------------------- - * PCI - *----------------------------------------------------------------------*/ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices */ -#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE) - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ -#endif - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h deleted file mode 100644 index 69ab5bb517..0000000000 --- a/include/configs/METROBOX.h +++ /dev/null @@ -1,349 +0,0 @@ -/* - * (C) Copyright 2004 Sandburst Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * METROBOX.h - configuration Sandburst MetroBox - ***********************************************************************/ - -/* - * $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $ - * - * - * $Log: METROBOX.h,v $ - * Revision 1.21 2005/06/03 15:05:25 tsawyer - * MB rev 2.0.3 KA rev 0.0.7. Add CONFIG_VERSION_VARIABLE, Add fakeled to MB - * - * Revision 1.20 2005/04/11 20:51:11 tsawyer - * fix ethernet - * - * Revision 1.19 2005/04/06 15:13:36 tsawyer - * Update appropriate files to coincide with u-boot 1.1.3 - * - * Revision 1.18 2005/03/10 14:16:02 tsawyer - * add def'n for cis8201 short etch option. - * - * Revision 1.17 2005/03/09 19:49:51 tsawyer - * Remove KGDB to allow use of 2nd serial port - * - * Revision 1.16 2004/12/02 19:00:23 tsawyer - * Add misc_init_f to turn on i2c-1 and all four fans before sdram init - * - * Revision 1.15 2004/09/15 18:04:12 tsawyer - * add multiple serial port support - * - * Revision 1.14 2004/09/03 15:27:51 tsawyer - * All metrobox boards are at 66.66 sys clock - * - * Revision 1.13 2004/08/05 20:27:46 tsawyer - * Remove system ace definitions, add net console support - * - * Revision 1.12 2004/07/29 20:00:13 tsawyer - * Add i2c bus 1 - * - * Revision 1.11 2004/07/21 13:44:18 tsawyer - * SystemACE is out, CF direct to local bus is in - * - * Revision 1.10 2004/06/29 19:08:55 tsawyer - * Add CONFIG_MISC_INIT_R - * - * Revision 1.9 2004/06/28 21:30:53 tsawyer - * Fix default BOOTARGS - * - * Revision 1.8 2004/06/17 15:51:08 tsawyer - * auto complete - * - * Revision 1.7 2004/06/17 15:08:49 tsawyer - * Add autocomplete - * - * Revision 1.6 2004/06/15 12:33:57 tsawyer - * debugging checkpoint - * - * Revision 1.5 2004/06/12 19:48:28 tsawyer - * Debugging checkpoint - * - * Revision 1.4 2004/06/02 13:03:06 tsawyer - * Fix eth addrs - * - * Revision 1.3 2004/05/18 19:56:10 tsawyer - * Change default bootcommand to pImage.metrobox - * - * Revision 1.2 2004/05/18 14:13:44 tsawyer - * Add bringup values for bootargs and bootcommand. - * Remove definition of ipaddress and serverip addresses. - * - * Revision 1.1 2004/04/16 15:08:54 tsawyer - * Initial Revision - * - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_METROBOX 1 /* Board is Metrobox */ -#define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 - -#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/ -#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ - -#define CONFIG_VERY_BIG_RAM 1 -#define CONFIG_VERSION_VARIABLE - -#define CONFIG_IDENT_STRING " Sandburst Metrobox" - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) -#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000) -#define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000) -#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/ -#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_PPC4XX_CH1 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */ -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F -#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */ - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ -#undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */ -#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ -#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */ - -#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR) - -#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none " -#define CONFIG_BOOTCOMMAND "tftp 8000000 pImage.metrobox;bootm 8000000" -#define CONFIG_BOOTDELAY 5 /* disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/*----------------------------------------------------------------------- - * Networking - *----------------------------------------------------------------------*/ -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ -#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ -#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */ -#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */ -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */ -#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */ -#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */ -#define CONFIG_PHY_RESET_DELAY 1000 -#define CONFIG_NETMASK 255.255.0.0 -#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */ -#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */ -#define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_PING -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT - - -/* Include NetConsole support */ -#define CONFIG_NETCONSOLE - -/* Include auto complete with tabs */ -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "MetroBox=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */ - - -/*----------------------------------------------------------------------- - * Console Buffer - *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ - -/*----------------------------------------------------------------------- - * Memory Test - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Compact Flash (in true IDE mode) - *----------------------------------------------------------------------*/ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */ - -#define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride - to get to the correct offset */ -#define CONFIG_DOS_PARTITION 1 /* Include dos partition */ - -/*----------------------------------------------------------------------- - * PCI - *----------------------------------------------------------------------*/ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices */ -#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE) - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ -#endif - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */ - -#endif /* __CONFIG_H */ -- cgit v1.2.3 From 1521cdc5303db2a3ec5a09231fbaa5831561bf71 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:37:58 +0900 Subject: powerpc: ppc4xx: remove board support for CRAYL1 This board has been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/ppc4xx/Kconfig | 4 - board/cray/L1/.gitignore | 2 - board/cray/L1/Kconfig | 12 -- board/cray/L1/L1.c | 350 ------------------------------- board/cray/L1/MAINTAINERS | 6 - board/cray/L1/Makefile | 23 -- board/cray/L1/bootscript.hush | 117 ----------- board/cray/L1/flash.c | 451 ---------------------------------------- board/cray/L1/init.S | 117 ----------- board/cray/L1/patchme | 30 --- board/cray/L1/u-boot.lds.debug | 121 ----------- board/cray/L1/x2c.awk | 6 - configs/CRAYL1_defconfig | 3 - doc/README.scrapyard | 1 + include/configs/CRAYL1.h | 228 -------------------- 15 files changed, 1 insertion(+), 1470 deletions(-) delete mode 100644 board/cray/L1/.gitignore delete mode 100644 board/cray/L1/Kconfig delete mode 100644 board/cray/L1/L1.c delete mode 100644 board/cray/L1/MAINTAINERS delete mode 100644 board/cray/L1/Makefile delete mode 100644 board/cray/L1/bootscript.hush delete mode 100644 board/cray/L1/flash.c delete mode 100644 board/cray/L1/init.S delete mode 100644 board/cray/L1/patchme delete mode 100644 board/cray/L1/u-boot.lds.debug delete mode 100644 board/cray/L1/x2c.awk delete mode 100644 configs/CRAYL1_defconfig delete mode 100644 include/configs/CRAYL1.h diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 7c645f1cdb..d525ad3bd6 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -106,9 +106,6 @@ config TARGET_FX12MM config TARGET_V5FX30TEVAL bool "Support v5fx30teval" -config TARGET_CRAYL1 - bool "Support CRAYL1" - config TARGET_CATCENTER bool "Support CATcenter" @@ -260,7 +257,6 @@ source "board/amcc/yosemite/Kconfig" source "board/amcc/yucca/Kconfig" source "board/avnet/fx12mm/Kconfig" source "board/avnet/v5fx30teval/Kconfig" -source "board/cray/L1/Kconfig" source "board/csb272/Kconfig" source "board/csb472/Kconfig" source "board/dave/PPChameleonEVB/Kconfig" diff --git a/board/cray/L1/.gitignore b/board/cray/L1/.gitignore deleted file mode 100644 index cd76d660ef..0000000000 --- a/board/cray/L1/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -bootscript.c -bootscript.image diff --git a/board/cray/L1/Kconfig b/board/cray/L1/Kconfig deleted file mode 100644 index 35a290af61..0000000000 --- a/board/cray/L1/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CRAYL1 - -config SYS_BOARD - default "L1" - -config SYS_VENDOR - default "cray" - -config SYS_CONFIG_NAME - default "CRAYL1" - -endif diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c deleted file mode 100644 index d706ff10d3..0000000000 --- a/board/cray/L1/L1.c +++ /dev/null @@ -1,350 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define L1_MEMSIZE (32*1024*1024) - -/* the std. DHCP stufff */ -#define DHCP_ROUTER 3 -#define DHCP_NETMASK 1 -#define DHCP_BOOTFILE 67 -#define DHCP_ROOTPATH 17 -#define DHCP_HOSTNAME 12 - -/* some extras used by CRAY - * - * on the server this looks like: - * - * option L1-initrd-image code 224 = string; - * option L1-initrd-image "/opt/craysv2/craymcu/l1/flash/initrd.image" - */ -#define DHCP_L1_INITRD 224 - -/* new, [better?] way via official vendor-extensions, defining an option - * space. - * on the server this looks like: - * - * option space CRAYL1; - * option CRAYL1.initrd code 3 = string; - * ..etc... - */ -#define DHCP_VENDOR_SPECX 43 -#define DHCP_VX_INITRD 3 -#define DHCP_VX_BOOTCMD 4 -#define DHCP_VX_BOOTARGS 5 -#define DHCP_VX_ROOTDEV 6 -#define DHCP_VX_FROMFLASH 7 -#define DHCP_VX_BOOTSCRIPT 8 -#define DHCP_VX_RCFILE 9 -#define DHCP_VX_MAGIC 10 - -/* Things DHCP server can tellme about. If there's no flash address, then - * they dont participate in 'update' to flash, and we force their values - * back to '0' every boot to be sure to get them fresh from DHCP. Yes, I - * know this is a pain... - * - * If I get no bootfile, boot from flash. If rootpath, use that. If no - * rootpath use initrd in flash. - */ -typedef struct dhcp_item_s { - u8 dhcp_option; - u8 dhcp_vendor_option; - char *dhcpvalue; - char *envname; -} dhcp_item_t; -static dhcp_item_t Things[] = { - {DHCP_ROUTER, 0, NULL, "gateway"}, - {DHCP_NETMASK, 0, NULL, "netmask"}, - {DHCP_BOOTFILE, 0, NULL, "bootfile"}, - {DHCP_ROOTPATH, 0, NULL, "rootpath"}, - {DHCP_HOSTNAME, 0, NULL, "hostname"}, - {DHCP_L1_INITRD, 0, NULL, "initrd"}, -/* and the other way.. */ - {DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"}, - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"}, - {DHCP_VENDOR_SPECX, DHCP_VX_FROMFLASH, NULL, "fromflash"}, - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTSCRIPT, NULL, "bootscript"}, - {DHCP_VENDOR_SPECX, DHCP_VX_RCFILE, NULL, "rcfile"}, - {DHCP_VENDOR_SPECX, DHCP_VX_BOOTARGS, NULL, "xbootargs"}, - {DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL}, - {DHCP_VENDOR_SPECX, DHCP_VX_MAGIC, NULL, NULL} -}; - -#define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t))) - -extern char bootscript[]; - -/* Here is the boot logic as HUSH script. Overridden by any TFP provided - * bootscript file. - */ - -static void init_sdram (void); - -/* ------------------------------------------------------------------------- */ -int board_early_init_f (void) -{ - /* Running from ROM: global data is still READONLY */ - init_sdram (); - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFFE0); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - return 0; -} - -/* ------------------------------------------------------------------------- */ -int checkboard (void) -{ - return (0); -} -/* ------------------------------------------------------------------------- */ - -/* ------------------------------------------------------------------------- */ -int misc_init_r (void) -{ - char *s, *e; - image_header_t *hdr; - time_t timestamp; - struct rtc_time tm; - char bootcmd[32]; - - hdr = (image_header_t *) (CONFIG_SYS_MONITOR_BASE - image_get_header_size ()); -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - timestamp = (time_t)image_get_time (hdr); - to_tm (timestamp, &tm); - printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); - -#define FACTORY_SETTINGS 0xFFFC0000 - if ((s = getenv ("ethaddr")) == NULL) { - e = (char *) (FACTORY_SETTINGS); - if (*(e + 0) != '0' - || *(e + 1) != '0' - || *(e + 2) != ':' - || *(e + 3) != '4' || *(e + 4) != '0' || *(e + 17) != '\0') { - printf ("No valid MAC address in flash location 0x3C0000!\n"); - } else { - printf ("Factory MAC: %s\n", e); - setenv ("ethaddr", e); - } - } - sprintf (bootcmd,"source %X",(unsigned)bootscript); - setenv ("bootcmd", bootcmd); - return (0); -} - -/* ------------------------------------------------------------------------- */ -/* stubs so we can print dates w/o any nvram RTC.*/ -int rtc_get (struct rtc_time *tmp) -{ - return 0; -} -int rtc_set (struct rtc_time *tmp) -{ - return 0; -} -void rtc_reset (void) -{ - return; -} - -/* ------------------------------------------------------------------------- */ -/* Do sdram bank init in C so I can read it..no console to print to yet! - */ -static void init_sdram (void) -{ - unsigned long tmp; - - /* write SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - mtdcr (SDRAM0_CFGDATA, 0x00062001); - -/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */ -/* To set the appropriate timings, we need to know the SDRAM speed. */ -/* We can use the PLB speed since the SDRAM speed is the same as */ -/* the PLB speed. The PLB speed is the FBK divider times the */ -/* 405GP reference clock, which on the L1 is 25MHz. */ -/* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is */ -/* 150MHz; if FBK is 3, SDRAM is 150MHz. */ - - /* divisor = ((mfdcr(strap)>> 28) & 0x3); */ - -/* write SDRAM timing for 100MHz. */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); - mtdcr (SDRAM0_CFGDATA, 0x0086400D); - -/* write SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); - mtdcr (SDRAM0_CFGDATA, 0x05F00000); - udelay (200); - -/* sdram controller.*/ - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - mtdcr (SDRAM0_CFGDATA, 0x90800000); - udelay (200); - -/* initially, disable ECC on all banks */ - udelay (200); - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - tmp = mfdcr (SDRAM0_CFGDATA); - tmp &= 0xff0fffff; - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - mtdcr (SDRAM0_CFGDATA, tmp); - - return; -} - -extern int memory_post_test (int flags); - -int testdram (void) -{ - unsigned long tmp; - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) L1_MEMSIZE; - uint *p; - - if (getenv_f("booted",NULL,0) <= 0) - { - printf ("testdram.."); - /*AA*/ - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", - (uint) p, *p, 0xaaaaaaaa); - return 1; - } - } - /*55*/ - for (p = pstart; p < pend; p++) - *p = 0x55555555; - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", - (uint) p, *p, 0x55555555); - return 1; - } - } - /*addr*/ - for (p = pstart; p < pend; p++) - *p = (unsigned)p; - for (p = pstart; p < pend; p++) { - if (*p != (unsigned)p) { - printf ("SDRAM test fails at: %08x, was %08x expected %08x\n", - (uint) p, *p, (uint)p); - return 1; - } - } - printf ("Success. "); - } - printf ("Enable ECC.."); - - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - mtdcr (SDRAM0_CFGDATA, tmp); - udelay (600); - for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L) - ; - udelay (400); - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - tmp = mfdcr (SDRAM0_CFGDATA); - tmp |= 0x00800000; - mtdcr (SDRAM0_CFGDATA, tmp); - udelay (400); - printf ("enabled.\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ -static u8 *dhcp_env_update (u8 thing, u8 * pop) -{ - u8 i, oplen; - - oplen = *(pop + 1); - - if ((Things[thing].dhcpvalue = malloc (oplen)) == NULL) { - printf ("Whoops! failed to malloc space for DHCP thing %s\n", - Things[thing].envname); - return NULL; - } - for (i = 0; (i < oplen); i++) - if ((*(Things[thing].dhcpvalue + i) = *(pop + 2 + i)) == ' ') - break; - *(Things[thing].dhcpvalue + i) = '\0'; - -/* set env. */ - if (Things[thing].envname) - { - setenv (Things[thing].envname, Things[thing].dhcpvalue); - } - return ((u8 *)(Things[thing].dhcpvalue)); -} - -/* ------------------------------------------------------------------------- */ -u8 *dhcp_vendorex_prep (u8 * e) -{ - u8 thing; - -/* ask for the things I want. */ - *e++ = 55; /* Parameter Request List */ - *e++ = N_THINGS; - for (thing = 0; thing < N_THINGS; thing++) - *e++ = Things[thing].dhcp_option; - *e++ = 255; - - return e; -} - -/* ------------------------------------------------------------------------- */ -/* .. return NULL means it wasnt mine, non-null means I got it..*/ -u8 *dhcp_vendorex_proc (u8 * pop) -{ - u8 oplen, *sub_op, sub_oplen, *retval; - u8 thing = 0; - - retval = NULL; - oplen = *(pop + 1); -/* if pop is vender spec indicator, there are sub-options. */ - if (*pop == DHCP_VENDOR_SPECX) { - for (sub_op = pop + 2; - oplen && (sub_oplen = *(sub_op + 1)); - oplen -= sub_oplen, sub_op += (sub_oplen + 2)) { - for (thing = 0; thing < N_THINGS; thing++) { - if (*sub_op == Things[thing].dhcp_vendor_option) { - if (!(retval = dhcp_env_update (thing, sub_op))) { - return NULL; - } - } - } - } - } else { - for (thing = 0; thing < N_THINGS; thing++) { - if (*pop == Things[thing].dhcp_option) - if (!(retval = dhcp_env_update (thing, pop))) - return NULL; - } - } - return (pop); -} diff --git a/board/cray/L1/MAINTAINERS b/board/cray/L1/MAINTAINERS deleted file mode 100644 index e43e91febe..0000000000 --- a/board/cray/L1/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -L1 BOARD -#M: David Updegraff -S: Orphan (since 2014-03) -F: board/cray/L1/ -F: include/configs/CRAYL1.h -F: configs/CRAYL1_defconfig diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile deleted file mode 100644 index 716a5a316b..0000000000 --- a/board/cray/L1/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = L1.o flash.o -obj-y += init.o -obj-y += bootscript.o - -quiet_cmd_awk = AWK $@ - cmd_awk = od -t x1 -v -A x $< | $(AWK) -f $(filter-out $<,$^) > $@ - -$(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk - $(call cmd,awk) - -MKIMAGEFLAGS_bootscript.image := -A ppc -O linux -T script -C none \ - -a 0 -e 0 -n bootscript -$(obj)/bootscript.image: $(src)/bootscript.hush - $(call cmd,mkimage) - -clean-files := bootscript.c bootscript.image diff --git a/board/cray/L1/bootscript.hush b/board/cray/L1/bootscript.hush deleted file mode 100644 index f2f78ad5c3..0000000000 --- a/board/cray/L1/bootscript.hush +++ /dev/null @@ -1,117 +0,0 @@ -# $Header$ -# hush bootscript for PPCBOOT on L1 -# note: all #s are in hex, do _NOT_ prefix it with 0x - -flash_rfs=ffc00000 -flash_krl=fff00000 -tftp_addr=100000 -tftp2_addr=1000000 - -if printenv booted -then - echo already booted before -else - echo first boot in environment, create and save settings - setenv booted OK - saveenv -fi - -setenv autoload no -# clear out stale env stuff, so we get fresh from dhcp. -for setting in initrd fromflash kernel rootfs rootpath -do -setenv $setting -done - -dhcp - -# if host provides us with a different bootscript, us it. -if printenv bootscript - then - tftp $tftp_addr $bootcript - if imi $tftp_addr - then - source $tftp_addr - fi -fi - -# default base kernel arguments. -setenv bootargs $xbootargs devfs=mount ip=$ipaddr:$serverip:$gatewayip:$netmask:L1:eth0:off wdt=120 - -# Have a kernel in flash? -if imi $flash_krl -then - echo ok kernel to boot from $flash_krl - setenv kernel $flash_krl -else - echo no kernel to boot from $flash_krl, need tftp -fi - -# Have a rootfs in flash? -echo test for SQUASHfs at $flash_rfs - -if imi $flash_rfs -then - echo appears to be a good initrd image at base of flash OK - setenv rootfs $flash_rfs -else - echo no image at base of flash, need nfsroot or initrd -fi - -# I boot from flash if told to and I can. -if printenv fromflash && printenv kernel && printenv rootfs -then - echo booting entirely from flash - setenv bootargs root=/dev/ram0 rw $bootargs - bootm $kernel $rootfs - echo oh no failed so I try some other stuff -fi - -# TFTP down a kernel -if printenv bootfile -then - tftp $tftp_addr $bootfile - setenv kernel $tftp_addr - echo I will boot the TFTP kernel -else - if printenv kernel - then - echo no bootfile specified, will use one from flash - else - setenv bootfile /opt/crayx1/craymcu/l1/flash/linux.image - echo OH NO! we have no bootfile,nor flash kernel! try default: $bootfile - tftp $tftp_addr $bootfile - setenv kernel $tftp_addr - fi -fi - -# the rootfs. -if printenv rootpath -then - echo rootpath is $rootpath - if printenv initrd - then - echo initrd is also specified, so use $initrd - tftp $tftp2_addr $initrd - setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs - bootm $kernel $tftp2_addr - else - echo initrd is not specified, so use NFSROOT $rootpat - setenv bootargs root=/dev/nfs ro nfsroot=$serverip:$rootpath $bootargs - bootm $kernel - fi -else - echo we have no rootpath check for one in flash - if printenv rootfs - then - echo I will use the one in flash - setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs - bootm $kernel - else - setenv rootpath /export/crayl1 - echo OH NO! we have no rootpath,nor flash kernel! try default: $rootpath - setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs - bootm $kernel - fi -fi -reset diff --git a/board/cray/L1/flash.c b/board/cray/L1/flash.c deleted file mode 100644 index 96a1e474a5..0000000000 --- a/board/cray/L1/flash.c +++ /dev/null @@ -1,451 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -/* - * Modified July 20, 2001 - * Strip down to support ONLY the AMD29F032B. - * Dave Updegraff - Cray, Inc. dave@cray.com - */ - -#include -#include -#include - -/* The flash chip we use... */ -#define AMD_ID_F032B 0x41 /* 29F032B ID 32 Mbit,64 64Kx8 sectors */ -#define FLASH_AM320B 0x0009 - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; isector_count; i++) - info->start[i] = base + (i * 0x00010000); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM320B:printf ("AM29F032B (32 Mbit 64x64KB uniform sectors)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; kstart[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_F032B: - info->flash_id += FLASH_AM320B; - info->sector_count = 64; - info->size = 0x0400000; /* => 4 MB */ - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -int wait_for_DQ7(flash_info_t *info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - printf("Erasing sector %p\n", addr2); - - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *)dest) & - (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) - { - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S deleted file mode 100644 index d4723c733f..0000000000 --- a/board/cray/L1/init.S +++ /dev/null @@ -1,117 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ - -/*----------------------------------------------------------------------------- */ -/* Function: ext_bus_cntlr_init */ -/* Description: Initializes the External Bus Controller for the external */ -/* peripherals. IMPORTANT: For pass1 this code must run from */ -/* cache since you can not reliably change a peripheral banks */ -/* timing register (pbxap) while running code from that bank. */ -/* For ex., since we are running from ROM on bank 0, we can NOT */ -/* execute the code that modifies bank 0 timings from ROM, so */ -/* we run it from cache. */ -/* Bank 0 - Flash and SRAM */ -/* Bank 1 - NVRAM/RTC */ -/* Bank 2 - Keyboard/Mouse controller */ -/* Bank 3 - IR controller */ -/* Bank 4 - not used */ -/* Bank 5 - not used */ -/* Bank 6 - not used */ -/* Bank 7 - FPGA registers */ -/*-----------------------------------------------------------------------------#include */ -#include - -#include -#include - -#include -#include - -/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */ -/* except for #1 which we use for DMA'ing to IOCA-like things, so the */ -/* control registers to set that up are determined by what we've */ -/* empirically discovered work there. */ - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - mflr r4 /* save link register */ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 10; used to prefetch */ - mtctr r4 /* 10 cache lines to fit this function */ - /* in cache (gives us 8x10=80 instrctns) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 10 cache lines */ - - /*------------------------------------------------------------------- */ - /* Delay to ensure all accesses to ROM are complete before changing */ - /* bank 0 timings. 200usec should be enough. */ - /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ - /*------------------------------------------------------------------- */ - addis r3,0,0x0 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - - /*---------------------------------------------------------------------- */ - /* Peripheral Bank 0 (Flash) initialization */ - /*---------------------------------------------------------------------- */ - /* 0x7F8FFE80 slowest boot */ - addi r4,0,PB1AP - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x9B01 - ori r4,r4,0x5480 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB0CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */ - ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr EBC0_CFGDATA,r4 - - blr - - /*---------------------------------------------------------------------- */ - /* Peripheral Bank 1 (NVRAM/RTC) initialization */ - /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */ - /* and we do DMA on it. The ConfigurationRegister part is threfore */ - /* almost arbitrary, except that our linux driver needs to know the */ - /* address, but it can query, it.. */ - /* */ - /* The AccessParameter is CRITICAL, */ - /* thouch, since it needs to agree with the electrical timings on the */ - /* IOCA parallel interface. That value is: 0x0185,4380 */ - /* BurstModeEnable BME=0 */ - /* TransferWait TWT=3 */ - /* ChipSelectOnTiming CSN=1 */ - /* OutputEnableOnTimimg OEN=1 */ - /* WriteByteEnableOnTiming WBN=1 */ - /* WriteByteEnableOffTiming WBF=0 */ - /* TransferHold TH=1 */ - /* ReadyEnable RE=1 */ - /* SampleOnReady SOR=1 */ - /* ByteEnableMode BEM=0 */ - /* ParityEnable PEN=0 */ - /* all reserved bits=0 */ - /*---------------------------------------------------------------------- */ - /*---------------------------------------------------------------------- */ - addi r4,0,PB1AP - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0185 /* hiword */ - ori r4,r4,0x4380 /* loword */ - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB1CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */ - ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr EBC0_CFGDATA,r4 - - blr diff --git a/board/cray/L1/patchme b/board/cray/L1/patchme deleted file mode 100644 index e77ee7e1f5..0000000000 --- a/board/cray/L1/patchme +++ /dev/null @@ -1,30 +0,0 @@ -# master confi.mk -echo "CROSS_COMPILE = powerpc-linux-" >>include/config.mk - -# patch the examples/Makefile to ignore return value from OBJCOPY -sed -e 's/$(OBJCOPY)/-&/' < examples/Makefile > examples/makefile - -# add a built target for mkimage on the target architecture -sed -e 's/^all:.*$/all: .depend envcrc mkimage mkimage.ppc/' < tools/Makefile > tools/makefile - -cat <>tools/makefile -mkimage.ppc : mkimage.o.ppc crc32.o.ppc - powerpc-linux-gcc -msoft-float -Wall -Wstrict-prototypes -o \$@ \$^ - powerpc-linux-strip $@ - -XFLAGS="-D__KERNEL__ -I../include -DCONFIG_4xx -Wall -Wstict-prototypes" -mkimage.o.ppc: mkimage.c - powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^ - -crc32.o.ppc: crc32.c - powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^ - -EOF - -# make an image by default out of the u-boot image -sed -e 's/^all:.*$/all: u-boot.image /' < Makefile > makefile -cat <>makefile -u-boot.image: u-boot.bin - tools/mkimage -A ppc -O linux -T firmware -C none -a 0 -e 0 -n U-Boot -d \$^ \$@ - -EOF diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug deleted file mode 100644 index 890f592e9b..0000000000 --- a/board/cray/L1/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/cray/L1/x2c.awk b/board/cray/L1/x2c.awk deleted file mode 100644 index 9235e6cb36..0000000000 --- a/board/cray/L1/x2c.awk +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/awk -BEGIN { print "unsigned char bootscript[] = { \n"} -{ for (i = 2; i <= NF ; i++ ) printf "0x"$i"," - print "" -} -END { print "\n};\n" } diff --git a/configs/CRAYL1_defconfig b/configs/CRAYL1_defconfig deleted file mode 100644 index ad6cbac815..0000000000 --- a/configs/CRAYL1_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_CRAYL1=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 92ba1e411a..48e94ab0aa 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +CRAYL1 powerpc ppc4xx - - David Updegraff KAREF powerpc ppc4xx - - Travis Sawyer METROBOX powerpc ppc4xx - - Travis Sawyer PK1C20 nios2 - 70fbc461 2014-08-24 Scott McNutt diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h deleted file mode 100644 index 788fa0f91c..0000000000 --- a/include/configs/CRAYL1.h +++ /dev/null @@ -1,228 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * David Updegraff, Cray, Inc. dave@cray.com: our 405 is walnut-lite.. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_CRAYL1 -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ - -/* - * Note: I make an "image" from U-Boot itself, which prefixes 0x40 - * bytes of header info, hence start address is thus shifted. - */ -#define CONFIG_SYS_TEXT_BASE 0xFFFD0040 - -#define CONFIG_SYS_CLK_FREQ 25000000 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */ -#define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to - * keep possible initrd ramdisk decompression out. This is in k (1024 bytes) - #define CONFIG_PRAM 16 - */ -#define CONFIG_LOADADDR 0x100000 /* where TFTP images go */ -#undef CONFIG_BOOTARGS - -/* Bootcmd is overridden by the bootscript in board/cray/L1 - */ -#define CONFIG_SYS_AUTOLOAD "no" -#define CONFIG_BOOTCOMMAND "dhcp" - -/* - * ..during experiments.. - #define CONFIG_SERVERIP 10.0.0.1 - #define CONFIG_ETHADDR 00:40:a6:80:14:5 - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SDRAM_BANK0 1 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_IDENT_STRING "Cray L1" -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_SYS_HUSH_PARSER 1 -#define CONFIG_SOURCE 1 - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BDI -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_SETGETDCR -#define CONFIG_CMD_SOURCE - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_VENDOREX -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * how many time to fail & restart a net-TFTP before giving up & resetting - * the board hoping that a reset of net interface might help.. - */ -#define CONFIG_NET_RESET 5 - -/* - * bauds. Just to make it compile; in our case, I read the base_baud - * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn - * drives the system clock. - */ -#define CONFIG_SYS_BASE_BAUD 403225 -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* where to load what we get from TFTP */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_DRAM_TEST 1 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - - -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */ -#define CONFIG_ENV_OFFSET 0x3c8000 -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment area */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ - -/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at - * 32meg-(128k+some_malloc_space+copy-of-ENV sector).. - */ -#define CONFIG_SYS_SDRAM_SIZE 32 /* megs of ram */ -#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */ - /* the exception vector table */ - /* to the end of the DRAM */ - /* less monitor and malloc area */ -#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128k for malloc space */ -#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ - + CONFIG_SYS_MALLOC_LEN \ - + CONFIG_ENV_SECT_SIZE \ - + CONFIG_SYS_STACK_USAGE ) - -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 - CONFIG_SYS_MEM_END_USAGE) -/* END ENVIRONNEMENT FLASH */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in OnChipMem ) - */ -#if 1 -/* On Chip Memory location */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#else -#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#endif - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - */ -#define EEPROM_WRITE_ADDRESS 0xA0 -#define EEPROM_READ_ADDRESS 0xA1 - -#endif /* __CONFIG_H */ -- cgit v1.2.3 From 9ed3246e19a42392bf0fd676dcbbe3539cc46ec1 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:37:59 +0900 Subject: powerpc: ppc4xx: remove board support for bluestone This board has been orphaned for more than 6 months. It is the last board defining CONFIG_APM821XX. The code inside #ifdef CONFIG_APM821XX should be removed too. Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/ppc4xx/Kconfig | 4 - arch/powerpc/cpu/ppc4xx/cpu.c | 14 --- arch/powerpc/cpu/ppc4xx/cpu_init.c | 4 +- arch/powerpc/cpu/ppc4xx/speed.c | 75 +------------- arch/powerpc/cpu/ppc4xx/start.S | 8 +- arch/powerpc/include/asm/apm821xx.h | 59 ----------- arch/powerpc/include/asm/ppc4xx-ebc.h | 3 +- arch/powerpc/include/asm/ppc4xx-isram.h | 10 +- arch/powerpc/include/asm/ppc4xx-sdram.h | 12 +-- arch/powerpc/include/asm/ppc4xx-uic.h | 5 +- arch/powerpc/include/asm/ppc4xx.h | 4 - board/amcc/bluestone/Kconfig | 12 --- board/amcc/bluestone/MAINTAINERS | 6 -- board/amcc/bluestone/Makefile | 9 -- board/amcc/bluestone/bluestone.c | 99 ------------------- board/amcc/bluestone/config.mk | 18 ---- board/amcc/bluestone/init.S | 45 --------- configs/bluestone_defconfig | 3 - doc/README.scrapyard | 1 + include/configs/bluestone.h | 168 -------------------------------- 20 files changed, 19 insertions(+), 540 deletions(-) delete mode 100644 arch/powerpc/include/asm/apm821xx.h delete mode 100644 board/amcc/bluestone/Kconfig delete mode 100644 board/amcc/bluestone/MAINTAINERS delete mode 100644 board/amcc/bluestone/Makefile delete mode 100644 board/amcc/bluestone/bluestone.c delete mode 100644 board/amcc/bluestone/config.mk delete mode 100644 board/amcc/bluestone/init.S delete mode 100644 configs/bluestone_defconfig delete mode 100644 include/configs/bluestone.h diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index d525ad3bd6..56abe8dc56 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -52,9 +52,6 @@ config TARGET_ACADIA config TARGET_BAMBOO bool "Support bamboo" -config TARGET_BLUESTONE - bool "Support bluestone" - config TARGET_BUBINGA bool "Support bubinga" @@ -239,7 +236,6 @@ endchoice source "board/amcc/acadia/Kconfig" source "board/amcc/bamboo/Kconfig" -source "board/amcc/bluestone/Kconfig" source "board/amcc/bubinga/Kconfig" source "board/amcc/canyonlands/Kconfig" source "board/amcc/ebony/Kconfig" diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c index 6a485264e7..aab65d405c 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu.c +++ b/arch/powerpc/cpu/ppc4xx/cpu.c @@ -234,20 +234,6 @@ static char *bootstrap_str[] = { }; static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; #endif -#if defined(CONFIG_APM821XX) -#define SDR0_PINSTP_SHIFT 29 -static char *bootstrap_str[] = { - "RESERVED", - "RESERVED", - "RESERVED", - "NAND (8 bits)", - "NOR (8 bits)", - "NOR (8 bits) w/PLL Bypassed", - "I2C (Addr 0x54)", - "I2C (Addr 0x52)", -}; -static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; -#endif #if defined(SDR0_PINSTP_SHIFT) static int bootstrap_option(void) diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index 0b27d2912d..22561231cb 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -284,7 +284,7 @@ cpu_init_f (void) reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \ - !defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE) + !defined(CONFIG_SYS_4xx_GPIO_TABLE) /* * GPIO0 setup (select GPIO or alternate function) */ @@ -440,7 +440,7 @@ cpu_init_f (void) #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 4baee7774c..3e1a7016d9 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -171,7 +171,7 @@ ulong get_PCI_freq (void) #elif defined(CONFIG_440) #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) static u8 pll_fwdv_multi_bits[] = { /* values for: 1 - 16 */ 0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c, @@ -232,78 +232,6 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv) return 0; } -#if defined(CONFIG_APM821XX) - -void get_sys_info(sys_info_t *sysInfo) -{ - unsigned long plld; - unsigned long temp; - unsigned long mul; - unsigned long cpudv; - unsigned long plb2dv; - unsigned long ddr2dv; - - /* Calculate Forward divisor A and Feeback divisor */ - mfcpr(CPR0_PLLD, plld); - - temp = CPR0_PLLD_FWDVA(plld); - sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); - - temp = CPR0_PLLD_FDV(plld); - sysInfo->pllFbkDiv = get_cpr0_fbdv(temp); - - /* Calculate OPB clock divisor */ - mfcpr(CPR0_OPBD, temp); - temp = CPR0_OPBD_OPBDV(temp); - sysInfo->pllOpbDiv = temp ? temp : 4; - - /* Calculate Peripheral clock divisor */ - mfcpr(CPR0_PERD, temp); - temp = CPR0_PERD_PERDV(temp); - sysInfo->pllExtBusDiv = temp ? temp : 4; - - /* Calculate CPU clock divisor */ - mfcpr(CPR0_CPUD, temp); - temp = CPR0_CPUD_CPUDV(temp); - cpudv = temp ? temp : 8; - - /* Calculate PLB2 clock divisor */ - mfcpr(CPR0_PLB2D, temp); - temp = CPR0_PLB2D_PLB2DV(temp); - plb2dv = temp ? temp : 4; - - /* Calculate DDR2 clock divisor */ - mfcpr(CPR0_DDR2D, temp); - temp = CPR0_DDR2D_DDR2DV(temp); - ddr2dv = temp ? temp : 4; - - /* Calculate 'M' based on feedback source */ - mfcpr(CPR0_PLLC, temp); - temp = CPR0_PLLC_SEL(temp); - if (temp == 0) { - /* PLL internal feedback */ - mul = sysInfo->pllFbkDiv; - } else { - /* PLL PerClk feedback */ - mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv - * plb2dv * 2 * sysInfo->pllOpbDiv * - sysInfo->pllExtBusDiv; - } - - /* Now calculate the individual clocks */ - sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1); - sysInfo->freqProcessor = sysInfo->freqVCOMhz / - sysInfo->pllFwdDivA / cpudv; - sysInfo->freqPLB = sysInfo->freqVCOMhz / - sysInfo->pllFwdDivA / cpudv / plb2dv / 2; - sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv; - sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv; - sysInfo->freqDDR = sysInfo->freqVCOMhz / - sysInfo->pllFwdDivA / cpudv / ddr2dv / 2; - sysInfo->freqUART = sysInfo->freqPLB; -} - -#else /* * AMCC_TODO: verify this routine against latest EAS, cause stuff changed * with latest EAS @@ -361,7 +289,6 @@ void get_sys_info (sys_info_t * sysInfo) return; } -#endif #elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 11b55d5a56..09a02d771c 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -664,8 +664,7 @@ _start: defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460SX) mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) lis r1, 0x0000 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ mtdcr L2_CACHE_CFG,r1 @@ -694,7 +693,7 @@ _start: ori r1,r1, 0x0980 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \ - defined(CONFIG_460GT) || defined(CONFIG_APM821XX) + defined(CONFIG_460GT) lis r1,0x0000 /* BAS = X_0000_0000 */ ori r1,r1,0x0984 /* first 64k */ mtdcr ISRAM0_SB0CR,r1 @@ -707,8 +706,7 @@ _start: lis r1, 0x0003 ori r1,r1, 0x0984 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) lis r2,0x7fff ori r2,r2,0xffff mfdcr r1,ISRAM1_DPC diff --git a/arch/powerpc/include/asm/apm821xx.h b/arch/powerpc/include/asm/apm821xx.h deleted file mode 100644 index d027866d3d..0000000000 --- a/arch/powerpc/include/asm/apm821xx.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _APM821XX_H_ -#define _APM821XX_H_ - -#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ - -/* Memory mapped registers */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) - -#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) - -#define SDR0_SRST0_DMC 0x00200000 -#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ - -/* AHB config. */ -#define AHB_TOP 0xA4 -#define AHB_BOT 0xA5 - -/* clk divisors */ -#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ -#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ -#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ -#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ -#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ -#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ -#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000/* PLB Early Clk Div*/ -#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ -#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ - -/* - + * Clocking Controller - + */ -#define CPR0_CLKUPD 0x0020 -#define CPR0_PLLC 0x0040 -#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24) -#define CPR0_PLLD 0x0060 -#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24) -#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16) -#define CPR0_CPUD 0x0080 -#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24) -#define CPR0_PLB2D 0x00a0 -#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25) -#define CPR0_OPBD 0x00c0 -#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24) -#define CPR0_PERD 0x00e0 -#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24) -#define CPR0_DDR2D 0x0100 -#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25) -#define CLK_ICFG 0x0140 - -#endif /* _APM821XX_H_ */ diff --git a/arch/powerpc/include/asm/ppc4xx-ebc.h b/arch/powerpc/include/asm/ppc4xx-ebc.h index 07a3fe033f..952783f961 100644 --- a/arch/powerpc/include/asm/ppc4xx-ebc.h +++ b/arch/powerpc/include/asm/ppc4xx-ebc.h @@ -53,8 +53,7 @@ #define EBC_NUM_BANKS 6 #endif -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define EBC_NUM_BANKS 3 #endif diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h index 4d1106b124..2ae399f248 100644 --- a/arch/powerpc/include/asm/ppc4xx-isram.h +++ b/arch/powerpc/include/asm/ppc4xx-isram.h @@ -8,8 +8,7 @@ /* * Internal SRAM */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define ISRAM0_DCR_BASE 0x380 #else #define ISRAM0_DCR_BASE 0x020 @@ -26,8 +25,7 @@ #define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ #define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) #define ISRAM1_DCR_BASE 0x0B0 #define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ #define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ @@ -41,8 +39,6 @@ #if defined(CONFIG_460EX) || defined(CONFIG_460GT) #define ISRAM1_SIZE 0x0984 /* OCM size 64k */ -#elif defined(CONFIG_APM821XX) -#define ISRAM1_SIZE 0x0784 /* OCM size 32k */ #endif /* @@ -51,7 +47,7 @@ #if defined (CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) #define L2_CACHE_BASE 0x030 #define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */ #define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */ diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index 12d6d038c7..e6fed83bf1 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -276,7 +276,7 @@ */ #if defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) @@ -349,7 +349,7 @@ /* * Memory controller registers */ -#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) +#if defined(CONFIG_405EX) #define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ #define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ #define SDRAM_BEARL 0x02 /* PLB bus error address low */ @@ -359,9 +359,9 @@ #define SDRAM_PLBOPT 0x08 /* PLB slave options */ #define SDRAM_PUABA 0x09 /* PLB upper address base */ #define SDRAM_MCSTAT 0x1F /* memory controller status */ -#else /* CONFIG_405EX || CONFIG_APM821XX */ +#else /* CONFIG_405EX */ #define SDRAM_MCSTAT 0x14 /* memory controller status */ -#endif /* CONFIG_405EX || CONFIG_APM821XX */ +#endif /* CONFIG_405EX */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ @@ -407,12 +407,12 @@ #define SDRAM_MEMODE 0x89 /* memory extended mode */ #define SDRAM_ECCES 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ -#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX) +#if !defined(CONFIG_405EX) #define SDRAM_RID 0xA8 /* revision ID */ #endif #define SDRAM_FCSR 0xB0 /* feedback calibration status */ #define SDRAM_RTSR 0xB1 /* run time status tracking */ -#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) +#if defined(CONFIG_405EX) #define SDRAM_RID 0xF8 /* revision ID */ #endif diff --git a/arch/powerpc/include/asm/ppc4xx-uic.h b/arch/powerpc/include/asm/ppc4xx-uic.h index 05b4690a5c..58e65c1336 100644 --- a/arch/powerpc/include/asm/ppc4xx-uic.h +++ b/arch/powerpc/include/asm/ppc4xx-uic.h @@ -15,7 +15,7 @@ */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) || defined(CONFIG_APM821XX) + defined(CONFIG_460SX) #define UIC_MAX 4 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) @@ -236,8 +236,7 @@ #define VECNUM_ETH0 (32 + 28) #endif /* CONFIG_440SPE */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_APM821XX) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) /* UIC 0 */ #define VECNUM_UIC2NCI 10 #define VECNUM_UIC2CI 11 diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h index e6a3bff079..b8b0ff9f25 100644 --- a/arch/powerpc/include/asm/ppc4xx.h +++ b/arch/powerpc/include/asm/ppc4xx.h @@ -56,10 +56,6 @@ #include #endif -#if defined(CONFIG_APM821XX) -#include -#endif - /* * Common registers for all SoC's */ diff --git a/board/amcc/bluestone/Kconfig b/board/amcc/bluestone/Kconfig deleted file mode 100644 index 255e013777..0000000000 --- a/board/amcc/bluestone/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_BLUESTONE - -config SYS_BOARD - default "bluestone" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "bluestone" - -endif diff --git a/board/amcc/bluestone/MAINTAINERS b/board/amcc/bluestone/MAINTAINERS deleted file mode 100644 index 9eb9bbd01b..0000000000 --- a/board/amcc/bluestone/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BLUESTONE BOARD -#M: Tirumala Marri -S: Orphan (since 2014-03) -F: board/amcc/bluestone/ -F: include/configs/bluestone.h -F: configs/bluestone_defconfig diff --git a/board/amcc/bluestone/Makefile b/board/amcc/bluestone/Makefile deleted file mode 100644 index 07320ce425..0000000000 --- a/board/amcc/bluestone/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (c) 2010, Applied Micro Circuits Corporation -# Author: Tirumala R Marri -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := bluestone.o -extra-y += init.o diff --git a/board/amcc/bluestone/bluestone.c b/board/amcc/bluestone/bluestone.c deleted file mode 100644 index 6520f75c68..0000000000 --- a/board/amcc/bluestone/bluestone.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Bluestone board support - * - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -int board_early_init_f(void) -{ - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - mtdcr(UIC3ER, 0x00000000); /* disable all */ - mtdcr(UIC3CR, 0x00000000); /* all non-critical */ - mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - - /* - * Configure PFC (Pin Function Control) registers - * UART0: 2 pins - */ - mtsdr(SDR0_PFC1, 0x0000000); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: Bluestone Evaluation Board"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -int misc_init_r(void) -{ - u32 sdr0_srst1 = 0; - - /* Setup PLB4-AHB bridge based on the system address map */ - mtdcr(AHB_TOP, 0x8000004B); - mtdcr(AHB_BOT, 0x8000004B); - - /* - * The AHB Bridge core is held in reset after power-on or reset - * so enable it now - */ - mfsdr(SDR0_SRST1, sdr0_srst1); - sdr0_srst1 &= ~SDR0_SRST1_AHB; - mtsdr(SDR0_SRST1, sdr0_srst1); - - return 0; -} diff --git a/board/amcc/bluestone/config.mk b/board/amcc/bluestone/config.mk deleted file mode 100644 index a947e82af7..0000000000 --- a/board/amcc/bluestone/config.mk +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2010, Applied Micro Circuits Corporation -# Author: Tirumala R Marri -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Applied Micro APM821XX Evaluation board. -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/bluestone/init.S b/board/amcc/bluestone/init.S deleted file mode 100644 index cf22ca6340..0000000000 --- a/board/amcc/bluestone/init.S +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* TLB 0 */ - tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, - 4, AC_RWX | SA_G) - - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, - 0, AC_RWX | SA_G) - - /* TLB-entry for OCM */ - tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4, - AC_RWX | SA_I) - - /* TLB-entry for Local Configuration registers => peripherals */ - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, - CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG) - tlbtab_end diff --git a/configs/bluestone_defconfig b/configs/bluestone_defconfig deleted file mode 100644 index 8f83a4308e..0000000000 --- a/configs/bluestone_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_BLUESTONE=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 48e94ab0aa..036bc838ab 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +bluestone powerpc ppc4xx - - Tirumala Marri CRAYL1 powerpc ppc4xx - - David Updegraff KAREF powerpc ppc4xx - - Travis Sawyer METROBOX powerpc ppc4xx - - Travis Sawyer diff --git a/include/configs/bluestone.h b/include/configs/bluestone.h deleted file mode 100644 index 8bd71c6a15..0000000000 --- a/include/configs/bluestone.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * bluestone.h - configuration for Bluestone (APM821XX) - * - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_APM821XX 1 /* APM821XX series */ -#define CONFIG_HOSTNAME bluestone - -#define CONFIG_440 1 - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 -#endif - -/* - * Include common defines/options for all AMCC eval boards - */ -#include "amcc-common.h" -#define CONFIG_SYS_CLK_FREQ 50000000 - -#define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -/* EBC stuff */ -/* later mapped to this addr */ -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#define CONFIG_SYS_FLASH_SIZE (4 << 20) /* 1MB usable */ - -/* EBC Boot Space: 0xFF000000 */ -#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 -#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */ -#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ -#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals*/ - -#define CONFIG_SYS_SRAM_SIZE (256 << 10) -/* - * Initial RAM & stack pointer (placed in OCM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ -#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Environment - */ -/* - * Define here the location of the environment variables (FLASH). - */ -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -/* - * FLASH related - */ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -/* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 80 -/* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 -/* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 -/* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_FLASH */ - -/* SDRAM */ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */ -#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ -#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ -#define CONFIG_DDR_ECC 1 /* with ECC support */ - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ - -/* - * I2C - */ -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet */ - -/* I2C bootstrap EEPROM */ -#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 -#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 -#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 - -/* - * Ethernet - */ -#define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII -#define CONFIG_HAS_ETH0 -/* PHY address, See schematics */ -#define CONFIG_PHY_ADDR 0x1f -/* reset phy upon startup */ -#define CONFIG_PHY_RESET 1 -/* Include GbE speed/duplex detection */ -#define CONFIG_PHY_GIGE 1 -#define CONFIG_PHY_DYNAMIC_ANEG 1 - -/* - * External Bus Controller (EBC) Setup - **/ -#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_LOCK | \ - EBC_CFG_PTD_ENABLE | \ - EBC_CFG_RTC_2048PERCLK | \ - EBC_CFG_ATC_HI | \ - EBC_CFG_DTC_HI | \ - EBC_CFG_CTC_HI | \ - EBC_CFG_OEO_PREVIOUS) -/* NOR Flash */ -#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ - EBC_BXAP_TWT_ENCODE(64) | \ - EBC_BXAP_BCE_DISABLE | \ - EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(1) | \ - EBC_BXAP_OEN_ENCODE(2) | \ - EBC_BXAP_WBN_ENCODE(2) | \ - EBC_BXAP_WBF_ENCODE(2) | \ - EBC_BXAP_TH_ENCODE(7) | \ - EBC_BXAP_SOR_DELAYED | \ - EBC_BXAP_BEM_WRITEONLY | \ - EBC_BXAP_PEN_DISABLED) -/* Peripheral Bank Configuration Register - EBC_BxCR */ -#define CONFIG_SYS_EBC_PB0CR \ - (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ - EBC_BXCR_BS_1MB | \ - EBC_BXCR_BU_RW | \ - EBC_BXCR_BW_8BIT) - - -#endif /* __CONFIG_H */ -- cgit v1.2.3 From e7a565638a7a727f1a4074c0b39e7de22ff3d6c9 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:38:00 +0900 Subject: powerpc: mpc83xx: remove board support for MERGERBOX and MVBLM7 These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/mpc83xx/Kconfig | 8 - board/matrix_vision/mergerbox/Kconfig | 12 - board/matrix_vision/mergerbox/MAINTAINERS | 6 - board/matrix_vision/mergerbox/Makefile | 8 - board/matrix_vision/mergerbox/README | 59 --- board/matrix_vision/mergerbox/fpga.c | 158 -------- board/matrix_vision/mergerbox/fpga.h | 13 - board/matrix_vision/mergerbox/mergerbox.c | 235 ------------ board/matrix_vision/mergerbox/mergerbox.h | 61 --- board/matrix_vision/mergerbox/pci.c | 128 ------- board/matrix_vision/mergerbox/sm107.c | 120 ------ board/matrix_vision/mvblm7/.gitignore | 1 - board/matrix_vision/mvblm7/Kconfig | 12 - board/matrix_vision/mvblm7/MAINTAINERS | 6 - board/matrix_vision/mvblm7/Makefile | 14 - board/matrix_vision/mvblm7/README.mvblm7 | 84 ----- board/matrix_vision/mvblm7/bootscript | 43 --- board/matrix_vision/mvblm7/fpga.c | 169 --------- board/matrix_vision/mvblm7/fpga.h | 17 - board/matrix_vision/mvblm7/mvblm7.c | 136 ------- board/matrix_vision/mvblm7/mvblm7.h | 20 - board/matrix_vision/mvblm7/pci.c | 89 ----- configs/MERGERBOX_defconfig | 3 - configs/MVBLM7_defconfig | 3 - doc/README.scrapyard | 2 + include/configs/MERGERBOX.h | 599 ------------------------------ include/configs/MVBLM7.h | 491 ------------------------ 27 files changed, 2 insertions(+), 2495 deletions(-) delete mode 100644 board/matrix_vision/mergerbox/Kconfig delete mode 100644 board/matrix_vision/mergerbox/MAINTAINERS delete mode 100644 board/matrix_vision/mergerbox/Makefile delete mode 100644 board/matrix_vision/mergerbox/README delete mode 100644 board/matrix_vision/mergerbox/fpga.c delete mode 100644 board/matrix_vision/mergerbox/fpga.h delete mode 100644 board/matrix_vision/mergerbox/mergerbox.c delete mode 100644 board/matrix_vision/mergerbox/mergerbox.h delete mode 100644 board/matrix_vision/mergerbox/pci.c delete mode 100644 board/matrix_vision/mergerbox/sm107.c delete mode 100644 board/matrix_vision/mvblm7/.gitignore delete mode 100644 board/matrix_vision/mvblm7/Kconfig delete mode 100644 board/matrix_vision/mvblm7/MAINTAINERS delete mode 100644 board/matrix_vision/mvblm7/Makefile delete mode 100644 board/matrix_vision/mvblm7/README.mvblm7 delete mode 100644 board/matrix_vision/mvblm7/bootscript delete mode 100644 board/matrix_vision/mvblm7/fpga.c delete mode 100644 board/matrix_vision/mvblm7/fpga.h delete mode 100644 board/matrix_vision/mvblm7/mvblm7.c delete mode 100644 board/matrix_vision/mvblm7/mvblm7.h delete mode 100644 board/matrix_vision/mvblm7/pci.c delete mode 100644 configs/MERGERBOX_defconfig delete mode 100644 configs/MVBLM7_defconfig delete mode 100644 include/configs/MERGERBOX.h delete mode 100644 include/configs/MVBLM7.h diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 6de9265088..42e0e29668 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -64,12 +64,6 @@ config TARGET_SUVD3 config TARGET_TUXX1 bool "Support tuxx1" -config TARGET_MERGERBOX - bool "Support MERGERBOX" - -config TARGET_MVBLM7 - bool "Support MVBLM7" - config TARGET_TQM834X bool "Support TQM834x" @@ -89,8 +83,6 @@ source "board/freescale/mpc837xemds/Kconfig" source "board/freescale/mpc837xerdb/Kconfig" source "board/ids/ids8313/Kconfig" source "board/keymile/km83xx/Kconfig" -source "board/matrix_vision/mergerbox/Kconfig" -source "board/matrix_vision/mvblm7/Kconfig" source "board/mpc8308_p1m/Kconfig" source "board/sbc8349/Kconfig" source "board/tqc/tqm834x/Kconfig" diff --git a/board/matrix_vision/mergerbox/Kconfig b/board/matrix_vision/mergerbox/Kconfig deleted file mode 100644 index 3857535a25..0000000000 --- a/board/matrix_vision/mergerbox/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MERGERBOX - -config SYS_BOARD - default "mergerbox" - -config SYS_VENDOR - default "matrix_vision" - -config SYS_CONFIG_NAME - default "MERGERBOX" - -endif diff --git a/board/matrix_vision/mergerbox/MAINTAINERS b/board/matrix_vision/mergerbox/MAINTAINERS deleted file mode 100644 index 20bd073b90..0000000000 --- a/board/matrix_vision/mergerbox/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MERGERBOX BOARD -#M: Andre Schwarz -S: Orphan (since 2014-03) -F: board/matrix_vision/mergerbox/ -F: include/configs/MERGERBOX.h -F: configs/MERGERBOX_defconfig diff --git a/board/matrix_vision/mergerbox/Makefile b/board/matrix_vision/mergerbox/Makefile deleted file mode 100644 index 11a7fd2c7c..0000000000 --- a/board/matrix_vision/mergerbox/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += mergerbox.o pci.o fpga.o sm107.o diff --git a/board/matrix_vision/mergerbox/README b/board/matrix_vision/mergerbox/README deleted file mode 100644 index 1994b65be1..0000000000 --- a/board/matrix_vision/mergerbox/README +++ /dev/null @@ -1,59 +0,0 @@ -Matrix Vision MergerBox ------------------------ - -1. Board Description - - The MergerBox is a 120x160mm single board computing platform - for 3D Full-HD digital video processing. - - Power Supply is 10-32VDC. - -2 System Components - -2.1 CPU - Freescale MPC8377 CPU running at 800MHz core and 333MHz csb. - 256 MByte DDR-II memory @ 333MHz data rate. - 64 MByte Nor Flash on local bus. - 1 GByte Nand Flash on FCM. - 1 Vitesse VSC8601 RGMII ethernet Phys. - 1 USB host controller over ULPI I/F with 4-Port hub. - 2 serial ports. Console running on ttyS0 @ 115200 8N1. - 1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt. - 2 PCIe x1 busses on local mPCIe and cutom expansion connector. - 2 SATA host ports. - System configuration (HRCW) is taken from I2C EEPROM. - -2.2 Graphics - SM107 emebedded video controller driving a 5" 800x480 TFT panel. - Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory. - -2.3 FPGA - Altera Cyclone-IV EP4C115 with several PCI DMA engines. - Connects to 7x Gennum 3G-SDI transceivers as video interconnect - as well as a HDMI v1.4 compliant output for 3D monitoring. - Utilizes two more DDR-II controllers providing 256MB memory. - -2.4 I2C - Bus1: - AD7418 @ 0x50 for voltage/temp. monitoring. - SX8650 @ 0x90 touch controller for HMI. - EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. - Bus2: - mPCIe SMBus - SiI9022A @ 0x72/0xC0 HDMI transmitter. - TCA6416A @ 0x40 + 0x42 16-Bit I/O expander. - LMH1983 @ 0xCA video PLL. - DS1338C @ 0xD0 real-time clock with embedded crystal. - 9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock. - -3 Flash layout. - - reset vector is 0x00000100, i.e. low boot. - - 00000000 u-boot binary. - 00100000 FPGA raw bit file. - 00300000 FIT image holding kernel, dtb and rescue squashfs. - 03d00000 u-boot environment. - 03e00000 splash image - - mtd partitions are propagated to linux kernel via device tree blob. diff --git a/board/matrix_vision/mergerbox/fpga.c b/board/matrix_vision/mergerbox/fpga.c deleted file mode 100644 index 57552c1ae6..0000000000 --- a/board/matrix_vision/mergerbox/fpga.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2011 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "mergerbox.h" -#include "fpga.h" - -Altera_CYC2_Passive_Serial_fns altera_fns = { - fpga_null_fn, - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_null_fn, - fpga_null_fn, -}; - -Altera_desc cyclone2 = { - Altera_CYC2, - passive_serial, - Altera_EP2C20_SIZE, - (void *) &altera_fns, - NULL, - 0 -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mergerbox_init_fpga(void) -{ - debug("Initialize FPGA interface\n"); - fpga_init(); - fpga_add(fpga_altera, &cyclone2); - - return 1; -} - -int fpga_null_fn(int cookie) -{ - return 0; -} - -int fpga_config_fn(int assert, int flush, int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - dvo &= ~FPGA_CONFIG; - gpio->dat = dvo; - udelay(5); - dvo |= FPGA_CONFIG; - gpio->dat = dvo; - - return assert; -} - -int fpga_done_fn(int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - int result = 0; - - udelay(10); - debug("CONF_DONE check ... "); - if (gpio->dat & FPGA_CONF_DONE) { - debug("high\n"); - result = 1; - } else - debug("low\n"); - - return result; -} - -int fpga_status_fn(int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - int result = 0; - - debug("STATUS check ... "); - if (gpio->dat & FPGA_STATUS) { - debug("high\n"); - result = 1; - } else - debug("low\n"); - - return result; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - debug("CLOCK %s\n", assert_clk ? "high" : "low"); - if (assert_clk) - dvo |= FPGA_CCLK; - else - dvo &= ~FPGA_CCLK; - - if (flush) - gpio->dat = dvo; - - return assert_clk; -} - -static inline int _write_fpga(u8 val, int dump) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; - int i; - u32 dvo = gpio->dat; - - if (dump) - debug(" %02x -> ", val); - for (i = 0; i < 8; i++) { - dvo &= ~FPGA_CCLK; - gpio->dat = dvo; - dvo &= ~FPGA_DIN; - if (dump) - debug("%d ", val&1); - if (val & 1) - dvo |= FPGA_DIN; - gpio->dat = dvo; - dvo |= FPGA_CCLK; - gpio->dat = dvo; - val >>= 1; - } - if (dump) - debug("\n"); - - return 0; -} - -int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) -{ - unsigned char *data = (unsigned char *) buf; - int i; - - debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) - _write_fpga(data[i], 0); - debug("\n"); - - return FPGA_SUCCESS; -} diff --git a/board/matrix_vision/mergerbox/fpga.h b/board/matrix_vision/mergerbox/fpga.h deleted file mode 100644 index dbe9bff25f..0000000000 --- a/board/matrix_vision/mergerbox/fpga.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mergerbox_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_status_fn(int cookie); -extern int fpga_config_fn(int assert, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); -extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mergerbox/mergerbox.c b/board/matrix_vision/mergerbox/mergerbox.c deleted file mode 100644 index 5c891d1283..0000000000 --- a/board/matrix_vision/mergerbox/mergerbox.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "mergerbox.h" -#include "fpga.h" -#include "../common/mv_common.h" - -static void setup_serdes(void) -{ - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); -} - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram(void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - -phys_size_t initdram(int board_type) -{ - u32 msize; - - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk; - - /* Enable PCI_CLK[0:1] */ - clk->occr |= 0xc0000000; - udelay(2000); - -#if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(); -#else - immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize_log2; - - msize = CONFIG_SYS_DDR_SIZE; - msize_log2 = __ilog2(msize); - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; - udelay(50000); - - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - udelay(1000); - - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - udelay(1000); - - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - __asm__ __volatile__("sync"); - udelay(1000); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - udelay(2000); -#endif - setup_serdes(); - - return msize << 20; -} - -int checkboard(void) -{ - puts("Board: Matrix Vision MergerBox\n"); - - return 0; -} - -int misc_init_r(void) -{ - u16 dim; - int result; - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (gpio83xx_t *)&immr->gpio[1]; - unsigned char mac[6], mac_verify[6]; - char *s = getenv("reset_env"); - - for (dim = 10; dim < 180; dim += 5) { - mergerbox_tft_dim(dim); - udelay(100000); - } - - if (s) - mv_reset_environment(); - - i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac, sizeof(mac)); - - /* check if Matrix Vision prefix present and export to env */ - if (mac[0] == 0x00 && mac[1] == 0x0c && mac[2] == 0x8d) { - printf("valid MAC found in eeprom: %pM\n", mac); - eth_setenv_enetaddr("ethaddr", mac); - } else { - printf("no valid MAC found in eeprom.\n"); - - /* no: check the env */ - if (!eth_getenv_enetaddr("ethaddr", mac)) { - printf("no valid MAC found in env either.\n"); - /* TODO: ask for valid MAC */ - } else { - printf("valid MAC found in env: %pM\n", mac); - printf("updating MAC in eeprom.\n"); - - do { - result = test_and_clear_bit(20, &gpio->dat); - if (result) - printf("unprotect EEPROM failed !\n"); - udelay(20000); - } while(result); - - i2c_write(SPD_EEPROM_ADDRESS, 0x80, 2, mac, 6); - udelay(20000); - - do { - result = test_and_set_bit(20, &gpio->dat); - if (result) - printf("protect EEPROM failed !\n"); - udelay(20000); - } while(result); - - printf("verify MAC %pM ... ", mac); - i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac_verify, 6); - - if (!strncmp((char *)mac, (char *)mac_verify, 6)) - printf("ok.\n"); - else - /* TODO: retry or do something useful */ - printf("FAILED (got %pM) !\n", mac_verify); - } - } - - return 0; -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat &= ~TFT_SPI_CPLD_CS; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat |= TFT_SPI_CPLD_CS; -} - -/* control backlight pwm (display brightness). - * allow values 0-250 with 0 = turn off and 250 = max brightness - */ -void mergerbox_tft_dim(u16 value) -{ - struct spi_slave *slave; - u16 din; - u16 dout = 0; - - if (value > 0 && value < 250) - dout = 0x4000 | value; - - slave = spi_setup_slave(0, 0, 1000000, SPI_MODE_0 | SPI_CS_HIGH); - spi_claim_bus(slave); - spi_xfer(slave, 16, &dout, &din, SPI_XFER_BEGIN | SPI_XFER_END); - spi_release_bus(slave); - spi_free_slave(slave); -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - fdt_fixup_dr_usb(blob, bd); - ft_pci_setup(blob, bd); -} diff --git a/board/matrix_vision/mergerbox/mergerbox.h b/board/matrix_vision/mergerbox/mergerbox.h deleted file mode 100644 index 53eab28f3d..0000000000 --- a/board/matrix_vision/mergerbox/mergerbox.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MERGERBOX_H__ -#define __MERGERBOX_H__ - -#define MV_GPIO - -/* - * GPIO Bank 1 - */ -#define TFT_SPI_EN (0x80000000>>0) -#define FPGA_CONFIG (0x80000000>>1) -#define FPGA_STATUS (0x80000000>>2) -#define FPGA_CONF_DONE (0x80000000>>3) -#define FPGA_DIN (0x80000000>>4) -#define FPGA_CCLK (0x80000000>>5) -#define MAN_RST (0x80000000>>6) -#define FPGA_SYS_RST (0x80000000>>7) -#define WD_WDI (0x80000000>>8) -#define TFT_RST (0x80000000>>9) -#define HISCON_GPIO1 (0x80000000>>10) -#define HISCON_GPIO2 (0x80000000>>11) -#define B2B_GPIO2 (0x80000000>>12) -#define CCU_GPIN (0x80000000>>13) -#define CCU_GPOUT (0x80000000>>14) -#define TFT_GPIO0 (0x80000000>>15) -#define TFT_GPIO1 (0x80000000>>16) -#define TFT_GPIO2 (0x80000000>>17) -#define TFT_GPIO3 (0x80000000>>18) -#define B2B_GPIO0 (0x80000000>>19) -#define B2B_GPIO1 (0x80000000>>20) -#define TFT_SPI_CPLD_CS (0x80000000>>21) -#define TFT_SPI_CS (0x80000000>>22) -#define CCU_PWR_EN (0x80000000>>23) -#define B2B_GPIO3 (0x80000000>>24) -#define CCU_PWR_STAT (0x80000000>>25) - -#define MV_GPIO1_DAT (FPGA_CONFIG|CCU_PWR_EN|TFT_SPI_CPLD_CS) -#define MV_GPIO1_OUT (TFT_SPI_EN|FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|CCU_PWR_EN| \ - TFT_SPI_CPLD_CS) -#define MV_GPIO1_ODE (FPGA_CONFIG|MAN_RST) - -/* - * GPIO Bank 2 - */ -#define SPI_FLASH_WP (0x80000000>>10) -#define SYS_EEPROM_WP (0x80000000>>11) -#define SPI_FLASH_CS (0x80000000>>22) - -#define MV_GPIO2_DAT (SYS_EEPROM_WP|SPI_FLASH_CS) -#define MV_GPIO2_OUT (SPI_FLASH_WP|SYS_EEPROM_WP|SPI_FLASH_CS) -#define MV_GPIO2_ODE 0 - -void mergerbox_tft_dim(u16 value); - -#endif diff --git a/board/matrix_vision/mergerbox/pci.c b/board/matrix_vision/mergerbox/pci.c deleted file mode 100644 index 480f3ed387..0000000000 --- a/board/matrix_vision/mergerbox/pci.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include "mergerbox.h" -#include "fpga.h" -#include "../common/mv_common.h" - -static struct pci_region pci_regions[] = { - { - .bus_start = CONFIG_SYS_PCI_MEM_BASE, - .phys_start = CONFIG_SYS_PCI_MEM_PHYS, - .size = CONFIG_SYS_PCI_MEM_SIZE, - .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - .bus_start = CONFIG_SYS_PCI_MMIO_BASE, - .phys_start = CONFIG_SYS_PCI_MMIO_PHYS, - .size = CONFIG_SYS_PCI_MMIO_SIZE, - .flags = PCI_REGION_MEM - }, - { - .bus_start = CONFIG_SYS_PCI_IO_BASE, - .phys_start = CONFIG_SYS_PCI_IO_PHYS, - .size = CONFIG_SYS_PCI_IO_SIZE, - .flags = PCI_REGION_IO - } -}; - -static struct pci_region pcie_regions_0[] = { - { - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, - .size = CONFIG_SYS_PCIE1_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE1_IO_BASE, - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, - .size = CONFIG_SYS_PCIE1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -static struct pci_region pcie_regions_1[] = { - { - .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, - .size = CONFIG_SYS_PCIE2_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE2_IO_BASE, - .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, - .size = CONFIG_SYS_PCIE2_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile sysconf83xx_t *sysconf = &immr->sysconf; - volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - volatile law83xx_t *pcie_law = sysconf->pcielaw; - struct pci_region *reg[] = { pci_regions }; - struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; - - volatile gpio83xx_t *gpio; - gpio = (gpio83xx_t *)&immr->gpio[0]; - - gpio->dat = MV_GPIO1_DAT; - gpio->odr = MV_GPIO1_ODE; - gpio->dir = MV_GPIO1_OUT; - - gpio = (gpio83xx_t *)&immr->gpio[1]; - - gpio->dat = MV_GPIO2_DAT; - gpio->odr = MV_GPIO2_ODE; - gpio->dir = MV_GPIO2_OUT; - - printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, - immr->sysconf.sicrl); - - /* Enable PCI_CLK[0:1] */ - clk->occr |= 0xc0000000; - udelay(2000); - - mergerbox_init_fpga(); - mv_load_fpga(); - - mergerbox_tft_dim(0); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - udelay(2000); - - mpc83xx_pci_init(1, reg); - - /* Deassert the resets in the control register */ - out_be32(&sysconf->pecr1, 0xE0008000); - out_be32(&sysconf->pecr2, 0xE0008000); - udelay(2000); - - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); - out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); - - mpc83xx_pcie_init(2, pcie_reg); -} diff --git a/board/matrix_vision/mergerbox/sm107.c b/board/matrix_vision/mergerbox/sm107.c deleted file mode 100644 index d24f926269..0000000000 --- a/board/matrix_vision/mergerbox/sm107.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "../common/mv_common.h" - -#ifdef CONFIG_VIDEO -static const SMI_REGS init_regs_800x480[] = { - /* set endianess to little endian */ - {0x0005c, 0x00000000}, - /* PCI drive 12mA */ - {0x00004, 0x42401001}, - /* current clock */ - {0x0003c, 0x310a1818}, - /* clocks for pm0... */ - {0x00040, 0x0002184f}, - {0x00044, 0x2a1a0a01}, - /* GPIO */ - {0x10008, 0x00000000}, - {0x1000C, 0x00000000}, - /* panel control regs */ - {0x80000, 0x0f017106}, - {0x80004, 0x0}, - {0x80008, 0x0}, - {0x8000C, 0x00000000}, - {0x80010, 0x0c800c80}, - /* width 0x320 */ - {0x80014, 0x03200000}, - /* height 0x1e0 */ - {0x80018, 0x01E00000}, - {0x8001C, 0x0}, - {0x80020, 0x01df031f}, - {0x80024, 0x041f031f}, - {0x80028, 0x00800347}, - {0x8002C, 0x020c01df}, - {0x80030, 0x000201e9}, - {0x80200, 0x00000000}, - /* ZV[0:7] */ - {0x00008, 0x00ff0000}, - /* 24-Bit TFT */ - {0x0000c, 0x3f000000}, - {0, 0} -}; - -/* - * Returns SM107 register base address. First thing called in the driver. - */ -unsigned int board_video_init(void) -{ - pci_dev_t devbusfn; - u32 addr; - - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, - (u32 *)&addr); - return addr & 0xfffffffe; - } - - return 0; -} - -/* - * Called after initializing the SM501 and before clearing the screen. - */ -void board_validate_screen(unsigned int base) -{ -} - -/* - * Returns SM107 framebuffer address - */ -unsigned int board_video_get_fb(void) -{ - pci_dev_t devbusfn; - u32 addr; - - devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0); - if (devbusfn != -1) { - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, - (u32 *)&addr); - addr &= 0xfffffffe; -#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET - addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET; -#endif - return addr; - } - - printf("board_video_get_fb(): FAILED\n"); - - return 0; -} - -/* - * Return a pointer to the initialization sequence. - */ -const SMI_REGS *board_get_regs(void) -{ - return init_regs_800x480; -} - -int board_get_width(void) -{ - return 800; -} - -int board_get_height(void) -{ - return 480; -} -#endif diff --git a/board/matrix_vision/mvblm7/.gitignore b/board/matrix_vision/mvblm7/.gitignore deleted file mode 100644 index 469f1bc4c1..0000000000 --- a/board/matrix_vision/mvblm7/.gitignore +++ /dev/null @@ -1 +0,0 @@ -bootscript.img diff --git a/board/matrix_vision/mvblm7/Kconfig b/board/matrix_vision/mvblm7/Kconfig deleted file mode 100644 index ea7a6f82c0..0000000000 --- a/board/matrix_vision/mvblm7/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MVBLM7 - -config SYS_BOARD - default "mvblm7" - -config SYS_VENDOR - default "matrix_vision" - -config SYS_CONFIG_NAME - default "MVBLM7" - -endif diff --git a/board/matrix_vision/mvblm7/MAINTAINERS b/board/matrix_vision/mvblm7/MAINTAINERS deleted file mode 100644 index 947a14ed50..0000000000 --- a/board/matrix_vision/mvblm7/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MVBLM7 BOARD -#M: Andre Schwarz -S: Orphan (since 2014-03) -F: board/matrix_vision/mvblm7/ -F: include/configs/MVBLM7.h -F: configs/MVBLM7_defconfig diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile deleted file mode 100644 index caa6cfd34c..0000000000 --- a/board/matrix_vision/mvblm7/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (C) Freescale Semiconductor, Inc. 2006. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mvblm7.o pci.o fpga.o - -extra-y := bootscript.img - -MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script - -$(obj)/bootscript.img: $(src)/bootscript - $(call cmd,mkimage) diff --git a/board/matrix_vision/mvblm7/README.mvblm7 b/board/matrix_vision/mvblm7/README.mvblm7 deleted file mode 100644 index a0686f7fa5..0000000000 --- a/board/matrix_vision/mvblm7/README.mvblm7 +++ /dev/null @@ -1,84 +0,0 @@ -Matrix Vision mvBlueLYNX-M7 (mvBL-M7) -------------------------------------- - -1. Board Description - - The mvBL-M7 is a 120x120mm single board computing platform - with strong focus on stereo image processing applications. - - Power Supply is either VDC 12-48V or Pover over Ethernet (PoE) - on any port (requires add-on board). - -2 System Components - -2.1 CPU - Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb. - 512MByte DDR-II memory @ 133MHz. - 8 MByte Nor Flash on local bus. - 2 Vitesse VSC8601 RGMII ethernet Phys. - 1 USB host controller over ULPI I/F. - 2 serial ports. Console running on ttyS0 @ 115200 8N1. - 1 SD-Card slot connected to SPI. - System configuration (HRCW) is taken from I2C EEPROM. - -2.2 PCI - A miniPCI Type-III socket is present. PCI clock fixed at 66MHz. - -2.3 FPGA - Altera Cyclone-II EP2C20/35 with PCI DMA engines. - Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces. - Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash. - -2.3.1 I/O @ FPGA - 2x8 Outputs : Infineon High-Side Switches to Main Supply. - 2x8 Inputs : Programmable input threshold + trigger capabilities - 2 dedicated flash interfaces for illuminator boards. - Cross trigger for chaining several boards. - -2.4 I2C - Bus1: - MAX5381 DAC @ 0x60 for 1st digital input threshold. - LM75 @ 0x90 for temperature monitoring. - EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. - 1st image sensor interface (slave addresses depend on sensor) - Bus2: - MAX5381 DAC @ 0x60 for 2nd digital input threshold. - 2nd image sensor interface (slave addresses depend on sensor) - -3 Flash layout. - - reset vector is 0xFFF00100, i.e. "HIGHBOOT". - - FF800000 environment - FF802000 redundant environment - FF804000 u-boot script image - FF806000 redundant u-boot script image - FF808000 device tree blob - FF80A000 redundant device tree blob - FF80C000 tbd. - FF80E000 tbd. - FF810000 kernel - FFC00000 root FS - FFF00000 u-boot - FFF80000 FPGA raw bit file - - mtd partitions are propagated to linux kernel via device tree blob. - -4 Booting - - On startup the bootscript @ FF804000 is executed. This script can be - exchanged easily. Default boot mode is "boot from flash", i.e. system - works stand-alone. - - This behaviour depends on some environment variables : - - "netboot" : yes ->try dhcp/bootp and boot from network. - A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for - DHCP server configuration, e.g. to provide different images to - different devices. - - During netboot the system tries to get 3 image files: - 1. Kernel - name + data is given during BOOTP. - 2. Initrd - name is stored in "initrd_name" - 3. device tree blob - name is stored in "dtb_name" - Fallback files are the flash versions. diff --git a/board/matrix_vision/mvblm7/bootscript b/board/matrix_vision/mvblm7/bootscript deleted file mode 100644 index dc385fde79..0000000000 --- a/board/matrix_vision/mvblm7/bootscript +++ /dev/null @@ -1,43 +0,0 @@ -echo -echo "==== running autoscript ====" -echo -setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} -setenv ramkernel setenv kernel_boot \${loadaddr} -setenv flashkernel setenv kernel_boot \${mv_kernel_addr} -setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} -setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb -setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} -setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 -setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup -setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel -if test ${console} = yes; -then -setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8 -else -setenv addcons setenv bootargs \${bootargs} console=tty0 -fi -setenv set_static_ip setenv ipaddr \${static_ipaddr} -setenv set_static_nm setenv netmask \${static_netmask} -setenv set_static_gw setenv gatewayip \${static_gateway} -setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} -setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs -if test ${autoscript_boot} != no; -then - if test ${netboot} = yes; - then - bootp - if test $? = 0; - then - echo "=== bootp succeeded -> netboot ===" - run set_ip - run getdtb rundtb bootfromnet ramparam addcons bootdtb - else - echo "=== netboot failed ===" - fi - fi - run set_static_ip set_static_nm set_static_gw set_ip - echo "=== bootfromflash ===" - run cpdtb rundtb bootfromflash -else - echo "=== boot stopped with autoscript_boot no ===" -fi diff --git a/board/matrix_vision/mvblm7/fpga.c b/board/matrix_vision/mvblm7/fpga.c deleted file mode 100644 index c0c5bedb2a..0000000000 --- a/board/matrix_vision/mvblm7/fpga.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "fpga.h" -#include "mvblm7.h" - -#ifdef FPGA_DEBUG -#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) -#else -#define fpga_debug(fmt, args...) -#endif - -Altera_CYC2_Passive_Serial_fns altera_fns = { - fpga_null_fn, - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_null_fn, - fpga_null_fn, -}; - -Altera_desc cyclone2 = { - Altera_CYC2, - passive_serial, - Altera_EP2C20_SIZE, - (void *) &altera_fns, - NULL, - 0 -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mvblm7_init_fpga(void) -{ - fpga_debug("Initialize FPGA interface\n"); - fpga_init(); - fpga_add(fpga_altera, &cyclone2); - fpga_config_fn(0, 1, 0); - udelay(60); - - return 1; -} - -int fpga_null_fn(int cookie) -{ - return 0; -} - -int fpga_config_fn(int assert, int flush, int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - fpga_debug("SET config : %s\n", assert ? "low" : "high"); - if (assert) - dvo |= FPGA_CONFIG; - else - dvo &= ~FPGA_CONFIG; - - if (flush) - gpio->dat = dvo; - - return assert; -} - -int fpga_done_fn(int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int result = 0; - - udelay(10); - fpga_debug("CONF_DONE check ... "); - if (gpio->dat & FPGA_CONF_DONE) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_status_fn(int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int result = 0; - - fpga_debug("STATUS check ... "); - if (gpio->dat & FPGA_STATUS) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low"); - if (assert_clk) - dvo |= FPGA_CCLK; - else - dvo &= ~FPGA_CCLK; - - if (flush) - gpio->dat = dvo; - - return assert_clk; -} - -static inline int _write_fpga(u8 val, int dump) -{ - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int i; - u32 dvo = gpio->dat; - - if (dump) - fpga_debug(" %02x -> ", val); - for (i = 0; i < 8; i++) { - dvo &= ~FPGA_CCLK; - gpio->dat = dvo; - dvo &= ~FPGA_DIN; - if (dump) - fpga_debug("%d ", val&1); - if (val & 1) - dvo |= FPGA_DIN; - gpio->dat = dvo; - dvo |= FPGA_CCLK; - gpio->dat = dvo; - val >>= 1; - } - if (dump) - fpga_debug("\n"); - - return 0; -} - -int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) -{ - unsigned char *data = (unsigned char *) buf; - int i; - - fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) - _write_fpga(data[i], 0); - fpga_debug("\n"); - - return FPGA_SUCCESS; -} diff --git a/board/matrix_vision/mvblm7/fpga.h b/board/matrix_vision/mvblm7/fpga.h deleted file mode 100644 index b480c09b24..0000000000 --- a/board/matrix_vision/mvblm7/fpga.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mvblm7_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_status_fn(int cookie); -extern int fpga_config_fn(int assert, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); -extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c deleted file mode 100644 index f3c16a3e9c..0000000000 --- a/board/matrix_vision/mvblm7/mvblm7.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_OF_LIBFDT) -#include -#endif - -#include "../common/mv_common.h" -#include "mvblm7.h" - -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - char *s = getenv("ddr_size"); - - msize = CONFIG_SYS_DDR_SIZE; - if (s) { - u32 env_ddr_size = simple_strtoul(s, NULL, 10); - if (env_ddr_size == 512) - msize = 512; - } - - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) - return -1; - } - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & - LAWAR_SIZE); - - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - - asm("sync;isync"); - udelay(600); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - asm("sync;isync"); - udelay(500); - - return msize; -} - -phys_size_t initdram(int board_type) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -1; - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; - msize = fixed_sdram(); - - /* return total bus RAM size(bytes) */ - return msize * 1024 * 1024; -} - -int misc_init_r(void) -{ - char *s = getenv("reset_env"); - - if (s) { - mv_reset_environment(); - } - - return 0; -} - -int checkboard(void) -{ - puts("Board: Matrix Vision mvBlueLYNX-M7\n"); - - return 0; -} - -#ifdef CONFIG_HARD_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat &= ~MVBLM7_MMC_CS; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat |= ~MVBLM7_MMC_CS; -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif -} - -#endif diff --git a/board/matrix_vision/mvblm7/mvblm7.h b/board/matrix_vision/mvblm7/mvblm7.h deleted file mode 100644 index de9fec7fb8..0000000000 --- a/board/matrix_vision/mvblm7/mvblm7.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __MVBC_H__ -#define __MVBC_H__ - -#define MV_GPIO - -#define FPGA_CONFIG 0x80000000 -#define FPGA_CCLK 0x40000000 -#define FPGA_DIN 0x20000000 -#define FPGA_STATUS 0x10000000 -#define FPGA_CONF_DONE 0x08000000 - -#define WD_WDI 0x00400000 -#define WD_TS 0x00200000 -#define MAN_RST 0x00100000 - -#define MV_GPIO_DAT (WD_TS) -#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS) -#define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST) - -#endif diff --git a/board/matrix_vision/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c deleted file mode 100644 index f14837ad40..0000000000 --- a/board/matrix_vision/mvblm7/pci.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#if defined(CONFIG_OF_LIBFDT) -#include -#endif -#include -#include -#include -#include "mvblm7.h" -#include "fpga.h" -#include "../common/mv_common.h" - -DECLARE_GLOBAL_DATA_PTR; - -static struct pci_region pci_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -void pci_init_board(void) -{ - int i; - volatile immap_t *immr; - volatile pcictrl83xx_t *pci_ctrl; - volatile gpio83xx_t *gpio; - volatile clk83xx_t *clk; - volatile law83xx_t *pci_law; - struct pci_region *reg[] = { pci_regions }; - - immr = (immap_t *) CONFIG_SYS_IMMR; - clk = (clk83xx_t *) &immr->clk; - pci_ctrl = immr->pci_ctrl; - pci_law = immr->sysconf.pcilaw; - gpio = (volatile gpio83xx_t *)&immr->gpio[0]; - - gpio->dat = MV_GPIO_DAT; - gpio->odr = MV_GPIO_ODE; - gpio->dir = MV_GPIO_OUT; - - printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, - immr->sysconf.sicrl); - - mvblm7_init_fpga(); - mv_load_fpga(); - - gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); - - /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */ - clk->occr = 0xc0000000; - - pci_ctrl[0].gcr = 0; - udelay(2000); - pci_ctrl[0].gcr = 1; - - for (i = 0; i < 1000; ++i) - udelay(1000); - - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - mpc83xx_pci_init(1, reg); -} diff --git a/configs/MERGERBOX_defconfig b/configs/MERGERBOX_defconfig deleted file mode 100644 index 34a527ee12..0000000000 --- a/configs/MERGERBOX_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC83xx=y -CONFIG_TARGET_MERGERBOX=y diff --git a/configs/MVBLM7_defconfig b/configs/MVBLM7_defconfig deleted file mode 100644 index cc81b5c805..0000000000 --- a/configs/MVBLM7_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC83xx=y -CONFIG_TARGET_MVBLM7=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 036bc838ab..3caa8cf294 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +MERGERBOX powerpc mpc83xx - - Andre Schwarz +MVBLM7 powerpc mpc83xx - - Andre Schwarz bluestone powerpc ppc4xx - - Tirumala Marri CRAYL1 powerpc ppc4xx - - David Updegraff KAREF powerpc ppc4xx - - Travis Sawyer diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h deleted file mode 100644 index 19ea3167af..0000000000 --- a/include/configs/MERGERBOX.h +++ /dev/null @@ -1,599 +0,0 @@ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011 Matrix Vision GmbH - * Andre Schwarz - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 -#define CONFIG_MPC837x 1 -#define CONFIG_MPC8377 1 - -#define CONFIG_SYS_TEXT_BASE 0xFC000000 - -#define CONFIG_PCI 1 -#define CONFIG_PCI_INDIRECT_BRIDGE 1 - -#define CONFIG_MASK_AER_AO -#define CONFIG_DISPLAY_AER_FULL - -#define CONFIG_MISC_INIT_R - -/* - * On-board devices - */ -#define CONFIG_TSEC_ENET - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ -#define CONFIG_PCIE -#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN - -/* - * Hardware Reset Configuration Word stored in EEPROM. - */ -#define CONFIG_SYS_HRCW_LOW 0 -#define CONFIG_SYS_HRCW_HIGH 0 - -/* Arbiter Configuration Register */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 -#define CONFIG_SYS_ACR_RPTCNT 3 - -/* System Priority Control Regsiter */ -#define CONFIG_SYS_SPCR_TSECEP 3 - -/* System Clock Configuration Register */ -#define CONFIG_SYS_SCCR_TSEC1CM 3 -#define CONFIG_SYS_SCCR_TSEC2CM 0 -#define CONFIG_SYS_SCCR_SDHCCM 3 -#define CONFIG_SYS_SCCR_ENCCM 3 /* also clock for I2C-1 */ -#define CONFIG_SYS_SCCR_USBDRCM CONFIG_SYS_SCCR_ENCCM /* must match */ -#define CONFIG_SYS_SCCR_PCIEXP1CM 3 -#define CONFIG_SYS_SCCR_PCIEXP2CM 3 -#define CONFIG_SYS_SCCR_PCICM 1 -#define CONFIG_SYS_SCCR_SATACM 0xFF - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x087c0000 -#define CONFIG_SYS_SICRL 0x40000000 - -/* - * Output Buffer Impedance - */ -#define CONFIG_SYS_OBIR 0x30000000 - -/* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_83XX_DDR_USES_CS0 - -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN | DDRCDR_PZ_HIZ |\ - DDRCDR_NZ_HIZ | DDRCDR_ODT |\ - DDRCDR_Q_DRN) - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 - -#define CONFIG_SYS_DDR_MODE_WEAK -#define CONFIG_SYS_DDR_WRITE_DATA_DELAY 2 -#define CONFIG_SYS_DDR_CPO 0x1f - -/* SPD table located at offset 0x20 in extended adressing ROM - * used for HRCW fetch after power-on reset - */ -#define CONFIG_SPD_EEPROM -#define SPD_EEPROM_ADDRESS 0x50 -#define SPD_EEPROM_OFFSET 0x20 -#define SPD_EEPROM_ADDR_LEN 2 - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (512*1024) -#define CONFIG_SYS_MALLOC_LEN (512*1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\ - GENERATED_GBL_DATA_SIZE) - -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 -#define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_FSL_ELBC 1 - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_FLASH_SIZE 64 - -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 |\ - BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\ - OR_GPCM_XACS | OR_GPCM_SCY_15 |\ - OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\ - OR_GPCM_EAD) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* - * NAND Flash on the Local Bus - */ -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 - -#define CONFIG_SYS_NAND_BASE 0xE0600000 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\ - BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\ - OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\ - OR_FCM_TRLX | OR_FCM_EHTR) - -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -#define CONFIG_CONSOLE ttyS0 -#define CONFIG_BAUDRATE 115200 - -/* SERDES */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 -#define CONFIG_FSL_SERDES2 0xe3100 - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE (256 << 20) -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE (256 << 20) -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI_IO_SIZE (1 << 20) - -#ifdef CONFIG_PCIE -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE (128 << 20) -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE (256 << 20) -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 -#define CONFIG_SYS_PCIE1_IO_SIZE (8 << 20) - -#define CONFIG_SYS_PCIE2_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_SIZE (128 << 20) -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE (256 << 20) -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 -#define CONFIG_SYS_PCIE2_IO_SIZE (8 << 20) -#endif - -#define CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -/* - * TSEC - */ -#define CONFIG_GMII /* MII PHY management */ -#define CONFIG_SYS_VSC8601_SKEWFIX -#define CONFIG_SYS_VSC8601_SKEW_TX 3 -#define CONFIG_SYS_VSC8601_SKEW_RX 3 - -#define CONFIG_TSEC1 -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 0x10 -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC1_PHYIDX 0 - -#define CONFIG_ETHPRIME "TSEC0" -#define CONFIG_HAS_ETH0 - -/* - * SATA - */ -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1_OFFSET 0x18000 -#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2_OFFSET 0x19000 -#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#define CONFIG_CMD_SATA -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_EXT2 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_VENDOREX -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_RANDOM_DELAY -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_LIB_RAND - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCI -#define CONFIG_CMD_USB -#define CONFIG_CMD_SPI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_SATA - -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 - -#define CONFIG_RBTREE -#define CONFIG_LZO - -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS - -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND" -#define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)" - -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE 1 - -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_AUTO_COMPLETE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_LOAD_ADDR 0x2000000 -#define CONFIG_LOADADDR 0x4000000 -#define CONFIG_SYS_CBSIZE 256 - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_LOADS_ECHO 1 -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 - -#define CONFIG_SYS_MEMTEST_START (60<<20) -#define CONFIG_SYS_MEMTEST_END (70<<20) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ - -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - -/* - * MMU Setup - */ -#define CONFIG_HIGH_BATS 1 - -/* DDR: cache cacheable */ -#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_RW |\ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* unused */ -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_RW |\ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* unused */ -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -/* - * I2C EEPROM settings - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_SIZE 0x4000 - -/* - * Environment Configuration - */ -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0xFFD00000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE - -/* - * Video - */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_SM501_PCI -#define VIDEO_FB_LITTLE_ENDIAN -#define CONFIG_CMD_BMP -#define CONFIG_VIDEO_SM501 -#define CONFIG_VIDEO_SM501_32BPP -#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) - -/* - * SPI - */ -#define CONFIG_MPC8XXX_SPI - -/* - * USB - */ -#define CONFIG_SYS_USB_HOST -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_FSL -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#define CONFIG_USB_STORAGE -#define CONFIG_USB_KEYBOARD -/* - * - */ -#define CONFIG_BOOTDELAY 5 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR "s" -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 1000 - -#define MV_CI "MergerBox" -#define MV_VCI "MergerBox" -#define MV_FPGA_DATA 0xfc100000 -#define MV_FPGA_SIZE 0x00200000 - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define MV_KERNEL_ADDR_RAM 0x02800000 -#define MV_DTB_ADDR_RAM 0x00600000 -#define MV_INITRD_ADDR_RAM 0x01000000 -#define MV_FITADDR 0xfc300000 -#define MV_SPLAH_ADDR 0xffe00000 - -#define CONFIG_BOOTCOMMAND "run i2c_init;if test ${boot_sqfs} -eq 1;"\ - "then; run fitboot;else;run ubiboot;fi;" -#define CONFIG_BOOTARGS "console=ttyS0,115200n8" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console_nr=0\0"\ - "stdin=serial\0"\ - "stdout=serial\0"\ - "stderr=serial\0"\ - "boot_sqfs=1\0"\ - "usb_dr_mode=host\0"\ - "bootfile=MergerBox.fit\0"\ - "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"\ - "fpga=0\0"\ - "fpgadata=" __stringify(MV_FPGA_DATA) "\0"\ - "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"\ - "mv_kernel_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"\ - "mv_initrd_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"\ - "mv_dtb_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"\ - "uboota=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"\ - "fitaddr=" __stringify(MV_FITADDR) "\0"\ - "mv_version=" U_BOOT_VERSION "\0"\ - "mtdids=" MTDIDS_DEFAULT "\0"\ - "mtdparts=" MTDPARTS_DEFAULT "\0"\ - "dhcp_client_id=" MV_CI "\0"\ - "dhcp_vendor-class-identifier=" MV_VCI "\0"\ - "upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\ - "protect off all;erase $uboota +0xC0000;"\ - "cp.b $loadaddr $uboota $filesize\0"\ - "upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\ - "cp.b $loadaddr $fpgadata $filesize\0"\ - "upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\ - "cp.b $loadaddr $fitaddr $filesize\0"\ - "addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\ - "rootfstype=squashfs\0"\ - "addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\ - "rootfstype=ubifs\0"\ - "addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\ - "rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\ - "netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\ - "netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\ - "ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\ - "doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\ - "fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\ - "imxtract $fitaddr ramdisk $mv_initrd_ram;"\ - "imxtract $fitaddr fdt $mv_dtb_ram\0"\ - "fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\ - "fitboot=run fitprep fdtprep addsqshrfs doboot\0"\ - "i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\ - "i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\ - "i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\ - "i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\ - "i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\ - "init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\ - "i2c mw 21 2 ff;i2c mw 21 3 3c\0"\ - "splashimage=" __stringify(MV_SPLAH_ADDR) "\0"\ - "" - -/* - * FPGA - */ -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA -#define CONFIG_FPGA_ALTERA -#define CONFIG_FPGA_CYCLON2 - -#endif diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h deleted file mode 100644 index 1ee4d7cc33..0000000000 --- a/include/configs/MVBLM7.h +++ /dev/null @@ -1,491 +0,0 @@ -/* - * Copyright (C) Matrix Vision GmbH 2008 - * - * Matrix Vision mvBlueLYNX-M7 configuration file - * based on Freescale's MPC8349ITX. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 -#define CONFIG_MPC834x 1 -#define CONFIG_MPC8343 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_SYS_IMMR 0xE0000000 - -#define CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_SKIP_HOST_BRIDGE -#define CONFIG_TSEC_ENET -#define CONFIG_MPC8XXX_SPI -#define CONFIG_HARD_SPI -#define MVBLM7_MMC_CS 0x04000000 -#define CONFIG_MISC_INIT_R - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 100000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* - * DDR Setup - */ -#undef CONFIG_SPD_EEPROM - -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_83XX_DDR_USES_CS0 1 -#define CONFIG_SYS_MEMTEST_START (60<<20) -#define CONFIG_SYS_MEMTEST_END (70<<20) -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_SYS_DDRCDR (DDRCDR_PZ_HIZ \ - | DDRCDR_NZ_HIZ \ - | DDRCDR_Q_DRN) - /* 0x22000001 */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 - -#define CONFIG_SYS_DDR_SIZE 512 - -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f - -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3837c322 -#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_INTERVAL 0x02000100 - -#define CONFIG_SYS_DDR_MODE 0x04040242 -#define CONFIG_SYS_DDR_MODE2 0x00800000 - -/* Flash */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_FLASH_BASE 0xFF800000 -#define CONFIG_SYS_FLASH_SIZE 8 -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 \ - | BR_MS_GPCM \ - | BR_V) -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) - -/* - * U-Boot memory configuration - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#undef CONFIG_SYS_RAMBOOT - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) - -/* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 -/* LB refresh timer prescal, 266MHz/32*/ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_CONSOLE ttyS0 -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 -#define MV_DTB_NAME "mvblm7.dtb" - -/* - * PCI - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCI1_MMIO_BASE \ - (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 - -#define CONFIG_NET_RETRY_COUNT 3 - -#define CONFIG_PCI_66M -#define CONFIG_83XX_CLKIN 66666667 -#define CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW - -/* TSEC */ -#define CONFIG_GMII -#define CONFIG_SYS_VSC8601_SKEWFIX -#define CONFIG_SYS_VSC8601_SKEW_TX 3 -#define CONFIG_SYS_VSC8601_SKEW_RX 3 - -#define CONFIG_TSEC1 -#define CONFIG_TSEC2 - -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_FEC1_PHY_NORXERR -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define TSEC1_PHY_ADDR 0x10 -#define TSEC1_PHYIDX 0 -#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) - -#define CONFIG_HAS_ETH1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_FEC2_PHY_NORXERR -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) -#define TSEC2_PHY_ADDR 0x11 -#define TSEC2_PHYIDX 0 -#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) - -#define CONFIG_ETHPRIME "TSEC0" - -#define CONFIG_BOOTP_VENDOREX -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_RANDOM_DELAY -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_LIB_RAND - -/* USB */ -#define CONFIG_SYS_USB_HOST -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_FSL -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -/* - * Environment - */ -#undef CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0xFF800000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_LOADS_ECHO -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_PCI -#define CONFIG_CMD_I2C -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_CMD_USB -#define CONFIG_DOS_PARTITION - -#undef CONFIG_WATCHDOG - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_SYS_HUSH_PARSER - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 0x200000 - -#define CONFIG_SYS_PROMPT "mvBL-M7> " -#define CONFIG_SYS_CBSIZE 256 - -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -#define CONFIG_SYS_HRCW_LOW 0x0 -#define CONFIG_SYS_HRCW_HIGH 0x0 - -/* - * System performance - */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ -#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ -#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ - -/* clocking */ -#define CONFIG_SYS_SCCR_ENCCM 0 -#define CONFIG_SYS_SCCR_USBMPHCM 0 -#define CONFIG_SYS_SCCR_USBDRCM 2 -#define CONFIG_SYS_SCCR_TSEC1CM 1 -#define CONFIG_SYS_SCCR_TSEC2CM 1 - -#define CONFIG_SYS_SICRH 0x1fef0003 -#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0) - -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ - HID0_ENABLE_INSTRUCTION_CACHE) - -#define CONFIG_SYS_HID2 HID2_HBE -#define CONFIG_HIGH_BATS 1 - -/* DDR */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* no PCI2 */ -#define CONFIG_SYS_IBAT3L 0 -#define CONFIG_SYS_IBAT3U 0 -#define CONFIG_SYS_IBAT4L 0 -#define CONFIG_SYS_IBAT4U 0 - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT7L 0 -#define CONFIG_SYS_IBAT7U 0 - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_NETDEV eth0 - -/* Default path and filenames */ -#define CONFIG_BOOTDELAY 5 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR "s" -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 1000 - -#define MV_CI "mvBL-M7" -#define MV_VCI "mvBL-M7" -#define MV_FPGA_DATA 0xfff40000 -#define MV_FPGA_SIZE 0 -#define MV_KERNEL_ADDR 0xff810000 -#define MV_INITRD_ADDR 0xffb00000 -#define MV_SCRIPT_ADDR 0xff804000 -#define MV_SCRIPT_ADDR2 0xff806000 -#define MV_DTB_ADDR 0xff808000 -#define MV_INITRD_LENGTH 0x00400000 - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define MV_KERNEL_ADDR_RAM 0x00100000 -#define MV_DTB_ADDR_RAM 0x00600000 -#define MV_INITRD_ADDR_RAM 0x01000000 - -#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; " \ - "then source ${script_addr}; " \ - "else source ${script_addr2}; " \ - "fi;" -#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console_nr=0\0" \ - "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "fpga=0\0" \ - "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \ - "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \ - "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \ - "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \ - "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \ - "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \ - "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \ - "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \ - "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \ - "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \ - "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \ - "dtb_name=" __stringify(MV_DTB_NAME) "\0" \ - "mv_version=" U_BOOT_VERSION "\0" \ - "dhcp_client_id=" MV_CI "\0" \ - "dhcp_vendor-class-identifier=" MV_VCI "\0" \ - "netretry=no\0" \ - "use_static_ipaddr=no\0" \ - "static_ipaddr=192.168.90.10\0" \ - "static_netmask=255.255.255.0\0" \ - "static_gateway=0.0.0.0\0" \ - "initrd_name=uInitrd.mvBL-M7-rfs\0" \ - "zcip=no\0" \ - "netboot=yes\0" \ - "mvtest=Ff\0" \ - "tried_bootfromflash=no\0" \ - "tried_bootfromnet=no\0" \ - "bootfile=mvblm72625.boot\0" \ - "use_dhcp=yes\0" \ - "gev_start=yes\0" \ - "mvbcdma_debug=0\0" \ - "mvbcia_debug=0\0" \ - "propdev_debug=0\0" \ - "gevss_debug=0\0" \ - "watchdog=0\0" \ - "usb_dr_mode=host\0" \ - "sensor_cnt=2\0" \ - "" - -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA -#define CONFIG_FPGA_ALTERA -#define CONFIG_FPGA_CYCLON2 - -#endif -- cgit v1.2.3 From af55e35d33894295cf0f2f94c050f67d05b50944 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Sep 2014 01:38:01 +0900 Subject: powerpc: mpc5xxx: remove board support for MVBC_P and MVSMR These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/mpc5xxx/Kconfig | 8 - board/matrix_vision/mvbc_p/Kconfig | 12 -- board/matrix_vision/mvbc_p/MAINTAINERS | 6 - board/matrix_vision/mvbc_p/Makefile | 11 - board/matrix_vision/mvbc_p/README.mvbc_p | 73 ------- board/matrix_vision/mvbc_p/fpga.c | 157 -------------- board/matrix_vision/mvbc_p/fpga.h | 17 -- board/matrix_vision/mvbc_p/mvbc_p.c | 255 ----------------------- board/matrix_vision/mvbc_p/mvbc_p.h | 43 ---- board/matrix_vision/mvbc_p/mvbc_p_autoscript | 48 ----- board/matrix_vision/mvsmr/.gitignore | 1 - board/matrix_vision/mvsmr/Kconfig | 12 -- board/matrix_vision/mvsmr/MAINTAINERS | 6 - board/matrix_vision/mvsmr/Makefile | 18 -- board/matrix_vision/mvsmr/README.mvsmr | 55 ----- board/matrix_vision/mvsmr/bootscript | 42 ---- board/matrix_vision/mvsmr/fpga.c | 112 ---------- board/matrix_vision/mvsmr/fpga.h | 15 -- board/matrix_vision/mvsmr/mvsmr.c | 248 ---------------------- board/matrix_vision/mvsmr/mvsmr.h | 43 ---- board/matrix_vision/mvsmr/u-boot.lds | 89 -------- configs/MVBC_P_defconfig | 4 - configs/MVSMR_defconfig | 3 - doc/README.scrapyard | 2 + include/configs/MVBC_P.h | 300 --------------------------- include/configs/MVSMR.h | 270 ------------------------ 26 files changed, 2 insertions(+), 1848 deletions(-) delete mode 100644 board/matrix_vision/mvbc_p/Kconfig delete mode 100644 board/matrix_vision/mvbc_p/MAINTAINERS delete mode 100644 board/matrix_vision/mvbc_p/Makefile delete mode 100644 board/matrix_vision/mvbc_p/README.mvbc_p delete mode 100644 board/matrix_vision/mvbc_p/fpga.c delete mode 100644 board/matrix_vision/mvbc_p/fpga.h delete mode 100644 board/matrix_vision/mvbc_p/mvbc_p.c delete mode 100644 board/matrix_vision/mvbc_p/mvbc_p.h delete mode 100644 board/matrix_vision/mvbc_p/mvbc_p_autoscript delete mode 100644 board/matrix_vision/mvsmr/.gitignore delete mode 100644 board/matrix_vision/mvsmr/Kconfig delete mode 100644 board/matrix_vision/mvsmr/MAINTAINERS delete mode 100644 board/matrix_vision/mvsmr/Makefile delete mode 100644 board/matrix_vision/mvsmr/README.mvsmr delete mode 100644 board/matrix_vision/mvsmr/bootscript delete mode 100644 board/matrix_vision/mvsmr/fpga.c delete mode 100644 board/matrix_vision/mvsmr/fpga.h delete mode 100644 board/matrix_vision/mvsmr/mvsmr.c delete mode 100644 board/matrix_vision/mvsmr/mvsmr.h delete mode 100644 board/matrix_vision/mvsmr/u-boot.lds delete mode 100644 configs/MVBC_P_defconfig delete mode 100644 configs/MVSMR_defconfig delete mode 100644 include/configs/MVBC_P.h delete mode 100644 include/configs/MVSMR.h diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig index cca58e5bbb..8a477e7e0c 100644 --- a/arch/powerpc/cpu/mpc5xxx/Kconfig +++ b/arch/powerpc/cpu/mpc5xxx/Kconfig @@ -97,12 +97,6 @@ config TARGET_MUCMC52 config TARGET_UC101 bool "Support uc101" -config TARGET_MVBC_P - bool "Support MVBC_P" - -config TARGET_MVSMR - bool "Support MVSMR" - config TARGET_PCM030 bool "Support pcm030" @@ -139,8 +133,6 @@ source "board/jupiter/Kconfig" source "board/manroland/hmi1001/Kconfig" source "board/manroland/mucmc52/Kconfig" source "board/manroland/uc101/Kconfig" -source "board/matrix_vision/mvbc_p/Kconfig" -source "board/matrix_vision/mvsmr/Kconfig" source "board/mcc200/Kconfig" source "board/motionpro/Kconfig" source "board/munices/Kconfig" diff --git a/board/matrix_vision/mvbc_p/Kconfig b/board/matrix_vision/mvbc_p/Kconfig deleted file mode 100644 index 4a68493fa3..0000000000 --- a/board/matrix_vision/mvbc_p/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MVBC_P - -config SYS_BOARD - default "mvbc_p" - -config SYS_VENDOR - default "matrix_vision" - -config SYS_CONFIG_NAME - default "MVBC_P" - -endif diff --git a/board/matrix_vision/mvbc_p/MAINTAINERS b/board/matrix_vision/mvbc_p/MAINTAINERS deleted file mode 100644 index aad14ed079..0000000000 --- a/board/matrix_vision/mvbc_p/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MVBC_P BOARD -#M: Andre Schwarz -S: Orphan (since 2014-03) -F: board/matrix_vision/mvbc_p/ -F: include/configs/MVBC_P.h -F: configs/MVBC_P_defconfig diff --git a/board/matrix_vision/mvbc_p/Makefile b/board/matrix_vision/mvbc_p/Makefile deleted file mode 100644 index 4c1994156f..0000000000 --- a/board/matrix_vision/mvbc_p/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004-2008 -# Matrix-Vision GmbH, info@matrix-vision.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mvbc_p.o fpga.o diff --git a/board/matrix_vision/mvbc_p/README.mvbc_p b/board/matrix_vision/mvbc_p/README.mvbc_p deleted file mode 100644 index a691137550..0000000000 --- a/board/matrix_vision/mvbc_p/README.mvbc_p +++ /dev/null @@ -1,73 +0,0 @@ -Matrix Vision mvBlueCOUGAR-P (mvBC-P) -------------------------------------- - -1. Board Description - - The mvBC-P is a 70x40x40mm multi board gigabit ethernet network camera - with main focus on GigEVision protocol in combination with local image - preprocessing. - - Power Supply is either VDC 48V or Pover over Ethernet (PoE). - -2 System Components - -2.1 CPU - Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB. - 64MB SDRAM @ 133MHz. - 8 MByte Nor Flash on local bus. - 1 serial ports. Console running on ttyS0 @ 115200 8N1. - -2.2 PCI - PCI clock fixed at 66MHz. Arbitration inside FPGA. - Intel GD82541ER network MAC/PHY and FPGA connected. - -2.3 FPGA - Altera Cyclone-II EP2C8 with PCI DMA engine. - Connects to Matrix Vision specific CCD/CMOS sensor interface. - Utilizes 64MB Nand Flash. - -2.3.1 I/O @ FPGA - 2 Outputs : photo coupler - 2 Inputs : photo coupler - -2.4 I2C - LM75 @ 0x90 for temperature monitoring. - EEPROM @ 0xA0 for vendor specifics. - image sensor interface (slave addresses depend on sensor) - -3 Flash layout. - - reset vector is 0x00000100, i.e. "LOWBOOT". - - FF800000 u-boot - FF840000 u-boot script image - FF850000 redundant u-boot script image - FF860000 FPGA raw bit file - FF8A0000 tbd. - FF900000 root FS - FFC00000 kernel - FFFC0000 device tree blob - FFFD0000 redundant device tree blob - FFFE0000 environment - FFFF0000 redundant environment - - mtd partitions are propagated to linux kernel via device tree blob. - -4 Booting - - On startup the bootscript @ FF840000 is executed. This script can be - exchanged easily. Default boot mode is "boot from flash", i.e. system - works stand-alone. - - This behaviour depends on some environment variables : - - "netboot" : yes ->try dhcp/bootp and boot from network. - A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for - DHCP server configuration, e.g. to provide different images to - different devices. - - During netboot the system tries to get 3 image files: - 1. Kernel - name + data is given during BOOTP. - 2. Initrd - name is stored in "initrd_name" - 3. device tree blob - name is stored in "dtb_name" - Fallback files are the flash versions. diff --git a/board/matrix_vision/mvbc_p/fpga.c b/board/matrix_vision/mvbc_p/fpga.c deleted file mode 100644 index b88f43f3e3..0000000000 --- a/board/matrix_vision/mvbc_p/fpga.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "fpga.h" -#include "mvbc_p.h" - -#ifdef FPGA_DEBUG -#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) -#else -#define fpga_debug(fmt, args...) -#endif - -Altera_CYC2_Passive_Serial_fns altera_fns = { - fpga_null_fn, - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_null_fn, - fpga_null_fn, -}; - -Altera_desc cyclone2 = { - Altera_CYC2, - passive_serial, - Altera_EP2C8_SIZE, - (void *) &altera_fns, - NULL, -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mvbc_p_init_fpga(void) -{ - fpga_debug("Initialize FPGA interface\n"); - fpga_init(); - fpga_add(fpga_altera, &cyclone2); - fpga_config_fn(0, 1, 0); - udelay(60); - - return 1; -} - -int fpga_null_fn(int cookie) -{ - return 0; -} - -int fpga_config_fn(int assert, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - u32 dvo = gpio->simple_dvo; - - fpga_debug("SET config : %s\n", assert ? "low" : "high"); - if (assert) - dvo |= FPGA_CONFIG; - else - dvo &= ~FPGA_CONFIG; - - if (flush) - gpio->simple_dvo = dvo; - - return assert; -} - -int fpga_done_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - int result = 0; - - udelay(10); - fpga_debug("CONF_DONE check ... "); - if (gpio->simple_ival & FPGA_CONF_DONE) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_status_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - int result = 0; - - fpga_debug("STATUS check ... "); - if (gpio->sint_ival & FPGA_STATUS) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - u32 dvo = gpio->simple_dvo; - - fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low"); - if (assert_clk) - dvo |= FPGA_CCLK; - else - dvo &= ~FPGA_CCLK; - - if (flush) - gpio->simple_dvo = dvo; - - return assert_clk; -} - -static inline int _write_fpga(u8 val) -{ - int i; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - u32 dvo = gpio->simple_dvo; - - for (i=0; i<8; i++) { - dvo &= ~FPGA_CCLK; - gpio->simple_dvo = dvo; - dvo &= ~FPGA_DIN; - if (val & 1) - dvo |= FPGA_DIN; - gpio->simple_dvo = dvo; - dvo |= FPGA_CCLK; - gpio->simple_dvo = dvo; - val >>= 1; - } - - return 0; -} - -int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) -{ - unsigned char *data = (unsigned char *) buf; - int i; - - fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) - _write_fpga(data[i]); - fpga_debug("\n"); - - return FPGA_SUCCESS; -} diff --git a/board/matrix_vision/mvbc_p/fpga.h b/board/matrix_vision/mvbc_p/fpga.h deleted file mode 100644 index 96d34654c9..0000000000 --- a/board/matrix_vision/mvbc_p/fpga.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mvbc_p_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_status_fn(int cookie); -extern int fpga_config_fn(int assert, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); -extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mvbc_p/mvbc_p.c b/board/matrix_vision/mvbc_p/mvbc_p.c deleted file mode 100644 index 8faebeeebe..0000000000 --- a/board/matrix_vision/mvbc_p/mvbc_p.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2005-2007 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "fpga.h" -#include "mvbc_p.h" -#include "../common/mv_common.h" - -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 - -DECLARE_GLOBAL_DATA_PTR; - -static void sdram_start (int hi_addr) -{ - long hi_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit); - - /* precharge all banks */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit); - - /* precharge all banks */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit); - - /* auto refresh */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit); - - /* set mode register */ - out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE); - - /* normal operation */ - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit); -} - -phys_addr_t initdram (int board_type) -{ - ulong dramsize = 0; - ulong test1, - test2; - - /* setup SDRAM chip selects */ - out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); - - /* setup config registers */ - out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); - out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else - dramsize = test2; - - if (dramsize < (1 << 20)) - dramsize = 0; - - if (dramsize > 0) - out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 + - __builtin_ffs(dramsize >> 20) - 1); - else - out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0); - - return dramsize; -} - -void mvbc_init_gpio(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - printf("Ports : 0x%08x\n", gpio->port_config); - printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG); - - out_be32(&gpio->simple_ddr, SIMPLE_DDR); - out_be32(&gpio->simple_dvo, SIMPLE_DVO); - out_be32(&gpio->simple_ode, SIMPLE_ODE); - out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN); - - out_8(&gpio->sint_ode, SINT_ODE); - out_8(&gpio->sint_ddr, SINT_DDR); - out_8(&gpio->sint_dvo, SINT_DVO); - out_8(&gpio->sint_inten, SINT_INTEN); - out_be16(&gpio->sint_itype, SINT_ITYPE); - out_8(&gpio->sint_gpioe, SINT_GPIOEN); - - out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE); - out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR); - out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO); - out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN); - - printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe); - printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe); -} - -int misc_init_r(void) -{ - char *s = getenv("reset_env"); - - if (!s) { - if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6) - return 0; - udelay(50000); - if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6) - return 0; - udelay(50000); - if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6) - return 0; - } - printf(" === FACTORY RESET ===\n"); - mv_reset_environment(); - saveenv(); - - return -1; -} - -int checkboard(void) -{ - mvbc_init_gpio(); - printf("Board: Matrix Vision mvBlueCOUGAR-P\n"); - - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1); -} - -void flash_afterinit(ulong size) -{ - out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START | - size)); - out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START | - size)); - out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size, - size)); - out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size, - size)); -} - -void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char line = 0xff; - char *s = getenv("pci_latency"); - u32 base; - u8 val = 0; - - if (s) - val = simple_strtoul(s, NULL, 16); - - if (PCI_BUS(dev) == 0) { - switch (PCI_DEV (dev)) { - case 0xa: /* FPGA */ - line = 3; - pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base); - printf("found FPGA - enable arbitration\n"); - writel(0x03, (u32*)(base + 0x80c0)); - writel(0xf0, (u32*)(base + 0x8080)); - if (val) - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val); - break; - case 0xb: /* LAN */ - line = 2; - if (val) - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val); - break; - case 0x1a: - break; - default: - printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev)); - break; - } - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line); - } -} - -struct pci_controller hose = { - fixup_irq:pci_mvbc_fixup_irq -}; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - mvbc_p_init_fpga(); - mv_load_fpga(); - pci_mpc5xxx_init(&hose); -} - -void show_boot_progress(int val) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - switch(val) { - case BOOTSTAGE_ID_START: /* FPGA ok */ - setbits_be32(&gpio->simple_dvo, LED_G0); - break; - case BOOTSTAGE_ID_NET_ETH_INIT: - setbits_be32(&gpio->simple_dvo, LED_G1); - break; - case BOOTSTAGE_ID_COPY_RAMDISK: - setbits_be32(&gpio->simple_dvo, LED_Y); - break; - case BOOTSTAGE_ID_RUN_OS: - setbits_be32(&gpio->simple_dvo, LED_R); - break; - default: - break; - } - -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -} - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Built in FEC comes first */ - return pci_eth_init(bis); -} diff --git a/board/matrix_vision/mvbc_p/mvbc_p.h b/board/matrix_vision/mvbc_p/mvbc_p.h deleted file mode 100644 index be1542b773..0000000000 --- a/board/matrix_vision/mvbc_p/mvbc_p.h +++ /dev/null @@ -1,43 +0,0 @@ -#ifndef __MVBC_H__ -#define __MVBC_H__ - -#define LED_G0 MPC5XXX_GPIO_SIMPLE_PSC2_0 -#define LED_G1 MPC5XXX_GPIO_SIMPLE_PSC2_1 -#define LED_Y MPC5XXX_GPIO_SIMPLE_PSC2_2 -#define LED_R MPC5XXX_GPIO_SIMPLE_PSC2_3 -#define ARB_X_EN MPC5XXX_GPIO_WKUP_PSC2_4 - -#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0 -#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1 -#define FPGA_CONF_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2 -#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3 -#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4 - -#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0 -#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1 -#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2 -#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3 -#define FACT_RST MPC5XXX_GPIO_WKUP_6 -#define FLASH_RBY MPC5XXX_GPIO_WKUP_7 - -#define SIMPLE_DDR (LED_G0 | LED_G1 | LED_Y | LED_R | \ - FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI) -#define SIMPLE_DVO (FPGA_CONFIG) -#define SIMPLE_ODE (FPGA_CONFIG | LED_G0 | LED_G1 | LED_Y | LED_R) -#define SIMPLE_GPIOEN (LED_G0 | LED_G1 | LED_Y | LED_R | \ - FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\ - WD_WDI | COP_PRESENT) - -#define SINT_ODE 0 -#define SINT_DDR 0 -#define SINT_DVO 0 -#define SINT_INTEN 0 -#define SINT_ITYPE 0 -#define SINT_GPIOEN (FPGA_STATUS) - -#define WKUP_ODE (MAN_RST) -#define WKUP_DIR (ARB_X_EN|MAN_RST|WD_TS) -#define WKUP_DO (ARB_X_EN|MAN_RST|WD_TS) -#define WKUP_EN (ARB_X_EN|MAN_RST|WD_TS|FACT_RST|FLASH_RBY) - -#endif diff --git a/board/matrix_vision/mvbc_p/mvbc_p_autoscript b/board/matrix_vision/mvbc_p/mvbc_p_autoscript deleted file mode 100644 index 9b21f30ece..0000000000 --- a/board/matrix_vision/mvbc_p/mvbc_p_autoscript +++ /dev/null @@ -1,48 +0,0 @@ -echo -echo "==== running autoscript ====" -echo -setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} -setenv ramkernel setenv kernel_boot \${loadaddr} -setenv flashkernel setenv kernel_boot \${mv_kernel_addr} -setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} -setenv bootfromflash run flashkernel cpird ramparam addcons e1000para addprofile bootdtb -setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} -setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 -setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup -setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel -if test ${console} = yes; -then -setenv addcons setenv bootargs \${bootargs} console=ttyPSC\${console_nr},\${baudrate}N8 -else -setenv addcons setenv bootargs \${bootargs} console=tty0 -fi -setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=256 e1000.SmartPowerDownEnable=1 -setenv set_static_ip setenv ipaddr \${static_ipaddr} -setenv set_static_nm setenv netmask \${static_netmask} -setenv set_static_gw setenv gatewayip \${static_gateway} -setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} -setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs -if test ${oprofile} = yes; -then -setenv addprofile setenv bootargs \${bootargs} profile=\${profile} -fi -if test ${autoscript_boot} != no; -then - if test ${netboot} = yes; - then - bootp - if test $? = 0; - then - echo "=== bootp succeeded -> netboot ===" - run set_ip - run getdtb rundtb bootfromnet ramparam addcons e1000para addprofile bootdtb - else - echo "=== netboot failed ===" - fi - fi - run set_static_ip set_static_nm set_static_gw set_ip - echo "=== bootfromflash ===" - run cpdtb rundtb bootfromflash -else - echo "=== boot stopped with autoscript_boot no ===" -fi diff --git a/board/matrix_vision/mvsmr/.gitignore b/board/matrix_vision/mvsmr/.gitignore deleted file mode 100644 index 469f1bc4c1..0000000000 --- a/board/matrix_vision/mvsmr/.gitignore +++ /dev/null @@ -1 +0,0 @@ -bootscript.img diff --git a/board/matrix_vision/mvsmr/Kconfig b/board/matrix_vision/mvsmr/Kconfig deleted file mode 100644 index d725c5ac49..0000000000 --- a/board/matrix_vision/mvsmr/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MVSMR - -config SYS_BOARD - default "mvsmr" - -config SYS_VENDOR - default "matrix_vision" - -config SYS_CONFIG_NAME - default "MVSMR" - -endif diff --git a/board/matrix_vision/mvsmr/MAINTAINERS b/board/matrix_vision/mvsmr/MAINTAINERS deleted file mode 100644 index ae3cf9c0b2..0000000000 --- a/board/matrix_vision/mvsmr/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MVSMR BOARD -#M: Andre Schwarz -S: Orphan (since 2014-03) -F: board/matrix_vision/mvsmr/ -F: include/configs/MVSMR.h -F: configs/MVSMR_defconfig diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile deleted file mode 100644 index cef1b7664c..0000000000 --- a/board/matrix_vision/mvsmr/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004-2008 -# Matrix-Vision GmbH, info@matrix-vision.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mvsmr.o fpga.o - -extra-y := bootscript.img - -MKIMAGEFLAGS_bootscript.image := -T script -C none -n mvSMR_Script - -$(obj)/bootscript.img: $(src)/bootscript - $(call cmd,mkimage) diff --git a/board/matrix_vision/mvsmr/README.mvsmr b/board/matrix_vision/mvsmr/README.mvsmr deleted file mode 100644 index 8e34cb7838..0000000000 --- a/board/matrix_vision/mvsmr/README.mvsmr +++ /dev/null @@ -1,55 +0,0 @@ -Matrix Vision mvSMR -------------------- - -1. Board Description - - The mvSMR is a 75x130mm single image processing board used - in automation. Power Supply is 24VDC. - -2 System Components - -2.1 CPU - Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB. - 64MB DDR-I @ 133MHz. - 8 MByte Nor Flash on local bus. - 2 serial ports. Console running on ttyS0 @ 115200 8N1. - -2.2 PCI - PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core. - -2.3 FPGA - Xilinx Spartan-3 XC3S200 with PCI DMA engine. - Connects to Matrix Vision specific CCD/CMOS sensor interface. - -2.4 I2C - EEPROM @ 0xA0 for vendor specifics. - image sensor interface (slave addresses depend on sensor) - -3 Flash layout. - - reset vector is 0x00000100, i.e. "LOWBOOT". - - FF800000 u-boot - FF806000 u-boot script image - FF808000 u-boot environment - FF840000 FPGA raw bit file - FF880000 root FS - FFF00000 kernel - -4 Booting - - On startup the bootscript @ FF806000 is executed. This script can be - exchanged easily. Default boot mode is "boot from flash", i.e. system - works stand-alone. - - This behaviour depends on some environment variables : - - "netboot" : yes ->try dhcp/bootp and boot from network. - A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for - DHCP server configuration, e.g. to provide different images to - different devices. - - During netboot the system tries to get 3 image files: - 1. Kernel - name + data is given during BOOTP. - 2. Initrd - name is stored in "initrd_name" - Fallback files are the flash versions. diff --git a/board/matrix_vision/mvsmr/bootscript b/board/matrix_vision/mvsmr/bootscript deleted file mode 100644 index 02c802c8c7..0000000000 --- a/board/matrix_vision/mvsmr/bootscript +++ /dev/null @@ -1,42 +0,0 @@ -echo -echo "==== running autoscript ====" -echo -setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}' -setenv ramkernel 'setenv kernel_boot ${loadaddr}' -setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}' -setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}' -setenv bootfromflash run flashkernel cpird addcons boot24 -setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel' -if test ${console} = yes; -then -setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8' -else -setenv addcons 'setenv bootargs ${bootargs} console=tty0' -fi -setenv set_static_ip 'setenv ipaddr ${static_ipaddr}' -setenv set_static_nm 'setenv netmask ${static_netmask}' -setenv set_static_gw 'setenv gatewayip ${static_gateway}' -setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}' -if test ${servicemode} != yes; -then - echo "=== forced flash mode ===" - run set_static_ip set_static_nm set_static_gw set_ip bootfromflash -fi -if test ${autoscript_boot} != no; -then - if test ${netboot} = yes; - then - bootp - if test $? = 0; - then - echo "=== bootp succeeded -> netboot ===" - run set_ip bootfromnet addcons boot24 - else - echo "=== netboot failed ===" - fi - fi - echo "=== bootfromflash ===" - run set_static_ip set_static_nm set_static_gw set_ip bootfromflash -else - echo "=== boot stopped with autoscript_boot no ===" -fi diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c deleted file mode 100644 index 518992578c..0000000000 --- a/board/matrix_vision/mvsmr/fpga.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2010 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include "fpga.h" -#include "mvsmr.h" - -xilinx_spartan3_slave_serial_fns fpga_fns = { - fpga_pre_config_fn, - fpga_pgm_fn, - fpga_clk_fn, - fpga_init_fn, - fpga_done_fn, - fpga_wr_fn, - 0 -}; - -xilinx_desc spartan3 = { - xilinx_spartan2, - slave_serial, - XILINX_XC3S200_SIZE, - (void *) &fpga_fns, - 0, -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mvsmr_init_fpga(void) -{ - fpga_init(); - fpga_add(fpga_xilinx, &spartan3); - - return 1; -} - -int fpga_init_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (in_be32(&gpio->simple_ival) & FPGA_CONFIG) - return 0; - - return 1; -} - -int fpga_done_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - int result = 0; - - udelay(10); - if (in_be32(&gpio->simple_ival) & FPGA_DONE) - result = 1; - - return result; -} - -int fpga_pgm_fn(int assert, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (!assert) - setbits_8(&gpio->sint_dvo, FPGA_STATUS); - else - clrbits_8(&gpio->sint_dvo, FPGA_STATUS); - - return assert; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (assert_clk) - setbits_be32(&gpio->simple_dvo, FPGA_CCLK); - else - clrbits_be32(&gpio->simple_dvo, FPGA_CCLK); - - return assert_clk; -} - -int fpga_wr_fn(int assert_write, int flush, int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (assert_write) - setbits_be32(&gpio->simple_dvo, FPGA_DIN); - else - clrbits_be32(&gpio->simple_dvo, FPGA_DIN); - - return assert_write; -} - -int fpga_pre_config_fn(int cookie) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - setbits_8(&gpio->sint_dvo, FPGA_STATUS); - - return 0; -} diff --git a/board/matrix_vision/mvsmr/fpga.h b/board/matrix_vision/mvsmr/fpga.h deleted file mode 100644 index 7ef878bd44..0000000000 --- a/board/matrix_vision/mvsmr/fpga.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int mvsmr_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_init_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(int assert_write, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_pre_config_fn(int cookie); diff --git a/board/matrix_vision/mvsmr/mvsmr.c b/board/matrix_vision/mvsmr/mvsmr.c deleted file mode 100644 index 2c513897f8..0000000000 --- a/board/matrix_vision/mvsmr/mvsmr.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2005-2010 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "fpga.h" -#include "mvsmr.h" -#include "../common/mv_common.h" - -#define SDRAM_DDR 1 -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x715f0f00 -#define SDRAM_CONFIG1 0xd3722930 -#define SDRAM_CONFIG2 0x46770000 - -DECLARE_GLOBAL_DATA_PTR; - -static void sdram_start(int hi_addr) -{ - long hi_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | - hi_bit); - - /* precharge all banks */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | - hi_bit); - - /* set mode register: extended mode */ - out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE); - - /* set mode register: reset DLL */ - out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000); - - /* precharge all banks */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | - hi_bit); - - /* auto refresh */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | - hi_bit); - - /* set mode register */ - out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); - - /* normal operation */ - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit); -} - -phys_addr_t initdram(int board_type) -{ - ulong dramsize = 0; - ulong test1, - test2; - - /* setup SDRAM chip selects */ - out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); - - /* setup config registers */ - out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); - out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else - dramsize = test2; - - if (dramsize < (1 << 20)) - dramsize = 0; - - if (dramsize > 0) - out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 + - __builtin_ffs(dramsize >> 20) - 1); - else - out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0); - - return dramsize; -} - -void mvsmr_init_gpio(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - - printf("Ports : 0x%08x\n", gpio->port_config); - printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG)); - - out_be32(&gpio->simple_ddr, SIMPLE_DDR); - out_be32(&gpio->simple_dvo, SIMPLE_DVO); - out_be32(&gpio->simple_ode, SIMPLE_ODE); - out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN); - - out_8(&gpio->sint_ode, SINT_ODE); - out_8(&gpio->sint_ddr, SINT_DDR); - out_8(&gpio->sint_dvo, SINT_DVO); - out_8(&gpio->sint_inten, SINT_INTEN); - out_be16(&gpio->sint_itype, SINT_ITYPE); - out_8(&gpio->sint_gpioe, SINT_GPIOEN); - - out_8(&wu_gpio->ode, WKUP_ODE); - out_8(&wu_gpio->ddr, WKUP_DIR); - out_8(&wu_gpio->dvo, WKUP_DO); - out_8(&wu_gpio->enable, WKUP_EN); - - out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */ - out_be32(&timers->gpt1.emsr, 0x00000234); - out_be32(&timers->gpt2.emsr, 0x00000234); - out_be32(&timers->gpt3.emsr, 0x00000234); - out_be32(&timers->gpt4.emsr, 0x00000234); - out_be32(&timers->gpt5.emsr, 0x00000234); - out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */ - out_be32(&timers->gpt7.emsr, 0x00000024); -} - -int misc_init_r(void) -{ - char *s = getenv("reset_env"); - - if (s) { - printf(" === FACTORY RESET ===\n"); - mv_reset_environment(); - saveenv(); - } - - return -1; -} - -void mvsmr_get_dbg_present(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1; - - if (in_be32(&gpio->simple_ival) & COP_PRESENT) { - setenv("dbg_present", "no\0"); - setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0"); - } else { - setenv("dbg_present", "yes\0"); - setenv("bootstopkey", "s\0"); - setbits_8(&psc->command, PSC_RX_ENABLE); - } -} - -void mvsmr_get_service_mode(void) -{ - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - - if (in_8(&wu_gpio->ival) & SERVICE_MODE) - setenv("servicemode", "no\0"); - else - setenv("servicemode", "yes\0"); -} - -int mvsmr_get_mac(void) -{ - unsigned char mac[6]; - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - - if (in_8(&wu_gpio->ival) & LAN_PRSNT) { - setenv("lan_present", "no\0"); - return -1; - } else - setenv("lan_present", "yes\0"); - - i2c_read(0x50, 0, 1, mac, 6); - - eth_setenv_enetaddr("ethaddr", mac); - - return 0; -} - -int checkboard(void) -{ - mvsmr_init_gpio(); - printf("Board: Matrix Vision mvSMR\n"); - - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1); -} - -void flash_afterinit(ulong size) -{ - out_be32((u32 *)MPC5XXX_BOOTCS_START, - START_REG(CONFIG_SYS_BOOTCS_START | size)); - out_be32((u32 *)MPC5XXX_CS0_START, - START_REG(CONFIG_SYS_BOOTCS_START | size)); - out_be32((u32 *)MPC5XXX_BOOTCS_STOP, - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size)); - out_be32((u32 *)MPC5XXX_CS0_STOP, - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size)); -} - -struct pci_controller hose; - -void pci_init_board(void) -{ - mvsmr_get_dbg_present(); - mvsmr_get_service_mode(); - mvsmr_init_fpga(); - mv_load_fpga(); - pci_mpc5xxx_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - if (!mvsmr_get_mac()) - return cpu_eth_init(bis); - - return pci_eth_init(bis); -} diff --git a/board/matrix_vision/mvsmr/mvsmr.h b/board/matrix_vision/mvsmr/mvsmr.h deleted file mode 100644 index b8320f1e6e..0000000000 --- a/board/matrix_vision/mvsmr/mvsmr.h +++ /dev/null @@ -1,43 +0,0 @@ -#include - -extern void pci_mpc5xxx_init(struct pci_controller *); - -#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0 -#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1 -#define FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2 -#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3 -#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4 -#define S_FPGA_DIN MPC5XXX_GPIO_SINT_PSC3_5 -#define S_FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_6 -#define S_FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_7 -#define S_FPGA_CONFIG MPC5XXX_GPIO_SINT_PSC3_8 -#define S_FPGA_STATUS MPC5XXX_GPIO_WKUP_PSC3_9 - -#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0 -#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1 -#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2 -#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3 -#define SERVICE_MODE MPC5XXX_GPIO_WKUP_6 -#define FLASH_RBY MPC5XXX_GPIO_WKUP_7 -#define UART_EN1 MPC5XXX_GPIO_WKUP_PSC1_4 -#define LAN_PRSNT MPC5XXX_GPIO_WKUP_PSC2_4 - -#define SIMPLE_DDR (FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\ - S_FPGA_CCLK) -#define SIMPLE_DVO (FPGA_CONFIG) -#define SIMPLE_ODE (FPGA_CONFIG) -#define SIMPLE_GPIOEN (FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\ - S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT) - -#define SINT_ODE 0x1 -#define SINT_DDR 0x3 -#define SINT_DVO 0x1 -#define SINT_INTEN 0 -#define SINT_ITYPE 0 -#define SINT_GPIOEN (FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG) - -#define WKUP_ODE (MAN_RST | S_FPGA_STATUS) -#define WKUP_DIR (MAN_RST | WD_TS | S_FPGA_STATUS) -#define WKUP_DO (MAN_RST | WD_TS | S_FPGA_STATUS) -#define WKUP_EN (MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\ - FLASH_RBY | UART_EN1 | LAN_PRSNT) diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds deleted file mode 100644 index e885b7c160..0000000000 --- a/board/matrix_vision/mvsmr/u-boot.lds +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2010 - * André Schwarz, Matrix Vision GmbH, as@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the first two sectors (=8KB) of our S29GL flash chip */ - arch/powerpc/cpu/mpc5xxx/start.o (.text*) - arch/powerpc/cpu/mpc5xxx/traps.o (.text*) - board/matrix_vision/common/built-in.o (.text*) - - /* This is only needed to force failure if size of above code will ever */ - /* increase and grow into reserved space. */ - . = ALIGN(0x2000); /* location counter has to be 0x4000 now */ - . += 0x4000; /* ->0x8000, i.e. move to env_offset */ - - . = env_offset; /* ld error as soon as above ALIGN misplaces lc */ - common/env_embedded.o (.ppcenv) - - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/configs/MVBC_P_defconfig b/configs/MVBC_P_defconfig deleted file mode 100644 index b0351fd219..0000000000 --- a/configs/MVBC_P_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MVBC_P" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MVBC_P=y diff --git a/configs/MVSMR_defconfig b/configs/MVSMR_defconfig deleted file mode 100644 index a84c173089..0000000000 --- a/configs/MVSMR_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MVSMR=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 3caa8cf294..1dcdcc7bb6 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +MVBC_P powerpc mpc5xxx - - Andre Schwarz +MVSMR powerpc mpc5xxx - - Andre Schwarz MERGERBOX powerpc mpc83xx - - Andre Schwarz MVBLM7 powerpc mpc83xx - - Andre Schwarz bluestone powerpc ppc4xx - - Tirumala Marri diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h deleted file mode 100644 index 1ab2b3d51a..0000000000 --- a/include/configs/MVBC_P.h +++ /dev/null @@ -1,300 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2008 - * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_MPC5200 1 - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFF800000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 - -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 -#endif - -#define CONFIG_PSC_CONSOLE 1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400} - -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#undef CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_XLB_PIPELINING 1 -#define CONFIG_HIGH_BATS 1 - -#define MV_CI mvBlueCOUGAR-P -#define MV_VCI mvBlueCOUGAR-P -#define MV_FPGA_DATA 0xff860000 -#define MV_FPGA_SIZE 0 -#define MV_KERNEL_ADDR 0xffd00000 -#define MV_INITRD_ADDR 0xff900000 -#define MV_INITRD_LENGTH 0x00400000 -#define MV_SCRATCH_ADDR 0x00000000 -#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH -#define MV_SCRIPT_ADDR 0xff840000 -#define MV_SCRIPT_ADDR2 0xff850000 -#define MV_DTB_ADDR 0xfffc0000 - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define MV_KERNEL_ADDR_RAM 0x00100000 -#define MV_DTB_ADDR_RAM 0x00600000 -#define MV_INITRD_ADDR_RAM 0x01000000 - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define MV_DTB_NAME mvbc-p.dtb -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * Supported commands - */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_PCI -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_CMD_I2C - -#undef CONFIG_WATCHDOG - -#define CONFIG_BOOTP_VENDOREX -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_RANDOM_DELAY -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_LIB_RAND - -/* - * Autoboot - */ -#define CONFIG_BOOTDELAY 2 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR "s" -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_RESET_TO_RETRY 1000 - -#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \ - then source ${script_addr}; \ - else source ${script_addr2}; \ - fi;" - -#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console_nr=0\0" \ - "console=yes\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "fpga=0\0" \ - "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \ - "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \ - "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \ - "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \ - "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \ - "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \ - "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \ - "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \ - "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \ - "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \ - "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \ - "dtb_name=" __stringify(MV_DTB_NAME) "\0" \ - "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \ - "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \ - "mv_version=" U_BOOT_VERSION "\0" \ - "dhcp_client_id=" __stringify(MV_CI) "\0" \ - "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \ - "netretry=no\0" \ - "use_static_ipaddr=no\0" \ - "static_ipaddr=192.168.90.10\0" \ - "static_netmask=255.255.255.0\0" \ - "static_gateway=0.0.0.0\0" \ - "initrd_name=uInitrd.mvbc-p-rfs\0" \ - "zcip=no\0" \ - "netboot=yes\0" \ - "mvtest=Ff\0" \ - "tried_bootfromflash=no\0" \ - "tried_bootfromnet=no\0" \ - "use_dhcp=yes\0" \ - "gev_start=yes\0" \ - "mvbcdma_debug=0\0" \ - "mvbcia_debug=0\0" \ - "propdev_debug=0\0" \ - "gevss_debug=0\0" \ - "watchdog=1\0" \ - "sensor_cnt=1\0" \ - "" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK -#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 - -/* - * Flash configuration - */ -#undef CONFIG_FLASH_16BIT -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_FLASH_ERASE_TOUT 50000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_LOWBOOT -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_FLASH_SIZE 0x00800000 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_SYS_FLASH_PROTECTION - -#define CONFIG_ENV_ADDR 0xFFFE0000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT 1 -#endif - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 << 10) -#define CONFIG_SYS_MALLOC_LEN (512 << 10) -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_MODULE 1 -#define CONFIG_SYS_I2C_SPEED 86000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * Ethernet configuration - */ -#define CONFIG_NET_RETRY_COUNT 5 - -#define CONFIG_E1000 -#define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 } -#undef CONFIG_MPC5xxx_FEC -#undef CONFIG_PHY_ADDR -#define CONFIG_NETDEV eth0 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#undef CONFIG_SYS_LONGHELP -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CBSIZE 1024 -#else -#define CONFIG_SYS_CBSIZE 256 -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00800000 -#define CONFIG_SYS_MEMTEST_END 0x02f00000 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x02000000 -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 0x00200000 - -/* - * Various low-level settings - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x20000004 - -#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI) -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047800 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS_BURST 0x000000f0 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333303 - -#define CONFIG_SYS_RESET_ADDRESS 0x00000100 - -#undef FPGA_DEBUG -#undef CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_FPGA -#define CONFIG_FPGA_ALTERA 1 -#define CONFIG_FPGA_CYCLON2 1 -#define CONFIG_FPGA_COUNT 1 - -#endif diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h deleted file mode 100644 index 27f730d84b..0000000000 --- a/include/configs/MVSMR.h +++ /dev/null @@ -1,270 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2010 - * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_MPC5200 1 - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFF800000 -#endif -#define CONFIG_SYS_LDSCRIPT "board/matrix_vision/mvsmr/u-boot.lds" - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 - -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 -#endif - -#define CONFIG_PSC_CONSOLE 1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200,\ - 230400} - -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -#undef CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_XLB_PIPELINING 1 -#define CONFIG_HIGH_BATS 1 - -#define MV_CI mvSMR -#define MV_VCI mvSMR -#define MV_FPGA_DATA 0xff840000 -#define MV_FPGA_SIZE 0x1ff88 -#define MV_KERNEL_ADDR 0xfff00000 -#define MV_SCRIPT_ADDR 0xff806000 -#define MV_INITRD_ADDR 0xff880000 -#define MV_INITRD_LENGTH 0x00240000 -#define MV_SCRATCH_ADDR 0xffcc0000 -#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define MV_KERNEL_ADDR_RAM 0x00100000 -#define MV_INITRD_ADDR_RAM 0x00400000 - -/* - * Supported commands - */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SDRAM - -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_RANDOM_DELAY -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_VENDOREX -#define CONFIG_LIB_RAND - -/* - * Autoboot - */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR "abcdefg" -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#define CONFIG_BOOTCOMMAND "source ${script_addr}" -#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" \ - " allocate=6M" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console_nr=0\0" \ - "console=no\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "fpga=0\0" \ - "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \ - "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \ - "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \ - "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \ - "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \ - "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \ - "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \ - "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \ - "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \ - "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \ - "mv_version=" U_BOOT_VERSION "\0" \ - "dhcp_client_id=" __stringify(MV_CI) "\0" \ - "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \ - "netretry=no\0" \ - "use_static_ipaddr=no\0" \ - "static_ipaddr=192.168.0.101\0" \ - "static_netmask=255.255.255.0\0" \ - "static_gateway=0.0.0.0\0" \ - "initrd_name=uInitrd.mvsmr-rfs\0" \ - "zcip=yes\0" \ - "netboot=no\0" \ - "" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK - -/* - * Flash configuration - */ -#undef CONFIG_FLASH_16BIT -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_FLASH_ERASE_TOUT 50000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_LOWBOOT -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_FLASH_SIZE 0x00800000 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 - -/* used by linker script to wrap code around */ -#define CONFIG_SCRIPT_OFFSET 0x6000 -#define CONFIG_SCRIPT_SECT_SIZE 0x2000 - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT 1 -#endif - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 << 10) -#define CONFIG_SYS_MALLOC_LEN (512 << 10) -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_MODULE 1 -#define CONFIG_SYS_I2C_SPEED 86000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * Ethernet configuration - */ -#define CONFIG_NET_RETRY_COUNT 5 - -#define CONFIG_MPC5xxx_FEC -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_NETDEV eth0 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#undef CONFIG_SYS_LONGHELP -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CBSIZE 1024 -#else -#define CONFIG_SYS_CBSIZE 256 -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00800000 -#define CONFIG_SYS_MEMTEST_END 0x02f00000 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x02000000 -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 0x00200000 - -/* - * Various low-level settings - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00050044 - -#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI) -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047800 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS_BURST 0x000000f0 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333303 - -#define CONFIG_SYS_RESET_ADDRESS 0x00000100 - -#undef FPGA_DEBUG -#undef CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX 1 -#define CONFIG_FPGA_SPARTAN2 1 -#define CONFIG_FPGA_COUNT 1 - -#endif -- cgit v1.2.3 From 04e2a13336f0e507ef416bbede3be92b79c46594 Mon Sep 17 00:00:00 2001 From: Alexander Kochetkov Date: Mon, 29 Sep 2014 21:46:48 +0400 Subject: beagleboard: Remove side effects of i2c2 pullup resisters initialization code Fix typo of commit d4e53f063dd25e071444b87303573e7440deeb89. i2c2 pullup resisters are controlled by bit 0 of CONTROL_PROG_IO1. It's value after reset is 0x00100001. In order to clear bit 0, original code write 0xfffffffe to CONTROL_PROG_IO1 and toggle almost all default values. Original code affect following: * disable i2c1 pullup resisters * increase far end load setting for many modules * setup invalid SC/LB combination Signed-off-by: Alexander Kochetkov CC: Tom Rini CC: Steve Kipisz --- board/ti/beagle/beagle.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 0674afdc09..94b99bf537 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -317,9 +317,12 @@ int misc_init_r(void) struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE; bool generate_fake_mac = false; + u32 value; /* Enable i2c2 pullup resisters */ - writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1); + value = readl(&prog_io_base->io1); + value &= ~(PRG_I2C2_PULLUPRESX); + writel(value, &prog_io_base->io1); switch (get_board_revision()) { case REVISION_AXBX: -- cgit v1.2.3 From 2ea9103924048637d28baf0f7b1dd410f6704c32 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 30 Sep 2014 10:44:01 +0200 Subject: SPDX License cleanup for LiMon imported files A number of network related files were imported from the LiMon project; these contain a somewhat unclear license statement: Copyright 1994 - 2000 Neil Russell. (See License) I analyzed the source code of LiMon v1.4.2 which was used for this import. It does not contain any "License" file, but the top level directory contains a file "COPYING", which turns out to be GPL v2 of June 1991. So it is legitimate to conclude that the LiMon derived files are also to be released under GPLv2. Mark them as such. Signed-off-by: Wolfgang Denk --- include/net.h | 2 +- net/arp.c | 1 + net/arp.h | 1 + net/cdp.c | 1 + net/cdp.h | 1 + net/net.c | 1 + net/ping.c | 1 + net/ping.h | 1 + 8 files changed, 8 insertions(+), 1 deletion(-) diff --git a/include/net.h b/include/net.h index 735b0b9d26..18d279ebe7 100644 --- a/include/net.h +++ b/include/net.h @@ -3,7 +3,7 @@ * * Copyright 1994 - 2000 Neil Russell. * (See License) - * + * SPDX-License-Identifier: GPL-2.0 * * History * 9/16/00 bor adapted to TQM823L/STK8xxL board, RARP/TFTP boot added diff --git a/net/arp.c b/net/arp.c index 20c6b2d42a..21ed31bf74 100644 --- a/net/arp.c +++ b/net/arp.c @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #include diff --git a/net/arp.h b/net/arp.h index bfd57e0105..3a0a13a372 100644 --- a/net/arp.h +++ b/net/arp.h @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __ARP_H__ diff --git a/net/cdp.c b/net/cdp.c index 3d9559eb3b..2d8fa03a7e 100644 --- a/net/cdp.c +++ b/net/cdp.c @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #include diff --git a/net/cdp.h b/net/cdp.h index ec7315af79..95e4ce025d 100644 --- a/net/cdp.h +++ b/net/cdp.h @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #if defined(CONFIG_CMD_CDP) diff --git a/net/net.c b/net/net.c index 722089f3b9..2bea07b3cd 100644 --- a/net/net.c +++ b/net/net.c @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ /* diff --git a/net/ping.c b/net/ping.c index 0710b9228d..2be56ed929 100644 --- a/net/ping.c +++ b/net/ping.c @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #include "ping.h" diff --git a/net/ping.h b/net/ping.h index 8c71be4fdf..b672b95739 100644 --- a/net/ping.h +++ b/net/ping.h @@ -6,6 +6,7 @@ * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __PING_H__ -- cgit v1.2.3 From 3f2b5bb6741fa21d7a7768be3a9be3730c9ecf3b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20M=C3=BCller=20=28ELSOFT=20AG=29?= Date: Tue, 30 Sep 2014 12:32:20 +0200 Subject: PIP405: convert to generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: David Müller --- include/configs/PIP405.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index a6f505aaa9..9a1b2acac3 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -21,6 +21,8 @@ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 +#define CONFIG_SYS_GENERIC_BOARD + /*********************************************************** * Clock ***********************************************************/ -- cgit v1.2.3 From d3b88405e5ee4e37bc14cb66c12aa61b9f1b8ead Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20M=C3=BCller=20=28ELSOFT=20AG=29?= Date: Tue, 30 Sep 2014 12:32:21 +0200 Subject: MIP405: convert to generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: David Müller --- include/configs/MIP405.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 68824fd2d4..147f122967 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -21,6 +21,8 @@ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 +#define CONFIG_SYS_GENERIC_BOARD + /*********************************************************** * Note that it may also be a MIP405T board which is a subset of the * MIP405 -- cgit v1.2.3 From 13bd4d877687c6b6f1031d21b4124de336b6abb2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20M=C3=BCller=20=28ELSOFT=20AG=29?= Date: Tue, 30 Sep 2014 12:32:22 +0200 Subject: VCMA9: convert to generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: David Müller --- include/configs/VCMA9.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index d40185e1e2..0d8a13cb46 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -28,6 +28,8 @@ #define CONFIG_SYS_TEXT_BASE 0x0 +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH /* input clock of PLL (VCMA9 has 12MHz input clock) */ -- cgit v1.2.3 From 6c4c9a7c0fc54760370ad0b09fba11fd2bc9717f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20M=C3=BCller=20=28ELSOFT=20AG=29?= Date: Tue, 30 Sep 2014 12:32:23 +0200 Subject: PATI: convert to generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: David Müller --- include/configs/PATI.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/PATI.h b/include/configs/PATI.h index d823b0f3cc..65ab65d445 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -21,6 +21,8 @@ #define CONFIG_SYS_TEXT_BASE 0xFFF00000 +#define CONFIG_SYS_GENERIC_BOARD + /* Serial Console Configuration */ #define CONFIG_5xx_CONS_SCI1 #undef CONFIG_5xx_CONS_SCI2 -- cgit v1.2.3 From cf7d4505e3403a4ce039dc28c3a473414e7ea6a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20M=C3=BCller=20=28ELSOFT=20AG=29?= Date: Tue, 30 Sep 2014 13:23:54 +0200 Subject: PATI: fix broken SPI access MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix broken SPI access by adding/activating BOARD_EARLY_INIT_F functionality and calling spi_init_f() from there. Signed-off-by: David Müller --- board/mpl/pati/pati.c | 5 +++++ include/configs/PATI.h | 1 + 2 files changed, 6 insertions(+) diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c index 5d701a7931..b9d88ee17e 100644 --- a/board/mpl/pati/pati.c +++ b/board/mpl/pati/pati.c @@ -311,6 +311,11 @@ void user_led1(int led_on) sysconf->sc_sgpiodt2=reg; /* Data register */ } +int board_early_init_f(void) +{ + spi_init_f(); + return 0; +} /**************************************************************** * Last Stage Init diff --git a/include/configs/PATI.h b/include/configs/PATI.h index 65ab65d445..3ca204e1e2 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -98,6 +98,7 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } +#define CONFIG_BOARD_EARLY_INIT_F /*********************************************************************** * Last Stage Init -- cgit v1.2.3 From fbad4641fb194f9a864d7f666f02851770184933 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20M=C3=BCller=20=28ELSOFT=20AG=29?= Date: Tue, 30 Sep 2014 13:53:28 +0200 Subject: VCMA9: remove EXT2 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit remove the seldomly used EXT2 support because the U-Boot binary will not fit into the 512KiB flash otherwise. Signed-off-by: David Müller --- include/configs/VCMA9.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 0d8a13cb46..a97f5faae4 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -216,7 +216,6 @@ /* File system */ #define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS #define CONFIG_CMD_JFFS2 -- cgit v1.2.3 From 16c429c9ea91b9ccbd567ee45b7b7e4bc0778640 Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Wed, 1 Oct 2014 17:22:58 +0200 Subject: multiconfig.sh: replace GNU sed specific match A SPL/TPL enabled target would was not recognized as such by BSD sed, since it relies on a GNU extension. Instead of or-ing just spell out both matches. Cc: Masahiro Yamada Signed-off-by: Jeroen Hofstee Acked-by: Masahiro Yamada --- scripts/multiconfig.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh index b5185a84cf..3dadd714e2 100644 --- a/scripts/multiconfig.sh +++ b/scripts/multiconfig.sh @@ -69,8 +69,8 @@ get_enabled_subimages() { # CONFIG_SPL=y -> spl # CONFIG_TPL=y -> tpl - sed -n -e 's/^CONFIG_\(SPL\|TPL\)=y$/\1/p' $KCONFIG_CONFIG | \ - tr '[A-Z]' '[a-z]' + sed -n -e 's/^CONFIG_SPL=y$/spl/p' -e 's/^CONFIG_TPL=y$/tpl/p' \ + $KCONFIG_CONFIG } do_silentoldconfig () { -- cgit v1.2.3 From 703a08f2b33b92f64277b0d06d10cc83bdc617f3 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 1 Oct 2014 08:44:55 -0700 Subject: scripts/multiconfig.sh: Fix a typo Fix the spelling of "configs". Signed-off-by: York Sun CC: Masahiro Yamada Acked-by: Masahiro Yamada --- scripts/multiconfig.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh index 3dadd714e2..3a963c7973 100644 --- a/scripts/multiconfig.sh +++ b/scripts/multiconfig.sh @@ -120,7 +120,7 @@ do_board_defconfig () { if [ ! -r $defconfig_path ]; then echo >&2 "***" - echo >&2 "*** Can't find default configuration \"confis/$1\"!" + echo >&2 "*** Can't find default configuration \"configs/$1\"!" echo >&2 "***" exit 1 fi -- cgit v1.2.3 From 207828e215f7e8331ea3c304b922de9d155fb68e Mon Sep 17 00:00:00 2001 From: Hannes Petermaier Date: Fri, 3 Oct 2014 07:30:15 +0200 Subject: board/BuR: fix pinmux for MII Ethernet Interface The lines COL (collision detect) and CRS (carrier sense) needs to be connected and muxed to the CPSW MAC for a proper function in half-duplex Mode of the interface. Signed-off-by: Hannes Petermaier Cc: Tom Rini --- board/BuR/kwb/mux.c | 2 ++ board/BuR/tseries/mux.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c index 1a5ffd5709..ecb2e7a427 100644 --- a/board/BuR/kwb/mux.c +++ b/board/BuR/kwb/mux.c @@ -105,6 +105,8 @@ static struct module_pin_mux i2c0_pin_mux[] = { }; static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c index 210ac71738..0ba25ee318 100644 --- a/board/BuR/tseries/mux.c +++ b/board/BuR/tseries/mux.c @@ -64,6 +64,8 @@ static struct module_pin_mux spi0_pin_mux[] = { }; static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */ + {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ @@ -96,6 +98,7 @@ static struct module_pin_mux mii2_pin_mux[] = { {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */ {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */ {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */ + {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* * MII2_CRS is shared with * NAND_WAIT0 -- cgit v1.2.3 From ae1a74ebe7b4627205703f19e60c1c2c2fa06c73 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 3 Oct 2014 11:16:19 +0200 Subject: common/board_r: remove warning in initr_mem for 64-bit phys_size_t Since on powerpc phys_size_t can be unsigned long long, this printout line can result in a not nice compile warning. Signed-off-by: Valentin Longchamp Acked-by: Simon Glass --- common/board_r.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/board_r.c b/common/board_r.c index c339aad7f5..7e1a76d97f 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -664,7 +664,7 @@ int initr_mem(void) /* Also take the logbuffer into account (pram is in kB) */ pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024; # endif - sprintf(memsz, "%ldk", (gd->ram_size / 1024) - pram); + sprintf(memsz, "%ldk", (long int) ((gd->ram_size / 1024) - pram)); setenv("mem", memsz); return 0; -- cgit v1.2.3 From 787011834ee59f5abf10fdef5a1fc14f89e8e9c0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 3 Oct 2014 15:57:00 -0400 Subject: am335x_evm: Correct BOOTCOUNT driver support We need to set the 'BE' flag here for things to work right. Signed-off-by: Tom Rini --- include/configs/am335x_evm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index e2f7ead9bc..476430ddd0 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -223,6 +223,7 @@ /* Bootcount using the RTC block */ #define CONFIG_BOOTCOUNT_LIMIT #define CONFIG_BOOTCOUNT_AM33XX +#define CONFIG_SYS_BOOTCOUNT_BE /* USB gadget RNDIS */ #define CONFIG_SPL_MUSB_NEW_SUPPORT -- cgit v1.2.3 From f6c7c75482e10d115dab3567d7da8225fb24be6d Mon Sep 17 00:00:00 2001 From: Murali Karicheri Date: Thu, 9 Oct 2014 22:20:36 +0300 Subject: configs:ks2_evm: update defconfigs to support SPL The K2HK and K2E boards support SPL by default, so add CONFIG_SPL option. Also export CONFIG_ARM, CONFIG_ARCH_KEYSTONE and TARGET_K2*_EVM options to spl/.config as they are the same. So now it's convinient to build gph images using only two commands: make k2hk_evm_defconfig make u-boot-spi.gph Acked-By: Murali Karicheri Signed-off-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- configs/k2e_evm_defconfig | 7 ++++--- configs/k2hk_evm_defconfig | 7 ++++--- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index be8d2ee5e9..9e702198be 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -1,3 +1,4 @@ -CONFIG_ARM=y -CONFIG_ARCH_KEYSTONE=y -CONFIG_TARGET_K2E_EVM=y +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_KEYSTONE=y ++S:CONFIG_TARGET_K2E_EVM=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index eee3335487..e04e3151b6 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -1,3 +1,4 @@ -CONFIG_ARM=y -CONFIG_ARCH_KEYSTONE=y -CONFIG_TARGET_K2HK_EVM=y +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_KEYSTONE=y ++S:CONFIG_TARGET_K2HK_EVM=y -- cgit v1.2.3 From a79c911f350f481f3cb64c65f1b71aa32515275e Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Thu, 9 Oct 2014 22:21:14 +0300 Subject: ks2_evm: readme: align according to actual sources Update readme file for Keystone II EVM boards to actual sources. Also correct some typos. For now the Edison evaluation board is added, README for K2E is mostly the same, so update README to contain information also for K2E evm. Rename file to README as it contains information for all keystone evm boards. Signed-off-by: Ivan Khoronzhuk --- board/ti/ks2_evm/README | 161 +++++++++++++++++++++++++++++++++++++++++++ board/ti/ks2_evm/README_K2HK | 148 --------------------------------------- 2 files changed, 161 insertions(+), 148 deletions(-) create mode 100644 board/ti/ks2_evm/README delete mode 100644 board/ti/ks2_evm/README_K2HK diff --git a/board/ti/ks2_evm/README b/board/ti/ks2_evm/README new file mode 100644 index 0000000000..a551e2869a --- /dev/null +++ b/board/ti/ks2_evm/README @@ -0,0 +1,161 @@ +U-Boot port for Texas Instruments Keystone II EVM boards +======================================================== + +Author: Murali Karicheri + +This README has information on the u-boot port for K2HK, K2E boards. +Documentation for this board can be found at +http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx +https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html + +The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K. +More details on these SoCs are available at company websites + K2K: http://www.ti.com/product/tci6638k2k + K2H: http://www.ti.com/product/tci6638k2h + +The K2E SoC details are available at + K2E http://www.ti.com/lit/ds/symlink/66ak2e05.pdf + +Board configuration: +==================== + +Some of the peripherals that are configured by u-boot ++------+-------+-------+-----------+-----------+-------+-------+----+ +| |DDR3 |NAND |MSM SRAM |ETH ports |UART |I2C |SPI | ++------+-------+-------+-----------+-----------+-------+-------+----+ +|K2HK |2 |512MB |6MB |4(2) |2 |3 |3 | +|K2E |4 |512MB |2MB |8(2) |2 |3 |3 | ++------+-------+-------+-----------+-----------+-------+-------+----+ + +There are only 2 eth port installed on the boards. + +There are separate PLLs to drive clocks to Tetris ARM and Peripherals. +To bring up SMP Linux on this board, there is a boot monitor +code that will be installed in MSMC SRAM. There is command available +to install this image from u-boot. + +The port related files can be found at following folders + keystone2 SoC related files: arch/arm/cpu/armv7/keystone/ + EVMs board files: board/ti/k2s_evm/ + +Board configuration files: +include/configs/k2hk_evm.h +include/configs/k2e_evm.h + +As u-boot is migrating to Kconfig there is also board defconfig files +configs/k2e_evm_defconfig +configs/k2hk_evm_defconfig + +Supported boot modes: + - SPI NOR boot + - AEMIF NAND boot + +Supported image formats: + - u-boot.bin: for loading and running u-boot.bin through Texas instruments + code composure studio (CCS) + - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot + - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot + +Build instructions: +=================== +Examples for k2hk, for k2e just replace k2hk prefix accordingly. +Don't forget to add ARCH=arm and CROSS_COMPILE. + +To build u-boot.bin + >make k2hk_evm_defconfig + >make u-boot-spi.gph + +To build u-boot-spi.gph + >make k2hk_evm_defconfig + >make u-boot-spi.gph + +To build u-boot-nand.gph + >make k2hk_evm_defconfig + >make u-boot-nand.gph + +Load and Run U-Boot on keystone EVMs using CCS +========================================= + +Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin +on EVM. See instructions at below link for installing CCS on a Windows PC. +http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started# +Installing_Code_Composer_Studio +Use u-boot.bin from the build folder for loading and running u-boot binary +on EVM. Follow instructions at +K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup +K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup +to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode" +and Power ON the EVM. Follow instructions to connect serial port of EVM to +PC and start TeraTerm or Hyper Terminal. + +Start CCS on a Windows machine and Launch Target +configuration as instructed at http://processors.wiki.ti.com/index.php/ +MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS. +The instructions provided in the above link uses a script for +loading the u-boot binary on the target EVM. Instead do the following:- + +1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D + is connected: Unknown)" at the debug window (This is created once Target + configuration is launched) and select "Connect Target". +2. Once target connect is successful, choose Tools->Load Memory option from the + top level menu. At the Load Memory window, choose the file u-boot.bin + through "Browse" button and click "next >" button. In the next window, enter + Start address as 0xc001000, choose Type-size "32 bits" and click "Finish" + button. +3. Click View -> Registers from the top level menu to view registers window. +4. From Registers, window expand "Core Registers" to view PC. Edit PC value + to be 0xc001000. From the "Run" top level menu, select "Free Run" +5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as + below and type any key to stop autoboot as instructed := + +U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59) + +I2C: ready +Detected SO-DIMM [SQR-SD3T-2G1333SED] +DRAM: 1.1 GiB +NAND: 512 MiB +Net: K2HK_EMAC +Warning: K2HK_EMAC using MAC address from net device +, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3 +Hit any key to stop autoboot: 0 + +SPI NOR Flash programming instructions +====================================== +U-Boot image can be flashed to first 512KB of the NOR flash using following +instructions: + +1. Start CCS and run U-boot as described above. +2. Suspend Target. Select Run -> Suspend from top level menu + CortexA15_1 (Free Running)" +3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000 + through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E EVM + using CCS", but using address 0x87000000. +4. Free Run the target as described earlier (step 4) to get u-boot prompt +5. At the U-Boot console type following to setup u-boot environment variables. + setenv addr_uboot 0x87000000 + setenv filesize + run burn_uboot_spi + Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch + to "SPI Little Endian Boot mode" as per instruction at + http://processors.wiki.ti.com/index.php/*_Hardware_Setup. +6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash. + +AEMIF NAND Flash programming instructions +====================================== +U-Boot image can be flashed to first 1024KB of the NAND flash using following +instructions: + +1. Start CCS and run U-boot as described above. +2. Suspend Target. Select Run -> Suspend from top level menu + CortexA15_1 (Free Running)" +3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000 + through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM + using CCS", but using address 0x87000000. +4. Free Run the target as described earlier (step 4) to get u-boot prompt +5. At the U-Boot console type following to setup u-boot environment variables. + setenv filesize + run burn_uboot_nand + Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch + to "ARM NAND Boot mode" as per instruction at + http://processors.wiki.ti.com/index.php/*_Hardware_Setup. +6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash. diff --git a/board/ti/ks2_evm/README_K2HK b/board/ti/ks2_evm/README_K2HK deleted file mode 100644 index 7426b8dc97..0000000000 --- a/board/ti/ks2_evm/README_K2HK +++ /dev/null @@ -1,148 +0,0 @@ -U-Boot port for Texas Instruments XTCIEVMK2X -============================================ - -Author: Murali Karicheri - -This README has information on the u-boot port for XTCIEVMK2X EVM board. -Documentation for this board can be found at - http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx - -The board is based on Texas Instruments Keystone2 family of SoCs : K2H, K2K. -More details on these SoCs are available at company websites - K2K: http://www.ti.com/product/tci6638k2k - K2H: http://www.ti.com/product/tci6638k2h - -Board configuration: -==================== - -Some of the peripherals that are configured by u-boot are:- - -1. 2GB DDR3 (can support 8GB SO DIMM as well) -2. 512M NAND (over ti emif16 bus) -3. 6MB MSM SRAM (part of the SoC) -4. two 1GBit Ethernet ports (SoC supports upto 4) -5. two UART ports -6. three i2c interfaces -7. three spi interfaces (only 1 interface supported in driver) - -There are seperate PLLs to drive clocks to Tetris ARM and Peripherals. -To bring up SMP Linux on this board, there is a boot monitor -code that will be installed in MSMC SRAM. There is command available -to install this image from u-boot. - -The port related files can be found at following folders - keystone2 SoC related files: arch/arm/cpu/armv7/keystone/ - K2HK evm board files: board/ti/k2hk_evm/ - -board configuration file: include/configs/k2hk_evm.h - -Supported boot modes: - - SPI NOR boot - - AEMIF NAND boot - -Supported image formats:- - - u-boot.bin: for loading and running u-boot.bin through Texas instruments - code composure studio (CCS) - - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot - - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot - -Build instructions: -=================== - -To build u-boot.bin - >make k2hk_evm_config - >make u-boot-spi.gph - -To build u-boot-spi.gph - >make k2hk_evm_config - >make u-boot-spi.gph - -To build u-boot-nand.gph - >make k2hk_evm_config - >make u-boot-nand.gph - -Load and Run U-Boot on K2HK EVM using CCS -========================================= - -Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin -on EVM. See instructions at below link for installing CCS on a Windows PC. -http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started# -Installing_Code_Composer_Studio -Use u-boot.bin from the build folder for loading annd running u-boot binary -on EVM. Follow instructions at -http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup -to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode" -and Power ON the EVM. Follow instructions to connect serial port of EVM to -PC and start TeraTerm or Hyper Terminal. - -Start CCS on a Windows machine and Launch Target -configuration as instructed at http://processors.wiki.ti.com/index.php/ -MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS. -The instructions provided in the above link uses a script for -loading the u-boot binary on the target EVM. Instead do the following:- - -1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D - isconnected: Unknown)" at the debug window (This is created once Target - configuration is launched) and select "Connect Target". -2. Once target connect is successful, choose Tools->Load Memory option from the - top level menu. At the Load Memory window, choose the file u-boot.bin - through "Browse" button and click "next >" button. In the next window, enter - Start address as 0xc001000, choose Type-size "32 bits" and click "Finish" - button. -3. Click View -> Registers from the top level menu to view registers window. -4. From Registers, window expand "Core Registers" to view PC. Edit PC value - to be 0xc001000. From the "Run" top level menu, select "Free Run" -5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as - below and type any key to stop autoboot as instructed := - -U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59) - -I2C: ready -Detected SO-DIMM [SQR-SD3T-2G1333SED] -DRAM: 1.1 GiB -NAND: 512 MiB -Net: K2HK_EMAC -Warning: K2HK_EMAC using MAC address from net device -, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3 -Hit any key to stop autoboot: 0 - -SPI NOR Flash programming instructions -====================================== -U-Boot image can be flashed to first 512KB of the NOR flash using following -instructions:- - -1. Start CCS and run U-boot as described above. -2. Suspend Target. Select Run -> Suspend from top level menu - CortexA15_1 (Free Running)" -3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000 - through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM - using CCS", but using address 0x87000000. -4. Free Run the target as desribed earlier (step 4) to get u-boot prompt -5. At the U-Boot console type following to setup u-boot environment variables. - setenv addr_uboot 0x87000000 - setenv filesize - run burn_uboot_spi - Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch - to "SPI Little Endian Boot mode" as per instruction at - http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. -6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash. - -AEMIF NAND Flash programming instructions -====================================== -U-Boot image can be flashed to first 1024KB of the NAND flash using following -instructions:- - -1. Start CCS and run U-boot as described above. -2. Suspend Target. Select Run -> Suspend from top level menu - CortexA15_1 (Free Running)" -3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000 - through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM - using CCS", but using address 0x87000000. -4. Free Run the target as desribed earlier (step 4) to get u-boot prompt -5. At the U-Boot console type following to setup u-boot environment variables. - setenv filesize - run burn_uboot_nand - Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch - to "ARM NAND Boot mode" as per instruction at - http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. -6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash. -- cgit v1.2.3 From 4a74298c54272f1b0397826072c193158d3e7f14 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 10 Oct 2014 18:30:17 +0200 Subject: serial-uclass: Fix compilation error Signed-off-by: Hans de Goede --- drivers/serial/serial-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index fd010cac42..6dde4eaf47 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -198,7 +198,7 @@ static int serial_pre_remove(struct udevice *dev) #ifdef CONFIG_SYS_STDIO_DEREGISTER struct serial_dev_priv *upriv = dev->uclass_priv; - if (stdio_deregister_dev(upriv->sdev), 0) + if (stdio_deregister_dev(upriv->sdev, 0)) return -EPERM; #endif -- cgit v1.2.3 From 476095772f3aa58ee581943e4e993d9b8a61239c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Thu, 18 Sep 2014 23:46:48 +0200 Subject: macb: simplify gmac initialisation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann Cc: Joe Hershberger Cc: Bo Shen --- drivers/net/macb.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 01a94a4c4d..375c8a4454 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -479,31 +479,22 @@ static int macb_phy_init(struct macb_device *macb) /* First check for GMAC */ if (macb_is_gem(macb)) { lpa = macb_mdio_read(macb, MII_STAT1000); - if (lpa & (1 << 11)) { - speed = 1000; - duplex = 1; - } else { - if (lpa & (1 << 10)) { - speed = 1000; - duplex = 1; - } else { - speed = 0; - } - } - if (speed == 1000) { - printf("%s: link up, %dMbps %s-duplex (lpa: 0x%04x)\n", + if (lpa & (LPA_1000FULL | LPA_1000HALF)) { + duplex = ((lpa & LPA_1000FULL) ? 1 : 0); + + printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n", netdev->name, - speed, duplex ? "full" : "half", lpa); ncfgr = macb_readl(macb, NCFGR); - ncfgr &= ~(GEM_BIT(GBE) | MACB_BIT(SPD) | MACB_BIT(FD)); - if (speed) - ncfgr |= GEM_BIT(GBE); + ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); + ncfgr |= GEM_BIT(GBE); + if (duplex) ncfgr |= MACB_BIT(FD); + macb_writel(macb, NCFGR, ncfgr); return 1; -- cgit v1.2.3 From b719a08863dc865fbdd049f50eefeca52fc2cdcc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Thu, 18 Sep 2014 23:46:49 +0200 Subject: sama5d3xek: run PHY's config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann Cc: Bo Shen --- board/atmel/sama5d3xek/sama5d3xek.c | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index f53754bc87..ca4f79ddc1 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -273,15 +274,25 @@ int dram_init(void) int board_phy_config(struct phy_device *phydev) { - /* rx data delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222); - /* tx data delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222); - /* rx/tx clock delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4); + /* board specific timings for GMAC */ + if (has_gmac()) { + /* rx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, + 0x2222); + /* tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, + 0x2222); + /* rx/tx clock delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, + 0xf2f4); + } + + /* always run the PHY's config routine */ + if (phydev->drv->config) + return phydev->drv->config(phydev); return 0; } -- cgit v1.2.3 From b2868187f46ce2d00f90139287661ace1af64ac2 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 24 Sep 2014 15:35:53 +0800 Subject: ARM: atmel: switch at91sam9263ek to generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann --- include/configs/at91sam9263ek.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 48c12ea880..b666d9494d 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -48,6 +48,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + /* * Hardware drivers */ -- cgit v1.2.3 From d0b3723034aa865b8618428739efe1d98b1a2e2b Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 1 Oct 2014 07:26:06 +0200 Subject: arm, at91: add generic board support for the taurus and corvus board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Heiko Schocher Cc: Andreas Bießmann Cc: Bo Shen Signed-off-by: Andreas Bießmann --- include/configs/corvus.h | 2 ++ include/configs/taurus.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 6171060e9c..eb1584d3cc 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -18,6 +18,8 @@ #define MACH_TYPE_CORVUS 2066 +#define CONFIG_SYS_GENERIC_BOARD + /* * Warning: changing CONFIG_SYS_TEXT_BASE requires * adapting the initial boot program. diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 20d4cee011..aadf4cd2f8 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -24,6 +24,8 @@ #define MACH_TYPE_TAURUS 2067 #define MACH_TYPE_AXM 2068 +#define CONFIG_SYS_GENERIC_BOARD + /* * Warning: changing CONFIG_SYS_TEXT_BASE requires * adapting the initial boot program. -- cgit v1.2.3 From ed8271d11c5c7a31eb49f787fa25eece6b82bb9e Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Tue, 7 Oct 2014 22:42:27 +0200 Subject: tools: compiler.h: Fix build on FreeBSD Commit 832472 "tools: socfpga: Add socfpga preloader signing to mkimage" added tools/socfpga.c which relies on htole32, le32toh and friends. While compiler.h includes these protypes for linux from endian.h, it doesn't do so for FreeBSD. Hence include for FreeBSD. Cc: Marek Vasut CC: Tom Rini Signed-off-by: Jeroen Hofstee --- include/compiler.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/compiler.h b/include/compiler.h index 14519163a3..21036022d7 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -48,6 +48,10 @@ # include typedef unsigned long ulong; #endif +#ifdef __FreeBSD__ +# include /* htole32 and friends */ +#endif + #include typedef uint8_t __u8; -- cgit v1.2.3 From d8540a16193703a8e5833befbf410c299b83c990 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Fri, 10 Oct 2014 01:50:22 +0200 Subject: arm: socfpga: add MAINTAINERS entry Add MAINTAINERS entry. Signed-off-by: Pavel Machek Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index aafa061ed8..fd346c9fca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -65,6 +65,13 @@ S: Maintained T: git git://git.denx.de/u-boot-arm.git F: arch/arm/ +ARM ALTERA SOCFPGA +M: Marek Vasut +S: Maintainted +T: git git://git.denx.de/u-boot-socfpga.git +F: arch/arm/cpu/armv7/socfpga/ +F: board/altera/socfpga/ + ARM ATMEL AT91 M: Andreas Bießmann S: Maintained -- cgit v1.2.3 From 5a1d0ad3ee1ba98ca273c4b35c68618f107ccadd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 10 Oct 2014 01:50:23 +0200 Subject: arm: socfpga: Use EMAC1 on SoCDK The SoCDK uses EMAC1, not EMAC0. This patch fixes the issue. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek --- include/configs/socfpga_cyclone5.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 8d54bf892d..60d7e20e83 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -53,7 +53,7 @@ /* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) -#define CONFIG_EMAC_BASE SOCFPGA_EMAC0_ADDRESS +#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII #define CONFIG_EPHY0_PHY_ADDR 0 -- cgit v1.2.3 From c7ad5cbb1ef2c33883f0fa7d0455095004fd306d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 13 Oct 2014 08:38:55 -0400 Subject: Makefile: drop "tools-only" from no-dot-config-targets With the introduction of CONFIG_LOCALVERSION support we cannot build tools without having a config file (as we won't know our PLAIN_VERSION until then). Reported-by: Otavio Salvador Signed-off-by: Tom Rini --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 8657417329..4aa7cba447 100644 --- a/Makefile +++ b/Makefile @@ -411,7 +411,7 @@ timestamp_h := include/generated/timestamp_autogenerated.h no-dot-config-targets := clean clobber mrproper distclean \ help %docs check% coccicheck \ - ubootversion backup tools-only + ubootversion backup config-targets := 0 mixed-targets := 0 -- cgit v1.2.3 From 74bf7961a0af0b725d7f0376422d0bdd5bd3c707 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 13 Oct 2014 14:51:40 +0200 Subject: sunxi: axp152: dcdc3 scale is 50mV / step not 25mV / step Currently uboot wrongly uses 25mV / step for dcdc3, this is a copy and paste error introduced when adding the axp152_mvolt_to_target during review of the axp152.c driver. This results in u-boot setting Vddr to 2.3V instead of 1.5V. This commit fixes this. Signed-off-by: Hans de Goede --- drivers/power/axp152.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/axp152.c b/drivers/power/axp152.c index fa4ea050a5..27c2c4c8da 100644 --- a/drivers/power/axp152.c +++ b/drivers/power/axp152.c @@ -62,7 +62,7 @@ int axp152_set_dcdc2(int mvolt) int axp152_set_dcdc3(int mvolt) { - u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 25); + u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 50); return axp152_write(AXP152_DCDC3_VOLTAGE, target); } -- cgit v1.2.3 From c43fd23cf619856b0763a64a6a3bcf3663058c49 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 14 Oct 2014 04:47:15 -0400 Subject: Prepare v2014.10 Signed-off-by: Tom Rini --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 4aa7cba447..99097e1e57 100644 --- a/Makefile +++ b/Makefile @@ -8,7 +8,7 @@ VERSION = 2014 PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = -rc3 +EXTRAVERSION = NAME = # *DOCUMENTATION* -- cgit v1.2.3