From d848771a7e3419bac437928e08f2573caf91c087 Mon Sep 17 00:00:00 2001
From: Max Krummenacher <max.krummenacher@toradex.com>
Date: Mon, 2 Nov 2015 19:38:19 +0100
Subject: imximage.cfg: check ram timings and align with mainline

---
 board/toradex/colibri_imx7/imximage.cfg | 81 ++++++++++++++++++++++++++-------
 1 file changed, 65 insertions(+), 16 deletions(-)

diff --git a/board/toradex/colibri_imx7/imximage.cfg b/board/toradex/colibri_imx7/imximage.cfg
index 3b8242e13f..4ca885ce32 100644
--- a/board/toradex/colibri_imx7/imximage.cfg
+++ b/board/toradex/colibri_imx7/imximage.cfg
@@ -49,62 +49,111 @@ CSF CONFIG_CSF_SIZE
  *	value	  value to be stored in the register
  */
 
+/* IOMUXC_GPR_GPR1 */
 DATA 4 0x30340004 0x4F400005
 
+/* DDR3L */
+/* assuming MEMC_FREQ_RATIO = 2 */
+/* SRC_DDRC_RCR */
 DATA 4 0x30391000 0x00000002
-DATA 4 0x307a0000 0x03040001
+/* DDRC_MSTR */
+DATA 4 0x307a0000 0x01040001
+/* DDRC_DFIUPD0 */
 DATA 4 0x307a01a0 0x80400003
+/* DDRC_DFIUPD1 */
 DATA 4 0x307a01a4 0x00100020
+/* DDRC_DFIUPD2 */
 DATA 4 0x307a01a8 0x80100004
-DATA 4 0x307a0064 0x0040005e
+/* DDRC_RFSHTMG */
+DATA 4 0x307a0064 0x00400045
+/* DDRC_MP_PCTRL_0 */
 DATA 4 0x307a0490 0x00000001
-DATA 4 0x307a00d0 0x00020001
-DATA 4 0x307a00d4 0x00010000
+/* DDRC_INIT0 */
+DATA 4 0x307a00d0 0x00020083
+/* DDRC_INIT1 */
+DATA 4 0x307a00d4 0x00690000
+/* DDRC_INIT3 MR0/MR1 */
 DATA 4 0x307a00dc 0x09300004
-DATA 4 0x307a00e0 0x04080000
-DATA 4 0x307a00e4 0x00090004
+/* DDRC_INIT4 MR2/MR3 */
+DATA 4 0x307a00e0 0x04480000
+/* DDRC_INIT5 */
+DATA 4 0x307a00e4 0x00100004
+/* DDRC_RANKCTL */
 DATA 4 0x307a00f4 0x0000033f
-DATA 4 0x307a0100 0x0908120a
-DATA 4 0x307a0104 0x0002020e
-DATA 4 0x307a0108 0x03040407
+/* DDRC_DRAMTMG0 */
+DATA 4 0x307a0100 0x090b090a
+/* DDRC_DRAMTMG1 */
+DATA 4 0x307a0104 0x000d020d
+/* DDRC_DRAMTMG2 */
+DATA 4 0x307a0108 0x03040307
+/* DDRC_DRAMTMG3 */
 DATA 4 0x307a010c 0x00002006
-DATA 4 0x307a0110 0x04020204
+/* DDRC_DRAMTMG4 */
+DATA 4 0x307a0110 0x04020205
+/* DDRC_DRAMTMG5 */
 DATA 4 0x307a0114 0x03030202
-DATA 4 0x307a0120 0x03030803
+/* DDRC_DRAMTMG8 */
+DATA 4 0x307a0120 0x00000803
+/* DDRC_ZQCTL0 */
 DATA 4 0x307a0180 0x00800020
+/* DDRC_ZQCTL1 */
+DATA 4 0x307a0184 0x02001000
+/* DDRC_DFITMG0 */
 DATA 4 0x307a0190 0x02098204
+/* DDRC_DFITMG1 */
 DATA 4 0x307a0194 0x00030303
+/* DDRC_ADDRMAP0 */
 DATA 4 0x307a0200 0x00000016
+/* DDRC_ADDRMAP1 */
 DATA 4 0x307a0204 0x00171717
+/* DDRC_ADDRMAP5 */
 DATA 4 0x307a0214 0x04040404
-DATA 4 0x307a0218 0x00040404
+/* DDRC_ADDRMAP6 */
+DATA 4 0x307a0218 0x0f040404
+/* DDRC_ODTCFG */
 DATA 4 0x307a0240 0x06000601
-DATA 4 0x307a0244 0x00001323
+/* DDRC_ODTMAP */
+DATA 4 0x307a0244 0x00000011
+/* SRC_DDRC_RCR */
 DATA 4 0x30391000 0x00000000
+/* DDR_PHY_PHY_CON0 */
 DATA 4 0x30790000 0x17420f40
+/* DDR_PHY_PHY_CON1 */
 DATA 4 0x30790004 0x10210100
+/* DDR_PHY_PHY_CON4 */
 DATA 4 0x30790010 0x00060807
+/* DDR_PHY_MDLL_CON0 */
+DATA 4 0x307900b0 0x1010007e
+/* DDR_PHY_DRVDS_CON0 */
 DATA 4 0x3079009c 0x00000d6e
+/* DDR_PHY_OFFSET_RD_CON0 */
 DATA 4 0x30790020 0x08080808
+/* DDR_PHY_OFFSET_WR_CON0 */
 DATA 4 0x30790030 0x08080808
+/* DDR_PHY_CMD_SDLL_CON0 */
 DATA 4 0x30790050 0x01000010
 DATA 4 0x30790050 0x00000010
 
+/* DDR_PHY_ZQ_CON0 */
 DATA 4 0x307900c0 0x0e407304
 DATA 4 0x307900c0 0x0e447304
 DATA 4 0x307900c0 0x0e447306
-
+/* DDR_PHY_ZQ_CON1 */
 CHECK_BITS_SET 4 0x307900c4 0x1
-
+/* DDR_PHY_ZQ_CON0 */
 DATA 4 0x307900c0 0x0e447304
 DATA 4 0x307900c0 0x0e407304
 
-
+/* CCM_CCGRn */
 DATA 4 0x30384130 0x00000000
+/* IOMUXC_GPR_GPR8 */
 DATA 4 0x30340020 0x00000178
+/* CCM_CCGRn */
 DATA 4 0x30384130 0x00000002
+/* DDR_PHY_LP_CON0 */
 DATA 4 0x30790018 0x0000000f
 
+/* DDRC_STAT */
 CHECK_BITS_SET 4 0x307a0004 0x1
 
 #endif
-- 
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