installing and testing RedBoot RedBootinstalling and testing Matsushita MN103E010 (AM33/2.0) ASB2305 Board installing and testing installing and testing Matsushita MN103E010 (AM33/2.0) ASB2305 Board RedBoot supports the debug serial port and the built in ethernet port for communication and downloads. The default serial port settings are 115200,8,N,1 with RTS/CTS flow control. RedBoot can run from either flash, and can support flash management for either the boot PROM or the system flash regions. The following RedBoot configurations are supported: Configuration Mode Description File PROM [ROM] RedBoot running from the boot PROM and able to access the system flash. redboot_ROM.ecm FLASH [ROM] RedBoot running from the system flash and able to access the boot PROM. redboot_FLASH.ecm RAM [RAM] RedBoot running from RAM and able to access the boot PROM. redboot_RAM.ecm Unless a pre-programmed system flash module is available to be plugged into a new board, RedBoot must be installed with the aid of a JTAG interface unit. To achieve this, the RAM mode RedBoot must be loaded directly into RAM by JTAG and started, and then that must be used to store the ROM mode RedBoot into the boot PROM. These instructions assume that you have binary images of the RAM-based and boot PROM-based RedBoot images available. If the board is to be programmed, whether via JTAG or RedBoot, some hardware settings need to be changed: Jumper across ST18 on the board to allow write access to the boot PROM. Set DIP switch S1-3 to OFF to allow RedBoot to write to the system flash. Set the switch S5 (on the front of the board) to boot from whichever flash is not being programmed. Note that the RedBoot image cannot access the flash from which it is currently executing (it can only access the other flash). The RedBoot binary image files should also be copied to the TFTP pickup area on the host providing TFTP services if that is how RedBoot should pick up the images it is going to program into the flash. Alternatively, the images can be passed by YMODEM over the serial link. The JTAG debugger will also need setting up: Install the JTAG debugger software (WICE103E) on a PC running Windows (WinNT is probably the best choice for this) in “C:/PanaX”. Install the Matsushita provided “project” into the “C:/Panax/wice103e/prj” directory. Install the RedBoot image files into the “C:/Panax/wice103e/prj” directory under the names redboot.ram and redboot.prom. Make sure the PC's BIOS has the parallel port set to full bidirectional mode. Connect the JTAG debugger to the PC's parallel port. Connect the JTAG debugger to the board. Set the switch on the front of the board to boot from “boot PROM”. Power up the JTAG debugger and then power up the board. Connect the board's Debug Serial port to a computer by a null modem cable. Start minicom or some other serial communication software and set for 115200 baud, 1-N-8 with hardware (RTS/CTS) flow control. To perform the first half of the operation, the following steps should be followed: Start the JTAG debugger software. Run the following commands at the JTAG debugger's prompt to set up the MMU registers on the CPU. ed 0xc0002000, 0x12000580 ed 0xd8c00100, 0x8000fe01 ed 0xd8c00200, 0x21111000 ed 0xd8c00204, 0x00100200 ed 0xd8c00208, 0x00000004 ed 0xd8c00110, 0x8400fe01 ed 0xd8c00210, 0x21111000 ed 0xd8c00214, 0x00100200 ed 0xd8c00218, 0x00000004 ed 0xd8c00120, 0x8600ff81 ed 0xd8c00220, 0x21111000 ed 0xd8c00224, 0x00100200 ed 0xd8c00228, 0x00000004 ed 0xd8c00130, 0x8680ff81 ed 0xd8c00230, 0x21111000 ed 0xd8c00234, 0x00100200 ed 0xd8c00238, 0x00000004 ed 0xd8c00140, 0x9800f801 ed 0xd8c00240, 0x00140000 ed 0xd8c00244, 0x11011100 ed 0xd8c00248, 0x01000001 ed 0xda000000, 0x55561645 ed 0xda000004, 0x000003c0 ed 0xda000008, 0x9000fe01 ed 0xda00000c, 0x9200fe01 ed 0xda000000, 0xa89b0654 Run the following commands at the JTAG debugger's prompt to tell it what regions of the CPU's address space it can access: ex 0x80000000,0x81ffffff,/mexram ex 0x84000000,0x85ffffff,/mexram ex 0x86000000,0x867fffff,/mexram ex 0x86800000,0x87ffffff,/mexram ex 0x8c000000,0x8cffffff,/mexram ex 0x90000000,0x93ffffff,/mexram Instruct the debugger to load the RAM RedBoot image into RAM: _pc=90000000 u_pc rd redboot.ram,90000000 Load the boot PROM RedBoot into RAM: rd redboot.prom,91020000 Start RedBoot in RAM: g Note that RedBoot may take some time to start up, as it will attempt to query a BOOTP or DHCP server to try and automatically get an IP address for the board. Note, however, that it should send a plus over the serial port immediately, and the 7-segment LEDs should display “rh 8”. Once the RAM mode RedBoot is up and running, it can be communicated with by way of the serial port. Commands can now be entered directly to RedBoot for flashing the boot PROM. Instruct RedBoot to initialise the boot PROM: RedBoot> fi init Write the previously loaded redboot.prom image into the boot PROM: RedBoot> fi write -f 0x80000000 -b 0x91020000 -l 0x00020000 Check that RedBoot has written the image: RedBoot> dump -b 0x91020000 RedBoot> dump -b 0x80000000 Barring the difference in address, the two dumps should be the same. Close the JTAG software and power-cycle the board. The RedBoot banners should be displayed again over the serial port, followed by the RedBoot prompt. The boot PROM-based RedBoot will now be running. Power off the board and unjumper ST18 to write-protect the contents of the boot PROM. Then power the board back up. Run the following command to initialise the system flash: RedBoot> fi init Then program the system flash based RedBoot into the system flash: RedBoot> load -r -b %{FREEMEMLO} redboot_FLASH.bin RedBoot> fi write -f 0x84000000 -b %{FREEMEMLO} -l 0x00020000 RedBoot arranges the flashes on booting such that they always appear at the same addresses, no matter which one was booted from. A similar sequence of commands can be used to program the boot PROM when RedBoot has been booted from an image stored in the system flash. RedBoot> load -r -b %{FREEMEMLO} /tftpboot/redboot_ROM.bin RedBoot> fi write -f 0x80000000 -b %{FREEMEMLO} -l 0x00020000 See for details on configuring the RedBoot in general, and also for more details on programming the system flash. The exec command which allows the loading and execution of Linux kernels, is supported for this architecture (see ). The exec parameters used for ASB2305 board are: -w <time> Wait time in seconds before starting kernel -c "params" Parameters passed to kernel <addr> Kernel entry point, defaulting to the entry point of the last image loaded The parameter string is stored in the on-chip memory at location 0x8C001000, and is prefixed by “cmdline:” if it was supplied. RedBoot sets up the following memory map on the ASB2305 board. The regions mapped between 0x80000000-0x9FFFFFFF are cached by the CPU. However, all those regions can be accessed uncached by adding 0x20000000 to the address. Physical Address Range Description ----------------------- ----------- 0x80000000 - 0x9FFFFFFF Cached Region 0x80000000 - 0x81FFFFFF Boot PROM 0x84000000 - 0x85FFFFFF System Flash 0x86000000 - 0x86007FFF 64Kbit Sys Config EEPROM 0x86F90000 - 0x86F90003 4x 7-segment LEDs 0x86FA0000 - 0x86FA0003 Software DIP Switches 0x86FB0000 - 0x86FB001F PC16550 Debug Serial Port 0x8C000000 - 0x8FFFFFFF On-Chip Memory (repeated 16Kb SRAM) 0x90000000 - 0x93FFFFFF SDRAM 0x98000000 - 0x9BFFFFFF Paged PCI Memory Space (64Mb) 0x9C000000 - 0x9DFFFFFF PCI Local SRAM (32Mb) 0x9E000000 - 0x9E03FFFF PCI I/O Space 0x9E040000 - 0x9E0400FF AM33-PCI Bridge Registers 0x9FFFFFF4 - 0x9FFFFFF7 PCI Memory Page Register 0x9FFFFFF8 - 0x9FFFFFFF PCI Config Registers 0xA0000000 - 0xBFFFFFFF Uncached Mirror Region 0xC0000000 - 0xDFFFFFFF CPU Control Registers The ASB2305 HAL makes use of the on-chip memory in the following way: 0x8C000000 - 0x8C0000FF hal_vsr_table 0x8C000100 - 0x8C0001FF hal_virtual_vector_table 0x8C001000 - Linux command line (RedBoot exec command) - 0x8C003FFF Emergency DoubleFault Exception Stack Currently the CPU's interrupt table lies at the beginning of the RedBoot image, which must therefore be aligned to a 0xFF000000 mask. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=asb2305 export ARCH_DIR=mn10300 export PLATFORM_DIR=asb2305 The names of configuration files are listed above with the description of the associated modes. ARM Evaluator7Tinstalling and testinginstalling and testing ARM Evaluator7TRedBoot supports both serial ports for communication and downloads. The default serial port settings are 38400,8,N,1. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from flash address 0x20000, with ARM Boot Monitor in flash boot sector. redboot_ROMA.ecm RedBoot is installed using the on-board boot environment. See the user manual for full details. Here are quick start instructions for downloading the prebuilt Redboot image: Boot the board and press ENTER: ARM Evaluator7T Boot Monitor PreRelease 1.00 Press ENTER within 2 seconds to stop autoboot Boot: Erase the part of the flash where RedBoot will get programmed: Boot: flasherase 01820000 10000 Prepare to download the UU-encoded version of the RedBoot image: Boot: download 10000 Ready to download. Use 'transmit' option on terminal emulator to download file. Either use ASCII transmit option in the terminal emulator, or on Linux, simply cat the file to the serial port: $ cat redboot.UU > /dev/ttyS0When complete, you should see: Loaded file redboot.bin at address 000100000, size = 41960 Boot: Program the flash: Boot: flashwrite 01820000 10000 10000 And verify that the module is available: Boot: rommodules Header Base Limit 018057c8 01800000 018059e7 BootStrapLoader v1.0 Apr 27 2000 10:33:58 01828f24 01820000 0182a3e8 RedBoot Apr 5 2001 Reboot the board and you should see the RedBoot banner. None. RedBoot sets up the following memory map on the E7T board. The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B). Physical Address Range C B Description ----------------------- - - ----------- 0x00000000 - 0x0007ffff Y N SDRAM 0x03ff0000 - 0x03ffffff N N Microcontroller registers 0x01820000 - 0x0187ffff N N System flash (mirrored) These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=e7t export ARCH_DIR=arm export PLATFORM_DIR=e7t The names of configuration files are listed above with the description of the associated modes. ARM Integratorinstalling and testinginstalling and testing ARM IntegratorRedBoot supports both serial ports for communication and downloads. The default serial port settings are 38400,8,N,1. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm ROMRAM [ROMRAM] RedBoot running from RAM, but contained in the board's flash boot sector. redboot_ROMRAM.ecm RedBoot is installed using the on-board bootPROM environment. See the user manual for full details. Here are quick start instructions for downloading the prebuilt Redboot image: Set DIP switch S1[1] to the ON position and reset or power the board up. You will see the bootPROM startup message on serial port A (J14): Initialising... ARM bootPROM [Version 1.3] Rebuilt on Jun 26 2001 at 22:04:10 Running on a Integrator Evaluation Board Board Revision V1.0, ARM966E-S Processor Memory Size is 16MBytes, Flash Size is 32MBytes Copyright (c) ARM Limited 1999 - 2001. All rights reserved. Board designed by ARM Limited Hardware support provided at http://www.arm.com/ For help on the available commands type ? or h boot Monitor > Issue the FLASH ROM load command: boot Monitor > L Load Motorola S-Records into flash Deleting Image 0 The S-Record loader only accepts input on the serial port. Type Ctrl/C to exit loader. Either use the ASCII transmit option in the terminal emulator, or on Linux, simply cat the file to the serial port: $ cat redboot.srec > /dev/ttyS0 When complete, type Ctrl-C and you should see something similar to: ................................ ................................ .................... Downloaded 5,394 records in 81 seconds. Overwritten block/s 0 boot Monitor > Set DIP switch S1[1] to the OFF position and reboot the board and you should see the RedBoot banner. None. RedBoot sets up the following memory map on the Integrator board. The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B). ARM7TDMI -------- Physical Address Range C B Description ----------------------- - - ----------- 0x00000000 - 0x0007ffff N N SSRAM 0x00080000 - 0x0fffffff N N SDRAM (depends on part fitted) 0x10000000 - 0x1fffffff N N System control and peripheral registers 0x20000000 - 0x23ffffff N N Boot ROM (contains boot Monitor) 0x24000000 - 0x27ffffff N N FLASH ROM (contains RedBoot) 0x28000000 - 0x2bffffff N N SSRAM echo area 0x40000000 - 0x5fffffff N N PCI Memory access windows 0x60000000 - 0x60ffffff N N PCI IO access window 0x61000000 - 0x61ffffff N N PCI config space window 0x62000000 - 0x6200ffff N N PCI bridge register window 0x80000000 - 0x8fffffff N N SDRAM echo area (used for PCI accesses) ARM966E ------- Physical Address Range C B Description ----------------------- - - ----------- 0x00000000 - 0x000fffff N N SSRAM 0x00100000 - 0x0fffffff N N SDRAM (depends on part fitted) 0x10000000 - 0x1fffffff N N System control and peripheral registers 0x20000000 - 0x23ffffff N N Boot ROM (contains boot Monitor) 0x24000000 - 0x27ffffff N N FLASH ROM (contains RedBoot) 0x28000000 - 0x2bffffff N N SSRAM echo area 0x40000000 - 0x5fffffff N N PCI Memory access windows 0x60000000 - 0x60ffffff N N PCI IO access window 0x61000000 - 0x61ffffff N N PCI config space window 0x62000000 - 0x6200ffff N N PCI bridge register window 0x80000000 - 0x8fffffff N N SDRAM echo area (used for PCI accesses) These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=integrator export ARCH_DIR=arm export PLATFORM_DIR=integrator The names of configuration files are listed above with the description of the associated modes. ARM ARM7 PID, Dev7 and Dev9 installing and testinginstalling and testingARM ARM7 PID, Dev7 and Dev9RedBoot uses either of the serial ports. The default serial port settings are 38400,8,N,1. Management of onboard flash is also supported. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm Device programmer is used to program socketed flash parts with ROM version of RedBoot. Alternatively, to install RedBoot on a target that already has eCos GDB stubs, download the RAM mode image of RedBoot and run it. Initialize the flash image directory: fis init Then download the ROM version of RedBoot and program it into flash: RedBoot> load -b %{FREEMEMLO} -m ymodem RedBoot> fi cr RedBoot None. RedBoot sets up the following memory map on the PID board. Physical Address Range Description ----------------------- ----------- 0x00000000 - 0x0007ffff DRAM 0x04000000 - 0x04080000 flash 0x08000000 - 0x09ffffff ASB Expansion 0x0a000000 - 0x0bffffff APB Reference Peripheral 0x0c000000 - 0x0fffffff NISA Serial, Parallel and PC Card ports These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=pid export ARCH_DIR=arm export PLATFORM_DIR=pid The names of configuration files are listed above with the description of the associated modes. Atmel AT91/EBXX installing and testing installing and testingAtmel AT91/EBXX RedBoot support is available for the EB40, EB40A, EB42 and EB55 boards. By default all these boards are shipped with only 256Kbytes of RAM. To minimize the amount of RAM used by RedBoot, only very basic flash management is provided, comprising of just the fis erase and fis write commands. RedBoot supports both serial ports. On all AT91 evaluation boards, serial port A requires a straight through cable to connect with a PC, whereas serial port B requires a null modem cable. If you fail to be able to connect to Angel in the instructions below when installing RedBoot, be sure to verify you are using the appropriate cable for the serial port. The default serial port settings for RedBoot are 38400,8,N,1. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm ROMRAM [ROMRAM] RedBoot running from RAM, but contained in the board's flash boot sector. redboot_ROMRAM.ecm RedBoot installation is essentially the same for all boards, however the details differ slightly. Please make sure you follow the directions from the correct section below. Any errors could result in an unusable board. This development board comes with ARM's debug tool, Angel, installed in flash. At this time, Angel will not be replaced. Rather, RedBoot will be placed in the alternate half of flash. Switch SW1 is used to select which monitor to boot. Once RedBoot is installed, selecting SW1 to lower mem will choose Angel, whereas selecting SW1 to upper mem will choose RedBoot. Set SW1 to lower mem and connect serial port A to a host computer. Using GDB from the host and Angel on the board, download and run the RAM mode image of RedBoot to the board. arm-elf-gdb redboot_RAM.elf (gdb) tar rdi s=/dev/ttyS0 Angel Debug Monitor (serial) 1.04 (Advanced RISC Machines SDT 2.5) for AT91EB40 (2.00) Angel Debug Monitor rebuilt on Apr 07 2000 at 12:40:31 Serial Rate: 9600 Connected to ARM RDI target. (gdb) set $cpsr=0xd3 (gdb) load Loading section .rom_vectors, size 0x40 lma 0x2020000 Loading section .text, size 0x7fd8 lma 0x2020040 Loading section .rodata, size 0x15a0 lma 0x2028018 Loading section .data, size 0x2e4 lma 0x20295b8 Start address 0x2020040 , load size 39068 Transfer rate: 6250 bits/sec, 500 bytes/write. (gdb) cont Continuing. Once RedBoot is started, the GDB session connected with Angel must be suspended (this can be done using Ctrl-Z) or terminated (with Ctrl-C or the Windows task manager). Follow this by connecting to the board using a terminal emulator such as hyperterminal or minicom at 38400-8N1. At this point, RedBoot will be running on the board in RAM. RedBoot> version RedBoot(tm) bootstrap and debug environment [RAM] Non-certified release, version UNKNOWN - built 14:09:27, Jul 20 2001 Platform: Atmel AT91/EB40 (ARM7TDMI) Copyright (C) 2000, 2001, Free Software Foundation, Inc. RAM: 0x02000000-0x02080000, 0x020116d8-0x0207fd00 available FLASH: 0x01010000 - 0x01020000, 256 blocks of 0x00000100 bytes each. RedBoot> Now, download the ROM mode image. RedBoot> load -m ymodem -b %{FREEMEMLO} Use your terminal emulator to send the file redboot_ROM.srec via YModem. e.g. Transfer->Send File in Hyperterminal, or Ctrl-A S in minicom. Finally, program it to flash. RedBoot> fi wr -f 0x01010000 -b %{FREEMEMLO} -l 0xe100 SW1 should now be set to upper mem to select booting with RedBoot rather than Angel. Finally, press the "reset" pushbutton and RedBoot should come up on the board. These development boards come with ARM's debug tool, Angel, installed in flash. At this time, Angel will not be replaced. Rather, RedBoot will be placed in the alternate half of flash. Jumper JP1 is used to select which monitor to boot. Once RedBoot is installed, setting JP1 to STD will choose Angel, whereas setting JP1 to USER will choose RedBoot. Set JP1 to STD and connect serial port A to a host computer. Using GDB from the host and Angel on the board, download the RAM mode image of RedBoot to the board, and start it using the 'cont' command. arm-elf-gdb redboot_RAM.elf (gdb) tar rdi s=/dev/ttyS0 Angel Debug Monitor (serial) 1.04 (Advanced RISC Machines SDT 2.5) for AT91EB55 (2.20) Angel Debug Monitor rebuilt on Feb 03 2002 at 16:10:20 Serial Rate: 9600 Connected to ARM RDI target. (gdb) set $cpsr=0xd3 (gdb) load Loading section .rom_vectors, size 0x40 lma 0x2008000 Loading section .text, size 0xb0b8 lma 0x2008040 Loading section .rodata, size 0x1c27 lma 0x20130f8 Loading section .data, size 0x5f0 lma 0x2014d20 Start address 0x2008040, load size 54031 Transfer rate: 6264 bits/sec, 500 bytes/write. (gdb) cont Continuing. Once RedBoot is started, the GDB session connected with Angel must be suspended (this can be done using Ctrl-Z) or terminated (with Ctrl-C or the Windows task manager). Follow this by connecting to the board using a terminal emulator such as hyperterminal or minicom at 38400-8N1. At this point, RedBoot will be running on the board in RAM. RedBoot> version RedBoot(tm) bootstrap and debug environment [RAM] Non-certified release, version UNKNOWN - built 16:58:52, May 7 2003 Platform: Atmel AT91/EB55 (ARM7TDMI) Copyright (C) 2000, 2001, 2002, Free Software Foundation, Inc. RAM: 0x02000000-0x02040000, 0x020068a8-0x0203f000 available FLASH: 0x01010000 - 0x01200000, 31 blocks of 0x00010000 bytes each. RedBoot> Now, download the ROM mode image. RedBoot> load -m ymodem -b %{FREEMEMLO} Use your terminal emulator to send the file redboot_ROM.srec via YModem. e.g. Transfer->Send File in Hyperterminal, or Ctrl-A S in minicom. Finally, program it to flash. RedBoot> fi wr -f 0x01100000 -b %{FREEMEMLO} -l 0x10000 Set JP1 to the USER setting, press the "reset" pushbutton and RedBoot should come up on the board. None. This processor has no MMU, so the only memory map is for physical addresses. The memory layout of the EB40 is as follows: Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x00000fff On-chip SRAM 0x01000000 - 0x0101ffff Flash 0x02000000 - 0x0207ffff RAM 0xffe00000 - 0xffffffff I/O registers The flash based RedBoot image occupies virtual addresses 0x01010000 - 0x0101dfff. The memory layout of the EB40A is as follows: Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x0003ffff On-chip SRAM 0x01000000 - 0x011fffff Flash 0x02000000 - 0x02ffffff External SRAM (optional) 0xffe00000 - 0xffffffff I/O registers The flash based RedBoot image occupies virtual addresses 0x01100000 - 0x0110ffff. The memory layout of the EB42 and EB55 is as follows: Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x00001fff On-chip SRAM 0x01000000 - 0x011fffff Flash 0x02000000 - 0x0203ffff RAM 0xffe00000 - 0xffffffff I/O registers The flash based RedBoot image occupies virtual addresses 0x01100000 - 0x0110ffff. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export ARCH_DIR=arm export TARGET=eb40 export PLATFORM_DIR=at91/eb40 export TARGET=eb40a export PLATFORM_DIR=at91/eb40a export TARGET=eb42 export PLATFORM_DIR=at91/eb42 export TARGET=eb55 export PLATFORM_DIR=at91/eb55 Use just one of the TARGET and PLATFORM_DIR variable pairs only. The names of configuration files are listed above with the description of the associated modes. When reprogramming RedBoot using RedBoot itself, you should load a RedBoot RAM image as normal, and load the new ROM image into RAM. However before programming the new image into Flash you must switch SW1 to lower mem (EB40) or set JP1 to STD (EB40A, EB42, EB55) before writing to Flash. Failure to set SW1 to lower mem (EB40) or JP1 to STD (EB40A, EB42, EB55) will cause the installation of RedBoot to overwrite Angel, thus making the board unbootable. Only hardware JTAG can restore the board once in this state. Atmel AT91/JTST installing and testing installing and testingAtmel AT91/JTST RedBoot support is available for the JTST board. By default this board is shipped with 256Kbytes of external SRAM. To minimize the amount of RAM used by RedBoot, only very basic flash management is provided, comprising of just the fis erase and fis write commands. RedBoot supports two serial ports. The default serial port settings for RedBoot are 115200,8,N,1. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm This development board comes with RedBoot installed on flash. To install a new version of RedBoot or another binary image in flash you must start a GDB session setting a remote target and load and run the jtstflashd.elf diopsis application. This is a daemon that listens on JTST serial port 1. On the PC side you must use the jtstflash.exe (both linux and windows PC are supported) to flash the image on JTST. The sources for win32 and linux/cygwin versions of this host tool can be found in the support directory of the jtst hal. The binaries can be found along with the binaries for redboot on the eCos website at http://ecos.sourceware.org/ecos/boards/redbootbins/at91jtst/ When the jtstflashd.elf is started, the user should open the jumper JP5 to write in the second half (512Kbytes) of the flash, in this way the original RedBoot image is preserved. arm-elf-gdb jtstflash.elf (gdb) set remotebaud 115200 (gdb) target remote /dev/ttyS0 Remote debugging using /dev/ttyS0 0x00502a44 in ?? () (gdb) load Loading section .internal_vectors, size 0x1c4 lma 0x160 Loading section .rom_vectors, size 0x40 lma 0x606000 Loading section .text, size 0x14198 lma 0x606040 Loading section .rodata, size 0xb6c lma 0x61a1d8 Loading section .data, size 0x498 lma 0x61ad44 Start address 0x606040, load size 86944 Transfer rate: 77283 bits/sec, 301 bytes/write. (gdb) c Continuing. * JTST FLASH PROGRAMMER * opening usart port 1 ... jtstflash mybinaryimage.bin * binary len 79536 bytes flash add 0x500000.. * flash id check ok * erasing space address 0x500000... please wait * flash erase check ok * start programming 79536 bytes. None. This processor has no MMU, so the only memory map is for physical addresses. The memory layout of the JTST after bootstrap is as follows: Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x00007fff On-chip SRAM 0x00500000 - 0x0057ffff Flash 0x00600000 - 0x0063ffff External SRAM 0x00410000 - 0x0042fffc On-chip Magic Data Memory Left 0x00430000 - 0x0043fffc On-chip Magic Data Memory Right 0x00430000 - 0x0044fffc On-chip Magic Program Memory 0x00490000 - 0x00490ffc On-chip Arm/Magic Data Exchange Left 0x004A0000 - 0x004A0ffc On-chip Arm/Magic Data Exchange Right 0x00450000 - 0x0045003c Magic I/O registers 0x00460000 - 0x0046000c Magic Control registers 0xffe00000 - 0xffffffff I/O registers Cirrus Logic EP7xxx (EDB7211, EDB7212, EDB7312) installing and testing installing and testingCirrus Logic EP7xxx (EDB7211, EDB7212, EDB7312) RedBoot supports both serial ports on the board and the ethernet port. The default serial port settings are 38400,8,N,1. RedBoot also supports flash management on the EDB7xxx for the NOR flash only. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm ROMRAM [ROMRAM] RedBoot running from RAM, but contained in the board's flash boot sector (EDB7312 only). redboot_ROMRAM.ecm A Windows or Linux utility is used to program flash using serial port #1 via on-chip programming firmware. See board documentation for details on in situ flash programming. None. The MMU page tables and LCD display buffer, if enabled, are located at the end of DRAM. The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B). Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x01ffffff NOR Flash (EDB7211, EDB7212) 0x00000000 - 0x00ffffff NOR Flash (EDB7312) 0x10000000 - 0x11ffffff NAND Flash 0x20000000 - 0x2fffffff Expansion 2 0x30000000 - 0x3fffffff Expansion 3 0x40000000 - 0x4fffffff PCMCIA 0 0x50000000 - 0x5fffffff PCMCIA 1 0x60000000 - 0x600007ff On-chip SRAM 0x80000000 - 0x8fffffff I/O registers 0xc0000000 - 0xc1ffffff DRAM (EDB7211, EDB7212) 0xc0000000 - 0xc0ffffff DRAM (EDB7312) Virtual Address Range C B Description ----------------------- - - ---------------------------------- 0x00000000 - 0x01ffffff Y Y DRAM 0x00000000 - 0x00fcffff Y Y DRAM (EDB7312) 0x20000000 - 0x2fffffff N N Expansion 2 0x30000000 - 0x3fffffff N N Expansion 3 0x40000000 - 0x4fffffff N N PCMCIA 0 0x50000000 - 0x5fffffff N N PCMCIA 1 0x60000000 - 0x600007ff Y Y On-chip SRAM 0x80000000 - 0x8fffffff N N I/O registers 0xc0000000 - 0xc001ffff N Y LCD buffer (if configured) 0xe0000000 - 0xe1ffffff Y Y NOR Flash (EDB7211, EDB7212) 0xe0000000 - 0xe0ffffff Y Y NOR Flash (EDB7312) 0xf0000000 - 0xf1ffffff Y Y NAND Flash The flash based RedBoot image occupies virtual addresses 0xe0000000 - 0xe003ffff. The EP7xxx timer #2 is used as a polled timer to provide timeout support for network and XModem file transfers. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=edb7211 export TARGET=edb7212 export TARGET=edb7312 export ARCH_DIR=arm export PLATFORM_DIR=edb7xxx Use one of the TARGET settings only. The names of configuration files are listed above with the description of the associated modes. Agilent AAED2000 ARM9 (aaed) installing and testing installing and testingAgilent AAED2000 ARM9 (aaed) RedBoot supports the serial and ethernet ports on the board. The default serial port settings are 38400,8,N,1. RedBoot also supports flash management on the AAED2000. The following RedBoot configurations are supported: Configuration Mode Description File ROMRAM [ROMRAM] RedBoot running from RAM, but contained in the board's flash boot sector. redboot_primary_ROMRAM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_primary_RAM.ecm It is possible to install RedBoot in one of two ways. Either as the primary bootmonitor on the board (installed to blocks 0-1 of the flash) or as the secondary bootmonitor on the board (installed to blocks 1-2 of the flash). Presently, only the former method is supported. RedBoot is installed in flash using the on-board ARM Boot Monitor. Boot the board while pressing SPACE. This should bring up the Boot Monitor: ARM bootPROM [Version 1.3] Rebuilt on Jul 16 2001 at 16:21:36 Running on a P920 board Evaluation Board Board Revision V1.0, ARM920T processor Processor Memory Size is 32MBytes, Flash Size is 32MBytes Copyright (c) ARM Limited 1999 - 2001. All rights reserved. Board designed by ARM Limited Hardware support provided at http://www.arm.com/ For help on the available commands type ? or h boot Monitor > Download the RAM mode image of RedBoot configured as a primary bootmonitor using the ARM bootmonitor's SREC-download command: boot Monitor > m Load Motorola S-Record image into memory and execute it The S-Record loader only accepts input on the serial port. Record addresses must be between 0x00008000 and 0x01E0F510. Type Ctrl/C to exit loader. Use the terminal emulator's ASCII upload command, or (on Linux) simply cat the file to the serial port: $ cat redboot_primary_RAM/redboot.srec >/dev/ttyS1 You should see RedBoot start up: FLASH configuration checksum error or invalid key Ethernet eth0: MAC address 00:30:d3:03:04:99 IP: 192.168.42.111, Default server: 192.168.42.3 RedBoot(tm) bootstrap and debug environment [RAM] Non-certified release, version UNKNOWN - built 13:15:40, Nov 9 2001 Platform: AAED2000 system (ARM9) [Primary] Copyright (C) 2000, 2001, Free Software Foundation, Inc. RAM: 0x00000000-0x01f80000, 0x0006f208-0x01f51000 available FLASH: 0x60000000 - 0x62000000, 256 blocks of 0x00020000 bytes each. RedBoot> As can be seen from the output above, the network has been configured to give the board an IP address and information about the default server. If things are not set up on your network, you can still continue, but use the Y-modem download method when loading the RedBoot ROMRAM mode image. Now initialize RedBoot's FIS: RedBoot> fis init About to initialize [format] FLASH image system - continue (y/n)? y *** Initialize FLASH Image System Warning: device contents not erased, some blocks may not be usable ... Erase from 0x61fe0000-0x62000000: . ... Program from 0x01f5f000-0x01f5f300 at 0x61fe0000: . Download the ROMRAM mode image of RedBoot via ethernet: RedBoot> load -b %{FREEMEMLO} redboot_primary_ROMRAM/redboot.srec or using serial Y-modem protocol: RedBoot> load -mode ymodem -b %{FREEMEMLO} (Use the terminal emulator's Y-modem upload command to send the file redboot_primary_ROMRAM/redboot.srec.) When the image has been downloaded, program it into flash: Address offset = 0x00ff8000 Entry point: 0x00008040, address range: 0x00008000-0x0002da80 RedBoot> fi cr RedBoot An image named 'RedBoot' exists - continue (y/n)? y * CAUTION * about to program 'RedBoot' at 0x60000000..0x6003ffff from 0x00100000 - continue (y/n)? y ... Erase from 0x60000000-0x60040000: .. ... Program from 0x00100000-0x00140000 at 0x60000000: .. ... Erase from 0x61fe0000-0x62000000: . ... Program from 0x01f5f000-0x01f7f000 at 0x61fe0000: . Now reset the board. You should see the RedBoot banner. The exec command which allows the loading and execution of Linux kernels, is supported for this board (see ). The exec parameters used for the AAED2000 are: -b <addr> Location Linux kernel was loaded to -l <len> Length of kernel -c "params" Parameters passed to kernel -r <addr> 'initrd' ramdisk location -s <len> Length of initrd ramdisk The parameters for kernel image base and size are automatically set after a load operation. So one way of starting the kernel would be: RedBoot> load -r -b 0x100000 zImage Raw file loaded 0x00100000-0x001a3d6c RedBoot> exec -c "console=ttyAC0,38400" Using base address 0x00100000 and length 0x000a3d6c Uncompressing Linux..... An image could also be put in flash and started directly: RedBoot> exec -b 0x60040000 -l 0xc0000 -c "console=ttyAC0,38400" Uncompressing Linux..... The MMU page tables are located at 0x4000. The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B). Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x01ffffff Flash 0x10000000 - 0x100fffff Ethernet 0x30000000 - 0x300fffff Board registers 0x40000000 - 0x4fffffff PCMCIA Slot (0) 0x50000000 - 0x5fffffff Compact Flash Slot (1) 0x80000000 - 0x800037ff I/O registers 0xb0060000 - 0xb00fffff On-chip SRAM 0xf0000000 - 0xfd3fffff SDRAM Virtual Address Range C B Description ----------------------- - - ---------------------------------- 0x00000000 - 0x01f7ffff Y Y SDRAM 0x01f80000 - 0x01ffffff Y Y SDRAM (used for LCD frame buffer) 0x10000000 - 0x100fffff N N Ethernet 0x30000000 - 0x300fffff N N Board registers 0x40000000 - 0x4fffffff N N PCMCIA Slot (0) 0x50000000 - 0x5fffffff N N Compact Flash Slot (1) 0x60000000 - 0x61ffffff N N Flash 0x80000000 - 0x800037ff N N I/O registers 0xf0000000 - 0xffffffff N N SDRAM (uncached) These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=aaed export ARCH_DIR=arm export PLATFORM_DIR=arm9/aaed2000 The names of configuration files are listed above with the description of the associated modes. Altera Excalibur ARM9 (excalibur_arm9) installing and testing installing and testingAltera Excalibur ARM9 (excalibur_arm9) RedBoot supports the serial port labelled P2 on the board. The default serial port settings are 57600,8,N,1. RedBoot also supports flash management on the Excalibur. The following RedBoot configurations are supported: Configuration Mode Description File ROMRAM [ROMRAM] RedBoot running from RAM, but contained in the board's flash boot sector. redboot_ROMRAM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm REDBOOT [ROMRAM] RedBoot running from top of RAM, but contained in the board's flash boot sector. redboot_REDBOOT.ecm RedBoot is currently hardwired to use a 128MB SDRAM SIMM module. A Windows utility (exc_flash_programmer.exe) is used to program flash using the ByteBlasterMV JTAG unit. See board documentation for details on in situ flash programming. For ethernet to work (under Linux) the following jumper settings should be used on a REV 2 board: SW2-9 : OFF U179 : 2-3 JP14-18 : OPEN JP40-41 : 2-3 JP51-55 : 2-3 The ROMRAM and REDBOOT configurations supported on this platform differ only in the memory layout (ROMRAM configuration runs RedBoot from 0x00008000 while REDBOOT configuration runs RedBoot from 0x07f80000). The REDBOOT configuration allows applications to be loaded and run from address 0x00008000. The exec command which allows the loading and execution of Linux kernels, is supported for this board (see ). The exec parameters used for the Excalibur are: -b <addr> Location Linux kernel was loaded to -l <len> Length of kernel -c "params" Parameters passed to kernel -r <addr> 'initrd' ramdisk location -s <len> Length of initrd ramdisk The parameters for kernel image base and size are automatically set after a load operation. So one way of starting the kernel would be: RedBoot> load -r -b 0x100000 zImage Raw file loaded 0x00100000-0x001a3d6c RedBoot> exec -c "console=ttyUA0,57600" Using base address 0x00100000 and length 0x000a3d6c Uncompressing Linux..... An image could also be put in flash and started directly: RedBoot> exec -b 0x40400000 -l 0xc0000 -c "console=ttyUA0,57600" Uncompressing Linux..... The MMU page tables are located at 0x4000. The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B). Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x07ffffff SDRAM 0x08000000 - 0x0805ffff On-chip SRAM 0x40000000 - 0x40ffffff Flash 0x7fffc000 - 0x7fffffff I/O registers 0x80000000 - 0x8001ffff PLD Virtual Address Range C B Description ----------------------- - - ---------------------------------- 0x00000000 - 0x07ffffff Y Y SDRAM 0x08000000 - 0x0805ffff Y Y On-chip SRAM 0x40000000 - 0x403fffff N Y Flash 0x7fffc000 - 0x7fffffff N N I/O registers 0x80000000 - 0x8001ffff N N PLD These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=excalibur_arm9 export ARCH_DIR=arm export PLATFORM_DIR=arm9/excalibur The names of configuration files are listed above with the description of the associated modes. Intel StrongArm EBSA 285installing and testinginstalling and testing Intel StrongArm EBSA 285RedBoot uses the single EBSA-285 serial port. The default serial port settings are 38400,8,N,1. If the EBSA-285 is used as a host on a PCI backplane, ethernet is supported using an Intel PRO/100+ ethernet adapter. Management of onboard flash is also supported. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm A linux application is used to program the flash over the PCI bus. Sources and build instructions for this utility are located in the RedBoot sources in: packages/hal/arm/ebsa285/current/support/linux/safl_util Serial, Intel PRO 10/100+ 82559 PCI ethernet card. None. Physical and virtual mapping are mapped one to one on the EBSA-285 using a first level page table located at address 0x4000. No second level tables are used. The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B). Address Range C B Description ----------------------- - - ---------------------------------- 0x00000000 - 0x01ffffff Y Y SDRAM 0x40000000 - 0x400fffff N N 21285 Registers 0x41000000 - 0x413fffff Y N flash 0x42000000 - 0x420fffff N N 21285 CSR Space 0x50000000 - 0x50ffffff Y Y Cache Clean 0x78000000 - 0x78ffffff N N Outbound Write Flush 0x79000000 - 0x7c0fffff N N PCI IACK/Config/IO 0x80000000 - 0xffffffff N Y PCI Memory Timer3 is used as a polled timer to provide timeout support for networking and XModem file transfers. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=ebsa285 export ARCH_DIR=arm export PLATFORM_DIR=ebsa285 The names of configuration files are listed above with the description of the associated modes. Intel-SA1100 (Brutus)installing and testinginstalling and testing Intel SA1100 (Brutus)RedBoot supports both board serial ports on the Brutus board. The default serial port settings are 38400,8,N,1. flash management is not currently supported. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm Device programmer is used to program socketed flash parts. None. The first level page table is located at physical address 0xc0004000. No second level tables are used. The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B). Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x000fffff Boot ROM 0x08000000 - 0x083fffff Application flash 0x10000000 - 0x100fffff SRAM 0x18000000 - 0x180fffff Chip Select 3 0x20000000 - 0x3fffffff PCMCIA 0x80000000 - 0xbfffffff SA-1100 Internal Registers 0xc0000000 - 0xc7ffffff DRAM Bank 0 0xc8000000 - 0xcfffffff DRAM Bank 1 0xd0000000 - 0xd7ffffff DRAM Bank 2 0xd8000000 - 0xdfffffff DRAM Bank 3 0xe0000000 - 0xe7ffffff Cache Clean Virtual Address Range C B Description ----------------------- - - ---------------------------------- 0x00000000 - 0x003fffff Y Y DRAM Bank 0 0x00400000 - 0x007fffff Y Y DRAM Bank 1 0x00800000 - 0x00bfffff Y Y DRAM Bank 2 0x00c00000 - 0x00ffffff Y Y DRAM Bank 3 0x08000000 - 0x083fffff Y Y Application flash 0x10000000 - 0x100fffff Y N SRAM 0x20000000 - 0x3fffffff N N PCMCIA 0x40000000 - 0x400fffff Y Y Boot ROM 0x80000000 - 0xbfffffff N N SA-1100 Internal Registers 0xe0000000 - 0xe7ffffff Y Y Cache Clean The SA11x0 OS timer is used as a polled timer to provide timeout support for XModem file transfers. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=brutus export ARCH_DIR=arm export PLATFORM_DIR=sa11x0/brutus The names of configuration files are listed above with the description of the associated modes. Intel SA1100 Multimedia Board installing and testinginstalling and testingIntel SA1100 Multimedia Board RedBoot supports both board serial ports. The default serial port settings are 38400,8,N,1. flash management is also supported. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm A device programmer is used to program socketed flash parts. None. The first level page table is located at physical address 0xc0004000. No second level tables are used. The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B). Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x000fffff Boot flash 0x08000000 - 0x083fffff Application flash 0x10000000 - 0x107fffff SA-1101 Board Registers 0x18000000 - 0x180fffff Ct8020 DSP 0x18400000 - 0x184fffff XBusReg 0x18800000 - 0x188fffff SysRegA 0x18c00000 - 0x18cfffff SysRegB 0x19000000 - 0x193fffff Spare CPLD A 0x19400000 - 0x197fffff Spare CPLD B 0x20000000 - 0x3fffffff PCMCIA 0x80000000 - 0xbfffffff SA1100 Internal Registers 0xc0000000 - 0xc07fffff DRAM Bank 0 0xe0000000 - 0xe7ffffff Cache Clean Virtual Address Range C B Description ----------------------- - - ---------------------------------- 0x00000000 - 0x007fffff Y Y DRAM Bank 0 0x08000000 - 0x083fffff Y Y Application flash 0x10000000 - 0x100fffff N N SA-1101 Registers 0x18000000 - 0x180fffff N N Ct8020 DSP 0x18400000 - 0x184fffff N N XBusReg 0x18800000 - 0x188fffff N N SysRegA 0x18c00000 - 0x18cfffff N N SysRegB 0x19000000 - 0x193fffff N N Spare CPLD A 0x19400000 - 0x197fffff N N Spare CPLD B 0x20000000 - 0x3fffffff N N PCMCIA 0x50000000 - 0x500fffff Y Y Boot flash 0x80000000 - 0xbfffffff N N SA1100 Internal Registers 0xc0000000 - 0xc07fffff N Y DRAM Bank 0 0xe0000000 - 0xe7ffffff Y Y Cache Clean The SA11x0 OS timer is used as a polled timer to provide timeout support for XModem file transfers. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=sa1100mm export ARCH_DIR=arm export PLATFORM_DIR=sa11x0/sa1100mm The names of configuration files are listed above with the description of the associated modes. Intel SA1110 (Assabet)installing and testinginstalling and testing Intel SA1110 (Assabet)RedBoot supports the board serial port and the compact flash ethernet port. The default serial port settings are 38400,8,N,1. RedBoot also supports flash management on the Assabet. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm A Windows or Linux utility is used to program flash over parallel port driven JTAG interface. See board documentation for details on in situ flash programming. The flash parts are also socketed and may be programmed in a suitable device programmer. None. The first level page table is located at physical address 0xc0004000. No second level tables are used. The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B). Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x07ffffff flash 0x08000000 - 0x0fffffff SA-1111 Board flash 0x10000000 - 0x17ffffff Board Registers 0x18000000 - 0x1fffffff Ethernet 0x20000000 - 0x2fffffff SA-1111 Board PCMCIA 0x30000000 - 0x3fffffff Compact Flash 0x40000000 - 0x47ffffff SA-1111 Board 0x48000000 - 0x4bffffff GFX 0x80000000 - 0xbfffffff SA-1110 Internal Registers 0xc0000000 - 0xc7ffffff DRAM Bank 0 0xc8000000 - 0xcfffffff DRAM Bank 1 0xd0000000 - 0xd7ffffff DRAM Bank 2 0xd8000000 - 0xdfffffff DRAM Bank 3 0xe0000000 - 0xe7ffffff Cache Clean Virtual Address Range C B Description ----------------------- - - ---------------------------------- 0x00000000 - 0x01ffffff Y Y DRAM Bank 0 0x08000000 - 0x0fffffff Y Y SA-1111 Board flash 0x10000000 - 0x17ffffff N N Board Registers 0x18000000 - 0x1fffffff N N Ethernet 0x20000000 - 0x2fffffff N N SA-1111 Board PCMCIA 0x30000000 - 0x3fffffff N N Compact Flash 0x40000000 - 0x47ffffff N N SA-1111 Board 0x48000000 - 0x4bffffff N N GFX 0x50000000 - 0x57ffffff Y Y flash 0x80000000 - 0xbfffffff N N SA-1110 Internal Registers 0xc0000000 - 0xc1ffffff N Y DRAM Bank 0 0xe0000000 - 0xe7ffffff Y Y Cache Clean The SA11x0 OS timer is used as a polled timer to provide timeout support for network and XModem file transfers. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=assabet export ARCH_DIR=arm export PLATFORM_DIR=sa11x0/assabet The names of configuration files are listed above with the description of the associated modes. commEngineinstalling and testing nanoEngine installing and testinginstalling and testingcommEngine installing and testingnanoEngine RedBoot supports a serial port and the built in ethernet port for communication and downloads. The default serial port settings are 38400,8,N,1. RedBoot runs from and supports flash management for the system flash region. The following RedBoot configurations are supported: Configuration Mode Description File POST [ROM] RedBoot running from the first free flash block at 0x40000. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm Unlike other targets, the nanoEngine comes equipped with boot firmware which you cannot modify. See chapter 5, "nanoEngine Firmware" of the nanoEngine Hardware Reference Manual (we refer to "July 17, 2000 Rev 0.6") from Bright Star Engineering. Because of this, eCos, and therefore Redboot, only supports a special configuration of the ROM mode, starting at offset 0x40000 in the flash. Briefly, the POST-configuration RedBoot image lives in flash following the BSE firmware. The BSE firmware is configured, using its standard bootcmd command, to run RedBoot at startup. You can perform the initial load of the POST-configuration RedBoot image into flash using the BSE firmware's load command. This will load a binary file, using TFTP, and program it into flash in one operation. Because no memory management is used in the BSE firmware, flash is mapped from address zero upwards, so the address for the RedBoot POST image is 0x40000. You must use the binary version of RedBoot for this, redboot-post.bin. This assumes you have set up the other BSE firmware config parameters such that it can communicate over your network to your TFTP server. >load redboot-post.bin 40000 loading ... erasing blk at 00040000 erasing blk at 00050000 94168 bytes loaded cksum 00008579 done > > set bootcmd "go 40000" > get myip = 10.16.19.198 netmask = 255.255.255.0 eth = 0 gateway = 10.16.19.66 serverip = 10.16.19.66 bootcmd = go 40000 > the BSE firmware runs its serial IO at 9600 Baud; RedBoot runs instead at 38400 Baud. You must select the right baud rate in your terminal program to be able to set up the BSE firmware. After a reset, the BSE firmware will print Boot: BSE 2000 Sep 12 2000 14:00:30 autoboot: "go 40000" [hit ESC to abort] and then RedBoot starts, switching to 38400 Baud. Once you have installed a bootable RedBoot in the system in this manner, we advise re-installing using the generic method described in in order that the Flash Image System contains an appropriate description of the flash entries. The configuration file named redboot_POST.ecm configures RedBoot to build for execution at address 0x50040000 (or, during bootup, 0x00040000). This is to allow power-on self-test (POST) code or immutable firmware to live in the lower addresses of the flash and to run before RedBoot gets control. The assumption is that RedBoot will be entered at its base address in physical memory, that is 0x00040000. Alternatively, for testing, you can call it in an already running system by using go 0x50040040 at another RedBoot prompt, or a branch to that address. The address is where the reset vector points. It is reported by RedBoot's load command and listed by the fis list command, amongst other places. Using the POST configuration enables a normal config option which causes linking and initialization against memory layout files called "...post..." rather than "...rom..." or "...ram..." in the include/pkgconf directory. Specifically:include/pkgconf/mlt_arm_sa11x0_nano_post.h include/pkgconf/mlt_arm_sa11x0_nano_post.ldi include/pkgconf/mlt_arm_sa11x0_nano_post.mlt It is these you should edit if you wish to move the execution address from 0x50040000 in the POST configuration. Startup mode naturally remains ROM in this configuration. Because the nanoEngine contains immutable boot firmware at the start of flash, RedBoot for this target is configured to reserve that area in the Flash Image System, and to create by default an entry for the POST mode RedBoot. RedBoot> fis list Name FLASH addr Mem addr Length Entry point (reserved) 0x50000000 0x50000000 0x00040000 0x00000000 RedBoot[post] 0x50040000 0x00100000 0x00020000 0x50040040 RedBoot config 0x503E0000 0x503E0000 0x00010000 0x00000000 FIS directory 0x503F0000 0x503F0000 0x00010000 0x00000000 RedBoot> The entry "(reserved)" ensures that the FIS cannot attempt to overwrite the BSE firmware, thus ensuring that the board remains bootable and recoverable even after installing a broken RedBoot image. The nanoEngine/commEngine has one or two Intel i82559 Ethernet controllers installed, but these have no associated serial EEPROM in which to record their Ethernet Station Address (ESA, or MAC address). The BSE firmware records an ESA for the device it uses, but this information is not available to RedBoot; we cannot share it. To keep the ESAs for the two ethernet interfaces, two new items of RedBoot configuration data are introduced. You can list them with the RedBoot command fconfig -l thus: RedBoot> fconfig -l Run script at boot: false Use BOOTP for network configuration: false Local IP address: 10.16.19.91 Default server IP address: 10.16.19.66 Network hardware address [MAC] for eth0: 0x00:0xB5:0xE0:0xB5:0xE0:0x99 Network hardware address [MAC] for eth1: 0x00:0xB5:0xE0:0xB5:0xE0:0x9A GDB connection port: 9000 Network debug at boot time: false RedBoot> You should set them before running RedBoot or eCos applications with the board connected to a network. The fconfig command can be used as for any configuration data item; the entire ESA is entered in one line. The first level page table is located at physical address 0xc0004000. No second level tables are used. The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B). Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x003fffff 4Mb FLASH (nCS0) 0x18000000 - 0x18ffffff Internal PCI bus - 2 x i82559 ethernet 0x40000000 - 0x4fffffff External IO or PCI bus 0x80000000 - 0xbfffffff SA-1110 Internal Registers 0xc0000000 - 0xc7ffffff DRAM Bank 0 - 32Mb SDRAM 0xc8000000 - 0xcfffffff DRAM Bank 1 - empty 0xe0000000 - 0xe7ffffff Cache Clean Virtual Address Range C B Description ----------------------- - - ---------------------------------- 0x00000000 - 0x001fffff Y Y DRAM - 8Mb to 32Mb 0x18000000 - 0x180fffff N N Internal PCI bus - 2 x i82559 ethernet 0x40000000 - 0x4fffffff N N External IO or PCI bus 0x50000000 - 0x51ffffff Y Y Up to 32Mb FLASH (nCS0) 0x80000000 - 0xbfffffff N N SA-1110 Internal Registers 0xc0000000 - 0xc0ffffff N Y DRAM Bank 0: 8 or 16Mb 0xc8000000 - 0xc8ffffff N Y DRAM Bank 1: 8 or 16Mb or absent 0xe0000000 - 0xe7ffffff Y Y Cache Clean The ethernet devices use a "PCI window" to communicate with the CPU. This is 1Mb of SDRAM which is shared with the ethernet devices that are on the PCI bus. It is neither cached nor buffered, to ensure that CPU and PCI accesses see correct data in the correct order. By default it is configured to be megabyte number 30, at addresses 0x01e00000-0x01efffff. This can be modified, and indeed must be, if less than 32Mb of SDRAM is installed, via the memory layout tool, or by moving the section __pci_window referred to by symbols CYGMEM_SECTION_pci_window* in the linker script. Though the nanoEngine ships with 32Mb of SDRAM all attached to DRAM bank 0, the code can cope with any of these combinations also; "2 x " in this context means one device in each DRAM Bank. 1 x 8Mb = 8Mb 2 x 8Mb = 16Mb 1 x 16Mb = 16Mb 2 x 16Mb = 32MbAll are programmed the same in the memory controller. Startup code detects which is fitted and programs the memory map accordingly. If the device(s) is 8Mb, then there are gaps in the physical memory map, because a high order address bit is not connected. The gaps are the higher 2Mb out of every 4Mb. The SA11x0 OS timer is used as a polled timer to provide timeout support within RedBoot. The nano is in the set of SA11X0-based platforms. It uses the arm architectural HAL, the sa11x0 variant HAL, plus the nano platform hal. These are components CYGPKG_HAL_ARM hal/arm/arch/ CYGPKG_HAL_ARM_SA11X0 hal/arm/sa11x0/var CYGPKG_HAL_ARM_SA11X0_NANO hal/arm/sa11x0/nano respectively. The target name is "nano" which includes all these, plus the ethernet driver packages, flash driver, and so on. The ethernet driver is in two parts: A generic ether driver for Intel i8255x series devices, specifically the i82559, is devs/eth/intel/i82559. Its package name is CYGPKG_DEVS_ETH_INTEL_I82559. The platform-specific ether driver is devs/eth/arm/nano . Its package is CYGPKG_DEVS_ETH_ARM_NANO . This tells the generic driver the address in IO memory of the chip, for example, and other configuration details. This driver picks up the ESA from RedBoot's configuration data - unless configured to use a static ESA in the usual manner. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=nano export ARCH_DIR=arm export PLATFORM_DIR=sa11x0/nano The names of configuration files are listed above with the description of the associated modes. Compaq iPAQ PocketPCinstalling and testinginstalling and testing Compaq iPAQ PocketPC RedBoot supports the serial port via cradle or cable, and Compact Flash ethernet cards if fitted for communication and downloads. The LCD touchscreen may also be used for the console, although by default RedBoot will switch exclusively to one channel once input arrives. The default serial port settings are 38400,8,N,1. RedBoot runs from and supports flash management for the system flash region. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm WinCE [RAM] RedBoot running from RAM, started from OSloader. redboot_WinCE.ecm RedBoot ROM and WinCE mode images are needed by the installation process. The Windows/CE environment originally shipped with the iPAQ contains a hidden mini-loader, sometimes referred to as the "Parrot" loader. This loader can be started by holding down the action button (the joypad) while resetting the unit or when powering on. At this point, a blue bird will appear on the LCD screen. Also at this point, a simple loader can be accessed over the serial port at 115200/8N1. Using this loader, the contents of the iPAQ flash memory can be saved to a Compact Flash memory card. We have only tested this operation with a 32Mbyte CF memory card. Given that the backup will take 16MBytes + 1KByte, something more than a 16MByte card will be required. Use the "r2c" command to dump Flash contents to the CF memory card. Once this completes, RedBoot can be installed with no fear since the Parrot loader can be used to restore the Flash contents at a later time. If you expect to completely recover the state of the iPAQ Win/CE environment, then HotSync should be run to backup all "RAM" files as well before installing RedBoot. The next step in installing RedBoot on the iPAQ actually involves Windows/CE, which is the native environment on the unit. Using WinCE, you need to install an application which will run a RAM based version of RedBoot. Once this is installed and running, RedBoot can be used to update the flash with a native/ROM version of RedBoot. Using ActiveSync, copy the file OSloader to your iPAQ. Using ActiveSync, copy the file redboot_WinCE.bin to the iPAQ as bootldr in its root directory. Note: this is not the top level folder displayed by Windows (Mobile Device), but rather the 'My Pocket PC' folder within it. Execute OSloader. If you didn't create a shortcut, then you will have to poke around for it using the WinCE file explorer. Choose the Tools->BootLdr->Run after loading from file menu item. At this point, the RAM based version of RedBoot should be running. You should be able to return to this point by just executing the last two steps of the previous process if necessary. This method of installation is no longer supported. If you have previously installed either the Compaq boot loader or older versions of RedBoot, restore the Win/CE environment and proceed as outlined above. When RedBoot first comes up, it will want to initialize its LCD touch screen parameters. It does this by displaying a keyboard graphic and asks you to press certain keys. Using the stylus, press and hold until the prompt is withdrawn. When you lift the stylus, RedBoot will continue with the next calibration. Once the LCD touchscreen has been calibrated, RedBoot will start. The calibration step can be skipped by pressing the return/abort button on the unit (right most button with a curved arrow icon). Additionally, the unit will assume default values if the screen is not touched within about 15 seconds. Once RedBoot has started, you should get information similar to this on the LCD screen. It will also appear on the serial port at 38400,8,N,1. RedBoot(tm) bootstrap and debug environment [ROM] Non-certified release, version UNKNOWN - built 06:17:41, Mar 19 2001 Platform: Compaq iPAQ Pocket PC (StrongARM 1110) Copyright (C) 2000, 2001, Free Software Foundation, Inc. RAM: 0x00000000-0x01fc0000, 0x0001f200-0x01f70000 available FLASH: 0x50000000 - 0x51000000, 64 blocks of 0x00040000 bytes each. Since the LCD touchscreen is only 30 characters wide, some of this data will be off the right hand side of the display. The joypad may be used to pan left and right in order to see the full lines. If you have a Compact Flash ethernet card, RedBoot should find it. You'll need to have BOOTP enabled for this unit (see your sysadmin for details). If it does, it will print a message like: ... Waiting for network card: .Ready! Socket Communications Inc: CF+ LPE Revision E 08/04/99 IP: 192.168.1.34, Default server: 192.168.1.101 Once you are satisfied with the setup and that RedBoot is operating properly in your environment, you can set up your iPAQ unit to have RedBoot be the bootstrap application. This step will destroy your Windows/CE environment. Before you take this step, it is strongly recommended you save your WinCE FLASH contents as outlined above using the "parrot" loader, or by using the Compaq OSloader: Using OSloader on the iPAQ, select the Tools->Flash->Save to files.... menu item. Four (4) files, 4MB each in size will be created. After each file is created, copy the file to your computer, then delete the file from the iPAQ to make room in the WinCE ramdisk for the next file. You will need to download the version of RedBoot designed as the ROM bootstrap. Then install it permanently using these commands: RedBoot> lo -r -b 0x100000 redboot_ROM.bin RedBoot> fi loc -f 0x50000000 -l 0x40000 RedBoot> fis init RedBoot> fi unl -f 0x50040000 -l 0x40000 RedBoot> fi cr RedBoot -b 0x100000 RedBoot> fi loc -f 0x50040000 -l 0x40000 RedBoot> reset You must type these commands exactly! Failure to do so may render your iPAQ totally useless. Once you've done this, RedBoot should come up every time you reset. To restore Windows/CE from the backup taken in , visit http://www.handhelds.org/projects/wincerestoration.html for directions. The exec command which allows the loading and execution of Linux kernels, is supported for this board (see ). The exec parameters used for the iPAQ are: -b <addr> Location Linux kernel was loaded to -l <len> Length of kernel -c "params" Parameters passed to kernel -r <addr> 'initrd' ramdisk location -s <len> Length of initrd ramdisk Linux kernels may be run on the iPAQ using the sources from the anonymous CVS repository at the Handhelds project ( http://www.handhelds.org/) with the elinux.patch patch file applied. This file can be found in the misc/ subdirectory of the iPAQ platform HAL in the RedBoot sources, normally hal/arm/sa11x0/ipaq/VERSION/misc/ On the iPAQ (and indeed all SA11x0 platforms), Linux expects to be loaded at address 0xC0008000 and the entry point is also at 0xC0008000. RedBoot sets up the following memory map on the iPAQ: The first level page table is located at physical address 0xC0004000. No second level tables are used. The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B). Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x01ffffff 16Mb to 32Mb FLASH (nCS0) [organized as below] 0x000000 - 0x0003ffff Parrot Loader 0x040000 - 0x0007ffff RedBoot 0xf80000 - 0x00fbffff Fconfig data 0xfc0000 - 0x00ffffff FIS directory 0x30000000 - 0x3fffffff Compact Flash 0x48000000 - 0x4bffffff iPAQ internal registers 0x80000000 - 0xbfffffff SA-1110 Internal Registers 0xc0000000 - 0xc1ffffff DRAM Bank 0 - 32Mb SDRAM 0xe0000000 - 0xe7ffffff Cache Clean Virtual Address Range C B Description ----------------------- - - ---------------------------------- 0x00000000 - 0x01ffffff Y Y DRAM - 32Mb 0x30000000 - 0x3fffffff N N Compact Flash 0x48000000 - 0x4bffffff N N iPAQ internal registers 0x50000000 - 0x51ffffff Y Y Up to 32Mb FLASH (nCS0) 0x80000000 - 0xbfffffff N N SA-1110 Internal Registers 0xc0000000 - 0xc1ffffff N Y DRAM Bank 0: 32Mb 0xe0000000 - 0xe7ffffff Y Y Cache Clean These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=ipaq export ARCH_DIR=arm export PLATFORM_DIR=sa11x0/ipaq The names of configuration files are listed above with the description of the associated modes. Intrinsyc CerfCubeinstalling and testinginstalling and testing Intrinsyc CerfCube RedBoot supports the serial port and the builtin ethernet connection for communication and downloads. The default serial port settings are 38400,8,N,1. RedBoot runs from and supports flash management for the system flash region. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm The original boot loader supplied with the CerfCube can be used to install RedBoot. Connect to the device using a serial port at 38400/8N1. Copy the binary RedBoot ROM mode image to an available TFTP server. Issue these commands to the Instrinsyc loader: download tftp:x.x.x.x redboot_ROM.bin 0xc0000000 flashloader 0x00000000 0xc0000000 0x20000 where x.x.x.x is the IP address of the TFTP server. Other installation methods may be available via the Intrinsyc loader. Contact Intrinsyc for details. The exec command which allows the loading and execution of Linux kernels, is supported for this board (see ). The exec parameters used for the CerfCube are: -b <addr> Location Linux kernel was loaded to -l <len> Length of kernel -c "params" Parameters passed to kernel -r <addr> 'initrd' ramdisk location -s <len> Length of initrd ramdisk RedBoot sets up the following memory map on the CerfCube: The first level page table is located at physical address 0xC0004000. No second level tables are used. The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B). Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x01ffffff 16Mb to 32Mb FLASH (nCS0) [organized as below] 0x000000 - 0x0001ffff RedBoot 0x020000 - 0x0003ffff RedBoot [RAM version] 0xfc0000 - 0x00fdffff Fconfig data 0xfe0000 - 0x00ffffff FIS directory 0x0f000000 - 0x0fffffff Onboard ethernet 0x10000000 - 0x17ffffff CerfCube internal registers 0x20000000 - 0x3fffffff PCMCIA / Compact Flash 0x80000000 - 0xbfffffff SA-1110 Internal Registers 0xc0000000 - 0xc1ffffff DRAM Bank 0 - 32Mb SDRAM 0xe0000000 - 0xe7ffffff Cache Clean Virtual Address Range C B Description ----------------------- - - ---------------------------------- 0x00000000 - 0x01ffffff Y Y DRAM - 32Mb 0x08000000 - 0x0fffffff N N Onboard ethernet controller 0x10000000 - 0x17ffffff N N CerfCube internal registers 0x20000000 - 0x3fffffff N N PCMCIA / Compact Flash 0x50000000 - 0x51ffffff Y Y Up to 32Mb FLASH (nCS0) 0x80000000 - 0xbfffffff N N SA-1110 Internal Registers 0xc0000000 - 0xc1ffffff N Y DRAM Bank 0: 32Mb 0xe0000000 - 0xe7ffffff Y Y Cache Clean These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=cerf export ARCH_DIR=arm export PLATFORM_DIR=sa11x0/cerf The names of configuration files are listed above with the description of the associated modes. Cyclone IQ80310installing and testinginstalling and testing Cyclone IQ80310RedBoot supports both serial ports and the built-in ethernet port for communication and downloads. The default serial port settings are 115200,8,N,1. RedBoot also supports flash management for the onboard 8MB flash. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm ROMA [ROM] RedBoot running from flash address 0x40000, with ARM bootloader in flash boot sector. redboot_ROMA.ecm RAMA [RAM] RedBoot running from RAM with ARM bootloader in flash boot sector. redboot_RAMA.ecm The board manufacturer provides a DOS application which is capable of programming the flash over the PCI bus, and this is required for initial installations of RedBoot. Please see the board manual for information on using this utility. In general, the process involves programming one of the two flash based RedBoot images to flash. The ROM mode RedBoot (which runs from the flash boot sector) should be programmed to flash address 0x00000000. The ROMA RedBoot mode (which is started by the ARM bootloader) should be programmed to flash address 0x00004000. To install RedBoot to run from the flash boot sector, use the manufacturer's flash utility to install the ROM mode image at address zero. To install RedBoot to run from address 0x40000 with the ARM bootloader in the flash boot sector, use the manufacturer's flash utility to install the ROMA mode image at address 0x40000. After booting the initial installation of RedBoot, this warning may be printed: flash configuration checksum error or invalid key This is normal, and indicates that the flash must be configured for use by RedBoot. Even if the above message is not printed, it may be a good idea to reinitialize the flash anyway. Do this with the fis command: RedBoot> fis init About to initialize [format] flash image system - continue (y/n)? y *** Initialize flash Image System Warning: device contents not erased, some blocks may not be usable ... Unlock from 0x007e0000-0x00800000: . ... Erase from 0x007e0000-0x00800000: . ... Program from 0xa1fd0000-0xa1fd0400 at 0x007e0000: . ... Lock from 0x007e0000-0x00800000: . Followed by the fconfig command: RedBoot> fconfig Run script at boot: false Use BOOTP for network configuration: false Local IP address: 192.168.1.153 Default server IP address: 192.168.1.10 GDB connection port: 1000 Network debug at boot time: false Update RedBoot non-volatile configuration - continue (y/n)? y ... Unlock from 0x007c0000-0x007e0000: . ... Erase from 0x007c0000-0x007e0000: . ... Program from 0xa0013018-0xa0013418 at 0x007c0000: . ... Lock from 0x007c0000-0x007e0000: . When later updating RedBoot in situ, it is important to use a matching ROM and RAM mode pair of images. So use either RAM/ROM or RAMA/ROMA images. Do not mix them. RedBoot uses the two digit LED display to indicate errors during board initialization. Possible error codes are: 88 - Unknown Error 55 - I2C Error FF - SDRAM Error 01 - No Error RedBoot can coexist with ARM tools in flash on the IQ80310 board. In this configuration, the ARM bootloader will occupy the flash boot sector while RedBoot is located at flash address 0x40000. The sixteen position rotary switch is used to tell the ARM bootloader to jump to the RedBoot image located at address 0x40000. RedBoot is selected by switch position 0 or 1. Other switch positions are used by the ARM firmware and RedBoot will not be started. A special RedBoot command, diag, is used to access a set of hardware diagnostics provided by the board manufacturer. To access the diagnostic menu, enter diag at the RedBoot prompt: RedBoot> diag Entering Hardware Diagnostics - Disabling Data Cache! 1 - Memory Tests 2 - Repeating Memory Tests 3 - 16C552 DUART Serial Port Tests 4 - Rotary Switch S1 Test for positions 0-3 5 - seven Segment LED Tests 6 - Backplane Detection Test 7 - Battery Status Test 8 - External Timer Test 9 - i82559 Ethernet Configuration 10 - i82559 Ethernet Test 11 - Secondary PCI Bus Test 12 - Primary PCI Bus Test 13 - i960Rx/303 PCI Interrupt Test 14 - Internal Timer Test 15 - GPIO Test 0 - quit Enter the menu item number (0 to quit): Tests for various hardware subsystems are provided, and some tests require special hardware in order to execute normally. The Ethernet Configuration item may be used to set the board ethernet address. 1 - Memory Tests 2 - Repeating Memory Tests 3 - 16C552 DUART Serial Port Tests 4 - Rotary Switch S1 Test for positions 0-3 5 - 7 Segment LED Tests 6 - Backplane Detection Test 7 - Battery Status Test 8 - External Timer Test 9 - i82559 Ethernet Configuration 10 - i82559 Ethernet Test 11 - i960Rx/303 PCI Interrupt Test 12 - Internal Timer Test 13 - Secondary PCI Bus Test 14 - Primary PCI Bus Test 15 - Battery Backup SDRAM Memory Test 16 - GPIO Test 17 - Repeat-On-Fail Memory Test 18 - Coyonosa Cache Loop (No return) 19 - Show Software and Hardware Revision 0 - quit Enter the menu item number (0 to quit): Tests for various hardware subsystems are provided, and some tests require special hardware in order to execute normally. The Ethernet Configuration item may be used to set the board ethernet address. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=iq80310 export ARCH_DIR=arm export PLATFORM_DIR=iq80310 The names of configuration files are listed above with the description of the associated modes. RedBoot uses an interrupt vector table which is located at address 0xA000A004. Entries in this table are pointers to functions with this protoype:: int irq_handler( unsigned vector, unsigned data )On an IQ80310 board, the vector argument is one of 49 interrupts defined in hal/arm/iq80310/current/include/hal_platform_ints.h:: // *** 80200 CPU *** #define CYGNUM_HAL_INTERRUPT_reserved0 0 #define CYGNUM_HAL_INTERRUPT_PMU_PMN0_OVFL 1 // See Ch.12 - Performance Mon. #define CYGNUM_HAL_INTERRUPT_PMU_PMN1_OVFL 2 // PMU counter 0/1 overflow #define CYGNUM_HAL_INTERRUPT_PMU_CCNT_OVFL 3 // PMU clock overflow #define CYGNUM_HAL_INTERRUPT_BCU_INTERRUPT 4 // See Ch.11 - Bus Control Unit #define CYGNUM_HAL_INTERRUPT_NIRQ 5 // external IRQ #define CYGNUM_HAL_INTERRUPT_NFIQ 6 // external FIQ // *** XINT6 interrupts *** #define CYGNUM_HAL_INTERRUPT_DMA_0 7 #define CYGNUM_HAL_INTERRUPT_DMA_1 8 #define CYGNUM_HAL_INTERRUPT_DMA_2 9 #define CYGNUM_HAL_INTERRUPT_GTSC 10 // Global Time Stamp Counter #define CYGNUM_HAL_INTERRUPT_PEC 11 // Performance Event Counter #define CYGNUM_HAL_INTERRUPT_AAIP 12 // application accelerator unit // *** XINT7 interrupts *** // I2C interrupts #define CYGNUM_HAL_INTERRUPT_I2C_TX_EMPTY 13 #define CYGNUM_HAL_INTERRUPT_I2C_RX_FULL 14 #define CYGNUM_HAL_INTERRUPT_I2C_BUS_ERR 15 #define CYGNUM_HAL_INTERRUPT_I2C_STOP 16 #define CYGNUM_HAL_INTERRUPT_I2C_LOSS 17 #define CYGNUM_HAL_INTERRUPT_I2C_ADDRESS 18 // Messaging Unit interrupts #define CYGNUM_HAL_INTERRUPT_MESSAGE_0 19 #define CYGNUM_HAL_INTERRUPT_MESSAGE_1 20 #define CYGNUM_HAL_INTERRUPT_DOORBELL 21 #define CYGNUM_HAL_INTERRUPT_NMI_DOORBELL 22 #define CYGNUM_HAL_INTERRUPT_QUEUE_POST 23 #define CYGNUM_HAL_INTERRUPT_OUTBOUND_QUEUE_FULL 24 #define CYGNUM_HAL_INTERRUPT_INDEX_REGISTER 25 // PCI Address Translation Unit #define CYGNUM_HAL_INTERRUPT_BIST 26 // *** External board interrupts (XINT3) *** #define CYGNUM_HAL_INTERRUPT_TIMER 27 // external timer #define CYGNUM_HAL_INTERRUPT_ETHERNET 28 // onboard enet #define CYGNUM_HAL_INTERRUPT_SERIAL_A 29 // 16x50 uart A #define CYGNUM_HAL_INTERRUPT_SERIAL_B 30 // 16x50 uart B #define CYGNUM_HAL_INTERRUPT_PCI_S_INTD 31 // secondary PCI INTD // The hardware doesn't (yet?) provide masking or status for these // even though they can trigger cpu interrupts. ISRs will need to // poll the device to see if the device actually triggered the // interrupt. #define CYGNUM_HAL_INTERRUPT_PCI_S_INTC 32 // secondary PCI INTC #define CYGNUM_HAL_INTERRUPT_PCI_S_INTB 33 // secondary PCI INTB #define CYGNUM_HAL_INTERRUPT_PCI_S_INTA 34 // secondary PCI INTA // *** NMI Interrupts go to FIQ *** #define CYGNUM_HAL_INTERRUPT_MCU_ERR 35 #define CYGNUM_HAL_INTERRUPT_PATU_ERR 36 #define CYGNUM_HAL_INTERRUPT_SATU_ERR 37 #define CYGNUM_HAL_INTERRUPT_PBDG_ERR 38 #define CYGNUM_HAL_INTERRUPT_SBDG_ERR 39 #define CYGNUM_HAL_INTERRUPT_DMA0_ERR 40 #define CYGNUM_HAL_INTERRUPT_DMA1_ERR 41 #define CYGNUM_HAL_INTERRUPT_DMA2_ERR 42 #define CYGNUM_HAL_INTERRUPT_MU_ERR 43 #define CYGNUM_HAL_INTERRUPT_reserved52 44 #define CYGNUM_HAL_INTERRUPT_AAU_ERR 45 #define CYGNUM_HAL_INTERRUPT_BIU_ERR 46 // *** ATU FIQ sources *** #define CYGNUM_HAL_INTERRUPT_P_SERR 47 #define CYGNUM_HAL_INTERRUPT_S_SERR 48The data passed to the ISR is pulled from a data table (hal_interrupt_data) which immediately follows the interrupt vector table. With 49 interrupts, the data table starts at address 0xA000A0C8. An application may create a normal C function with the above prototype to be an ISR. Just poke its address into the table at the correct index and enable the interrupt at its source. The return value of the ISR is ignored by RedBoot. The first level page table is located at 0xa0004000. Two second level tables are also used. One second level table is located at 0xa0008000 and maps the first 1MB of flash. The other second level table is at 0xa0008400, and maps the first 1MB of SDRAM. The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B). Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x00000fff flash Memory 0x00001000 - 0x00001fff 80312 Internal Registers 0x00002000 - 0x007fffff flash Memory 0x00800000 - 0x7fffffff PCI ATU Outbound Direct Window 0x80000000 - 0x83ffffff Primary PCI 32-bit Memory 0x84000000 - 0x87ffffff Primary PCI 64-bit Memory 0x88000000 - 0x8bffffff Secondary PCI 32-bit Memory 0x8c000000 - 0x8fffffff Secondary PCI 64-bit Memory 0x90000000 - 0x9000ffff Primary PCI IO Space 0x90010000 - 0x9001ffff Secondary PCI IO Space 0x90020000 - 0x9fffffff Unused 0xa0000000 - 0xbfffffff SDRAM 0xc0000000 - 0xefffffff Unused 0xf0000000 - 0xffffffff 80200 Internal Registers Virtual Address Range C B Description ----------------------- - - ---------------------------------- 0x00000000 - 0x00000fff Y Y SDRAM 0x00001000 - 0x00001fff N N 80312 Internal Registers 0x00002000 - 0x007fffff Y N flash Memory 0x00800000 - 0x7fffffff N N PCI ATU Outbound Direct Window 0x80000000 - 0x83ffffff N N Primary PCI 32-bit Memory 0x84000000 - 0x87ffffff N N Primary PCI 64-bit Memory 0x88000000 - 0x8bffffff N N Secondary PCI 32-bit Memory 0x8c000000 - 0x8fffffff N N Secondary PCI 64-bit Memory 0x90000000 - 0x9000ffff N N Primary PCI IO Space 0x90010000 - 0x9001ffff N N Secondary PCI IO Space 0xa0000000 - 0xbfffffff Y Y SDRAM 0xc0000000 - 0xcfffffff Y Y Cache Flush Region 0xd0000000 - 0xd0000fff Y N first 4k page of flash 0xf0000000 - 0xffffffff N N 80200 Internal Registers The external timer is used as a polled timer to provide timeout support for networking and XModem file transfers. Intel IQ80321installing and testinginstalling and testing Intel IQ80321RedBoot supports the serial port and the built-in ethernet port for communication and downloads. The default serial port settings are 115200,8,N,1. RedBoot also supports flash management for the onboard 8MB flash. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm The board manufacturer provides a DOS application which is capable of programming the flash over the PCI bus, and this is required for initial installations of RedBoot. Please see the board manual for information on using this utility. In general, the process involves programming the ROM mode RedBoot image to flash. RedBoot should be programmed to flash address 0x00000000 using the DOS utility. After booting the initial installation of RedBoot, this warning may be printed: flash configuration checksum error or invalid key This is normal, and indicates that the flash must be configured for use by RedBoot. Even if the above message is not printed, it may be a good idea to reinitialize the flash anyway. Do this with the fis command: RedBoot> fis init About to initialize [format] FLASH image system - continue (y/n)? y *** Initialize FLASH Image System Warning: device contents not erased, some blocks may not be usable ... Unlock from 0xf07e0000-0xf0800000: . ... Erase from 0xf07e0000-0xf0800000: . ... Program from 0x01ddf000-0x01ddf400 at 0xf07e0000: . ... Lock from 0xf07e0000-0xf0800000: . The 80321 board is highly configurable through a number of switches and jumpers. RedBoot makes some assumptions about board configuration and attention must be paid to these assumptions for reliable RedBoot operation: The onboard ethernet and the secondary slot may be placed in a private space so that they are not seen by a PC BIOS. If the board is to be used in a PC with BIOS, then the ethernet should be placed in this private space so that RedBoot and the BIOS do not conflict. RedBoot assumes that the board is plugged into a PC with BIOS. This requires RedBoot to detect when the BIOS has configured the PCI-X secondary bus. If the board is placed in a backplane, RedBoot will never see the BIOS configure the secondary bus. To prevent this wait, set switch S7E1-3 to ON when using the board in a backplane. For the remaining switch settings, the following is a known good configuration: S1D1All OFF S7E17 is ON, all others OFF S8E12,3,5,6 are ON, all others OFF S8E22,3 are ON, all others OFF S9E13 is ON, all others OFF S4D11,3 are ON, all others OFF J9E12,3 jumpered J9F12,3 jumpered J3F1Nothing jumpered J3G12,3 jumpered J1G22,3 jumpered RedBoot uses the two digit LED display to indicate status during board initialization. Possible codes are: LED Actions ------------------------------------------------------------- Power-On/Reset 88 Set the CPSR Enable coprocessor access Drain write and fill buffer Setup PBIU chip selects A1 Enable the Icache A2 Move FLASH chip select from 0x0 to 0xF0000000 Jump to new FLASH location A3 Setup and enable the MMU A4 I2C interface initialization 90 Wait for I2C initialization to complete 91 Send address (via I2C) to the DIMM 92 Wait for transmit complete 93 Read SDRAM PD data from DIMM 94 Read remainder of EEPROM data. An error will result in one of the following error codes on the LEDs: 77 BAD EEPROM checksum 55 I2C protocol error FF bank size error A5 Setup DDR memory interface A6 Enable branch target buffer Drain the write & fill buffers Flush Icache, Dcache and BTB Flush instuction and data TLBs Drain the write & fill buffers SL ECC Scrub Loop SE A7 Clean, drain, flush the main Dcache A8 Clean, drain, flush the mini Dcache Flush Dcache Drain the write & fill buffers A9 Enable ECC AA Save SDRAM size Move MMU tables into RAM AB Clean, drain, flush the main Dcache Clean, drain, flush the mini Dcache Drain the write & fill buffers AC Set the TTB register to DRAM mmu_table AD Set mode to IRQ mode A7 Move SWI & Undefined "vectors" to RAM (at 0x0) A6 Switch to supervisor mode A5 Move remaining "vectors" to RAM (at 0x0) A4 Copy DATA to RAM Initialize interrupt exception environment Initialize stack Clear BSS section A3 Call platform specific hardware initialization A2 Run through static constructors A1 Start up the eCos kernel or RedBoot A special RedBoot command, diag, is used to access a set of hardware diagnostics. To access the diagnostic menu, enter diag at the RedBoot prompt: RedBoot> diag Entering Hardware Diagnostics - Disabling Data Cache! IQ80321 Hardware Tests 1 - Memory Tests 2 - Repeating Memory Tests 3 - Repeat-On-Fail Memory Tests 4 - Rotary Switch S1 Test 5 - 7 Segment LED Tests 6 - i82544 Ethernet Configuration 7 - Baterry Status Test 8 - Battery Backup SDRAM Memory Test 9 - Timer Test 10 - PCI Bus test 11 - CPU Cache Loop (No Return) 0 - quit Enter the menu item number (0 to quit): Tests for various hardware subsystems are provided, and some tests require special hardware in order to execute normally. The Ethernet Configuration item may be used to set the board ethernet address. This test is used to test installed DDR SDRAM memory. Five different tests are run over the given address ranges. If errors are encountered, the test is aborted and information about the failure is printed. When selected, the user will be prompted to enter the base address of the test range and its size. The numbers must be in hex with no leading “0x” Enter the menu item number (0 to quit): 1 Base address of memory to test (in hex): 100000 Size of memory to test (in hex): 200000 Testing memory from 0x00100000 to 0x002fffff. Walking 1's test: 0000000100000002000000040000000800000010000000200000004000000080 0000010000000200000004000000080000001000000020000000400000008000 0001000000020000000400000008000000100000002000000040000000800000 0100000002000000040000000800000010000000200000004000000080000000 passed 32-bit address test: passed 32-bit address bar test: passed 8-bit address test: passed Byte address bar test: passed Memory test done. The repeating memory tests are exactly the same as the above memory tests, except that the tests are automatically rerun after completion. The only way out of this test is to reset the board. This is similar to the repeating memory tests except that when an error is found, the failing test continuously retries on the failing address. This tests the operation of the sixteen position rotary switch. When run, this test will display the current position of the rotary switch on the LED display. Slowly dial through each position and confirm reading on LED. This tests the operation of the seven segment displays. When run, each LED cycles through 0 through F and a decimal point. This test initializes the ethernet controller’s serial EEPROM if the current contents are invalid. In any case, this test will also allow the user to enter a six byte ethernet MAC address into the serial EEPROM. Enter the menu item number (0 to quit): 6 Current MAC address: 00:80:4d:46:00:02 Enter desired MAC address: 00:80:4d:46:00:01 Writing to the Serial EEPROM... Done ******** Reset The Board To Have Changes Take Effect ******** This tests the current status of the battery. First, the test checks to see if the battery is installed and reports that finding. If the battery is installed, the test further determines whether the battery status is one or more of the following: Battery is charging. Battery is fully discharged. Battery voltage measures within normal operating range. This tests the battery backup of SDRAM memory. This test is a three step process: Select Battery backup test from main diag menu, then write data to SDRAM. Turn off power for 60 seconds, then repower the board. Select Battery backup test from main diag menu, then check data that was written in step 1. This tests the internal timer by printing a number of dots at one second intervals. This tests the secondary PCI-X bus and socket. This test requires that an IQ80310 board be plugged into the secondary slot of the IOP80321 board. The test assumes at least 32MB of installed memory on the IQ80310. That memory is mapped into the IOP80321 address space and the memory tests are run on that memory. This test puts the CPU into a tight loop run entirely from the ICache. This should prevent all external bus accesses. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=iq80321 export ARCH_DIR=arm export PLATFORM_DIR=xscale/iq80321 The names of configuration files are listed above with the description of the associated modes. RedBoot uses an interrupt vector table which is located at address 0x8004. Entries in this table are pointers to functions with this protoype:: int irq_handler( unsigned vector, unsigned data )On an IQ80321 board, the vector argument is one of 32 interrupts defined in hal/arm/xscale/verde/current/include/hal_var_ints.h:: // *** 80200 CPU *** #define CYGNUM_HAL_INTERRUPT_DMA0_EOT 0 #define CYGNUM_HAL_INTERRUPT_DMA0_EOC 1 #define CYGNUM_HAL_INTERRUPT_DMA1_EOT 2 #define CYGNUM_HAL_INTERRUPT_DMA1_EOC 3 #define CYGNUM_HAL_INTERRUPT_RSVD_4 4 #define CYGNUM_HAL_INTERRUPT_RSVD_5 5 #define CYGNUM_HAL_INTERRUPT_AA_EOT 6 #define CYGNUM_HAL_INTERRUPT_AA_EOC 7 #define CYGNUM_HAL_INTERRUPT_CORE_PMON 8 #define CYGNUM_HAL_INTERRUPT_TIMER0 9 #define CYGNUM_HAL_INTERRUPT_TIMER1 10 #define CYGNUM_HAL_INTERRUPT_I2C_0 11 #define CYGNUM_HAL_INTERRUPT_I2C_1 12 #define CYGNUM_HAL_INTERRUPT_MESSAGING 13 #define CYGNUM_HAL_INTERRUPT_ATU_BIST 14 #define CYGNUM_HAL_INTERRUPT_PERFMON 15 #define CYGNUM_HAL_INTERRUPT_CORE_PMU 16 #define CYGNUM_HAL_INTERRUPT_BIU_ERR 17 #define CYGNUM_HAL_INTERRUPT_ATU_ERR 18 #define CYGNUM_HAL_INTERRUPT_MCU_ERR 19 #define CYGNUM_HAL_INTERRUPT_DMA0_ERR 20 #define CYGNUM_HAL_INTERRUPT_DMA1_ERR 22 #define CYGNUM_HAL_INTERRUPT_AA_ERR 23 #define CYGNUM_HAL_INTERRUPT_MSG_ERR 24 #define CYGNUM_HAL_INTERRUPT_SSP 25 #define CYGNUM_HAL_INTERRUPT_RSVD_26 26 #define CYGNUM_HAL_INTERRUPT_XINT0 27 #define CYGNUM_HAL_INTERRUPT_XINT1 28 #define CYGNUM_HAL_INTERRUPT_XINT2 29 #define CYGNUM_HAL_INTERRUPT_XINT3 30 #define CYGNUM_HAL_INTERRUPT_HPI 31 The data passed to the ISR is pulled from a data table (hal_interrupt_data) which immediately follows the interrupt vector table. With 32 interrupts, the data table starts at address 0x8084. An application may create a normal C function with the above prototype to be an ISR. Just poke its address into the table at the correct index and enable the interrupt at its source. The return value of the ISR is ignored by RedBoot. The RAM based page table is located at RAM start + 0x4000. RedBoot may be configured for one of two memory maps. The difference between them is the location of RAM and the PCI outbound windows. The alternative memory map may be used when building RedBoot or eCos by using the RAM_ALTMAP and ROM_ALTMAP startup types in the configuration. The virtual memory maps in this section use a C, B, and X column to indicate the caching policy for the region.. X C B Description - - - --------------------------------------------- 0 0 0 Uncached/Unbuffered 0 0 1 Uncached/Buffered 0 1 0 Cached/Buffered Write Through, Read Allocate 0 1 1 Cached/Buffered Write Back, Read Allocate 1 0 0 Invalid -- not used 1 0 1 Uncached/Buffered No write buffer coalescing 1 1 0 Mini DCache - Policy set by Aux Ctl Register 1 1 1 Cached/Buffered Write Back, Read/Write Allocate Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x7fffffff ATU Outbound Direct Window 0x80000000 - 0x900fffff ATU Outbound Translate Windows 0xa0000000 - 0xbfffffff SDRAM 0xf0000000 - 0xf0800000 FLASH (PBIU CS0) 0xfe800000 - 0xfe800fff UART (PBIU CS1) 0xfe840000 - 0xfe840fff Left 7-segment LED (PBIU CS3) 0xfe850000 - 0xfe850fff Right 7-segment LED (PBIU CS2) 0xfe8d0000 - 0xfe8d0fff Rotary Switch (PBIU CS4) 0xfe8f0000 - 0xfe8f0fff Baterry Status (PBIU CS5) 0xfff00000 - 0xffffffff Verde Memory mapped Registers Default Virtual Map X C B Description ----------------------- - - - ---------------------------------- 0x00000000 - 0x1fffffff 1 1 1 SDRAM 0x20000000 - 0x9fffffff 0 0 0 ATU Outbound Direct Window 0xa0000000 - 0xb00fffff 0 0 0 ATU Outbound Translate Windows 0xc0000000 - 0xdfffffff 0 0 0 Uncached alias for SDRAM 0xe0000000 - 0xe00fffff 1 1 1 Cache flush region (no phys mem) 0xf0000000 - 0xf0800000 0 1 0 FLASH (PBIU CS0) 0xfe800000 - 0xfe800fff 0 0 0 UART (PBIU CS1) 0xfe840000 - 0xfe840fff 0 0 0 Left 7-segment LED (PBIU CS3) 0xfe850000 - 0xfe850fff 0 0 0 Right 7-segment LED (PBIU CS2) 0xfe8d0000 - 0xfe8d0fff 0 0 0 Rotary Switch (PBIU CS4) 0xfe8f0000 - 0xfe8f0fff 0 0 0 Baterry Status (PBIU CS5) 0xfff00000 - 0xffffffff 0 0 0 Verde Memory mapped Registers Alternate Virtual Map X C B Description ----------------------- - - - ---------------------------------- 0x00000000 - 0x000fffff 1 1 1 Alias for 1st MB of SDRAM 0x00100000 - 0x7fffffff 0 0 0 ATU Outbound Direct Window 0x80000000 - 0x900fffff 0 0 0 ATU Outbound Translate Windows 0xa0000000 - 0xbfffffff 1 1 1 SDRAM 0xc0000000 - 0xdfffffff 0 0 0 Uncached alias for SDRAM 0xe0000000 - 0xe00fffff 1 1 1 Cache flush region (no phys mem) 0xf0000000 - 0xf0800000 0 1 0 FLASH (PBIU CS0) 0xfe800000 - 0xfe800fff 0 0 0 UART (PBIU CS1) 0xfe840000 - 0xfe840fff 0 0 0 Left 7-segment LED (PBIU CS3) 0xfe850000 - 0xfe850fff 0 0 0 Right 7-segment LED (PBIU CS2) 0xfe8d0000 - 0xfe8d0fff 0 0 0 Rotary Switch (PBIU CS4) 0xfe8f0000 - 0xfe8f0fff 0 0 0 Baterry Status (PBIU CS5) 0xfff00000 - 0xffffffff 0 0 0 Verde Memory mapped Registers The Verde programmable timer0 is used for timeout support for networking and XModem file transfers. Intel IXDP425installing and testinginstalling and testing Intel IXDPRedBoot supports the builtin high-speed and console UARTs and a PCI based i82559 ethernet card for communication and downloads. The default serial port settings are 115200,8,N,1. RedBoot also supports flash management for the 16MB boot flash on the mainboard. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from flash sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm The IXDP425 flash is socketed, so initial installation may be done using an appropriate device programmer. JTAG based initial may also be used. In either case, the ROM mode RedBoot is programmed into the boot flash at address 0x00000000. After booting the initial installation of RedBoot, this warning may be printed: flash configuration checksum error or invalid key This is normal, and indicates that the flash should be configured for use by RedBoot. See for more details. RedBoot uses the 4 digit LED display to indicate status during board initialization. Possible codes are: LED Actions ------------------------------------------------------------- Power-On/Reset Set the CPSR Enable coprocessor access Drain write and fill buffer Setup expansion bus chip selects 1001 Enable Icache 1002 Initialize SDRAM controller 1003 Switch flash (CS0) from 0x00000000 to 0x50000000 1004 Copy MMU table to RAM 1005 Setup TTB and domain permissions 1006 Enable MMU 1007 Enable DCache 1008 Enable branch target buffer 1009 Drain write and fill buffer Flush caches 100A Start up the eCos kernel or RedBoot 0001 These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=ixdp425 export ARCH_DIR=arm export PLATFORM_DIR=xscale/ixdp425 The names of configuration files are listed above with the description of the associated modes. RedBoot uses an interrupt vector table which is located at address 0x8004. Entries in this table are pointers to functions with this protoype:: int irq_handler( unsigned vector, unsigned data )On the IXDP425 board, the vector argument is one of many interrupts defined in hal/arm/xscale/ixp425/current/include/hal_var_ints.h:: #define CYGNUM_HAL_INTERRUPT_NPEA 0 #define CYGNUM_HAL_INTERRUPT_NPEB 1 #define CYGNUM_HAL_INTERRUPT_NPEC 2 #define CYGNUM_HAL_INTERRUPT_QM1 3 #define CYGNUM_HAL_INTERRUPT_QM2 4 #define CYGNUM_HAL_INTERRUPT_TIMER0 5 #define CYGNUM_HAL_INTERRUPT_GPIO0 6 #define CYGNUM_HAL_INTERRUPT_GPIO1 7 #define CYGNUM_HAL_INTERRUPT_PCI_INT 8 #define CYGNUM_HAL_INTERRUPT_PCI_DMA1 9 #define CYGNUM_HAL_INTERRUPT_PCI_DMA2 10 #define CYGNUM_HAL_INTERRUPT_TIMER1 11 #define CYGNUM_HAL_INTERRUPT_USB 12 #define CYGNUM_HAL_INTERRUPT_UART2 13 #define CYGNUM_HAL_INTERRUPT_TIMESTAMP 14 #define CYGNUM_HAL_INTERRUPT_UART1 15 #define CYGNUM_HAL_INTERRUPT_WDOG 16 #define CYGNUM_HAL_INTERRUPT_AHB_PMU 17 #define CYGNUM_HAL_INTERRUPT_XSCALE_PMU 18 #define CYGNUM_HAL_INTERRUPT_GPIO2 19 #define CYGNUM_HAL_INTERRUPT_GPIO3 20 #define CYGNUM_HAL_INTERRUPT_GPIO4 21 #define CYGNUM_HAL_INTERRUPT_GPIO5 22 #define CYGNUM_HAL_INTERRUPT_GPIO6 23 #define CYGNUM_HAL_INTERRUPT_GPIO7 24 #define CYGNUM_HAL_INTERRUPT_GPIO8 25 #define CYGNUM_HAL_INTERRUPT_GPIO9 26 #define CYGNUM_HAL_INTERRUPT_GPIO10 27 #define CYGNUM_HAL_INTERRUPT_GPIO11 28 #define CYGNUM_HAL_INTERRUPT_GPIO12 29 #define CYGNUM_HAL_INTERRUPT_SW_INT1 30 #define CYGNUM_HAL_INTERRUPT_SW_INT2 31 The data passed to the ISR is pulled from a data table (hal_interrupt_data) which immediately follows the interrupt vector table. With 32 interrupts, the data table starts at address 0x8084. An application may create a normal C function with the above prototype to be an ISR. Just poke its address into the table at the correct index and enable the interrupt at its source. The return value of the ISR is ignored by RedBoot. The RAM based page table is located at RAM start + 0x4000. The virtual memory maps in this section use a C, B, and X column to indicate the caching policy for the region.. X C B Description - - - --------------------------------------------- 0 0 0 Uncached/Unbuffered 0 0 1 Uncached/Buffered 0 1 0 Cached/Buffered Write Through, Read Allocate 0 1 1 Cached/Buffered Write Back, Read Allocate 1 0 0 Invalid -- not used 1 0 1 Uncached/Buffered No write buffer coalescing 1 1 0 Mini DCache - Policy set by Aux Ctl Register 1 1 1 Cached/Buffered Write Back, Read/Write Allocate Virtual Address Physical Address XCB Size (MB) Description --------------- ---------------- --- --------- ----------- 0x00000000 0x00000000 010 256 SDRAM (cached) 0x10000000 0x10000000 010 256 SDRAM (alias) 0x20000000 0x00000000 000 256 SDRAM (uncached) 0x48000000 0x48000000 000 64 PCI Data 0x50000000 0x50000000 010 16 Flash (CS0) 0x51000000 0x51000000 000 112 CS1 - CS7 0x60000000 0x60000000 000 64 Queue Manager 0xC0000000 0xC0000000 000 1 PCI Controller 0xC4000000 0xC4000000 000 1 Exp. Bus Config 0xC8000000 0xC8000000 000 1 Misc IXP425 IO 0xCC000000 0xCC000000 000 1 SDRAM Config The IXP425 programmable OStimer0 is used for timeout support for networking and XModem file transfers. Intel GRGinstalling and testinginstalling and testing Intel GRGRedBoot supports the console UART and a PCI based i82559 ethernet card for communication and downloads. The default serial port settings are 115200,8,N,1. RedBoot also supports flash management for the 16MB onboard flash. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from flash sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm The GRG flash is socketed, so initial installation may be done using an appropriate device programmer. JTAG based initial may also be used. In either case, the ROM mode RedBoot is programmed into the boot flash at address 0x00000000. After booting the initial installation of RedBoot, this warning may be printed: flash configuration checksum error or invalid key This is normal, and indicates that the flash should be configured for use by RedBoot. See for more details. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=grg export ARCH_DIR=arm export PLATFORM_DIR=xscale/grg The names of configuration files are listed above with the description of the associated modes. RedBoot uses an interrupt vector table which is located at address 0x8004. Entries in this table are pointers to functions with this protoype:: int irq_handler( unsigned vector, unsigned data )On the GRG board, the vector argument is one of many interrupts defined in hal/arm/xscale/ixp425/current/include/hal_var_ints.h:: #define CYGNUM_HAL_INTERRUPT_NPEA 0 #define CYGNUM_HAL_INTERRUPT_NPEB 1 #define CYGNUM_HAL_INTERRUPT_NPEC 2 #define CYGNUM_HAL_INTERRUPT_QM1 3 #define CYGNUM_HAL_INTERRUPT_QM2 4 #define CYGNUM_HAL_INTERRUPT_TIMER0 5 #define CYGNUM_HAL_INTERRUPT_GPIO0 6 #define CYGNUM_HAL_INTERRUPT_GPIO1 7 #define CYGNUM_HAL_INTERRUPT_PCI_INT 8 #define CYGNUM_HAL_INTERRUPT_PCI_DMA1 9 #define CYGNUM_HAL_INTERRUPT_PCI_DMA2 10 #define CYGNUM_HAL_INTERRUPT_TIMER1 11 #define CYGNUM_HAL_INTERRUPT_USB 12 #define CYGNUM_HAL_INTERRUPT_UART2 13 #define CYGNUM_HAL_INTERRUPT_TIMESTAMP 14 #define CYGNUM_HAL_INTERRUPT_UART1 15 #define CYGNUM_HAL_INTERRUPT_WDOG 16 #define CYGNUM_HAL_INTERRUPT_AHB_PMU 17 #define CYGNUM_HAL_INTERRUPT_XSCALE_PMU 18 #define CYGNUM_HAL_INTERRUPT_GPIO2 19 #define CYGNUM_HAL_INTERRUPT_GPIO3 20 #define CYGNUM_HAL_INTERRUPT_GPIO4 21 #define CYGNUM_HAL_INTERRUPT_GPIO5 22 #define CYGNUM_HAL_INTERRUPT_GPIO6 23 #define CYGNUM_HAL_INTERRUPT_GPIO7 24 #define CYGNUM_HAL_INTERRUPT_GPIO8 25 #define CYGNUM_HAL_INTERRUPT_GPIO9 26 #define CYGNUM_HAL_INTERRUPT_GPIO10 27 #define CYGNUM_HAL_INTERRUPT_GPIO11 28 #define CYGNUM_HAL_INTERRUPT_GPIO12 29 #define CYGNUM_HAL_INTERRUPT_SW_INT1 30 #define CYGNUM_HAL_INTERRUPT_SW_INT2 31 The data passed to the ISR is pulled from a data table (hal_interrupt_data) which immediately follows the interrupt vector table. With 32 interrupts, the data table starts at address 0x8084. An application may create a normal C function with the above prototype to be an ISR. Just poke its address into the table at the correct index and enable the interrupt at its source. The return value of the ISR is ignored by RedBoot. The RAM based page table is located at RAM start + 0x4000. The virtual memory maps in this section use a C, B, and X column to indicate the caching policy for the region.. X C B Description - - - --------------------------------------------- 0 0 0 Uncached/Unbuffered 0 0 1 Uncached/Buffered 0 1 0 Cached/Buffered Write Through, Read Allocate 0 1 1 Cached/Buffered Write Back, Read Allocate 1 0 0 Invalid -- not used 1 0 1 Uncached/Buffered No write buffer coalescing 1 1 0 Mini DCache - Policy set by Aux Ctl Register 1 1 1 Cached/Buffered Write Back, Read/Write Allocate Virtual Address Physical Address XCB Size (MB) Description --------------- ---------------- --- --------- ----------- 0x00000000 0x00000000 010 32 SDRAM (cached) 0x10000000 0x00000000 010 32 SDRAM (alias) 0x20000000 0x00000000 000 32 SDRAM (uncached) 0x48000000 0x48000000 000 64 PCI Data 0x50000000 0x50000000 010 16 Flash (CS0) 0x51000000 0x51000000 000 112 CS1 - CS7 0x60000000 0x60000000 000 64 Queue Manager 0xC0000000 0xC0000000 000 1 PCI Controller 0xC4000000 0xC4000000 000 1 Exp. Bus Config 0xC8000000 0xC8000000 000 1 Misc IXP425 IO 0xCC000000 0xCC000000 000 1 SDRAM Config The IXP425 programmable OStimer0 is used for timeout support for networking and XModem file transfers. Motorola PrPMC1100installing and testinginstalling and testing Motorola PrPMC1100RedBoot supports the builtin high-speed and console UARTs . The console UART is the default and feeds the front panel COM1 connector. The high-speed UART signals are only available from the PN4 IO connector. Therefore, usability of this port depends on the carrier board used. The default serial port settings are 115200,8,N,1. RedBoot also supports flash management for the 16MB boot flash on the mainboard. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from flash sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm The PrPMC1100 flash is socketed, so initial installation may be done using an appropriate device programmer. JTAG based flash programming may also be used. In either case, the ROM mode RedBoot is programmed into the boot flash at address 0x00000000. After booting the initial installation of RedBoot, this warning may be printed: flash configuration checksum error or invalid key This is normal, and indicates that the flash should be configured for use by RedBoot. Even if this message is not seen, it is recommended that the fconfig be run to initialize the flash configuration area. See for more details. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=prpmc1100 export ARCH_DIR=arm export PLATFORM_DIR=xscale/prpmc1100 The names of configuration files are listed above with the description of the associated modes. RedBoot uses an interrupt vector table which is located at address 0x8004. Entries in this table are pointers to functions with this protoype:: int irq_handler( unsigned vector, unsigned data )On the PrPMC1100 board, the vector argument is one of many interrupts defined in hal/arm/xscale/ixp425/current/include/hal_var_ints.h:: #define CYGNUM_HAL_INTERRUPT_NPEA 0 #define CYGNUM_HAL_INTERRUPT_NPEB 1 #define CYGNUM_HAL_INTERRUPT_NPEC 2 #define CYGNUM_HAL_INTERRUPT_QM1 3 #define CYGNUM_HAL_INTERRUPT_QM2 4 #define CYGNUM_HAL_INTERRUPT_TIMER0 5 #define CYGNUM_HAL_INTERRUPT_GPIO0 6 #define CYGNUM_HAL_INTERRUPT_GPIO1 7 #define CYGNUM_HAL_INTERRUPT_PCI_INT 8 #define CYGNUM_HAL_INTERRUPT_PCI_DMA1 9 #define CYGNUM_HAL_INTERRUPT_PCI_DMA2 10 #define CYGNUM_HAL_INTERRUPT_TIMER1 11 #define CYGNUM_HAL_INTERRUPT_USB 12 #define CYGNUM_HAL_INTERRUPT_UART2 13 #define CYGNUM_HAL_INTERRUPT_TIMESTAMP 14 #define CYGNUM_HAL_INTERRUPT_UART1 15 #define CYGNUM_HAL_INTERRUPT_WDOG 16 #define CYGNUM_HAL_INTERRUPT_AHB_PMU 17 #define CYGNUM_HAL_INTERRUPT_XSCALE_PMU 18 #define CYGNUM_HAL_INTERRUPT_GPIO2 19 #define CYGNUM_HAL_INTERRUPT_GPIO3 20 #define CYGNUM_HAL_INTERRUPT_GPIO4 21 #define CYGNUM_HAL_INTERRUPT_GPIO5 22 #define CYGNUM_HAL_INTERRUPT_GPIO6 23 #define CYGNUM_HAL_INTERRUPT_GPIO7 24 #define CYGNUM_HAL_INTERRUPT_GPIO8 25 #define CYGNUM_HAL_INTERRUPT_GPIO9 26 #define CYGNUM_HAL_INTERRUPT_GPIO10 27 #define CYGNUM_HAL_INTERRUPT_GPIO11 28 #define CYGNUM_HAL_INTERRUPT_GPIO12 29 #define CYGNUM_HAL_INTERRUPT_SW_INT1 30 #define CYGNUM_HAL_INTERRUPT_SW_INT2 31 The data passed to the ISR is pulled from a data table (hal_interrupt_data) which immediately follows the interrupt vector table. With 32 interrupts, the data table starts at address 0x8084. An application may create a normal C function with the above prototype to be an ISR. Just poke its address into the table at the correct index and enable the interrupt at its source. The return value of the ISR is ignored by RedBoot. The RAM based page table is located at RAM start + 0x4000. The virtual memory maps in this section use a C, B, and X column to indicate the caching policy for the region.. X C B Description - - - --------------------------------------------- 0 0 0 Uncached/Unbuffered 0 0 1 Uncached/Buffered 0 1 0 Cached/Buffered Write Through, Read Allocate 0 1 1 Cached/Buffered Write Back, Read Allocate 1 0 0 Invalid -- not used 1 0 1 Uncached/Buffered No write buffer coalescing 1 1 0 Mini DCache - Policy set by Aux Ctl Register 1 1 1 Cached/Buffered Write Back, Read/Write Allocate Virtual Address Physical Address XCB Size (MB) Description --------------- ---------------- --- --------- ----------- 0x00000000 0x00000000 010 256 SDRAM (cached) 0x10000000 0x10000000 010 256 SDRAM (alias) 0x20000000 0x00000000 000 256 SDRAM (uncached) 0x48000000 0x48000000 000 64 PCI Data 0x50000000 0x50000000 010 16 Flash (CS0) 0x51000000 0x51000000 000 112 CS1 - CS7 0x60000000 0x60000000 000 64 Queue Manager 0xC0000000 0xC0000000 000 1 PCI Controller 0xC4000000 0xC4000000 000 1 Exp. Bus Config 0xC8000000 0xC8000000 000 1 Misc CPU IO 0xCC000000 0xCC000000 000 1 SDRAM Config The CPU programmable OStimer0 is used for timeout support for networking and XModem file transfers. Samsung CalmRISC16 Core EVBinstalling and testinginstalling and testing Samsung CalmRISC16 Core EVB The Samsung CalmRISC16 evaluation platform consists of two boards connected by a ribbon cable. One board contains the CPU core and memory. The other board is called the MDSChip board and provides the host interface. The calmRISC16 is a harvard architecture with separate 22-bit program and data addresses. The instruction set provides no instruction for writing to program memory. The MDSChip board firmware (called CalmBreaker) provides a pseudo register interface so that code running on the core has access to a serial channel and a mechanism to write to program memory. The serial channel is fixed at 57600-8-N-1 by the firmware. The CalmBreaker firmware also provides a serial protocol which allows a host to download a program and to start or stop the core board. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running via the MDSChip board. redboot_ROM.ecm The CalmRISC16 core is controlled through the MDSChip board. There is no non-volatile storage available for RedBoot, so RedBoot must be downloaded to the board on every power cycle. A small utility program is used to download S-record files to the eval board. Sources and build instructions for this utility are located in the RedBoot sources in: packages/hal/calmrisc16/ceb/current/support To download the RedBoot image, first press the reset button on the MDSChip board. The green 'Run' LED on the core board should go off. Now, use the utility to download the RedBoot image with: $ calmbreaker -p /dev/term/b --reset --srec-code -f redboot.elf Note that the '-p /dev/term/b' specifies the serial port to use and will vary from system to system. The download will take about two minutes. After it finishes, start RedBoot with: $ calmbreaker -p /dev/term/b --run The 'Run' LED on the core board should be on. Connecting to the MDSboard with a terminal and typing enter should result in RedBoot reprinting the command prompt. None. The MDSChip board uses a relatively slow microcontroller to provide the pseudo-register interface to the core board. This pseudo-register interface provides access to the serial channel and write access to program memory. Those interfaces are slow and the serial channel is easily overrun by a fast host. For this reason, GDB must be told to limit the size of code download packets to avoid serial overrun. This is done with the following GDB command: (gdb) set download-write-size 25 These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=calm16_ceb export ARCH_DIR=calmrisc16 export PLATFORM_DIR=ceb The names of configuration files are listed above with the description of the associated modes. Samsung CalmRISC32 Core EVBinstalling and testinginstalling and testing Samsung CalmRISC32 Core EVB The Samsung CalmRISC32 evaluation platform consists of two boards connected by a ribbon cable. One board contains the CPU core and memory. The other board is called the MDSChip board and provides the host interface. The calmRISC32 is a harvard architecture with separate 32-bit program and data addresses. The instruction set provides no instruction for writing to program memory. The MDSChip board firmware (called CalmBreaker) provides a pseudo register interface so that code running on the core has access to a serial channel and a mechanism to write to program memory. The serial channel is fixed at 57600-8-N-1 by the firmware. The CalmBreaker firmware also provides a serial protocol which allows a host to download a program and to start or stop the core board. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running via the MDSChip board. redboot_ROM.ecm The calmRISC32 core is controlled through the MDSChip board. There is no non-volatile storage available for RedBoot, so RedBoot must be downloaded to the board on every power cycle. A small utility program is used to download S-record files to the eval board. Sources and build instructions for this utility are located in the RedBoot sources in: packages/hal/calmrisc32/ceb/current/support To download the RedBoot image, first press the reset button on the MDSChip board. The green 'Run' LED on the core board should go off. Now, use the utility to download the RedBoot image with: $ calmbreaker -p /dev/term/b --reset --srec-code -f redboot.elf Note that the '-p /dev/term/b' specifies the serial port to use and will vary from system to syetm. The download will take about two minutes. After it finishes, start RedBoot with: $ calmbreaker -p /dev/term/b --run The 'Run' LED on the core board should be on. Connecting to the MDSboard with a terminal and typing enter should result in RedBoot reprinting the command prompt. None. The MDSChip board uses a relatively slow microcontroller to provide the pseudo-register interface to the core board. This pseudo-register interface provides access to the serial channel and write access to program memory. Those interfaces are slow and the serial channel is easily overrun by a fast host. For this reason, GDB must be told to limit the size of code download packets to avoid serial overrun. This is done with the following GDB command: (gdb) set download-write-size 25 These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=calm32_ceb export ARCH_DIR=calmrisc32 export PLATFORM_DIR=ceb The names of configuration files are listed above with the description of the associated modes. Fujitsu FR-V 400 installing and testing installing and testing Fujitsu FR-V 400 RedBoot supports both serial ports, which are available via the stacked serial connectors on the mother board. The topmost port is the default and is considered to be port 0 by RedBoot. The bottommost port is serial port 1. The default serial port settings are 38400,8,N,1. FLASH management is also supported, but only for the FLASH device in IC7. This arrangement allows for IC8 to retain either the original Fujitsu board firmware, or some application specific contents. The following RedBoot configurations are supported: Configuration Mode Description File ROMRAM [ROMRAM] RedBoot running from RAM, but contained in the board's flash boot sector. redboot_ROMRAM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm RedBoot can be installed by directly programming the FLASH device in IC7 or by using the Fujitsu provided software to download and install a version into the FLASH device. Complete instructions are provided separately. None. The memory map of this platform is fixed by the hardware (cannot be changed by software). The only attributes which can be modified are control over cacheability, as noted below. Address Cache? Resource 00000000-03EFFFFF Yes SDRAM (via plugin DIMM) 03F00000-03FFFFFF No SDRAM (used for PCI window) 10000000-1FFFFFFF No MB86943 PCI bridge 20000000-201FFFFF No SRAM 21000000-23FFFFFF No Motherboard resources 24000000-25FFFFFF No PCI I/O space 26000000-2FFFFFFF No PCI Memory space 30000000-FDFFFFFF ?? Unused FE000000-FEFFFFFF No I/O devices FF000000-FF1FFFFF No IC7 - RedBoot FLASH FF200000-FF3FFFFF No IC8 - unused FLASH FF400000-FFFFFFFF No Misc other I/O The only configuration currently suppored requires a 64MB SDRAM DIMM to be present on the CPU card. No other memory configuration is supported at this time. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=frv400 export ARCH_DIR=frv export PLATFORM_DIR=frv400 The names of configuration files are listed above with the description of the associated modes. Fujitsu FR-V MB93091-CBxx Design Kit installing and testing installing and testing Fujitsu FR-V MB93091-CBxx Design Kit RedBoot supports both serial ports, which are available via the stacked serial connectors on the mother board in the case of the FR400 CPU board, and via serial connectors present on the other supported CPU boards themselves. The topmost port is the default and is considered to be port 0 by RedBoot. The bottommost port is serial port 1. The default serial port settings are 115200,8,N,1. The serial port supports baud rates up to 460800, which can be set using the baud command as described in . FLASH management is also supported, but only for the FLASH device in IC7. This arrangement allows for IC8 to retain either the original Fujitsu board firmware, or some application specific contents. Two basic RedBoot configurations are supported: Configuration Mode Description File ROMRAM [ROMRAM] RedBoot running from RAM, but contained in the board's flash boot sector. redboot_ROMRAM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm Since the normal RedBoot configuration does not use the FLASH ROM except during startup, it is unnecessary to load a RAM-based RedBoot before reprogramming the FLASH. RedBoot can be installed by directly programming the FLASH device in IC7 or by using the Fujitsu provided software to download and install a version into the FLASH device. Complete instructions are provided separately. The exec command as described in is supported by RedBoot on this target, for executing Linux kernels. Only the command line and timeout options are relevant to this platform. The memory map of this platform is fixed by the hardware (cannot be changed by software). The only attributes which can be modified are control over cacheability, as noted below. Address Cache? Resource 00000000-03EFFFFF Yes SDRAM (via plugin DIMM) 03F00000-03FFFFFF No SDRAM (used for PCI window) 10000000-1FFFFFFF No MB86943 PCI bridge 20000000-201FFFFF No SRAM 21000000-23FFFFFF No Motherboard resources 24000000-25FFFFFF No PCI I/O space 26000000-2FFFFFFF No PCI Memory space 30000000-FDFFFFFF ?? Unused FE000000-FEFFFFFF No I/O devices FF000000-FF1FFFFF No IC7 - RedBoot FLASH FF200000-FF3FFFFF No IC8 - unused FLASH FF400000-FFFFFFFF No Misc other I/O The only configuration currently suppored requires a 64MiB SDRAM DIMM to be present on the CPU card. No other memory configuration is supported at this time. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=mb93091 export ARCH_DIR=frv export PLATFORM_DIR=mb93091 The names of configuration files are listed above with the description of the associated modes. The RedBoot image occupies flash addresses 0xFF000000 - 0xFF03FFFF. To execute it copies itself out of there to RAM at 0x03E00000. RedBoot reserves memory from 0x00000000 to 0x0001FFFF for its own use. User programs can use memory from 0x00020000 to 0x03DFFFFF. RAM based RedBoot configurations are designed to run from RAM at 0x00020000. Fujitsu FR-V Portable Demonstration Kit installing and testing installing and testing Fujitsu FR-V Portable Demonstration Kit RedBoot supports the serial port which is available via a special cable connected to the CON_UART connector on the board. The default serial port settings are 115200,8,N,1. The serial port supports baud rates up to 460800, which can be set using the baud command as described in . FLASH management is also supported. Two basic RedBoot configurations are supported: Configuration Mode Description File ROMRAM [ROMRAM] RedBoot running from RAM, but contained in the board's flash boot sector. redboot_ROMRAM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm Since the normal RedBoot configuration does not use the FLASH ROM except during startup, it is unnecessary to load a RAM-based RedBoot before reprogramming the FLASH. The Portable Demonstration Kit should have been shipped with an existing version of RedBoot, which can be upgraded to the current version using the instructions below. The exec command as described in is supported by RedBoot on this target, for executing Linux kernels. Only the command line and timeout options are relevant to this platform. The memory map of this platform is fixed by the hardware (cannot be changed by software). The only attributes which can be modified are control over cacheability, as noted below. Address Cache? Resource 00000000-03EFFFFF Yes SDRAM (via plugin DIMM) 03F00000-03FFFFFF No Unused (SDRAM) 10000000-1FFFFFFF No AX88796 Ethernet 20000000-2FFFFFFF No System FPGA 30000000-3FFFFFFF No MB93493 companion chip (unused) 40000000-FCFFFFFF ?? Unused FD000000-FDFFFFFF ?? FLASH (ROM3,ROM4) (unused) FE000000-FEFFFFFF No Miscellaneous on-chip I/O FF000000-FFFFFFFF No RedBoot FLASH (16MiB) The only configuration currently suppored requires a 64MiB SDRAM DIMM to be present on the CPU card. No other memory configuration is supported at this time. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=mb93093 export ARCH_DIR=frv export PLATFORM_DIR=mb93093 The RedBoot image occupies flash addresses 0xFF000000 - 0xFF03FFFF. To execute it copies itself out of there to RAM at 0x03E00000. RedBoot reserves memory from 0x00000000 to 0x0001FFFF for its own use. User programs can use memory from 0x00020000 to 0x03DFFFFF. RAM based RedBoot configurations are designed to run from RAM at 0x00020000. x86 Based PCinstalling and testinginstalling and testing x86 Based PCRedBoot supports two serial ports and an Intel i82559 based ethernet card (for example an Intel EtherExpress Pro 10/100) for communication and downloads. The default serial port settings are 38400,8,N,1. The following RedBoot configurations are supported: Configuration Mode Description File Floppy [Floppy] RedBoot running from a boot floppy disk installed in the A: drive of the PC. redboot_ROM.ecm RedBoot takes the form of a self-booting image that must be written onto a formatted floppy disk. The process will erase any file system or data that already exists on that disk, so proceed with caution. For Red Hat Linux users, this can be done by: $ dd conv=sync if=install/bin/redboot.bin of=/dev/fd0H1440 For NT Cygwin users, this can be done by first ensuring that the raw floppy device is mounted as /dev/fd0. To check if this is the case, type the command mount at the Cygwin bash prompt. If the floppy drive is already mounted, it will be listed as something similar to the following line: \\.\a: /dev/fd0 user binmode If this line is not listed, then mount the floppy drive using the command: $ mount -f -b //./a: /dev/fd0 To actually install the boot image on the floppy, use the command: $ dd conv=sync if=install/bin/redboot.bin of=/dev/fd0 Insert this floppy in the A: drive of the PC to be used as a target and ensure that the BIOS is configured to boot from A: by default. On reset, the PC will boot from the floppy and be ready to be debugged via either serial line, or via the ethernet interface if it is installed. Unreliable floppy media may cause the write to silently fail. This can be determined if the RedBoot image does not correctly boot. In such cases, the floppy should be (unconditionally) reformatted using the fdformat command on Linux, or format a: /u on DOS/Windows. PC RedBoot does not support any FLASH commands. None. All selectors are initialized to map the entire 32-bit address space in the familiar protected mode flat model. Page translation is not used. RAM up to 640K is mapped to 0x0 to 0xa0000. RAM above 640K is mapped from address 0x100000 upwards. Space is reserved between 0xa0000 and 0x100000 for option ROMs and the BIOS. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=pc export ARCH_DIR=i386 export PLATFORM_DIR=pc The names of configuration files are listed above with the description of the associated modes. MIPS Atlas Board with CoreLV 4KC and CoreLV 5KC installing and testing installing and testingMIPS Atlas Board with CoreLV 4KC and CoreLV 5KCRedBoot supports the DgbSer serial port and the built in ethernet port for communication and downloads. The default serial port settings are 115200,8,N,1. RedBoot runs from and supports flash management for the system flash region. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm RedBoot is installed using the code download facility built into the Atlas board. See the Atlas User manual for details, and also the Atlas download format in . Here are quick start instructions for downloading the prebuilt RedBoot image. Locate the prebuilt files in the bin directory: deleteall.dl and redboot.dl. Make sure switch S1-1 is OFF and switch S5-1 is ON. Reset the board and verify that the LED display reads Flash DL. Make sure your parallel port is connected to the 1284 port Of the Atlas board. Send the deleteall.dl file to the parallel port to erase previous images: $ cat deleteall.dl >/dev/lp0 When this is complete, the LED display should read Deleted. Send the ROM mode RedBoot image to the board: $ cat redboot.dl >/dev/lp0 When this is complete, the LED display should show the last address programmed. This will be something like: 1fc17000 . Change switch S5-1 to OFF and reset the board. The LED display should read RedBoot. Run the RedBoot fis init and fconfig commands to initialize the flash. See , and for details. In order to download RedBoot to the Atlas board, it must be converted to the Atlas download format. There are different ways of doing this depending on which version of the developer's kit is shipped with the board. The Atlas Developer's Kit CD contains an srec2flash utility. The source code for this utility is part of the yamon/yamon-src-01.01.tar.gz tarball on the Dev Kit CD. The path in the expanded tarball is yamon/bin/tools. To use srec2flash to convert the S-record file: $ srec2flash -EL -S29 redboot.srec >redboot.dl The Atlas/Malta Developer's Kit CD contains an srecconv.pl utility which requires Perl. This utilty is part of the yamon/yamon-src-02.00.tar.gz tarball on the Dev Kit CD. The path in the expanded tarball is yamon/bin/tools. To use srecconv to convert the S-record file: $ cp redboot_ROM.srec redboot_ROM.rec $ srecconv.pl -ES L -A 29 redboot_ROM The resulting file is named redboot_ROM.fl. The ethernet MAC address is stored in flash manually using the fconfig command. You can use the YAMON setenv ethaddr command to print out the board ethernet address. Typically, it is: 00:0d:a0:00:xx:xx where xx.xx is the hex representation of the board serial number. The exec command which allows the loading and execution of Linux kernels, is supported for this architecture (see ). The exec parameters used for MIPS boards are: -b <addr> Location to store command line and environment passed to kernel -w <time> Wait time in seconds before starting kernel -c "params" Parameters passed to kernel <addr> Kernel entry point, defaulting to the entry point of the last image loaded Linux kernels on MIPS platforms expect the entry point to be called with arguments in the registers equivalent to a C call with prototype: void Linux(int argc, char **argv, char **envp); RedBoot will place the appropriate data at the offset specified by the -b parameter, or by default at address 0x80080000, and will set the arguments accordingly when calling into the kernel. The default entry point, if no image with explicit entry point has been loaded and none is specified, is 0x80000750. RedBoot uses an interrupt vector table which is located at address 0x80000400. Entries in this table are pointers to functions with this protoype: int irq_handler( unsigned vector, unsigned data )On an atlas board, the vector argument is one of 25 interrupts defined in hal/mips/atlas/VERSION/include/plf_intr.h: #define CYGNUM_HAL_INTERRUPT_SER 0 #define CYGNUM_HAL_INTERRUPT_TIM0 1 #define CYGNUM_HAL_INTERRUPT_2 2 #define CYGNUM_HAL_INTERRUPT_3 3 #define CYGNUM_HAL_INTERRUPT_RTC 4 #define CYGNUM_HAL_INTERRUPT_COREHI 5 #define CYGNUM_HAL_INTERRUPT_CORELO 6 #define CYGNUM_HAL_INTERRUPT_7 7 #define CYGNUM_HAL_INTERRUPT_PCIA 8 #define CYGNUM_HAL_INTERRUPT_PCIB 9 #define CYGNUM_HAL_INTERRUPT_PCIC 10 #define CYGNUM_HAL_INTERRUPT_PCID 11 #define CYGNUM_HAL_INTERRUPT_ENUM 12 #define CYGNUM_HAL_INTERRUPT_DEG 13 #define CYGNUM_HAL_INTERRUPT_ATXFAIL 14 #define CYGNUM_HAL_INTERRUPT_INTA 15 #define CYGNUM_HAL_INTERRUPT_INTB 16 #define CYGNUM_HAL_INTERRUPT_INTC 17 #define CYGNUM_HAL_INTERRUPT_INTD 18 #define CYGNUM_HAL_INTERRUPT_SERR 19 #define CYGNUM_HAL_INTERRUPT_HW1 20 #define CYGNUM_HAL_INTERRUPT_HW2 21 #define CYGNUM_HAL_INTERRUPT_HW3 22 #define CYGNUM_HAL_INTERRUPT_HW4 23 #define CYGNUM_HAL_INTERRUPT_HW5 24The data passed to the ISR is pulled from a data table (hal_interrupt_data ) which immediately follows the interrupt vector table. With 25 interrupts, the data table starts at address 0x80000464 on atlas. An application may create a normal C function with the above prototype to be an ISR. Just poke its address into the table at the correct index and enable the interrupt at its source. The return value of the ISR is ignored by RedBoot. Memory Maps RedBoot sets up the following memory map on the Atlas board. Physical Address Range Description ----------------------- ------------- 0x00000000 - 0x07ffffff SDRAM 0x08000000 - 0x17ffffff PCI Memory Space 0x18000000 - 0x1bdfffff PCI I/O Space 0x1be00000 - 0x1bffffff System Controller 0x1c000000 - 0x1dffffff System flash 0x1e000000 - 0x1e3fffff Monitor flash 0x1f000000 - 0x1fbfffff FPGA These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=atlas_mips32_4kc export TARGET=atlas_mips64_5kc export ARCH_DIR=mips export PLATFORM_DIR=atlas Use one of the TARGET settings only. The names of configuration files are listed above with the description of the associated modes. MIPS Malta Board with CoreLV 4KC and CoreLV 5KC installing and testing installing and testingMIPS Malta Board with CoreLV 4KC and CoreLV 5KCRedBoot supports both front facing serial ports and the built in ethernet port for communication and downloads. The default serial port settings are 38400,8,N,1. RedBoot runs from and supports flash management for the system flash region. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm RedBoot is installed using the code download facility built into the Malta board. See the Malta User manual for details, and also the Malta download format in . Here are quick start instructions for downloading the prebuilt RedBoot image. Locate the prebuilt files in the bin directory: deleteall.fl and redboot_ROM.fl. Make sure switch S5-1 is ON. Reset the board and verify that the LED display reads Flash DL. Make sure your parallel port is connected to the 1284 port Of the Atlas board. Send the deleteall.fl file to the parallel port to erase previous images: $ cat deleteall.fl >/dev/lp0 When this is complete, the LED display should read Deleted. Send the RedBoot image to the board: $ cat redboot_ROM.fl >/dev/lp0 When this is complete, the LED display should show the last address programmed. This will be something like: 1fc17000. Change switch S5-1 to OFF and reset the board. The LED display should read RedBoot. Run the RedBoot fis init and fconfig commands to initialize the flash. See and for details. In order to download RedBoot to the Malta board, it must be converted to the Malta download format. The Atlas/Malta Developer's Kit CD contains an srecconv.pl utility which requires Perl. This utility is part of the yamon/yamon-src-02.00.tar.gz tarball on the Dev Kit CD. The path in the expanded tarball is yamon/bin/tools. To use srecconv to convert the S-record file: $ cp redboot_ROM.srec redboot_ROM.rec $ srecconv.pl -ES L -A 29 redboot_ROM The resulting file is named redboot_ROM.fl. The exec command which allows the loading and execution of Linux kernels, is supported for this architecture (see ). The exec parameters used for MIPS boards are: -b <addr> Location to store command line and environment passed to kernel -w <time> Wait time in seconds before starting kernel -c "params" Parameters passed to kernel <addr> Kernel entry point, defaulting to the entry point of the last image loaded Linux kernels on MIPS platforms expect the entry point to be called with arguments in the registers equivalent to a C call with prototype: void Linux(int argc, char **argv, char **envp); RedBoot will place the appropriate data at the offset specified by the -b parameter, or by default at address 0x80080000, and will set the arguments accordingly when calling into the kernel. The default entry point, if no image with explicit entry point has been loaded and none is specified, is 0x80000750. RedBoot uses an interrupt vector table which is located at address 0x80000200. Entries in this table are pointers to functions with this protoype: int irq_handler( unsigned vector, unsigned data )On the malta board, the vector argument is one of 22 interrupts defined in hal/mips/malta/VERSION/include/plf_intr.h: #define CYGNUM_HAL_INTERRUPT_SOUTH_BRIDGE_INTR 0 #define CYGNUM_HAL_INTERRUPT_SOUTH_BRIDGE_SMI 1 #define CYGNUM_HAL_INTERRUPT_CBUS_UART 2 #define CYGNUM_HAL_INTERRUPT_COREHI 3 #define CYGNUM_HAL_INTERRUPT_CORELO 4 #define CYGNUM_HAL_INTERRUPT_COMPARE 5 #define CYGNUM_HAL_INTERRUPT_TIMER 6 #define CYGNUM_HAL_INTERRUPT_KEYBOARD 7 #define CYGNUM_HAL_INTERRUPT_CASCADE 8 #define CYGNUM_HAL_INTERRUPT_TTY1 9 #define CYGNUM_HAL_INTERRUPT_TTY0 10 #define CYGNUM_HAL_INTERRUPT_11 11 #define CYGNUM_HAL_INTERRUPT_FLOPPY 12 #define CYGNUM_HAL_INTERRUPT_PARALLEL 13 #define CYGNUM_HAL_INTERRUPT_REAL_TIME_CLOCK 14 #define CYGNUM_HAL_INTERRUPT_I2C 15 #define CYGNUM_HAL_INTERRUPT_PCI_AB 16 #define CYGNUM_HAL_INTERRUPT_PCI_CD 17 #define CYGNUM_HAL_INTERRUPT_MOUSE 18 #define CYGNUM_HAL_INTERRUPT_19 19 #define CYGNUM_HAL_INTERRUPT_IDE_PRIMARY 20 #define CYGNUM_HAL_INTERRUPT_IDE_SECONDARY 21The data passed to the ISR is pulled from a data table (hal_interrupt_data ) which immediately follows the interrupt vector table. With 22 interrupts, the data table starts at address 0x80000258. An application may create a normal C function with the above prototype to be an ISR. Just poke its address into the table at the correct index and enable the interrupt at its source. The return value of the ISR is ignored by RedBoot. Memory Maps RedBoot sets up the following memory map on the Malta board. The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B). Physical Address Range C B Description ----------------------- - - ----------- 0x80000000 - 0x81ffffff Y Y SDRAM 0x9e000000 - 0x9e3fffff Y N System flash (cached) 0x9fc00000 - 0x9fffffff Y N System flash (mirrored) 0xa8000000 - 0xb7ffffff N N PCI Memory Space 0xb4000000 - 0xb40fffff N N Galileo System Controller 0xb8000000 - 0xb80fffff N N Southbridge / ISA 0xb8100000 - 0xbbdfffff N N PCI I/O Space 0xbe000000 - 0xbe3fffff N N System flash (noncached) 0xbf000000 - 0xbfffffff N N Board logic FPGA These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=malta_mips32_4kc export ARCH_DIR=mips export PLATFORM_DIR=malta The names of configuration files are listed above with the description of the associated modes. PMC-Sierra MIPS RM7000 Ocelotinstalling and testinginstalling and testing PMC-Sierra MIPS RM7000 OcelotRedBoot uses the front facing serial port. The default serial port settings are 38400,8,N,1. RedBoot also supports ethernet. Management of onboard flash is also supported. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm The exec command which allows the loading and execution of Linux kernels, is supported for this architecture (see ). The exec parameters used for MIPS boards are: -b <addr> Location to store command line and environment passed to kernel -w <time> Wait time in seconds before starting kernel -c "params" Parameters passed to kernel <addr> Kernel entry point, defaulting to the entry point of the last image loaded Linux kernels on MIPS platforms expect the entry point to be called with arguments in the registers equivalent to a C call with prototype: void Linux(int argc, char **argv, char **envp); RedBoot will place the appropriate data at the offset specified by the -b parameter, or by default at address 0x80080000, and will set the arguments accordingly when calling into the kernel. The default entry point, if no image with explicit entry point has been loaded and none is specified, is 0x80000750. RedBoot sets up the following memory map on the Ocelot board. Note that these addresses are accessed through kseg0/1 and thus translate to the actual address range 0x80000000-0xbfffffff, depending on the need for caching/non-caching access to the bus. The virtual memory maps in this section use a C and B column to indicate whether or not the region is cached (C) or buffered (B). Physical Address Range Description ----------------------- ----------- 0x00000000 - 0x0fffffff SDRAM 0x10000000 - 0x10ffffff PCI I/O space 0x12000000 - 0x13ffffff PCI Memory space 0x14000000 - 0x1400ffff Galileo system controller 0x1c000000 - 0x1c0000ff PLD (board logic) 0x1fc00000 - 0x1fc7ffff flash These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=ocelot export ARCH_DIR=mips export PLATFORM_DIR=rm7000/ocelot The names of configuration files are listed above with the description of the associated modes. NEC DDB-VRC4375 installing and testing installing and testingNEC DDB-VRC4375 RedBoot supports only serial port 1, which is connected to the upper of the stacked serial connectors on the board. The default serial port settings are 38400,8,N,1. FLASH management is also supported. The following RedBoot configurations are supported: Configuration Mode Description File ROMRAM [ROMRAM] RedBoot running from RAM, but contained in the board's flash boot sector. redboot_ROMRAM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm A device programmer should be used to program a socketed FLASH part (AMD 29F040). The board as delivered is configured for a 512K EPROM. To install a FLASH ROM, Jumpers J30, J31 and J36 need to be changed as described in the board's User Manual. None. RedBoot sets up the memory map primarily as described in the board's User Manual. There are some minor differences, noted in the following table: Physical Virtual Resource Addresses Addresses 00000000-01FFFFFF 80000000-81FFFFFF Base SDRAM (cached) 00000000-01FFFFFF A0000000-A1FFFFFF Base SDRAM (uncached) 0C000000-0C0BFFFF AC000000-AC0B0000 PCI IO space 0F000000-0F0001FF AF000000-AF0001FF VRC4375 Registers 1C000000-1C0FFFFF BC000000-BC0FFFFF VRC4372 Registers 1C100000-1DFFFFFF BC100000-BDFFFFFF PCI Memory space 1FC00000-1FC7FFFF BFC00000-BFC7FFFF FLASH ROM 80000000-8000000D C0000000-C000000D RTC 8000000E-80007FFF C000000E-C0007FFF NVRAM 81000000-81FFFFFF C1000000-C1FFFFFF Z85C30 DUART 82000000-82FFFFFF C2000000-C2FFFFFF Z8536 Timer 83000000-83FFFFFF C3000000-C3FFFFFF 8255 Parallel port 87000000-87FFFFFF C7000000-C7FFFFFF Seven segment display By default the VRC4375 SIMM control registers are not programmed since the values used must depend on the SIMMs installed. If SIMMs are to be used, correct values must be placed in these registers before accessing the SIMM address range. The allocation of address ranges to devices in the PCI IO and memory spaces is handled by the eCos PCI support library. They do not correspond to those described in the board User Manual. The MMU has been set up to relocate the VRC4372 supported devices mapped at physical addresses 0x8xxxxxxx to virtual addresses 0xCxxxxxxx. The ethernet driver is in two parts: A generic ether driver for the Intel i21143 device is located in devs/eth/intel/i21143. Its package name is CYGPKG_DEVS_ETH_INTEL_I21143. The platform-specific ether driver is devs/eth/mips/vrc4375. Its package is CYGPKG_DEVS_ETH_MIPS_VRC4375. This tells the generic driver the address in IO memory of the chip, for example, and other configuration details. The ESA (MAC address) is by default collected from on-board serial EEPROM, unless configured statically within this package. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=vrc4373 export ARCH_DIR=mips export PLATFORM_DIR=vrc4373 The names of configuration files are listed above with the description of the associated modes. Analogue & Micro PowerPC 860Tinstalling and testinginstalling and testing Analogue & Micro PowerPC 860TRedBoot uses the SMC1 serial port. The default serial port settings are 38400,8,N,1. Ethernet is also supported using the RJ-45 connector. Management of onboard flash is also supported. The following RedBoot configurations are supported: Configuration Mode Description File ROMRAM [ROMRAM] RedBoot running from RAM, but contained in the board's flash boot sector. redboot_ROMRAM.ecm RedBoot must be installed at the A & M factory. None. Memory Maps RedBoot sets up the following memory map on the MBX board. Physical Address Range Description ----------------------- ----------- 0x00000000 - 0x007fffff DRAM 0xfe000000 - 0xfe0fffff flash (AMD29LV8008B) 0xff000000 - 0xff0fffff MPC registers These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=viper export ARCH_DIR=powerpc export PLATFORM_DIR=viper The names of configuration files are listed above with the description of the associated modes. Motorola PowerPC MBXinstalling and testinginstalling and testing Motorola PowerPC MBXRedBoot uses the SMC1/COM1 serial port. The default serial port settings are 38400,8,N,1. Ethernet is also supported using the 10-base T connector. Management of onboard flash is also supported. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm Device programmer is used to program the XU1 socketed flash part (AM29F040B) with the ROM mode image of RedBoot. Use the on-board EPPC-Bug monitor to update RedBoot. This assumes that you have EPPC-Bug in the on-board flash. This can be determined by setting up the board according to the following instructions and powering up the board. The EPPC-Bug prompt should appear on the SMC1 connector at 9600 baud, 8N1. Set jumper 3 to 2-3 [allow XU1 flash to be programmed] Set jumper 4 to 2-3 [boot EPPC-Bug] If it is available, program the flash by following these steps: Prepare EPPC-Bug for download: EPPC-Bug>lo 0 At this point the monitor is ready for input. It will not return the prompt until the file has been downloaded. Use the terminal emulator's ASCII download feature (or a simple clipboard copy/paste operation) to download the redboot.ppcbug file. Note that on Linux, Minicom's ASCII download feature seems to be broken. A workaround is to load the file into emacs (or another editor) and copy the full contents to the clipboard. Then press the mouse paste-button (usually the middle one) over the Minicom window. Program the flash with the downloaded data: EPPC-Bug>pflash 40000 60000 fc000000 Switch off the power, and change jumper 4 to 1-2. Turn on the power again. The board should now boot using the newly programmed RedBoot. None. Memory Maps RedBoot sets up the following memory map on the MBX board. Physical Address Range Description ----------------------- ----------- 0x00000000 - 0x003fffff DRAM 0xfa100000 - 0xfa100003 LEDs 0xfe000000 - 0xfe07ffff flash (AMD29F040B) 0xff000000 - 0xff0fffff MPC registers These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=mbx export ARCH_DIR=powerpc export PLATFORM_DIR=mbx The names of configuration files are listed above with the description of the associated modes. Hitachi SH EDK7708installing and testinginstalling and testing Hitachi SH EDK7708RedBoot uses the serial port. The default serial port settings are 38400,8,N,1. Management of onboard flash is also supported. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm Program the ROM RedBoot image into flash using an eprom programmer. RedBoot sets up the following memory map on the EDK7708 board. Physical Address Range Description ----------------------- ----------- 0x80000000 - 0x8001ffff Flash (AT29LV1024) 0x88000000 - 0x881fffff DRAM 0xa4000000 - 0xa40000ff LED ON 0xb8000000 - 0xb80000ff LED ON These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=edk7708 export ARCH_DIR=sh export PLATFORM_DIR=edk7708 The names of configuration files are listed above with the description of the associated modes. Hitachi SH SE7709installing and testinginstalling and testing Hitachi SH SE7709This description covers the MS7709SE01 variant. See for instructions for the MS7729SE01 and MS7709SSE0101 variants. RedBoot uses the COM1 and COM2 serial ports. The default serial port settings are 38400,8,N,1. Ethernet is also supported using the 10-base T connector. Management of onboard flash is also supported. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm The Solution Engine ships with the Hitachi boot monitor in EPROM which allows for initial programming of RedBoot: Set switch SW4-1 to ON [boot from EPROM] Connect a serial cable to CN1 (SCI) and power up the board. After the boot monitor banner, invoke the flash download/program command:Ready >fl The monitor should now ask for input: Flash ROM data copy to RAM Please Send A S-format RecordAt this point copy the RedBoot ROM SREC file to the serial port: $ cat redboot_SE7709RP_ROM.eprom.srec > /dev/ttyS0 Eventually you should see something likeStart Addrs = A1000000 End Addrs = A1xxxxxx Transfer complete from the monitor. Set switch SW4-1 to OFF [boot from flash] and reboot the board. You should now see the RedBoot banner. The exec command which allows the loading and execution of Linux kernels is supported for this board (see ). The exec parameters used for the SE77x9 are: -b <addr> Parameter block address. This is normally the first page of the kernel image and defaults to 0x8c101000 -i <addr> Start address of initrd image -j <size> Size of initrd image -c "args" Kernel arguments string -m <flags> Mount rdonly flags. If set to a non-zero value the root partition will be mounted read-only. -f <flags> RAM disk flags. Should normally be 0x4000 -r <device number> Root device specification. /dev/ram is 0x0101 -l <type> Loader type Finally the kernel entry address can be specified as an optional argument. The default is 0x8c102000 For the the SE77x9, Linux by default expects to be loaded at 0x8c001000 which conflicts with the data space used by RedBoot. To work around this, either change the CONFIG_MEMORY_START kernel option to a higher address, or use the compressed kernel image and load it at a higher address. For example, setting CONFIG_MEMORY_START to 0x8c100000, the kernel expects to be loaded at address 0x8c101000 with the entry point at 0x8c102000. RedBoot sets up the following memory map on the SE77x9 board. Physical Address Range Description ----------------------- ----------- 0x80000000 - 0x803fffff Flash (MBM29LV160) 0x81000000 - 0x813fffff EPROM (M27C800) 0x8c000000 - 0x8dffffff DRAM 0xb0000000 - 0xb03fffff Ethernet (DP83902A) 0xb0800000 - 0xb08fffff 16C552A 0xb1000000 - 0xb100ffff Switches 0xb1800000 - 0xb18fffff LEDs 0xb8000000 - 0xbbffffff PCMCIA (MaruBun) The ethernet driver uses a hardwired ESA which can, at present, only be changed in CDL. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=se77x9 export ARCH_DIR=sh export PLATFORM_DIR=se77x9 The names of configuration files are listed above with the description of the associated modes. Hitachi SH HS7729PCIinstalling and testinginstalling and testing Hitachi SH HS7729PCIRedBoot uses the COM1 and COM2 serial ports (and the debug port on the motherboard). The default serial port settings are 38400,8,N,1. Ethernet is also supported using a D-Link DFE-530TX PCI plugin card. Management of onboard flash is also supported. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm A ROM mode RedBoot image must be programmed into the two EPROMs. Two files with a split version of the ROM mode image is provided: it is also possible to recreate these from the redboot.bin file, but requires the split_word.c program in hal/sh/hs7729pci/VERSION/misc to be built and executed with the redboot.bin filename as sole argument. After doing this it is advised that another ROM mode image of RedBoot is programmed into the on-board flash, and that copy be used for booting the board. This allows for software programmed updates of RedBoot instead of having to reprogram the EPROMs. Program the EPROMs with RedBoot. The .lo image should go in socket M1 and the .hi image in socket M2. Set switch SW1-6 to ON [boot from EPROM] Follow the instructions under Flash management for updating the flash copy of RedBoot, but force the flash destination address with -f 0x80400000 due to setting of the SW1-6 switch. Set switch SW1-6 to OFF [boot from flash] and reboot the board. You should now see the RedBoot banner. At this time you may want to issue the command fis init to initialize the flash table with the correct addresses. The exec command which allows the loading and execution of Linux kernels is supported for this board (see ). The exec parameters used for the HS7729PCI are: -b <addr> Parameter block address. This is normally the first page of the kernel image and defaults to 0x8c101000 -i <addr> Start address of initrd image -j <size> Size of initrd image -c "args" Kernel arguments string -m <flags> Mount rdonly flags. If set to a non-zero value the root partition will be mounted read-only. -f <flags> RAM disk flags. Should normally be 0x4000 -r <device number> Root device specification. /dev/ram is 0x0101 -l <type> Loader type Finally the kernel entry address can be specified as an optional argument. The default is 0x8c102000 On the HS7729PCI, Linux expects to be loaded at address 0x8c101000 with the entry point at 0x8c102000. This is configurable in the kernel using the CONFIG_MEMORY_START option. RedBoot sets up the following memory map on the HS7729PCI board. Physical Address Range Description ----------------------- ----------- 0x80000000 - 0x803fffff Flash (MBM29LV160) 0x80400000 - 0x807fffff EPROM (M27C800) 0x82000000 - 0x82ffffff SRAM 0x89000000 - 0x89ffffff SRAM 0x8c000000 - 0x8fffffff SDRAM 0xa8000000 - 0xa800ffff SuperIO (FDC37C935A) 0xa8400000 - 0xa87fffff USB function (ML60851C) 0xa8800000 - 0xa8bfffff USB host (SL11HT) 0xa8c00000 - 0xa8c3ffff Switches 0xa8c40000 - 0xa8c7ffff LEDs 0xa8c80000 - 0xa8cfffff Interrupt controller 0xb0000000 - 0xb3ffffff PCI (SD0001) 0xb8000000 - 0xbbffffff PCMCIA (MaruBun) These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=hs7729pci export ARCH_DIR=sh export PLATFORM_DIR=hs7729pci The names of configuration files are listed above with the description of the associated modes. Hitachi SH SE77X9installing and testinginstalling and testing Hitachi SH SE77X9This description covers the MS7729SE01 and MS7709SSE0101 variants. See for instructions for the MS7709SE01 variant. RedBoot uses the COM1 and COM2 serial ports. The default serial port settings are 38400,8,N,1. Ethernet is also supported using the 10-base T connector. Management of onboard flash is also supported. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm The Solution Engine ships with the Hitachi boot monitor in EPROM which allows for initial programming of RedBoot: Set switches SW4-3 and SW4-4 to ON [boot from EPROM] Connect a serial cable to COM2 and power up the board. After the boot monitor banner, invoke the flash download/program command:Ready >fl The monitor should now ask for input: Flash ROM data copy to RAM Please Send A S-format RecordAt this point copy the RedBoot ROM SREC file to the serial port: $ cat redboot_ROM.eprom.srec > /dev/ttyS0 Eventually you should see something likeStart Addrs = A1000000 End Addrs = A1xxxxxx Transfer complete from the monitor. Set switch SW4-3 to OFF [boot from flash] and reboot the board. You should now see the RedBoot banner. The exec command which allows the loading and execution of Linux kernels is supported for this board (see ). The exec parameters used for the SE77x9 are: -b <addr> Parameter block address. This is normally the first page of the kernel image and defaults to 0x8c101000 -i <addr> Start address of initrd image -j <size> Size of initrd image -c "args" Kernel arguments string -m <flags> Mount rdonly flags. If set to a non-zero value the root partition will be mounted read-only. -f <flags> RAM disk flags. Should normally be 0x4000 -r <device number> Root device specification. /dev/ram is 0x0101 -l <type> Loader type Finally the kernel entry address can be specified as an optional argument. The default is 0x8c102000 On the SE77x9, Linux expects to be loaded at address 0x8c101000 with the entry point at 0x8c102000. This is configurable in the kernel using the CONFIG_MEMORY_START option. RedBoot sets up the following memory map on the SE77x9 board. Physical Address Range Description ----------------------- ----------- 0x80000000 - 0x803fffff Flash (MBM29LV160) 0x81000000 - 0x813fffff EPROM (M27C800) 0x8c000000 - 0x8dffffff SDRAM 0xb0000000 - 0xb03fffff Ethernet (DP83902A) 0xb0400000 - 0xb07fffff SuperIO (FDC37C935A) 0xb0800000 - 0xb0bfffff Switches 0xb0c00000 - 0xbfffffff LEDs 0xb1800000 - 0xb1bfffff PCMCIA (MaruBun) The ethernet driver uses a hardwired ESA which can, at present, only be changed in CDL. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=se77x9 export ARCH_DIR=sh export PLATFORM_DIR=se77x9 The names of configuration files are listed above with the description of the associated modes. Hitachi SH SE7751installing and testinginstalling and testing Hitachi SH SE7751RedBoot uses the COM1 serial port. The default serial port settings are 38400,8,N,1. Ethernet is also supported using the 10-base T connector. Management of onboard flash is also supported. The following RedBoot configurations are supported: Configuration Mode Description File ROM [ROM] RedBoot running from the board's flash boot sector. redboot_ROM.ecm RAM [RAM] RedBoot running from RAM with RedBoot in the flash boot sector. redboot_RAM.ecm The Solution Engine ships with the Hitachi boot monitor in EPROM which allows for initial programming of RedBoot: Set switches SW5-3 and SW5-4 to ON [boot from EPROM] Connect a serial cable to COM1 and power up the board. After the boot monitor banner, invoke the flash download/program command:Ready >fl The monitor should now ask for input: Flash ROM data copy to RAM Please Send A S-format RecordAt this point copy the RedBoot ROM SREC file to the serial port: $ cat redboot_ROM.eprom.srec > /dev/ttyS0 Eventually you should see something likeStart Addrs = A1000000 End Addrs = A1xxxxxx Transfer complete from the monitor. Set switch SW5-3 to OFF [boot from flash] and reboot the board. You should now see the RedBoot banner. The exec command which allows the loading and execution of Linux kernels is supported for this board (see ). The exec parameters used for the SE7751 are: -b <addr> Parameter block address. This is normally the first page of the kernel image and defaults to 0x8c101000 -i <addr> Start address of initrd image -j <size> Size of initrd image -c "args" Kernel arguments string -m <flags> Mount rdonly flags. If set to a non-zero value the root partition will be mounted read-only. -f <flags> RAM disk flags. Should normally be 0x4000 -r <device number> Root device specification. /dev/ram is 0x0101 -l <type> Loader type Finally the kernel entry address can be specified as an optional argument. The default is 0x8c102000 On the SE7751, Linux expects to be loaded at address 0x8c101000 with the entry point at 0x8c102000. This is configurable in the kernel using the CONFIG_MEMORY_START option. RedBoot sets up the following memory map on the SE7751 board. Physical Address Range Description ----------------------- ----------- 0x80000000 - 0x803fffff Flash (MBM29LV160) 0x81000000 - 0x813fffff EPROM (M27C800) 0x8c000000 - 0x8fffffff SDRAM 0xb8000000 - 0xb8ffffff PCMCIA (MaruBun) 0xb9000000 - 0xb9ffffff Switches 0xba000000 - 0xbaffffff LEDs 0xbd000000 - 0xbdffffff PCI MEM space 0xbe200000 - 0xbe23ffff PCI Ctrl space 0xbe240000 - 0xbe27ffff PCI IO space The ethernet driver uses a hardwired ESA which can, at present, only be changed in CDL. These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in : export TARGET=se7751 export ARCH_DIR=sh export PLATFORM_DIR=se7751 The names of configuration files are listed above with the description of the associated modes.