diff options
author | Dominik Sliwa <dominik.sliwa@toradex.com> | 2018-02-14 16:53:49 +0100 |
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committer | Dominik Sliwa <dominik.sliwa@toradex.com> | 2018-02-28 14:38:45 +0100 |
commit | 4a48136e9c6d55ff9d9427a91ef43d44d26333d7 (patch) | |
tree | bc8d4630e75c10ba6580cabedbba619a006aeca3 /board | |
parent | 3020f5caf0b09fcaf85b3b3fa84fdf688ba22cc0 (diff) |
spi, can and general improvements
SPI:
-move to single transfer read
-clear interrupt register on read
-perform multibyte read transfers with DMA
-make frame format consistant
CAN:
-move from mailbox to CAN FIFO
-implement buffering
-support for reading multiple frames per transfer
General:
-use PLL at 100MHz
-remove debug task
-do not compile release with debug console enabled
-bumped version to 0.13
Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com>
Diffstat (limited to 'board')
-rw-r--r-- | board/clock_config.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/board/clock_config.c b/board/clock_config.c index 16bfe39..4da9ef5 100644 --- a/board/clock_config.c +++ b/board/clock_config.c @@ -54,6 +54,7 @@ #define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */ #define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */ #define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */ +#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */ #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ /******************************************************************************* @@ -139,9 +140,9 @@ const mcg_config_t mcgConfig_BOARD_BootClockRUN = }; const sim_clock_config_t simConfig_BOARD_BootClockRUN = { - .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */ + .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */ .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */ - .clkdiv1 = 0x1130000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /4 */ + .clkdiv1 = 0x01130000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /4 */ }; const osc_config_t oscConfig_BOARD_BootClockRUN = { |