ksd:ksdk update to 2.2

This include FreeRTOS update to version 9.0.0

Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com>

1 files changed, 63 insertions, 30 deletions

diff --git a/drivers/fsl_clock.c b/drivers/fsl_clock.c
index b5549aa..210c080 100644
--- a/drivers/fsl_clock.c
+++ b/drivers/fsl_clock.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016 - 2017 , NXP
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
@@ -12,7 +13,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -28,7 +29,6 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "fsl_common.h"
 #include "fsl_clock.h"
 
 /*******************************************************************************
@@ -190,17 +190,36 @@ static uint32_t CLOCK_GetPll0RefFreq(void);
  */
 static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq);
 
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN
 /*!
  * @brief Delay function to wait FLL stable.
  *
  * Delay function to wait FLL stable in FEI mode or FEE mode, should wait at least
  * 1ms. Every time changes FLL setting, should wait this time for FLL stable.
  */
-static void CLOCK_FllStableDelay(void);
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
+void CLOCK_FllStableDelay(void)
+{
+    /*
+       Should wait at least 1ms. Because in these modes, the core clock is 100MHz
+       at most, so this function could obtain the 1ms delay.
+     */
+    volatile uint32_t i = 30000U;
+    while (i--)
+    {
+        __NOP();
+    }
+}
+#else  /* With MCG_USER_CONFIG_FLL_STABLE_DELAY_EN defined. */
+/* Once user defines the MCG_USER_CONFIG_FLL_STABLE_DELAY_EN to use their own delay function, he has to
+ * create his own CLOCK_FllStableDelay() function in application code. Since the clock functions in this
+ * file would call the CLOCK_FllStableDelay() regardness how it is defined.
+ */
+extern void CLOCK_FllStableDelay(void);
+#endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */
 
 static uint32_t CLOCK_GetMcgExtClkFreq(void)
 {
@@ -334,19 +353,6 @@ static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
     return range;
 }
 
-static void CLOCK_FllStableDelay(void)
-{
-    /*
-       Should wait at least 1ms. Because in these modes, the core clock is 100MHz
-       at most, so this function could obtain the 1ms delay.
-     */
-    volatile uint32_t i = 30000U;
-    while (i--)
-    {
-        __NOP();
-    }
-}
-
 uint32_t CLOCK_GetOsc0ErClkFreq(void)
 {
     if (OSC0->CR & OSC_CR_ERCLKEN_MASK)
@@ -653,16 +659,6 @@ status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
     }
 
     MCG->C7 = (MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
-    if (kMCG_OscselOsc == oscsel)
-    {
-        if (MCG->C2 & MCG_C2_EREFS_MASK)
-        {
-            while (!(MCG->S & MCG_S_OSCINIT0_MASK))
-            {
-            }
-        }
-    }
-
     if (needDelay)
     {
         /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */
@@ -1251,6 +1247,17 @@ status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void
                 | MCG_C1_FRDIV(frdiv)                  /* FRDIV */
                 | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
 
+    /* If use external crystal as clock source, wait for it stable. */
+    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
+    {
+        if (MCG->C2 & MCG_C2_EREFS_MASK)
+        {
+            while (!(MCG->S & MCG_S_OSCINIT0_MASK))
+            {
+            }
+        }
+    }
+
     /* Wait and check status. */
     while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
     {
@@ -1393,6 +1400,17 @@ status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void
                 | MCG_C1_FRDIV(frdiv)                  /* FRDIV = frdiv */
                 | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
 
+    /* If use external crystal as clock source, wait for it stable. */
+    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
+    {
+        if (MCG->C2 & MCG_C2_EREFS_MASK)
+        {
+            while (!(MCG->S & MCG_S_OSCINIT0_MASK))
+            {
+            }
+        }
+    }
+
     /* Wait for Reference clock Status bit to clear */
     while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
     {
@@ -1453,6 +1471,8 @@ status_t CLOCK_SetBlpeMode(void)
 
 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
 {
+    assert(config);
+
     /*
        This function is designed to change MCG to PBE mode from PEE/BLPE/FBE,
        but with this workflow, the source mode could be all modes except PEI/PBI.
@@ -1481,6 +1501,8 @@ status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *co
 
     /* Change to PLL mode. */
     MCG->C6 |= MCG_C6_PLLS_MASK;
+
+    /* Wait for PLL mode changed. */
     while (!(MCG->S & MCG_S_PLLST_MASK))
     {
     }
@@ -1594,6 +1616,17 @@ status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
         ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcExternal)    /* CLKS = 2 */
                                                                 | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
 
+    /* If use external crystal as clock source, wait for it stable. */
+    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
+    {
+        if (MCG->C2 & MCG_C2_EREFS_MASK)
+        {
+            while (!(MCG->S & MCG_S_OSCINIT0_MASK))
+            {
+            }
+        }
+    }
+
     /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
     while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
            (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))