From 4a48136e9c6d55ff9d9427a91ef43d44d26333d7 Mon Sep 17 00:00:00 2001 From: Dominik Sliwa Date: Wed, 14 Feb 2018 16:53:49 +0100 Subject: spi, can and general improvements SPI: -move to single transfer read -clear interrupt register on read -perform multibyte read transfers with DMA -make frame format consistant CAN: -move from mailbox to CAN FIFO -implement buffering -support for reading multiple frames per transfer General: -use PLL at 100MHz -remove debug task -do not compile release with debug console enabled -bumped version to 0.13 Signed-off-by: Dominik Sliwa --- drivers/fsl_flexcan.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/fsl_flexcan.c') diff --git a/drivers/fsl_flexcan.c b/drivers/fsl_flexcan.c index 8fd3399..6c7e0bd 100644 --- a/drivers/fsl_flexcan.c +++ b/drivers/fsl_flexcan.c @@ -402,19 +402,20 @@ void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudR /* Assertion: Source clock should greater than baud rate * FLEXCAN_TIME_QUANTA_NUM. */ assert(priDiv <= sourceClock_Hz); + if (0 == priDiv) { priDiv = 1; } priDiv = (sourceClock_Hz / priDiv) - 1; - /* Desired baud rate is too low. */ if (priDiv > 0xFF) { priDiv = 0xFF; } + /* FlexCAN timing setting formula: * FLEXCAN_TIME_QUANTA_NUM = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1); */ @@ -768,7 +769,7 @@ void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *con FLEXCAN_SetRxMbConfig(base, 4, NULL, false); FLEXCAN_SetRxMbConfig(base, 5, NULL, false); } - + base->MCR |= CAN_MCR_SRXDIS_MASK; /* Exit Freeze Mode. */ FLEXCAN_ExitFreezeMode(base); } -- cgit v1.2.3