/* ** ################################################################### ** Processors: MCIMX7D_M4 ** ** Compilers: Keil ARM C/C++ Compiler ** Freescale C/C++ for Embedded ARM ** GNU C Compiler ** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM ** ** Reference manual: ** Version: rev. 1.0, 2015-04-23 ** Build: b150423 ** ** Abstract: ** CMSIS Peripheral Access Layer for iMX7D ** ** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. ** All rights reserved. ** ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** ** o Redistributions of source code must retain the above copyright notice, this list ** of conditions and the following disclaimer. ** ** o Redistributions in binary form must reproduce the above copyright notice, this ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.freescale.com ** mail: support@freescale.com ** ** Revisions: ** - rev. 1.0 (2015-04-23) ** Initial version by Wang Ge. ** ** ################################################################### */ /*! * @file MCIMX7D_M4.h * @version 1.0 * @date 2015-04-23 * @brief CMSIS Peripheral Access Layer for MCIMX7D_M4 * * CMSIS Peripheral Access Layer for MCIMX7D_M4 */ /* ---------------------------------------------------------------------------- -- MCU activation ---------------------------------------------------------------------------- */ /* Prevention from multiple including the same memory map */ #if !defined(MCIMX7D_M4_H_) /* Check if memory map has not been already included */ #define MCIMX7D_M4_H_ #define MCU_MCIMX7D_M4 /* Check if another memory map has not been also included */ #if (defined(MCU_ACTIVE)) #error MCIMX7D_M4 memory map: There is already included another memory map. Only one memory map can be included. #endif /* (defined(MCU_ACTIVE)) */ #define MCU_ACTIVE #include /** Memory map major version (memory maps with equal major version number are * compatible) */ #define MCU_MEM_MAP_VERSION 0x0100u /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000u /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ /*! * @addtogroup Interrupt_vector_numbers Interrupt vector numbers * @{ */ /** Interrupt Number Definitions */ #define NUMBER_OF_INT_VECTORS 16 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Auxiliary constants */ NotAvail_IRQn = -128, /**< Not available device specific interrupt */ /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ /* Device specific interrupts */ GPR_IRQn = 0, /**< Used to notify cores on exception condition while boot */ DAP_IRQn = 1, /**< DAP Interrupt */ SDMA_IRQn = 2, /**< AND of all 48 SDMA interrupts (events) from all the channels */ DBGMON_IRQn = 3, /**< DBGMON Sync Interrupt */ SNVS_IRQn = 4, /**< WRAPPER ON-OFF button press shorter than 5 seconds (pulse event) */ LCDIF_IRQn = 5, /**< LCDIF Sync Interrupt */ SIM2_IRQn = 6, /**< SIM Interrupt */ CSI_IRQn = 7, /**< CSI Interrupt */ PXP1_IRQn = 8, /**< PXP Interrupt */ Reserved_IRQn = 9, /**< Reserved */ WDOG3_IRQn = 10, /**< Watchdog Timer reset */ HS1_IRQn = 11, /**< SEMA4-HS M4 Interrupt Request */ APBHDMA_IRQn = 12, /**< GPMI operation channel 0 description complete interrupt */ EIM_IRQn = 13, /**< EIM Interrupt */ BCH_IRQn = 14, /**< BCH operation complete interrupt */ GPMI_IRQn = 15, /**< GPMI operation TIMEOUT ERROR interrupt */ UART6_IRQn = 16, /**< UART-6 ORed interrupt */ FTM1_IRQn = 17, /**< Flex Timer1 Fault / Counter / Channel interrupt */ FTM2_IRQn = 18, /**< Flex Timer2 Fault / Counter / Channel interrupt */ SNVS_CONSOLIDATED_IRQn = 19, /**< SRTC Consolidated Interrupt. Non TZ. */ SNVS_SECURITY_IRQn = 20, /**< SRTC Security Interrupt. TZ. */ CSU_IRQn = 21, /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted */ USDHC1_IRQn = 22, /**< uSDHC1 Enhanced SDHC Interrupt Request */ USDHC2_IRQn = 23, /**< uSDHC2 Enhanced SDHC Interrupt Request */ USDHC3_IRQn = 24, /**< uSDHC3 Enhanced SDHC Interrupt Request */ MIPI_CSI_IRQn = 25, /**< MIPI CSI interrupt */ UART1_IRQn = 26, /**< UART-1 ORed interrupt */ UART2_IRQn = 27, /**< UART-2 ORed interrupt */ UART3_IRQn = 28, /**< UART-3 ORed interrupt */ UART4_IRQn = 29, /**< UART-4 ORed interrupt */ UART5_IRQn = 30, /**< UART-5 ORed interrupt */ eCSPI1_IRQn = 31, /**< eCSPI1 interrupt request line to the core. */ eCSPI2_IRQn = 32, /**< eCSPI2 interrupt request line to the core. */ eCSPI3_IRQn = 33, /**< eCSPI3 interrupt request line to the core. */ eCSPI4_IRQn = 34, /**< eCSPI4 interrupt request line to the core. */ I2C1_IRQn = 35, /**< I2C-1 Interrupt */ I2C2_IRQn = 36, /**< I2C-2 Interrupt */ I2C3_IRQn = 37, /**< I2C-3 Interrupt */ I2C4_IRQn = 38, /**< I2C-4 Interrupt */ RDC_IRQn = 39, /**< RDC interrupt */ USB_OH3_OTG2_1_IRQn = 40, /**< USB OH3 OTG2 */ MIPI_DSI_IRQn = 41, /**< MIPI CSI Interrupt */ USB_OH3_OTG2_2_IRQn = 42, /**< USB OH3 OTG2 */ USB_OH2_OTG_IRQn = 43, /**< USB OH2 OTG */ USB_OTG1_IRQn = 44, /**< USB OTG1 Interrupt */ USB_OTG2_IRQn = 45, /**< USB OTG2 Interrupt */ PXP2_IRQn = 46, /**< PXP interrupt */ SCTR1_IRQn = 47, /**< ISO7816IP Interrupt */ SCTR2_IRQn = 48, /**< ISO7816IP Interrupt */ Analog_TempSensor_IRQn = 49, /**< TempSensor (Temperature low alarm). */ SAI3_IRQn = 50, /**< SAI3 Receive / Transmit Interrupt */ Analog_brown_out_IRQn = 51, /**< Brown-out event on either analog regulators. */ GPT4_IRQn = 52, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */ GPT3_IRQn = 53, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */ GPT2_IRQn = 54, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */ GPT1_IRQn = 55, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */ GPIO1_INT7_IRQn = 56, /**< Active HIGH Interrupt from INT7 from GPIO */ GPIO1_INT6_IRQn = 57, /**< Active HIGH Interrupt from INT6 from GPIO */ GPIO1_INT5_IRQn = 58, /**< Active HIGH Interrupt from INT5 from GPIO */ GPIO1_INT4_IRQn = 59, /**< Active HIGH Interrupt from INT4 from GPIO */ GPIO1_INT3_IRQn = 60, /**< Active HIGH Interrupt from INT3 from GPIO */ GPIO1_INT2_IRQn = 61, /**< Active HIGH Interrupt from INT2 from GPIO */ GPIO1_INT1_IRQn = 62, /**< Active HIGH Interrupt from INT1 from GPIO */ GPIO1_INT0_IRQn = 63, /**< Active HIGH Interrupt from INT0 from GPIO */ GPIO1_INT15_0_IRQn = 64, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */ GPIO1_INT31_16_IRQn = 65, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */ GPIO2_INT15_0_IRQn = 66, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */ GPIO2_INT31_16_IRQn = 67, /**< Combined interrupt indication for GPIO2 signals 16 throughout 31 */ GPIO3_INT15_0_IRQn = 68, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */ GPIO3_INT31_16_IRQn = 69, /**< Combined interrupt indication for GPIO3 signals 16 throughout 31 */ GPIO4_INT15_0_IRQn = 70, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */ GPIO4_INT31_16_IRQn = 71, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */ GPIO5_INT15_0_IRQn = 72, /**< Combined interrupt indication for GPIO5 signals 0 throughout 15 */ GPIO5_INT31_16_IRQn = 73, /**< Combined interrupt indication for GPIO5 signals 16 throughout 31 */ GPIO6_INT15_0_IRQn = 74, /**< Combined interrupt indication for GPIO6 signals 0 throughtout 15 */ GPIO6_INT31_16_IRQn = 75, /**< Combined interrupt indication for GPIO6 signals 16 throughtout 31 */ GPIO7_INT15_0_IRQn = 76, /**< Combined interrupt indication for GPIO7 signals 0 throughout 15 */ GPIO7_INT31_16_IRQn = 77, /**< Combined interrupt indication for GPIO7 signals 16 throughout 31 */ WDOG1_IRQn = 78, /**< Watchdog Timer reset */ WDOG2_IRQn = 79, /**< Watchdog Timer reset */ KPP_IRQn = 80, /**< Keypad Interrupt */ PWM1_IRQn = 81, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ PWM2_IRQn = 82, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ PWM3_IRQn = 83, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ PWM4_IRQn = 84, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ CCM_INT1_IRQn = 85, /**< CCM, Interrupt Request 1 */ CCM_INT2_IRQn = 86, /**< CCM, Interrupt Request 2 */ GPC_IRQn = 87, /**< GPC Interrupt Request 1 */ MU_IRQn = 88, /**< Interrupt to A7 */ SRC_IRQn = 89, /**< SRC interrupt request */ SIM1_IRQn = 90, /**< Sim Interrupt */ RTIC_IRQn = 91, /**< RTIC Interrupt */ CPU_IRQn = 92, /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[0]) */ /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[1]) */ CPU_CTI_IRQn = 93, /**< CTI trigger outputs (internal: nCTIIRQ[0]) */ /**< CTI trigger outputs (internal: nCTIIRQ[1]) */ CCM_SRC_GPC_IRQn = 94, /**< SRC GPC Combined CPU wdog interrupts (4x) out of SRC. */ SAI1_IRQn = 95, /**< SAI1 Receive / Transmit Interrupt */ SAI2_IRQn = 96, /**< SAI2 Receive / Transmit Interrupt */ MU_INT_M4_IRQn = 97, /**< Interrupt to M4 */ ADC1_IRQn = 98, /**< ADC-1 Interrupt */ ADC2_IRQn = 99, /**< ADC-2 Interrupt */ ENET2_MAC0_TRANS1_IRQn = 100, /**< MAC 0 Receive / Transmit Frame / Buffer Done */ ENET2_MAC0_TRANS2_IRQn = 101, /**< MAC 0 Receive / Transmit Frame / Buffer Done */ ENET2_MAC0_IRQ_IRQn = 102, /**< MAC 0 IRQ */ ENET2_1588_TIMER_IRQ_IRQn = 103, /**< MAC 0 1588 Timer Interrupt - synchronous */ TPR_IRQn = 104, /**< IRQ TPR IRQ */ CAAM_QUEUE_IRQn = 105, /**< WRAPPER CAAM interrupt queue for JQ */ CAAM_ERROR_IRQn = 106, /**< WRAPPER CAAM interrupt queue for JQ */ QSPI_IRQn = 107, /**< QSPI Interrupt */ TZASC1_IRQn = 108, /**< TZASC (PL380) interrupt */ WDOG4_IRQn = 109, /**< Watchdog Timer reset */ FLEXCAN1_IRQn = 110, /**< FlexCAN1 Interrupt */ FLEXCAN2_IRQn = 111, /**< FlexCAN2 Interrupt */ PERFMON1_IRQn = 112, /**< General interrupt */ PERFMON2_IRQn = 113, /**< General interrupt */ CAAM_WRAPPER1_IRQn = 114, /**< CAAM interrupt queue for JQ */ CAAM_WRAPPER2_IRQn = 115, /**< Recoverable error interrupt */ HS0_IRQn = 116, /**< SEMA4-HS processor A7 Interrupt Request */ EPDC_IRQn = 117, /**< EPDC Interrupt */ ENET1_MAC0_TRANS1_IRQn = 118, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ ENET1_MAC0_TRANS2_IRQn = 119, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ ENET1_MAC0_IRQn = 120, /**< MAC 0 IRQ */ ENET1_1588_TIMER_IRQn = 121, /**< MAC 0 1588 Timer Interrupt - synchronous */ PCIE_CTRL1_IRQn = 122, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ PCIE_CTRL2_IRQn = 123, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ PCIE_CTRL3_IRQn = 124, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ PCIE_CTRL4_IRQn = 125, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ UART7_IRQn = 126, /**< UART-7 ORed interrupt */ PCIE_CTRL_REQUEST_IRQn = 127, /**< Channels [63:32] interrupts requests */ } IRQn_Type; /*! * @} */ /* end of group Interrupt_vector_numbers */ /* ---------------------------------------------------------------------------- -- Cortex M4 Core Configuration ---------------------------------------------------------------------------- */ /*! * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration * @{ */ #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ #include "system_MCIMX7D_M4.h" /* Device specific configuration file */ /*! * @} */ /* end of group Cortex_Core_Configuration */ /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup Peripheral_access_layer Device Peripheral Access Layer * @{ */ /* ** Start of section using anonymous unions */ #if defined(__ARMCC_VERSION) #pragma push #pragma anon_unions #elif defined(__CWCC__) #pragma push #pragma cpp_extensions on #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=extended #else #error Not supported compiler type #endif /* ---------------------------------------------------------------------------- -- ADC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer * @{ */ /** ADC - Register Layout Typedef */ typedef struct { __IO uint32_t CH_A_CFG1; /**< Channel A configuration 1, offset: 0x0 */ uint8_t RESERVED_0[12]; __IO uint32_t CH_A_CFG2; /**< Channel A configuration 2, offset: 0x10 */ uint8_t RESERVED_1[12]; __IO uint32_t CH_B_CFG1; /**< , offset: 0x20 */ uint8_t RESERVED_2[12]; __IO uint32_t CH_B_CFG2; /**< Channel B Configuration 2, offset: 0x30 */ uint8_t RESERVED_3[12]; __IO uint32_t CH_C_CFG1; /**< Channel C Configuration 1, offset: 0x40 */ uint8_t RESERVED_4[12]; __IO uint32_t CH_C_CFG2; /**< Channel C Configuration 2, offset: 0x50 */ uint8_t RESERVED_5[12]; __IO uint32_t CH_D_CFG1; /**< Channel D Configuration 1, offset: 0x60 */ uint8_t RESERVED_6[12]; __IO uint32_t CH_D_CFG2; /**< Channel D Configuration 2, offset: 0x70 */ uint8_t RESERVED_7[12]; __IO uint32_t CH_SW_CFG; /**< Channel Software Configuration, offset: 0x80 */ uint8_t RESERVED_8[12]; __IO uint32_t TIMER_UNIT; /**< Timer Unit, offset: 0x90 */ uint8_t RESERVED_9[12]; __IO uint32_t DMA_FIFO; /**< DMA FIFO, offset: 0xA0 */ uint8_t RESERVED_10[12]; __IO uint32_t FIFO_STATUS; /**< FIFO Status, offset: 0xB0 */ uint8_t RESERVED_11[12]; __IO uint32_t INT_SIG_EN; /**< , offset: 0xC0 */ uint8_t RESERVED_12[12]; __IO uint32_t INT_EN; /**< Interrupt Enable, offset: 0xD0 */ uint8_t RESERVED_13[12]; __IO uint32_t INT_STATUS; /**< , offset: 0xE0 */ uint8_t RESERVED_14[12]; __IO uint32_t CHA_B_CNV_RSLT; /**< Channel A and B Conversion Result, offset: 0xF0 */ uint8_t RESERVED_15[12]; __IO uint32_t CHC_D_CNV_RSLT; /**< Channel C and D Conversion Result, offset: 0x100 */ uint8_t RESERVED_16[12]; __IO uint32_t CH_SW_CNV_RSLT; /**< Channel Software Conversion Result, offset: 0x110 */ uint8_t RESERVED_17[12]; __IO uint32_t DMA_FIFO_DAT; /**< DMA FIFO Data, offset: 0x120 */ uint8_t RESERVED_18[12]; __IO uint32_t ADC_CFG; /**< ADC Configuration, offset: 0x130 */ } ADC_Type, *ADC_MemMapPtr; /* ---------------------------------------------------------------------------- -- ADC - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros * @{ */ /* ADC - Register accessors */ #define ADC_CH_A_CFG1_REG(base) ((base)->CH_A_CFG1) #define ADC_CH_A_CFG2_REG(base) ((base)->CH_A_CFG2) #define ADC_CH_B_CFG1_REG(base) ((base)->CH_B_CFG1) #define ADC_CH_B_CFG2_REG(base) ((base)->CH_B_CFG2) #define ADC_CH_C_CFG1_REG(base) ((base)->CH_C_CFG1) #define ADC_CH_C_CFG2_REG(base) ((base)->CH_C_CFG2) #define ADC_CH_D_CFG1_REG(base) ((base)->CH_D_CFG1) #define ADC_CH_D_CFG2_REG(base) ((base)->CH_D_CFG2) #define ADC_CH_SW_CFG_REG(base) ((base)->CH_SW_CFG) #define ADC_TIMER_UNIT_REG(base) ((base)->TIMER_UNIT) #define ADC_DMA_FIFO_REG(base) ((base)->DMA_FIFO) #define ADC_FIFO_STATUS_REG(base) ((base)->FIFO_STATUS) #define ADC_INT_SIG_EN_REG(base) ((base)->INT_SIG_EN) #define ADC_INT_EN_REG(base) ((base)->INT_EN) #define ADC_INT_STATUS_REG(base) ((base)->INT_STATUS) #define ADC_CHA_B_CNV_RSLT_REG(base) ((base)->CHA_B_CNV_RSLT) #define ADC_CHC_D_CNV_RSLT_REG(base) ((base)->CHC_D_CNV_RSLT) #define ADC_CH_SW_CNV_RSLT_REG(base) ((base)->CH_SW_CNV_RSLT) #define ADC_DMA_FIFO_DAT_REG(base) ((base)->DMA_FIFO_DAT) #define ADC_ADC_CFG_REG(base) ((base)->ADC_CFG) /*! * @} */ /* end of group ADC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Masks ADC Register Masks * @{ */ /* CH_A_CFG1 Bit Fields */ #define ADC_CH_A_CFG1_CHA_TIMER_MASK 0xFFFFFFu #define ADC_CH_A_CFG1_CHA_TIMER_SHIFT 0 #define ADC_CH_A_CFG1_CHA_TIMER(x) (((uint32_t)(((uint32_t)(x))<CTRL0) #define APBH_CTRL0_SET_REG(base) ((base)->CTRL0_SET) #define APBH_CTRL0_CLR_REG(base) ((base)->CTRL0_CLR) #define APBH_CTRL0_TOG_REG(base) ((base)->CTRL0_TOG) #define APBH_CTRL1_REG(base) ((base)->CTRL1) #define APBH_CTRL1_SET_REG(base) ((base)->CTRL1_SET) #define APBH_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) #define APBH_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) #define APBH_CTRL2_REG(base) ((base)->CTRL2) #define APBH_CTRL2_SET_REG(base) ((base)->CTRL2_SET) #define APBH_CTRL2_CLR_REG(base) ((base)->CTRL2_CLR) #define APBH_CTRL2_TOG_REG(base) ((base)->CTRL2_TOG) #define APBH_CHANNEL_CTRL_REG(base) ((base)->CHANNEL_CTRL) #define APBH_CHANNEL_CTRL_SET_REG(base) ((base)->CHANNEL_CTRL_SET) #define APBH_CHANNEL_CTRL_CLR_REG(base) ((base)->CHANNEL_CTRL_CLR) #define APBH_CHANNEL_CTRL_TOG_REG(base) ((base)->CHANNEL_CTRL_TOG) #define APBH_DEVSEL_REG(base) ((base)->DEVSEL) #define APBH_DMA_BURST_SIZE_REG(base) ((base)->DMA_BURST_SIZE) #define APBH_DEBUG_REG(base) ((base)->DEBUG) #define APBH_CH_CURCMDAR_REG(base,index) ((base)->CH_[index].CH_CURCMDAR) #define APBH_CH_NXTCMDAR_REG(base,index) ((base)->CH_[index].CH_NXTCMDAR) #define APBH_CH_CMD_REG(base,index) ((base)->CH_[index].CH_CMD) #define APBH_CH_BAR_REG(base,index) ((base)->CH_[index].CH_BAR) #define APBH_CH_SEMA_REG(base,index) ((base)->CH_[index].CH_SEMA) #define APBH_CH_DEBUG1_REG(base,index) ((base)->CH_[index].CH_DEBUG1) #define APBH_CH_DEBUG2_REG(base,index) ((base)->CH_[index].CH_DEBUG2) #define APBH_VERSION_REG(base) ((base)->VERSION) /*! * @} */ /* end of group APBH_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- APBH Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup APBH_Register_Masks APBH Register Masks * @{ */ /* CTRL0 Bit Fields */ #define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xFFFFu #define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT 0 #define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<CTRL) #define BCH_CTRL_SET_REG(base) ((base)->CTRL_SET) #define BCH_CTRL_CLR_REG(base) ((base)->CTRL_CLR) #define BCH_CTRL_TOG_REG(base) ((base)->CTRL_TOG) #define BCH_STATUS0_REG(base) ((base)->STATUS0) #define BCH_STATUS0_SET_REG(base) ((base)->STATUS0_SET) #define BCH_STATUS0_CLR_REG(base) ((base)->STATUS0_CLR) #define BCH_STATUS0_TOG_REG(base) ((base)->STATUS0_TOG) #define BCH_MODE_REG(base) ((base)->MODE) #define BCH_MODE_SET_REG(base) ((base)->MODE_SET) #define BCH_MODE_CLR_REG(base) ((base)->MODE_CLR) #define BCH_MODE_TOG_REG(base) ((base)->MODE_TOG) #define BCH_ENCODEPTR_REG(base) ((base)->ENCODEPTR) #define BCH_ENCODEPTR_SET_REG(base) ((base)->ENCODEPTR_SET) #define BCH_ENCODEPTR_CLR_REG(base) ((base)->ENCODEPTR_CLR) #define BCH_ENCODEPTR_TOG_REG(base) ((base)->ENCODEPTR_TOG) #define BCH_DATAPTR_REG(base) ((base)->DATAPTR) #define BCH_DATAPTR_SET_REG(base) ((base)->DATAPTR_SET) #define BCH_DATAPTR_CLR_REG(base) ((base)->DATAPTR_CLR) #define BCH_DATAPTR_TOG_REG(base) ((base)->DATAPTR_TOG) #define BCH_METAPTR_REG(base) ((base)->METAPTR) #define BCH_METAPTR_SET_REG(base) ((base)->METAPTR_SET) #define BCH_METAPTR_CLR_REG(base) ((base)->METAPTR_CLR) #define BCH_METAPTR_TOG_REG(base) ((base)->METAPTR_TOG) #define BCH_LAYOUTSELECT_REG(base) ((base)->LAYOUTSELECT) #define BCH_LAYOUTSELECT_SET_REG(base) ((base)->LAYOUTSELECT_SET) #define BCH_LAYOUTSELECT_CLR_REG(base) ((base)->LAYOUTSELECT_CLR) #define BCH_LAYOUTSELECT_TOG_REG(base) ((base)->LAYOUTSELECT_TOG) #define BCH_FLASH0LAYOUT0_REG(base) ((base)->FLASH0LAYOUT0) #define BCH_FLASH0LAYOUT0_SET_REG(base) ((base)->FLASH0LAYOUT0_SET) #define BCH_FLASH0LAYOUT0_CLR_REG(base) ((base)->FLASH0LAYOUT0_CLR) #define BCH_FLASH0LAYOUT0_TOG_REG(base) ((base)->FLASH0LAYOUT0_TOG) #define BCH_FLASH0LAYOUT1_REG(base) ((base)->FLASH0LAYOUT1) #define BCH_FLASH0LAYOUT1_SET_REG(base) ((base)->FLASH0LAYOUT1_SET) #define BCH_FLASH0LAYOUT1_CLR_REG(base) ((base)->FLASH0LAYOUT1_CLR) #define BCH_FLASH0LAYOUT1_TOG_REG(base) ((base)->FLASH0LAYOUT1_TOG) #define BCH_FLASH1LAYOUT0_REG(base) ((base)->FLASH1LAYOUT0) #define BCH_FLASH1LAYOUT0_SET_REG(base) ((base)->FLASH1LAYOUT0_SET) #define BCH_FLASH1LAYOUT0_CLR_REG(base) ((base)->FLASH1LAYOUT0_CLR) #define BCH_FLASH1LAYOUT0_TOG_REG(base) ((base)->FLASH1LAYOUT0_TOG) #define BCH_FLASH1LAYOUT1_REG(base) ((base)->FLASH1LAYOUT1) #define BCH_FLASH1LAYOUT1_SET_REG(base) ((base)->FLASH1LAYOUT1_SET) #define BCH_FLASH1LAYOUT1_CLR_REG(base) ((base)->FLASH1LAYOUT1_CLR) #define BCH_FLASH1LAYOUT1_TOG_REG(base) ((base)->FLASH1LAYOUT1_TOG) #define BCH_FLASH2LAYOUT0_REG(base) ((base)->FLASH2LAYOUT0) #define BCH_FLASH2LAYOUT0_SET_REG(base) ((base)->FLASH2LAYOUT0_SET) #define BCH_FLASH2LAYOUT0_CLR_REG(base) ((base)->FLASH2LAYOUT0_CLR) #define BCH_FLASH2LAYOUT0_TOG_REG(base) ((base)->FLASH2LAYOUT0_TOG) #define BCH_FLASH2LAYOUT1_REG(base) ((base)->FLASH2LAYOUT1) #define BCH_FLASH2LAYOUT1_SET_REG(base) ((base)->FLASH2LAYOUT1_SET) #define BCH_FLASH2LAYOUT1_CLR_REG(base) ((base)->FLASH2LAYOUT1_CLR) #define BCH_FLASH2LAYOUT1_TOG_REG(base) ((base)->FLASH2LAYOUT1_TOG) #define BCH_FLASH3LAYOUT0_REG(base) ((base)->FLASH3LAYOUT0) #define BCH_FLASH3LAYOUT0_SET_REG(base) ((base)->FLASH3LAYOUT0_SET) #define BCH_FLASH3LAYOUT0_CLR_REG(base) ((base)->FLASH3LAYOUT0_CLR) #define BCH_FLASH3LAYOUT0_TOG_REG(base) ((base)->FLASH3LAYOUT0_TOG) #define BCH_FLASH3LAYOUT1_REG(base) ((base)->FLASH3LAYOUT1) #define BCH_FLASH3LAYOUT1_SET_REG(base) ((base)->FLASH3LAYOUT1_SET) #define BCH_FLASH3LAYOUT1_CLR_REG(base) ((base)->FLASH3LAYOUT1_CLR) #define BCH_FLASH3LAYOUT1_TOG_REG(base) ((base)->FLASH3LAYOUT1_TOG) #define BCH_DEBUG0_REG(base) ((base)->DEBUG0) #define BCH_DEBUG0_SET_REG(base) ((base)->DEBUG0_SET) #define BCH_DEBUG0_CLR_REG(base) ((base)->DEBUG0_CLR) #define BCH_DEBUG0_TOG_REG(base) ((base)->DEBUG0_TOG) #define BCH_DBGKESREAD_REG(base) ((base)->DBGKESREAD) #define BCH_DBGKESREAD_SET_REG(base) ((base)->DBGKESREAD_SET) #define BCH_DBGKESREAD_CLR_REG(base) ((base)->DBGKESREAD_CLR) #define BCH_DBGKESREAD_TOG_REG(base) ((base)->DBGKESREAD_TOG) #define BCH_DBGCSFEREAD_REG(base) ((base)->DBGCSFEREAD) #define BCH_DBGCSFEREAD_SET_REG(base) ((base)->DBGCSFEREAD_SET) #define BCH_DBGCSFEREAD_CLR_REG(base) ((base)->DBGCSFEREAD_CLR) #define BCH_DBGCSFEREAD_TOG_REG(base) ((base)->DBGCSFEREAD_TOG) #define BCH_DBGSYNDGENREAD_REG(base) ((base)->DBGSYNDGENREAD) #define BCH_DBGSYNDGENREAD_SET_REG(base) ((base)->DBGSYNDGENREAD_SET) #define BCH_DBGSYNDGENREAD_CLR_REG(base) ((base)->DBGSYNDGENREAD_CLR) #define BCH_DBGSYNDGENREAD_TOG_REG(base) ((base)->DBGSYNDGENREAD_TOG) #define BCH_DBGAHBMREAD_REG(base) ((base)->DBGAHBMREAD) #define BCH_DBGAHBMREAD_SET_REG(base) ((base)->DBGAHBMREAD_SET) #define BCH_DBGAHBMREAD_CLR_REG(base) ((base)->DBGAHBMREAD_CLR) #define BCH_DBGAHBMREAD_TOG_REG(base) ((base)->DBGAHBMREAD_TOG) #define BCH_BLOCKNAME_REG(base) ((base)->BLOCKNAME) #define BCH_BLOCKNAME_SET_REG(base) ((base)->BLOCKNAME_SET) #define BCH_BLOCKNAME_CLR_REG(base) ((base)->BLOCKNAME_CLR) #define BCH_BLOCKNAME_TOG_REG(base) ((base)->BLOCKNAME_TOG) #define BCH_VERSION_REG(base) ((base)->VERSION) #define BCH_VERSION_SET_REG(base) ((base)->VERSION_SET) #define BCH_VERSION_CLR_REG(base) ((base)->VERSION_CLR) #define BCH_VERSION_TOG_REG(base) ((base)->VERSION_TOG) #define BCH_DEBUG1_REG(base) ((base)->DEBUG1) #define BCH_DEBUG1_SET_REG(base) ((base)->DEBUG1_SET) #define BCH_DEBUG1_CLR_REG(base) ((base)->DEBUG1_CLR) #define BCH_DEBUG1_TOG_REG(base) ((base)->DEBUG1_TOG) /*! * @} */ /* end of group BCH_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- BCH Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup BCH_Register_Masks BCH Register Masks * @{ */ /* CTRL Bit Fields */ #define BCH_CTRL_COMPLETE_IRQ_MASK 0x1u #define BCH_CTRL_COMPLETE_IRQ_SHIFT 0 #define BCH_CTRL_RSVD0_MASK 0x2u #define BCH_CTRL_RSVD0_SHIFT 1 #define BCH_CTRL_DEBUG_STALL_IRQ_MASK 0x4u #define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT 2 #define BCH_CTRL_BM_ERROR_IRQ_MASK 0x8u #define BCH_CTRL_BM_ERROR_IRQ_SHIFT 3 #define BCH_CTRL_RSVD1_MASK 0xF0u #define BCH_CTRL_RSVD1_SHIFT 4 #define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<MCR) #define CAN_CTRL1_REG(base) ((base)->CTRL1) #define CAN_TIMER_REG(base) ((base)->TIMER) #define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) #define CAN_RX14MASK_REG(base) ((base)->RX14MASK) #define CAN_RX15MASK_REG(base) ((base)->RX15MASK) #define CAN_ECR_REG(base) ((base)->ECR) #define CAN_ESR1_REG(base) ((base)->ESR1) #define CAN_IMASK2_REG(base) ((base)->IMASK2) #define CAN_IMASK1_REG(base) ((base)->IMASK1) #define CAN_IFLAG2_REG(base) ((base)->IFLAG2) #define CAN_IFLAG1_REG(base) ((base)->IFLAG1) #define CAN_CTRL2_REG(base) ((base)->CTRL2) #define CAN_ESR2_REG(base) ((base)->ESR2) #define CAN_CRCR_REG(base) ((base)->CRCR) #define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) #define CAN_RXFIR_REG(base) ((base)->RXFIR) #define CAN_CS_REG(base,index) ((base)->MB[index].CS) #define CAN_CS_COUNT 64 #define CAN_ID_REG(base,index) ((base)->MB[index].ID) #define CAN_ID_COUNT 64 #define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) #define CAN_WORD0_COUNT 64 #define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) #define CAN_WORD1_COUNT 64 #define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) #define CAN_RXIMR_COUNT 64 #define CAN_GFWR_REG(base) ((base)->GFWR) /*! * @} */ /* end of group CAN_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CAN Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAN_Register_Masks CAN Register Masks * @{ */ /* MCR Bit Fields */ #define CAN_MCR_MAXMB_MASK 0x7Fu #define CAN_MCR_MAXMB_SHIFT 0 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<GPR0) #define CCM_GPR0_SET_REG(base) ((base)->GPR0_SET) #define CCM_GPR0_CLR_REG(base) ((base)->GPR0_CLR) #define CCM_GPR0_TOG_REG(base) ((base)->GPR0_TOG) #define CCM_PLL_CTRL0_REG(base) ((base)->PLL_CTRL0) #define CCM_PLL_CTRL0_SET_REG(base) ((base)->PLL_CTRL0_SET) #define CCM_PLL_CTRL0_CLR_REG(base) ((base)->PLL_CTRL0_CLR) #define CCM_PLL_CTRL0_TOG_REG(base) ((base)->PLL_CTRL0_TOG) #define CCM_PLL_CTRL1_REG(base) ((base)->PLL_CTRL1) #define CCM_PLL_CTRL1_SET_REG(base) ((base)->PLL_CTRL1_SET) #define CCM_PLL_CTRL1_CLR_REG(base) ((base)->PLL_CTRL1_CLR) #define CCM_PLL_CTRL1_TOG_REG(base) ((base)->PLL_CTRL1_TOG) #define CCM_PLL_CTRL2_REG(base) ((base)->PLL_CTRL2) #define CCM_PLL_CTRL2_SET_REG(base) ((base)->PLL_CTRL2_SET) #define CCM_PLL_CTRL2_CLR_REG(base) ((base)->PLL_CTRL2_CLR) #define CCM_PLL_CTRL2_TOG_REG(base) ((base)->PLL_CTRL2_TOG) #define CCM_PLL_CTRL3_REG(base) ((base)->PLL_CTRL3) #define CCM_PLL_CTRL3_SET_REG(base) ((base)->PLL_CTRL3_SET) #define CCM_PLL_CTRL3_CLR_REG(base) ((base)->PLL_CTRL3_CLR) #define CCM_PLL_CTRL3_TOG_REG(base) ((base)->PLL_CTRL3_TOG) #define CCM_PLL_CTRL4_REG(base) ((base)->PLL_CTRL4) #define CCM_PLL_CTRL4_SET_REG(base) ((base)->PLL_CTRL4_SET) #define CCM_PLL_CTRL4_CLR_REG(base) ((base)->PLL_CTRL4_CLR) #define CCM_PLL_CTRL4_TOG_REG(base) ((base)->PLL_CTRL4_TOG) #define CCM_PLL_CTRL5_REG(base) ((base)->PLL_CTRL5) #define CCM_PLL_CTRL5_SET_REG(base) ((base)->PLL_CTRL5_SET) #define CCM_PLL_CTRL5_CLR_REG(base) ((base)->PLL_CTRL5_CLR) #define CCM_PLL_CTRL5_TOG_REG(base) ((base)->PLL_CTRL5_TOG) #define CCM_PLL_CTRL6_REG(base) ((base)->PLL_CTRL6) #define CCM_PLL_CTRL6_SET_REG(base) ((base)->PLL_CTRL6_SET) #define CCM_PLL_CTRL6_CLR_REG(base) ((base)->PLL_CTRL6_CLR) #define CCM_PLL_CTRL6_TOG_REG(base) ((base)->PLL_CTRL6_TOG) #define CCM_PLL_CTRL7_REG(base) ((base)->PLL_CTRL7) #define CCM_PLL_CTRL7_SET_REG(base) ((base)->PLL_CTRL7_SET) #define CCM_PLL_CTRL7_CLR_REG(base) ((base)->PLL_CTRL7_CLR) #define CCM_PLL_CTRL7_TOG_REG(base) ((base)->PLL_CTRL7_TOG) #define CCM_PLL_CTRL8_REG(base) ((base)->PLL_CTRL8) #define CCM_PLL_CTRL8_SET_REG(base) ((base)->PLL_CTRL8_SET) #define CCM_PLL_CTRL8_CLR_REG(base) ((base)->PLL_CTRL8_CLR) #define CCM_PLL_CTRL8_TOG_REG(base) ((base)->PLL_CTRL8_TOG) #define CCM_PLL_CTRL9_REG(base) ((base)->PLL_CTRL9) #define CCM_PLL_CTRL9_SET_REG(base) ((base)->PLL_CTRL9_SET) #define CCM_PLL_CTRL9_CLR_REG(base) ((base)->PLL_CTRL9_CLR) #define CCM_PLL_CTRL9_TOG_REG(base) ((base)->PLL_CTRL9_TOG) #define CCM_PLL_CTRL10_REG(base) ((base)->PLL_CTRL10) #define CCM_PLL_CTRL10_SET_REG(base) ((base)->PLL_CTRL10_SET) #define CCM_PLL_CTRL10_CLR_REG(base) ((base)->PLL_CTRL10_CLR) #define CCM_PLL_CTRL10_TOG_REG(base) ((base)->PLL_CTRL10_TOG) #define CCM_PLL_CTRL11_REG(base) ((base)->PLL_CTRL11) #define CCM_PLL_CTRL11_SET_REG(base) ((base)->PLL_CTRL11_SET) #define CCM_PLL_CTRL11_CLR_REG(base) ((base)->PLL_CTRL11_CLR) #define CCM_PLL_CTRL11_TOG_REG(base) ((base)->PLL_CTRL11_TOG) #define CCM_PLL_CTRL12_REG(base) ((base)->PLL_CTRL12) #define CCM_PLL_CTRL12_SET_REG(base) ((base)->PLL_CTRL12_SET) #define CCM_PLL_CTRL12_CLR_REG(base) ((base)->PLL_CTRL12_CLR) #define CCM_PLL_CTRL12_TOG_REG(base) ((base)->PLL_CTRL12_TOG) #define CCM_PLL_CTRL13_REG(base) ((base)->PLL_CTRL13) #define CCM_PLL_CTRL13_SET_REG(base) ((base)->PLL_CTRL13_SET) #define CCM_PLL_CTRL13_CLR_REG(base) ((base)->PLL_CTRL13_CLR) #define CCM_PLL_CTRL13_TOG_REG(base) ((base)->PLL_CTRL13_TOG) #define CCM_PLL_CTRL14_REG(base) ((base)->PLL_CTRL14) #define CCM_PLL_CTRL14_SET_REG(base) ((base)->PLL_CTRL14_SET) #define CCM_PLL_CTRL14_CLR_REG(base) ((base)->PLL_CTRL14_CLR) #define CCM_PLL_CTRL14_TOG_REG(base) ((base)->PLL_CTRL14_TOG) #define CCM_PLL_CTRL15_REG(base) ((base)->PLL_CTRL15) #define CCM_PLL_CTRL15_SET_REG(base) ((base)->PLL_CTRL15_SET) #define CCM_PLL_CTRL15_CLR_REG(base) ((base)->PLL_CTRL15_CLR) #define CCM_PLL_CTRL15_TOG_REG(base) ((base)->PLL_CTRL15_TOG) #define CCM_PLL_CTRL16_REG(base) ((base)->PLL_CTRL16) #define CCM_PLL_CTRL16_SET_REG(base) ((base)->PLL_CTRL16_SET) #define CCM_PLL_CTRL16_CLR_REG(base) ((base)->PLL_CTRL16_CLR) #define CCM_PLL_CTRL16_TOG_REG(base) ((base)->PLL_CTRL16_TOG) #define CCM_PLL_CTRL17_REG(base) ((base)->PLL_CTRL17) #define CCM_PLL_CTRL17_SET_REG(base) ((base)->PLL_CTRL17_SET) #define CCM_PLL_CTRL17_CLR_REG(base) ((base)->PLL_CTRL17_CLR) #define CCM_PLL_CTRL17_TOG_REG(base) ((base)->PLL_CTRL17_TOG) #define CCM_PLL_CTRL18_REG(base) ((base)->PLL_CTRL18) #define CCM_PLL_CTRL18_SET_REG(base) ((base)->PLL_CTRL18_SET) #define CCM_PLL_CTRL18_CLR_REG(base) ((base)->PLL_CTRL18_CLR) #define CCM_PLL_CTRL18_TOG_REG(base) ((base)->PLL_CTRL18_TOG) #define CCM_PLL_CTRL19_REG(base) ((base)->PLL_CTRL19) #define CCM_PLL_CTRL19_SET_REG(base) ((base)->PLL_CTRL19_SET) #define CCM_PLL_CTRL19_CLR_REG(base) ((base)->PLL_CTRL19_CLR) #define CCM_PLL_CTRL19_TOG_REG(base) ((base)->PLL_CTRL19_TOG) #define CCM_PLL_CTRL20_REG(base) ((base)->PLL_CTRL20) #define CCM_PLL_CTRL20_SET_REG(base) ((base)->PLL_CTRL20_SET) #define CCM_PLL_CTRL20_CLR_REG(base) ((base)->PLL_CTRL20_CLR) #define CCM_PLL_CTRL20_TOG_REG(base) ((base)->PLL_CTRL20_TOG) #define CCM_PLL_CTRL21_REG(base) ((base)->PLL_CTRL21) #define CCM_PLL_CTRL21_SET_REG(base) ((base)->PLL_CTRL21_SET) #define CCM_PLL_CTRL21_CLR_REG(base) ((base)->PLL_CTRL21_CLR) #define CCM_PLL_CTRL21_TOG_REG(base) ((base)->PLL_CTRL21_TOG) #define CCM_PLL_CTRL22_REG(base) ((base)->PLL_CTRL22) #define CCM_PLL_CTRL22_SET_REG(base) ((base)->PLL_CTRL22_SET) #define CCM_PLL_CTRL22_CLR_REG(base) ((base)->PLL_CTRL22_CLR) #define CCM_PLL_CTRL22_TOG_REG(base) ((base)->PLL_CTRL22_TOG) #define CCM_PLL_CTRL23_REG(base) ((base)->PLL_CTRL23) #define CCM_PLL_CTRL23_SET_REG(base) ((base)->PLL_CTRL23_SET) #define CCM_PLL_CTRL23_CLR_REG(base) ((base)->PLL_CTRL23_CLR) #define CCM_PLL_CTRL23_TOG_REG(base) ((base)->PLL_CTRL23_TOG) #define CCM_PLL_CTRL24_REG(base) ((base)->PLL_CTRL24) #define CCM_PLL_CTRL24_SET_REG(base) ((base)->PLL_CTRL24_SET) #define CCM_PLL_CTRL24_CLR_REG(base) ((base)->PLL_CTRL24_CLR) #define CCM_PLL_CTRL24_TOG_REG(base) ((base)->PLL_CTRL24_TOG) #define CCM_PLL_CTRL25_REG(base) ((base)->PLL_CTRL25) #define CCM_PLL_CTRL25_SET_REG(base) ((base)->PLL_CTRL25_SET) #define CCM_PLL_CTRL25_CLR_REG(base) ((base)->PLL_CTRL25_CLR) #define CCM_PLL_CTRL25_TOG_REG(base) ((base)->PLL_CTRL25_TOG) #define CCM_PLL_CTRL26_REG(base) ((base)->PLL_CTRL26) #define CCM_PLL_CTRL26_SET_REG(base) ((base)->PLL_CTRL26_SET) #define CCM_PLL_CTRL26_CLR_REG(base) ((base)->PLL_CTRL26_CLR) #define CCM_PLL_CTRL26_TOG_REG(base) ((base)->PLL_CTRL26_TOG) #define CCM_PLL_CTRL27_REG(base) ((base)->PLL_CTRL27) #define CCM_PLL_CTRL27_SET_REG(base) ((base)->PLL_CTRL27_SET) #define CCM_PLL_CTRL27_CLR_REG(base) ((base)->PLL_CTRL27_CLR) #define CCM_PLL_CTRL27_TOG_REG(base) ((base)->PLL_CTRL27_TOG) #define CCM_PLL_CTRL28_REG(base) ((base)->PLL_CTRL28) #define CCM_PLL_CTRL28_SET_REG(base) ((base)->PLL_CTRL28_SET) #define CCM_PLL_CTRL28_CLR_REG(base) ((base)->PLL_CTRL28_CLR) #define CCM_PLL_CTRL28_TOG_REG(base) ((base)->PLL_CTRL28_TOG) #define CCM_PLL_CTRL29_REG(base) ((base)->PLL_CTRL29) #define CCM_PLL_CTRL29_SET_REG(base) ((base)->PLL_CTRL29_SET) #define CCM_PLL_CTRL29_CLR_REG(base) ((base)->PLL_CTRL29_CLR) #define CCM_PLL_CTRL29_TOG_REG(base) ((base)->PLL_CTRL29_TOG) #define CCM_PLL_CTRL30_REG(base) ((base)->PLL_CTRL30) #define CCM_PLL_CTRL30_SET_REG(base) ((base)->PLL_CTRL30_SET) #define CCM_PLL_CTRL30_CLR_REG(base) ((base)->PLL_CTRL30_CLR) #define CCM_PLL_CTRL30_TOG_REG(base) ((base)->PLL_CTRL30_TOG) #define CCM_PLL_CTRL31_REG(base) ((base)->PLL_CTRL31) #define CCM_PLL_CTRL31_SET_REG(base) ((base)->PLL_CTRL31_SET) #define CCM_PLL_CTRL31_CLR_REG(base) ((base)->PLL_CTRL31_CLR) #define CCM_PLL_CTRL31_TOG_REG(base) ((base)->PLL_CTRL31_TOG) #define CCM_PLL_CTRL32_REG(base) ((base)->PLL_CTRL32) #define CCM_PLL_CTRL32_SET_REG(base) ((base)->PLL_CTRL32_SET) #define CCM_PLL_CTRL32_CLR_REG(base) ((base)->PLL_CTRL32_CLR) #define CCM_PLL_CTRL32_TOG_REG(base) ((base)->PLL_CTRL32_TOG) #define CCM_CCGR0_REG(base) ((base)->CCGR0) #define CCM_CCGR0_SET_REG(base) ((base)->CCGR0_SET) #define CCM_CCGR0_CLR_REG(base) ((base)->CCGR0_CLR) #define CCM_CCGR0_TOG_REG(base) ((base)->CCGR0_TOG) #define CCM_CCGR1_REG(base) ((base)->CCGR1) #define CCM_CCGR1_SET_REG(base) ((base)->CCGR1_SET) #define CCM_CCGR1_CLR_REG(base) ((base)->CCGR1_CLR) #define CCM_CCGR1_TOG_REG(base) ((base)->CCGR1_TOG) #define CCM_CCGR2_REG(base) ((base)->CCGR2) #define CCM_CCGR2_SET_REG(base) ((base)->CCGR2_SET) #define CCM_CCGR2_CLR_REG(base) ((base)->CCGR2_CLR) #define CCM_CCGR2_TOG_REG(base) ((base)->CCGR2_TOG) #define CCM_CCGR3_REG(base) ((base)->CCGR3) #define CCM_CCGR3_SET_REG(base) ((base)->CCGR3_SET) #define CCM_CCGR3_CLR_REG(base) ((base)->CCGR3_CLR) #define CCM_CCGR3_TOG_REG(base) ((base)->CCGR3_TOG) #define CCM_CCGR4_REG(base) ((base)->CCGR4) #define CCM_CCGR4_SET_REG(base) ((base)->CCGR4_SET) #define CCM_CCGR4_CLR_REG(base) ((base)->CCGR4_CLR) #define CCM_CCGR4_TOG_REG(base) ((base)->CCGR4_TOG) #define CCM_CCGR5_REG(base) ((base)->CCGR5) #define CCM_CCGR5_SET_REG(base) ((base)->CCGR5_SET) #define CCM_CCGR5_CLR_REG(base) ((base)->CCGR5_CLR) #define CCM_CCGR5_TOG_REG(base) ((base)->CCGR5_TOG) #define CCM_CCGR6_REG(base) ((base)->CCGR6) #define CCM_CCGR6_SET_REG(base) ((base)->CCGR6_SET) #define CCM_CCGR6_CLR_REG(base) ((base)->CCGR6_CLR) #define CCM_CCGR6_TOG_REG(base) ((base)->CCGR6_TOG) #define CCM_CCGR7_REG(base) ((base)->CCGR7) #define CCM_CCGR7_SET_REG(base) ((base)->CCGR7_SET) #define CCM_CCGR7_CLR_REG(base) ((base)->CCGR7_CLR) #define CCM_CCGR7_TOG_REG(base) ((base)->CCGR7_TOG) #define CCM_CCGR8_REG(base) ((base)->CCGR8) #define CCM_CCGR8_SET_REG(base) ((base)->CCGR8_SET) #define CCM_CCGR8_CLR_REG(base) ((base)->CCGR8_CLR) #define CCM_CCGR8_TOG_REG(base) ((base)->CCGR8_TOG) #define CCM_CCGR9_REG(base) ((base)->CCGR9) #define CCM_CCGR9_SET_REG(base) ((base)->CCGR9_SET) #define CCM_CCGR9_CLR_REG(base) ((base)->CCGR9_CLR) #define CCM_CCGR9_TOG_REG(base) ((base)->CCGR9_TOG) #define CCM_CCGR10_REG(base) ((base)->CCGR10) #define CCM_CCGR10_SET_REG(base) ((base)->CCGR10_SET) #define CCM_CCGR10_CLR_REG(base) ((base)->CCGR10_CLR) #define CCM_CCGR10_TOG_REG(base) ((base)->CCGR10_TOG) #define CCM_CCGR11_REG(base) ((base)->CCGR11) #define CCM_CCGR11_SET_REG(base) ((base)->CCGR11_SET) #define CCM_CCGR11_CLR_REG(base) ((base)->CCGR11_CLR) #define CCM_CCGR11_TOG_REG(base) ((base)->CCGR11_TOG) #define CCM_CCGR12_REG(base) ((base)->CCGR12) #define CCM_CCGR12_SET_REG(base) ((base)->CCGR12_SET) #define CCM_CCGR12_CLR_REG(base) ((base)->CCGR12_CLR) #define CCM_CCGR12_TOG_REG(base) ((base)->CCGR12_TOG) #define CCM_CCGR13_REG(base) ((base)->CCGR13) #define CCM_CCGR13_SET_REG(base) ((base)->CCGR13_SET) #define CCM_CCGR13_CLR_REG(base) ((base)->CCGR13_CLR) #define CCM_CCGR13_TOG_REG(base) ((base)->CCGR13_TOG) #define CCM_CCGR14_REG(base) ((base)->CCGR14) #define CCM_CCGR14_SET_REG(base) ((base)->CCGR14_SET) #define CCM_CCGR14_CLR_REG(base) ((base)->CCGR14_CLR) #define CCM_CCGR14_TOG_REG(base) ((base)->CCGR14_TOG) #define CCM_CCGR15_REG(base) ((base)->CCGR15) #define CCM_CCGR15_SET_REG(base) ((base)->CCGR15_SET) #define CCM_CCGR15_CLR_REG(base) ((base)->CCGR15_CLR) #define CCM_CCGR15_TOG_REG(base) ((base)->CCGR15_TOG) #define CCM_CCGR16_REG(base) ((base)->CCGR16) #define CCM_CCGR16_SET_REG(base) ((base)->CCGR16_SET) #define CCM_CCGR16_CLR_REG(base) ((base)->CCGR16_CLR) #define CCM_CCGR16_TOG_REG(base) ((base)->CCGR16_TOG) #define CCM_CCGR17_REG(base) ((base)->CCGR17) #define CCM_CCGR17_SET_REG(base) ((base)->CCGR17_SET) #define CCM_CCGR17_CLR_REG(base) ((base)->CCGR17_CLR) #define CCM_CCGR17_TOG_REG(base) ((base)->CCGR17_TOG) #define CCM_CCGR18_REG(base) ((base)->CCGR18) #define CCM_CCGR18_SET_REG(base) ((base)->CCGR18_SET) #define CCM_CCGR18_CLR_REG(base) ((base)->CCGR18_CLR) #define CCM_CCGR18_TOG_REG(base) ((base)->CCGR18_TOG) #define CCM_CCGR19_REG(base) ((base)->CCGR19) #define CCM_CCGR19_SET_REG(base) ((base)->CCGR19_SET) #define CCM_CCGR19_CLR_REG(base) ((base)->CCGR19_CLR) #define CCM_CCGR19_TOG_REG(base) ((base)->CCGR19_TOG) #define CCM_CCGR20_REG(base) ((base)->CCGR20) #define CCM_CCGR20_SET_REG(base) ((base)->CCGR20_SET) #define CCM_CCGR20_CLR_REG(base) ((base)->CCGR20_CLR) #define CCM_CCGR20_TOG_REG(base) ((base)->CCGR20_TOG) #define CCM_CCGR21_REG(base) ((base)->CCGR21) #define CCM_CCGR21_SET_REG(base) ((base)->CCGR21_SET) #define CCM_CCGR21_CLR_REG(base) ((base)->CCGR21_CLR) #define CCM_CCGR21_TOG_REG(base) ((base)->CCGR21_TOG) #define CCM_CCGR22_REG(base) ((base)->CCGR22) #define CCM_CCGR22_SET_REG(base) ((base)->CCGR22_SET) #define CCM_CCGR22_CLR_REG(base) ((base)->CCGR22_CLR) #define CCM_CCGR22_TOG_REG(base) ((base)->CCGR22_TOG) #define CCM_CCGR23_REG(base) ((base)->CCGR23) #define CCM_CCGR23_SET_REG(base) ((base)->CCGR23_SET) #define CCM_CCGR23_CLR_REG(base) ((base)->CCGR23_CLR) #define CCM_CCGR23_TOG_REG(base) ((base)->CCGR23_TOG) #define CCM_CCGR24_REG(base) ((base)->CCGR24) #define CCM_CCGR24_SET_REG(base) ((base)->CCGR24_SET) #define CCM_CCGR24_CLR_REG(base) ((base)->CCGR24_CLR) #define CCM_CCGR24_TOG_REG(base) ((base)->CCGR24_TOG) #define CCM_CCGR25_REG(base) ((base)->CCGR25) #define CCM_CCGR25_SET_REG(base) ((base)->CCGR25_SET) #define CCM_CCGR25_CLR_REG(base) ((base)->CCGR25_CLR) #define CCM_CCGR25_TOG_REG(base) ((base)->CCGR25_TOG) #define CCM_CCGR26_REG(base) ((base)->CCGR26) #define CCM_CCGR26_SET_REG(base) ((base)->CCGR26_SET) #define CCM_CCGR26_CLR_REG(base) ((base)->CCGR26_CLR) #define CCM_CCGR26_TOG_REG(base) ((base)->CCGR26_TOG) #define CCM_CCGR27_REG(base) ((base)->CCGR27) #define CCM_CCGR27_SET_REG(base) ((base)->CCGR27_SET) #define CCM_CCGR27_CLR_REG(base) ((base)->CCGR27_CLR) #define CCM_CCGR27_TOG_REG(base) ((base)->CCGR27_TOG) #define CCM_CCGR28_REG(base) ((base)->CCGR28) #define CCM_CCGR28_SET_REG(base) ((base)->CCGR28_SET) #define CCM_CCGR28_CLR_REG(base) ((base)->CCGR28_CLR) #define CCM_CCGR28_TOG_REG(base) ((base)->CCGR28_TOG) #define CCM_CCGR29_REG(base) ((base)->CCGR29) #define CCM_CCGR29_SET_REG(base) ((base)->CCGR29_SET) #define CCM_CCGR29_CLR_REG(base) ((base)->CCGR29_CLR) #define CCM_CCGR29_TOG_REG(base) ((base)->CCGR29_TOG) #define CCM_CCGR30_REG(base) ((base)->CCGR30) #define CCM_CCGR30_SET_REG(base) ((base)->CCGR30_SET) #define CCM_CCGR30_CLR_REG(base) ((base)->CCGR30_CLR) #define CCM_CCGR30_TOG_REG(base) ((base)->CCGR30_TOG) #define CCM_CCGR31_REG(base) ((base)->CCGR31) #define CCM_CCGR31_SET_REG(base) ((base)->CCGR31_SET) #define CCM_CCGR31_CLR_REG(base) ((base)->CCGR31_CLR) #define CCM_CCGR31_TOG_REG(base) ((base)->CCGR31_TOG) #define CCM_CCGR32_REG(base) ((base)->CCGR32) #define CCM_CCGR32_SET_REG(base) ((base)->CCGR32_SET) #define CCM_CCGR32_CLR_REG(base) ((base)->CCGR32_CLR) #define CCM_CCGR32_TOG_REG(base) ((base)->CCGR32_TOG) #define CCM_CCGR33_REG(base) ((base)->CCGR33) #define CCM_CCGR33_SET_REG(base) ((base)->CCGR33_SET) #define CCM_CCGR33_CLR_REG(base) ((base)->CCGR33_CLR) #define CCM_CCGR33_TOG_REG(base) ((base)->CCGR33_TOG) #define CCM_CCGR34_REG(base) ((base)->CCGR34) #define CCM_CCGR34_SET_REG(base) ((base)->CCGR34_SET) #define CCM_CCGR34_CLR_REG(base) ((base)->CCGR34_CLR) #define CCM_CCGR34_TOG_REG(base) ((base)->CCGR34_TOG) #define CCM_CCGR35_REG(base) ((base)->CCGR35) #define CCM_CCGR35_SET_REG(base) ((base)->CCGR35_SET) #define CCM_CCGR35_CLR_REG(base) ((base)->CCGR35_CLR) #define CCM_CCGR35_TOG_REG(base) ((base)->CCGR35_TOG) #define CCM_CCGR36_REG(base) ((base)->CCGR36) #define CCM_CCGR36_SET_REG(base) ((base)->CCGR36_SET) #define CCM_CCGR36_CLR_REG(base) ((base)->CCGR36_CLR) #define CCM_CCGR36_TOG_REG(base) ((base)->CCGR36_TOG) #define CCM_CCGR37_REG(base) ((base)->CCGR37) #define CCM_CCGR37_SET_REG(base) ((base)->CCGR37_SET) #define CCM_CCGR37_CLR_REG(base) ((base)->CCGR37_CLR) #define CCM_CCGR37_TOG_REG(base) ((base)->CCGR37_TOG) #define CCM_CCGR38_REG(base) ((base)->CCGR38) #define CCM_CCGR38_SET_REG(base) ((base)->CCGR38_SET) #define CCM_CCGR38_CLR_REG(base) ((base)->CCGR38_CLR) #define CCM_CCGR38_TOG_REG(base) ((base)->CCGR38_TOG) #define CCM_CCGR39_REG(base) ((base)->CCGR39) #define CCM_CCGR39_SET_REG(base) ((base)->CCGR39_SET) #define CCM_CCGR39_CLR_REG(base) ((base)->CCGR39_CLR) #define CCM_CCGR39_TOG_REG(base) ((base)->CCGR39_TOG) #define CCM_CCGR40_REG(base) ((base)->CCGR40) #define CCM_CCGR40_SET_REG(base) ((base)->CCGR40_SET) #define CCM_CCGR40_CLR_REG(base) ((base)->CCGR40_CLR) #define CCM_CCGR40_TOG_REG(base) ((base)->CCGR40_TOG) #define CCM_CCGR41_REG(base) ((base)->CCGR41) #define CCM_CCGR41_SET_REG(base) ((base)->CCGR41_SET) #define CCM_CCGR41_CLR_REG(base) ((base)->CCGR41_CLR) #define CCM_CCGR41_TOG_REG(base) ((base)->CCGR41_TOG) #define CCM_CCGR42_REG(base) ((base)->CCGR42) #define CCM_CCGR42_SET_REG(base) ((base)->CCGR42_SET) #define CCM_CCGR42_CLR_REG(base) ((base)->CCGR42_CLR) #define CCM_CCGR42_TOG_REG(base) ((base)->CCGR42_TOG) #define CCM_CCGR43_REG(base) ((base)->CCGR43) #define CCM_CCGR43_SET_REG(base) ((base)->CCGR43_SET) #define CCM_CCGR43_CLR_REG(base) ((base)->CCGR43_CLR) #define CCM_CCGR43_TOG_REG(base) ((base)->CCGR43_TOG) #define CCM_CCGR44_REG(base) ((base)->CCGR44) #define CCM_CCGR44_SET_REG(base) ((base)->CCGR44_SET) #define CCM_CCGR44_CLR_REG(base) ((base)->CCGR44_CLR) #define CCM_CCGR44_TOG_REG(base) ((base)->CCGR44_TOG) #define CCM_CCGR45_REG(base) ((base)->CCGR45) #define CCM_CCGR45_SET_REG(base) ((base)->CCGR45_SET) #define CCM_CCGR45_CLR_REG(base) ((base)->CCGR45_CLR) #define CCM_CCGR45_TOG_REG(base) ((base)->CCGR45_TOG) #define CCM_CCGR46_REG(base) ((base)->CCGR46) #define CCM_CCGR46_SET_REG(base) ((base)->CCGR46_SET) #define CCM_CCGR46_CLR_REG(base) ((base)->CCGR46_CLR) #define CCM_CCGR46_TOG_REG(base) ((base)->CCGR46_TOG) #define CCM_CCGR47_REG(base) ((base)->CCGR47) #define CCM_CCGR47_SET_REG(base) ((base)->CCGR47_SET) #define CCM_CCGR47_CLR_REG(base) ((base)->CCGR47_CLR) #define CCM_CCGR47_TOG_REG(base) ((base)->CCGR47_TOG) #define CCM_CCGR48_REG(base) ((base)->CCGR48) #define CCM_CCGR48_SET_REG(base) ((base)->CCGR48_SET) #define CCM_CCGR48_CLR_REG(base) ((base)->CCGR48_CLR) #define CCM_CCGR48_TOG_REG(base) ((base)->CCGR48_TOG) #define CCM_CCGR49_REG(base) ((base)->CCGR49) #define CCM_CCGR49_SET_REG(base) ((base)->CCGR49_SET) #define CCM_CCGR49_CLR_REG(base) ((base)->CCGR49_CLR) #define CCM_CCGR49_TOG_REG(base) ((base)->CCGR49_TOG) #define CCM_CCGR50_REG(base) ((base)->CCGR50) #define CCM_CCGR50_SET_REG(base) ((base)->CCGR50_SET) #define CCM_CCGR50_CLR_REG(base) ((base)->CCGR50_CLR) #define CCM_CCGR50_TOG_REG(base) ((base)->CCGR50_TOG) #define CCM_CCGR51_REG(base) ((base)->CCGR51) #define CCM_CCGR51_SET_REG(base) ((base)->CCGR51_SET) #define CCM_CCGR51_CLR_REG(base) ((base)->CCGR51_CLR) #define CCM_CCGR51_TOG_REG(base) ((base)->CCGR51_TOG) #define CCM_CCGR52_REG(base) ((base)->CCGR52) #define CCM_CCGR52_SET_REG(base) ((base)->CCGR52_SET) #define CCM_CCGR52_CLR_REG(base) ((base)->CCGR52_CLR) #define CCM_CCGR52_TOG_REG(base) ((base)->CCGR52_TOG) #define CCM_CCGR53_REG(base) ((base)->CCGR53) #define CCM_CCGR53_SET_REG(base) ((base)->CCGR53_SET) #define CCM_CCGR53_CLR_REG(base) ((base)->CCGR53_CLR) #define CCM_CCGR53_TOG_REG(base) ((base)->CCGR53_TOG) #define CCM_CCGR54_REG(base) ((base)->CCGR54) #define CCM_CCGR54_SET_REG(base) ((base)->CCGR54_SET) #define CCM_CCGR54_CLR_REG(base) ((base)->CCGR54_CLR) #define CCM_CCGR54_TOG_REG(base) ((base)->CCGR54_TOG) #define CCM_CCGR55_REG(base) ((base)->CCGR55) #define CCM_CCGR55_SET_REG(base) ((base)->CCGR55_SET) #define CCM_CCGR55_CLR_REG(base) ((base)->CCGR55_CLR) #define CCM_CCGR55_TOG_REG(base) ((base)->CCGR55_TOG) #define CCM_CCGR56_REG(base) ((base)->CCGR56) #define CCM_CCGR56_SET_REG(base) ((base)->CCGR56_SET) #define CCM_CCGR56_CLR_REG(base) ((base)->CCGR56_CLR) #define CCM_CCGR56_TOG_REG(base) ((base)->CCGR56_TOG) #define CCM_CCGR57_REG(base) ((base)->CCGR57) #define CCM_CCGR57_SET_REG(base) ((base)->CCGR57_SET) #define CCM_CCGR57_CLR_REG(base) ((base)->CCGR57_CLR) #define CCM_CCGR57_TOG_REG(base) ((base)->CCGR57_TOG) #define CCM_CCGR58_REG(base) ((base)->CCGR58) #define CCM_CCGR58_SET_REG(base) ((base)->CCGR58_SET) #define CCM_CCGR58_CLR_REG(base) ((base)->CCGR58_CLR) #define CCM_CCGR58_TOG_REG(base) ((base)->CCGR58_TOG) #define CCM_CCGR59_REG(base) ((base)->CCGR59) #define CCM_CCGR59_SET_REG(base) ((base)->CCGR59_SET) #define CCM_CCGR59_CLR_REG(base) ((base)->CCGR59_CLR) #define CCM_CCGR59_TOG_REG(base) ((base)->CCGR59_TOG) #define CCM_CCGR60_REG(base) ((base)->CCGR60) #define CCM_CCGR60_SET_REG(base) ((base)->CCGR60_SET) #define CCM_CCGR60_CLR_REG(base) ((base)->CCGR60_CLR) #define CCM_CCGR60_TOG_REG(base) ((base)->CCGR60_TOG) #define CCM_CCGR61_REG(base) ((base)->CCGR61) #define CCM_CCGR61_SET_REG(base) ((base)->CCGR61_SET) #define CCM_CCGR61_CLR_REG(base) ((base)->CCGR61_CLR) #define CCM_CCGR61_TOG_REG(base) ((base)->CCGR61_TOG) #define CCM_CCGR62_REG(base) ((base)->CCGR62) #define CCM_CCGR62_SET_REG(base) ((base)->CCGR62_SET) #define CCM_CCGR62_CLR_REG(base) ((base)->CCGR62_CLR) #define CCM_CCGR62_TOG_REG(base) ((base)->CCGR62_TOG) #define CCM_CCGR63_REG(base) ((base)->CCGR63) #define CCM_CCGR63_SET_REG(base) ((base)->CCGR63_SET) #define CCM_CCGR63_CLR_REG(base) ((base)->CCGR63_CLR) #define CCM_CCGR63_TOG_REG(base) ((base)->CCGR63_TOG) #define CCM_CCGR64_REG(base) ((base)->CCGR64) #define CCM_CCGR64_SET_REG(base) ((base)->CCGR64_SET) #define CCM_CCGR64_CLR_REG(base) ((base)->CCGR64_CLR) #define CCM_CCGR64_TOG_REG(base) ((base)->CCGR64_TOG) #define CCM_CCGR65_REG(base) ((base)->CCGR65) #define CCM_CCGR65_SET_REG(base) ((base)->CCGR65_SET) #define CCM_CCGR65_CLR_REG(base) ((base)->CCGR65_CLR) #define CCM_CCGR65_TOG_REG(base) ((base)->CCGR65_TOG) #define CCM_CCGR66_REG(base) ((base)->CCGR66) #define CCM_CCGR66_SET_REG(base) ((base)->CCGR66_SET) #define CCM_CCGR66_CLR_REG(base) ((base)->CCGR66_CLR) #define CCM_CCGR66_TOG_REG(base) ((base)->CCGR66_TOG) #define CCM_CCGR67_REG(base) ((base)->CCGR67) #define CCM_CCGR67_SET_REG(base) ((base)->CCGR67_SET) #define CCM_CCGR67_CLR_REG(base) ((base)->CCGR67_CLR) #define CCM_CCGR67_TOG_REG(base) ((base)->CCGR67_TOG) #define CCM_CCGR68_REG(base) ((base)->CCGR68) #define CCM_CCGR68_SET_REG(base) ((base)->CCGR68_SET) #define CCM_CCGR68_CLR_REG(base) ((base)->CCGR68_CLR) #define CCM_CCGR68_TOG_REG(base) ((base)->CCGR68_TOG) #define CCM_CCGR69_REG(base) ((base)->CCGR69) #define CCM_CCGR69_SET_REG(base) ((base)->CCGR69_SET) #define CCM_CCGR69_CLR_REG(base) ((base)->CCGR69_CLR) #define CCM_CCGR69_TOG_REG(base) ((base)->CCGR69_TOG) #define CCM_CCGR70_REG(base) ((base)->CCGR70) #define CCM_CCGR70_SET_REG(base) ((base)->CCGR70_SET) #define CCM_CCGR70_CLR_REG(base) ((base)->CCGR70_CLR) #define CCM_CCGR70_TOG_REG(base) ((base)->CCGR70_TOG) #define CCM_CCGR71_REG(base) ((base)->CCGR71) #define CCM_CCGR71_SET_REG(base) ((base)->CCGR71_SET) #define CCM_CCGR71_CLR_REG(base) ((base)->CCGR71_CLR) #define CCM_CCGR71_TOG_REG(base) ((base)->CCGR71_TOG) #define CCM_CCGR72_REG(base) ((base)->CCGR72) #define CCM_CCGR72_SET_REG(base) ((base)->CCGR72_SET) #define CCM_CCGR72_CLR_REG(base) ((base)->CCGR72_CLR) #define CCM_CCGR72_TOG_REG(base) ((base)->CCGR72_TOG) #define CCM_CCGR73_REG(base) ((base)->CCGR73) #define CCM_CCGR73_SET_REG(base) ((base)->CCGR73_SET) #define CCM_CCGR73_CLR_REG(base) ((base)->CCGR73_CLR) #define CCM_CCGR73_TOG_REG(base) ((base)->CCGR73_TOG) #define CCM_CCGR74_REG(base) ((base)->CCGR74) #define CCM_CCGR74_SET_REG(base) ((base)->CCGR74_SET) #define CCM_CCGR74_CLR_REG(base) ((base)->CCGR74_CLR) #define CCM_CCGR74_TOG_REG(base) ((base)->CCGR74_TOG) #define CCM_CCGR75_REG(base) ((base)->CCGR75) #define CCM_CCGR75_SET_REG(base) ((base)->CCGR75_SET) #define CCM_CCGR75_CLR_REG(base) ((base)->CCGR75_CLR) #define CCM_CCGR75_TOG_REG(base) ((base)->CCGR75_TOG) #define CCM_CCGR76_REG(base) ((base)->CCGR76) #define CCM_CCGR76_SET_REG(base) ((base)->CCGR76_SET) #define CCM_CCGR76_CLR_REG(base) ((base)->CCGR76_CLR) #define CCM_CCGR76_TOG_REG(base) ((base)->CCGR76_TOG) #define CCM_CCGR77_REG(base) ((base)->CCGR77) #define CCM_CCGR77_SET_REG(base) ((base)->CCGR77_SET) #define CCM_CCGR77_CLR_REG(base) ((base)->CCGR77_CLR) #define CCM_CCGR77_TOG_REG(base) ((base)->CCGR77_TOG) #define CCM_CCGR78_REG(base) ((base)->CCGR78) #define CCM_CCGR78_SET_REG(base) ((base)->CCGR78_SET) #define CCM_CCGR78_CLR_REG(base) ((base)->CCGR78_CLR) #define CCM_CCGR78_TOG_REG(base) ((base)->CCGR78_TOG) #define CCM_CCGR79_REG(base) ((base)->CCGR79) #define CCM_CCGR79_SET_REG(base) ((base)->CCGR79_SET) #define CCM_CCGR79_CLR_REG(base) ((base)->CCGR79_CLR) #define CCM_CCGR79_TOG_REG(base) ((base)->CCGR79_TOG) #define CCM_CCGR80_REG(base) ((base)->CCGR80) #define CCM_CCGR80_SET_REG(base) ((base)->CCGR80_SET) #define CCM_CCGR80_CLR_REG(base) ((base)->CCGR80_CLR) #define CCM_CCGR80_TOG_REG(base) ((base)->CCGR80_TOG) #define CCM_CCGR81_REG(base) ((base)->CCGR81) #define CCM_CCGR81_SET_REG(base) ((base)->CCGR81_SET) #define CCM_CCGR81_CLR_REG(base) ((base)->CCGR81_CLR) #define CCM_CCGR81_TOG_REG(base) ((base)->CCGR81_TOG) #define CCM_CCGR82_REG(base) ((base)->CCGR82) #define CCM_CCGR82_SET_REG(base) ((base)->CCGR82_SET) #define CCM_CCGR82_CLR_REG(base) ((base)->CCGR82_CLR) #define CCM_CCGR82_TOG_REG(base) ((base)->CCGR82_TOG) #define CCM_CCGR83_REG(base) ((base)->CCGR83) #define CCM_CCGR83_SET_REG(base) ((base)->CCGR83_SET) #define CCM_CCGR83_CLR_REG(base) ((base)->CCGR83_CLR) #define CCM_CCGR83_TOG_REG(base) ((base)->CCGR83_TOG) #define CCM_CCGR84_REG(base) ((base)->CCGR84) #define CCM_CCGR84_SET_REG(base) ((base)->CCGR84_SET) #define CCM_CCGR84_CLR_REG(base) ((base)->CCGR84_CLR) #define CCM_CCGR84_TOG_REG(base) ((base)->CCGR84_TOG) #define CCM_CCGR85_REG(base) ((base)->CCGR85) #define CCM_CCGR85_SET_REG(base) ((base)->CCGR85_SET) #define CCM_CCGR85_CLR_REG(base) ((base)->CCGR85_CLR) #define CCM_CCGR85_TOG_REG(base) ((base)->CCGR85_TOG) #define CCM_CCGR86_REG(base) ((base)->CCGR86) #define CCM_CCGR86_SET_REG(base) ((base)->CCGR86_SET) #define CCM_CCGR86_CLR_REG(base) ((base)->CCGR86_CLR) #define CCM_CCGR86_TOG_REG(base) ((base)->CCGR86_TOG) #define CCM_CCGR87_REG(base) ((base)->CCGR87) #define CCM_CCGR87_SET_REG(base) ((base)->CCGR87_SET) #define CCM_CCGR87_CLR_REG(base) ((base)->CCGR87_CLR) #define CCM_CCGR87_TOG_REG(base) ((base)->CCGR87_TOG) #define CCM_CCGR88_REG(base) ((base)->CCGR88) #define CCM_CCGR88_SET_REG(base) ((base)->CCGR88_SET) #define CCM_CCGR88_CLR_REG(base) ((base)->CCGR88_CLR) #define CCM_CCGR88_TOG_REG(base) ((base)->CCGR88_TOG) #define CCM_CCGR89_REG(base) ((base)->CCGR89) #define CCM_CCGR89_SET_REG(base) ((base)->CCGR89_SET) #define CCM_CCGR89_CLR_REG(base) ((base)->CCGR89_CLR) #define CCM_CCGR89_TOG_REG(base) ((base)->CCGR89_TOG) #define CCM_CCGR90_REG(base) ((base)->CCGR90) #define CCM_CCGR90_SET_REG(base) ((base)->CCGR90_SET) #define CCM_CCGR90_CLR_REG(base) ((base)->CCGR90_CLR) #define CCM_CCGR90_TOG_REG(base) ((base)->CCGR90_TOG) #define CCM_CCGR91_REG(base) ((base)->CCGR91) #define CCM_CCGR91_SET_REG(base) ((base)->CCGR91_SET) #define CCM_CCGR91_CLR_REG(base) ((base)->CCGR91_CLR) #define CCM_CCGR91_TOG_REG(base) ((base)->CCGR91_TOG) #define CCM_CCGR92_REG(base) ((base)->CCGR92) #define CCM_CCGR92_SET_REG(base) ((base)->CCGR92_SET) #define CCM_CCGR92_CLR_REG(base) ((base)->CCGR92_CLR) #define CCM_CCGR92_TOG_REG(base) ((base)->CCGR92_TOG) #define CCM_CCGR93_REG(base) ((base)->CCGR93) #define CCM_CCGR93_SET_REG(base) ((base)->CCGR93_SET) #define CCM_CCGR93_CLR_REG(base) ((base)->CCGR93_CLR) #define CCM_CCGR93_TOG_REG(base) ((base)->CCGR93_TOG) #define CCM_CCGR94_REG(base) ((base)->CCGR94) #define CCM_CCGR94_SET_REG(base) ((base)->CCGR94_SET) #define CCM_CCGR94_CLR_REG(base) ((base)->CCGR94_CLR) #define CCM_CCGR94_TOG_REG(base) ((base)->CCGR94_TOG) #define CCM_CCGR95_REG(base) ((base)->CCGR95) #define CCM_CCGR95_SET_REG(base) ((base)->CCGR95_SET) #define CCM_CCGR95_CLR_REG(base) ((base)->CCGR95_CLR) #define CCM_CCGR95_TOG_REG(base) ((base)->CCGR95_TOG) #define CCM_CCGR96_REG(base) ((base)->CCGR96) #define CCM_CCGR96_SET_REG(base) ((base)->CCGR96_SET) #define CCM_CCGR96_CLR_REG(base) ((base)->CCGR96_CLR) #define CCM_CCGR96_TOG_REG(base) ((base)->CCGR96_TOG) #define CCM_CCGR97_REG(base) ((base)->CCGR97) #define CCM_CCGR97_SET_REG(base) ((base)->CCGR97_SET) #define CCM_CCGR97_CLR_REG(base) ((base)->CCGR97_CLR) #define CCM_CCGR97_TOG_REG(base) ((base)->CCGR97_TOG) #define CCM_CCGR98_REG(base) ((base)->CCGR98) #define CCM_CCGR98_SET_REG(base) ((base)->CCGR98_SET) #define CCM_CCGR98_CLR_REG(base) ((base)->CCGR98_CLR) #define CCM_CCGR98_TOG_REG(base) ((base)->CCGR98_TOG) #define CCM_CCGR99_REG(base) ((base)->CCGR99) #define CCM_CCGR99_SET_REG(base) ((base)->CCGR99_SET) #define CCM_CCGR99_CLR_REG(base) ((base)->CCGR99_CLR) #define CCM_CCGR99_TOG_REG(base) ((base)->CCGR99_TOG) #define CCM_CCGR100_REG(base) ((base)->CCGR100) #define CCM_CCGR100_SET_REG(base) ((base)->CCGR100_SET) #define CCM_CCGR100_CLR_REG(base) ((base)->CCGR100_CLR) #define CCM_CCGR100_TOG_REG(base) ((base)->CCGR100_TOG) #define CCM_CCGR101_REG(base) ((base)->CCGR101) #define CCM_CCGR101_SET_REG(base) ((base)->CCGR101_SET) #define CCM_CCGR101_CLR_REG(base) ((base)->CCGR101_CLR) #define CCM_CCGR101_TOG_REG(base) ((base)->CCGR101_TOG) #define CCM_CCGR102_REG(base) ((base)->CCGR102) #define CCM_CCGR102_SET_REG(base) ((base)->CCGR102_SET) #define CCM_CCGR102_CLR_REG(base) ((base)->CCGR102_CLR) #define CCM_CCGR102_TOG_REG(base) ((base)->CCGR102_TOG) #define CCM_CCGR103_REG(base) ((base)->CCGR103) #define CCM_CCGR103_SET_REG(base) ((base)->CCGR103_SET) #define CCM_CCGR103_CLR_REG(base) ((base)->CCGR103_CLR) #define CCM_CCGR103_TOG_REG(base) ((base)->CCGR103_TOG) #define CCM_CCGR104_REG(base) ((base)->CCGR104) #define CCM_CCGR104_SET_REG(base) ((base)->CCGR104_SET) #define CCM_CCGR104_CLR_REG(base) ((base)->CCGR104_CLR) #define CCM_CCGR104_TOG_REG(base) ((base)->CCGR104_TOG) #define CCM_CCGR105_REG(base) ((base)->CCGR105) #define CCM_CCGR105_SET_REG(base) ((base)->CCGR105_SET) #define CCM_CCGR105_CLR_REG(base) ((base)->CCGR105_CLR) #define CCM_CCGR105_TOG_REG(base) ((base)->CCGR105_TOG) #define CCM_CCGR106_REG(base) ((base)->CCGR106) #define CCM_CCGR106_SET_REG(base) ((base)->CCGR106_SET) #define CCM_CCGR106_CLR_REG(base) ((base)->CCGR106_CLR) #define CCM_CCGR106_TOG_REG(base) ((base)->CCGR106_TOG) #define CCM_CCGR107_REG(base) ((base)->CCGR107) #define CCM_CCGR107_SET_REG(base) ((base)->CCGR107_SET) #define CCM_CCGR107_CLR_REG(base) ((base)->CCGR107_CLR) #define CCM_CCGR107_TOG_REG(base) ((base)->CCGR107_TOG) #define CCM_CCGR108_REG(base) ((base)->CCGR108) #define CCM_CCGR108_SET_REG(base) ((base)->CCGR108_SET) #define CCM_CCGR108_CLR_REG(base) ((base)->CCGR108_CLR) #define CCM_CCGR108_TOG_REG(base) ((base)->CCGR108_TOG) #define CCM_CCGR109_REG(base) ((base)->CCGR109) #define CCM_CCGR109_SET_REG(base) ((base)->CCGR109_SET) #define CCM_CCGR109_CLR_REG(base) ((base)->CCGR109_CLR) #define CCM_CCGR109_TOG_REG(base) ((base)->CCGR109_TOG) #define CCM_CCGR110_REG(base) ((base)->CCGR110) #define CCM_CCGR110_SET_REG(base) ((base)->CCGR110_SET) #define CCM_CCGR110_CLR_REG(base) ((base)->CCGR110_CLR) #define CCM_CCGR110_TOG_REG(base) ((base)->CCGR110_TOG) #define CCM_CCGR111_REG(base) ((base)->CCGR111) #define CCM_CCGR111_SET_REG(base) ((base)->CCGR111_SET) #define CCM_CCGR111_CLR_REG(base) ((base)->CCGR111_CLR) #define CCM_CCGR111_TOG_REG(base) ((base)->CCGR111_TOG) #define CCM_CCGR112_REG(base) ((base)->CCGR112) #define CCM_CCGR112_SET_REG(base) ((base)->CCGR112_SET) #define CCM_CCGR112_CLR_REG(base) ((base)->CCGR112_CLR) #define CCM_CCGR112_TOG_REG(base) ((base)->CCGR112_TOG) #define CCM_CCGR113_REG(base) ((base)->CCGR113) #define CCM_CCGR113_SET_REG(base) ((base)->CCGR113_SET) #define CCM_CCGR113_CLR_REG(base) ((base)->CCGR113_CLR) #define CCM_CCGR113_TOG_REG(base) ((base)->CCGR113_TOG) #define CCM_CCGR114_REG(base) ((base)->CCGR114) #define CCM_CCGR114_SET_REG(base) ((base)->CCGR114_SET) #define CCM_CCGR114_CLR_REG(base) ((base)->CCGR114_CLR) #define CCM_CCGR114_TOG_REG(base) ((base)->CCGR114_TOG) #define CCM_CCGR115_REG(base) ((base)->CCGR115) #define CCM_CCGR115_SET_REG(base) ((base)->CCGR115_SET) #define CCM_CCGR115_CLR_REG(base) ((base)->CCGR115_CLR) #define CCM_CCGR115_TOG_REG(base) ((base)->CCGR115_TOG) #define CCM_CCGR116_REG(base) ((base)->CCGR116) #define CCM_CCGR116_SET_REG(base) ((base)->CCGR116_SET) #define CCM_CCGR116_CLR_REG(base) ((base)->CCGR116_CLR) #define CCM_CCGR116_TOG_REG(base) ((base)->CCGR116_TOG) #define CCM_CCGR117_REG(base) ((base)->CCGR117) #define CCM_CCGR117_SET_REG(base) ((base)->CCGR117_SET) #define CCM_CCGR117_CLR_REG(base) ((base)->CCGR117_CLR) #define CCM_CCGR117_TOG_REG(base) ((base)->CCGR117_TOG) #define CCM_CCGR118_REG(base) ((base)->CCGR118) #define CCM_CCGR118_SET_REG(base) ((base)->CCGR118_SET) #define CCM_CCGR118_CLR_REG(base) ((base)->CCGR118_CLR) #define CCM_CCGR118_TOG_REG(base) ((base)->CCGR118_TOG) #define CCM_CCGR119_REG(base) ((base)->CCGR119) #define CCM_CCGR119_SET_REG(base) ((base)->CCGR119_SET) #define CCM_CCGR119_CLR_REG(base) ((base)->CCGR119_CLR) #define CCM_CCGR119_TOG_REG(base) ((base)->CCGR119_TOG) #define CCM_CCGR120_REG(base) ((base)->CCGR120) #define CCM_CCGR120_SET_REG(base) ((base)->CCGR120_SET) #define CCM_CCGR120_CLR_REG(base) ((base)->CCGR120_CLR) #define CCM_CCGR120_TOG_REG(base) ((base)->CCGR120_TOG) #define CCM_CCGR121_REG(base) ((base)->CCGR121) #define CCM_CCGR121_SET_REG(base) ((base)->CCGR121_SET) #define CCM_CCGR121_CLR_REG(base) ((base)->CCGR121_CLR) #define CCM_CCGR121_TOG_REG(base) ((base)->CCGR121_TOG) #define CCM_CCGR122_REG(base) ((base)->CCGR122) #define CCM_CCGR122_SET_REG(base) ((base)->CCGR122_SET) #define CCM_CCGR122_CLR_REG(base) ((base)->CCGR122_CLR) #define CCM_CCGR122_TOG_REG(base) ((base)->CCGR122_TOG) #define CCM_CCGR123_REG(base) ((base)->CCGR123) #define CCM_CCGR123_SET_REG(base) ((base)->CCGR123_SET) #define CCM_CCGR123_CLR_REG(base) ((base)->CCGR123_CLR) #define CCM_CCGR123_TOG_REG(base) ((base)->CCGR123_TOG) #define CCM_CCGR124_REG(base) ((base)->CCGR124) #define CCM_CCGR124_SET_REG(base) ((base)->CCGR124_SET) #define CCM_CCGR124_CLR_REG(base) ((base)->CCGR124_CLR) #define CCM_CCGR124_TOG_REG(base) ((base)->CCGR124_TOG) #define CCM_CCGR125_REG(base) ((base)->CCGR125) #define CCM_CCGR125_SET_REG(base) ((base)->CCGR125_SET) #define CCM_CCGR125_CLR_REG(base) ((base)->CCGR125_CLR) #define CCM_CCGR125_TOG_REG(base) ((base)->CCGR125_TOG) #define CCM_CCGR126_REG(base) ((base)->CCGR126) #define CCM_CCGR126_SET_REG(base) ((base)->CCGR126_SET) #define CCM_CCGR126_CLR_REG(base) ((base)->CCGR126_CLR) #define CCM_CCGR126_TOG_REG(base) ((base)->CCGR126_TOG) #define CCM_CCGR127_REG(base) ((base)->CCGR127) #define CCM_CCGR127_SET_REG(base) ((base)->CCGR127_SET) #define CCM_CCGR127_CLR_REG(base) ((base)->CCGR127_CLR) #define CCM_CCGR127_TOG_REG(base) ((base)->CCGR127_TOG) #define CCM_CCGR128_REG(base) ((base)->CCGR128) #define CCM_CCGR128_SET_REG(base) ((base)->CCGR128_SET) #define CCM_CCGR128_CLR_REG(base) ((base)->CCGR128_CLR) #define CCM_CCGR128_TOG_REG(base) ((base)->CCGR128_TOG) #define CCM_CCGR129_REG(base) ((base)->CCGR129) #define CCM_CCGR129_SET_REG(base) ((base)->CCGR129_SET) #define CCM_CCGR129_CLR_REG(base) ((base)->CCGR129_CLR) #define CCM_CCGR129_TOG_REG(base) ((base)->CCGR129_TOG) #define CCM_CCGR130_REG(base) ((base)->CCGR130) #define CCM_CCGR130_SET_REG(base) ((base)->CCGR130_SET) #define CCM_CCGR130_CLR_REG(base) ((base)->CCGR130_CLR) #define CCM_CCGR130_TOG_REG(base) ((base)->CCGR130_TOG) #define CCM_CCGR131_REG(base) ((base)->CCGR131) #define CCM_CCGR131_SET_REG(base) ((base)->CCGR131_SET) #define CCM_CCGR131_CLR_REG(base) ((base)->CCGR131_CLR) #define CCM_CCGR131_TOG_REG(base) ((base)->CCGR131_TOG) #define CCM_CCGR132_REG(base) ((base)->CCGR132) #define CCM_CCGR132_SET_REG(base) ((base)->CCGR132_SET) #define CCM_CCGR132_CLR_REG(base) ((base)->CCGR132_CLR) #define CCM_CCGR132_TOG_REG(base) ((base)->CCGR132_TOG) #define CCM_CCGR133_REG(base) ((base)->CCGR133) #define CCM_CCGR133_SET_REG(base) ((base)->CCGR133_SET) #define CCM_CCGR133_CLR_REG(base) ((base)->CCGR133_CLR) #define CCM_CCGR133_TOG_REG(base) ((base)->CCGR133_TOG) #define CCM_CCGR134_REG(base) ((base)->CCGR134) #define CCM_CCGR134_SET_REG(base) ((base)->CCGR134_SET) #define CCM_CCGR134_CLR_REG(base) ((base)->CCGR134_CLR) #define CCM_CCGR134_TOG_REG(base) ((base)->CCGR134_TOG) #define CCM_CCGR135_REG(base) ((base)->CCGR135) #define CCM_CCGR135_SET_REG(base) ((base)->CCGR135_SET) #define CCM_CCGR135_CLR_REG(base) ((base)->CCGR135_CLR) #define CCM_CCGR135_TOG_REG(base) ((base)->CCGR135_TOG) #define CCM_CCGR136_REG(base) ((base)->CCGR136) #define CCM_CCGR136_SET_REG(base) ((base)->CCGR136_SET) #define CCM_CCGR136_CLR_REG(base) ((base)->CCGR136_CLR) #define CCM_CCGR136_TOG_REG(base) ((base)->CCGR136_TOG) #define CCM_CCGR137_REG(base) ((base)->CCGR137) #define CCM_CCGR137_SET_REG(base) ((base)->CCGR137_SET) #define CCM_CCGR137_CLR_REG(base) ((base)->CCGR137_CLR) #define CCM_CCGR137_TOG_REG(base) ((base)->CCGR137_TOG) #define CCM_CCGR138_REG(base) ((base)->CCGR138) #define CCM_CCGR138_SET_REG(base) ((base)->CCGR138_SET) #define CCM_CCGR138_CLR_REG(base) ((base)->CCGR138_CLR) #define CCM_CCGR138_TOG_REG(base) ((base)->CCGR138_TOG) #define CCM_CCGR139_REG(base) ((base)->CCGR139) #define CCM_CCGR139_SET_REG(base) ((base)->CCGR139_SET) #define CCM_CCGR139_CLR_REG(base) ((base)->CCGR139_CLR) #define CCM_CCGR139_TOG_REG(base) ((base)->CCGR139_TOG) #define CCM_CCGR140_REG(base) ((base)->CCGR140) #define CCM_CCGR140_SET_REG(base) ((base)->CCGR140_SET) #define CCM_CCGR140_CLR_REG(base) ((base)->CCGR140_CLR) #define CCM_CCGR140_TOG_REG(base) ((base)->CCGR140_TOG) #define CCM_CCGR141_REG(base) ((base)->CCGR141) #define CCM_CCGR141_SET_REG(base) ((base)->CCGR141_SET) #define CCM_CCGR141_CLR_REG(base) ((base)->CCGR141_CLR) #define CCM_CCGR141_TOG_REG(base) ((base)->CCGR141_TOG) #define CCM_CCGR142_REG(base) ((base)->CCGR142) #define CCM_CCGR142_SET_REG(base) ((base)->CCGR142_SET) #define CCM_CCGR142_CLR_REG(base) ((base)->CCGR142_CLR) #define CCM_CCGR142_TOG_REG(base) ((base)->CCGR142_TOG) #define CCM_CCGR143_REG(base) ((base)->CCGR143) #define CCM_CCGR143_SET_REG(base) ((base)->CCGR143_SET) #define CCM_CCGR143_CLR_REG(base) ((base)->CCGR143_CLR) #define CCM_CCGR143_TOG_REG(base) ((base)->CCGR143_TOG) #define CCM_CCGR144_REG(base) ((base)->CCGR144) #define CCM_CCGR144_SET_REG(base) ((base)->CCGR144_SET) #define CCM_CCGR144_CLR_REG(base) ((base)->CCGR144_CLR) #define CCM_CCGR144_TOG_REG(base) ((base)->CCGR144_TOG) #define CCM_CCGR145_REG(base) ((base)->CCGR145) #define CCM_CCGR145_SET_REG(base) ((base)->CCGR145_SET) #define CCM_CCGR145_CLR_REG(base) ((base)->CCGR145_CLR) #define CCM_CCGR145_TOG_REG(base) ((base)->CCGR145_TOG) #define CCM_CCGR146_REG(base) ((base)->CCGR146) #define CCM_CCGR146_SET_REG(base) ((base)->CCGR146_SET) #define CCM_CCGR146_CLR_REG(base) ((base)->CCGR146_CLR) #define CCM_CCGR146_TOG_REG(base) ((base)->CCGR146_TOG) #define CCM_CCGR147_REG(base) ((base)->CCGR147) #define CCM_CCGR147_SET_REG(base) ((base)->CCGR147_SET) #define CCM_CCGR147_CLR_REG(base) ((base)->CCGR147_CLR) #define CCM_CCGR147_TOG_REG(base) ((base)->CCGR147_TOG) #define CCM_CCGR148_REG(base) ((base)->CCGR148) #define CCM_CCGR148_SET_REG(base) ((base)->CCGR148_SET) #define CCM_CCGR148_CLR_REG(base) ((base)->CCGR148_CLR) #define CCM_CCGR148_TOG_REG(base) ((base)->CCGR148_TOG) #define CCM_CCGR149_REG(base) ((base)->CCGR149) #define CCM_CCGR149_SET_REG(base) ((base)->CCGR149_SET) #define CCM_CCGR149_CLR_REG(base) ((base)->CCGR149_CLR) #define CCM_CCGR149_TOG_REG(base) ((base)->CCGR149_TOG) #define CCM_CCGR150_REG(base) ((base)->CCGR150) #define CCM_CCGR150_SET_REG(base) ((base)->CCGR150_SET) #define CCM_CCGR150_CLR_REG(base) ((base)->CCGR150_CLR) #define CCM_CCGR150_TOG_REG(base) ((base)->CCGR150_TOG) #define CCM_CCGR151_REG(base) ((base)->CCGR151) #define CCM_CCGR151_SET_REG(base) ((base)->CCGR151_SET) #define CCM_CCGR151_CLR_REG(base) ((base)->CCGR151_CLR) #define CCM_CCGR151_TOG_REG(base) ((base)->CCGR151_TOG) #define CCM_CCGR152_REG(base) ((base)->CCGR152) #define CCM_CCGR152_SET_REG(base) ((base)->CCGR152_SET) #define CCM_CCGR152_CLR_REG(base) ((base)->CCGR152_CLR) #define CCM_CCGR152_TOG_REG(base) ((base)->CCGR152_TOG) #define CCM_CCGR153_REG(base) ((base)->CCGR153) #define CCM_CCGR153_SET_REG(base) ((base)->CCGR153_SET) #define CCM_CCGR153_CLR_REG(base) ((base)->CCGR153_CLR) #define CCM_CCGR153_TOG_REG(base) ((base)->CCGR153_TOG) #define CCM_CCGR154_REG(base) ((base)->CCGR154) #define CCM_CCGR154_SET_REG(base) ((base)->CCGR154_SET) #define CCM_CCGR154_CLR_REG(base) ((base)->CCGR154_CLR) #define CCM_CCGR154_TOG_REG(base) ((base)->CCGR154_TOG) #define CCM_CCGR155_REG(base) ((base)->CCGR155) #define CCM_CCGR155_SET_REG(base) ((base)->CCGR155_SET) #define CCM_CCGR155_CLR_REG(base) ((base)->CCGR155_CLR) #define CCM_CCGR155_TOG_REG(base) ((base)->CCGR155_TOG) #define CCM_CCGR156_REG(base) ((base)->CCGR156) #define CCM_CCGR156_SET_REG(base) ((base)->CCGR156_SET) #define CCM_CCGR156_CLR_REG(base) ((base)->CCGR156_CLR) #define CCM_CCGR156_TOG_REG(base) ((base)->CCGR156_TOG) #define CCM_CCGR157_REG(base) ((base)->CCGR157) #define CCM_CCGR157_SET_REG(base) ((base)->CCGR157_SET) #define CCM_CCGR157_CLR_REG(base) ((base)->CCGR157_CLR) #define CCM_CCGR157_TOG_REG(base) ((base)->CCGR157_TOG) #define CCM_CCGR158_REG(base) ((base)->CCGR158) #define CCM_CCGR158_SET_REG(base) ((base)->CCGR158_SET) #define CCM_CCGR158_CLR_REG(base) ((base)->CCGR158_CLR) #define CCM_CCGR158_TOG_REG(base) ((base)->CCGR158_TOG) #define CCM_CCGR159_REG(base) ((base)->CCGR159) #define CCM_CCGR159_SET_REG(base) ((base)->CCGR159_SET) #define CCM_CCGR159_CLR_REG(base) ((base)->CCGR159_CLR) #define CCM_CCGR159_TOG_REG(base) ((base)->CCGR159_TOG) #define CCM_CCGR160_REG(base) ((base)->CCGR160) #define CCM_CCGR160_SET_REG(base) ((base)->CCGR160_SET) #define CCM_CCGR160_CLR_REG(base) ((base)->CCGR160_CLR) #define CCM_CCGR160_TOG_REG(base) ((base)->CCGR160_TOG) #define CCM_CCGR161_REG(base) ((base)->CCGR161) #define CCM_CCGR161_SET_REG(base) ((base)->CCGR161_SET) #define CCM_CCGR161_CLR_REG(base) ((base)->CCGR161_CLR) #define CCM_CCGR161_TOG_REG(base) ((base)->CCGR161_TOG) #define CCM_CCGR162_REG(base) ((base)->CCGR162) #define CCM_CCGR162_SET_REG(base) ((base)->CCGR162_SET) #define CCM_CCGR162_CLR_REG(base) ((base)->CCGR162_CLR) #define CCM_CCGR162_TOG_REG(base) ((base)->CCGR162_TOG) #define CCM_CCGR163_REG(base) ((base)->CCGR163) #define CCM_CCGR163_SET_REG(base) ((base)->CCGR163_SET) #define CCM_CCGR163_CLR_REG(base) ((base)->CCGR163_CLR) #define CCM_CCGR163_TOG_REG(base) ((base)->CCGR163_TOG) #define CCM_CCGR164_REG(base) ((base)->CCGR164) #define CCM_CCGR164_SET_REG(base) ((base)->CCGR164_SET) #define CCM_CCGR164_CLR_REG(base) ((base)->CCGR164_CLR) #define CCM_CCGR164_TOG_REG(base) ((base)->CCGR164_TOG) #define CCM_CCGR165_REG(base) ((base)->CCGR165) #define CCM_CCGR165_SET_REG(base) ((base)->CCGR165_SET) #define CCM_CCGR165_CLR_REG(base) ((base)->CCGR165_CLR) #define CCM_CCGR165_TOG_REG(base) ((base)->CCGR165_TOG) #define CCM_CCGR166_REG(base) ((base)->CCGR166) #define CCM_CCGR166_SET_REG(base) ((base)->CCGR166_SET) #define CCM_CCGR166_CLR_REG(base) ((base)->CCGR166_CLR) #define CCM_CCGR166_TOG_REG(base) ((base)->CCGR166_TOG) #define CCM_CCGR167_REG(base) ((base)->CCGR167) #define CCM_CCGR167_SET_REG(base) ((base)->CCGR167_SET) #define CCM_CCGR167_CLR_REG(base) ((base)->CCGR167_CLR) #define CCM_CCGR167_TOG_REG(base) ((base)->CCGR167_TOG) #define CCM_CCGR168_REG(base) ((base)->CCGR168) #define CCM_CCGR168_SET_REG(base) ((base)->CCGR168_SET) #define CCM_CCGR168_CLR_REG(base) ((base)->CCGR168_CLR) #define CCM_CCGR168_TOG_REG(base) ((base)->CCGR168_TOG) #define CCM_CCGR169_REG(base) ((base)->CCGR169) #define CCM_CCGR169_SET_REG(base) ((base)->CCGR169_SET) #define CCM_CCGR169_CLR_REG(base) ((base)->CCGR169_CLR) #define CCM_CCGR169_TOG_REG(base) ((base)->CCGR169_TOG) #define CCM_CCGR170_REG(base) ((base)->CCGR170) #define CCM_CCGR170_SET_REG(base) ((base)->CCGR170_SET) #define CCM_CCGR170_CLR_REG(base) ((base)->CCGR170_CLR) #define CCM_CCGR170_TOG_REG(base) ((base)->CCGR170_TOG) #define CCM_CCGR171_REG(base) ((base)->CCGR171) #define CCM_CCGR171_SET_REG(base) ((base)->CCGR171_SET) #define CCM_CCGR171_CLR_REG(base) ((base)->CCGR171_CLR) #define CCM_CCGR171_TOG_REG(base) ((base)->CCGR171_TOG) #define CCM_CCGR172_REG(base) ((base)->CCGR172) #define CCM_CCGR172_SET_REG(base) ((base)->CCGR172_SET) #define CCM_CCGR172_CLR_REG(base) ((base)->CCGR172_CLR) #define CCM_CCGR172_TOG_REG(base) ((base)->CCGR172_TOG) #define CCM_CCGR173_REG(base) ((base)->CCGR173) #define CCM_CCGR173_SET_REG(base) ((base)->CCGR173_SET) #define CCM_CCGR173_CLR_REG(base) ((base)->CCGR173_CLR) #define CCM_CCGR173_TOG_REG(base) ((base)->CCGR173_TOG) #define CCM_CCGR174_REG(base) ((base)->CCGR174) #define CCM_CCGR174_SET_REG(base) ((base)->CCGR174_SET) #define CCM_CCGR174_CLR_REG(base) ((base)->CCGR174_CLR) #define CCM_CCGR174_TOG_REG(base) ((base)->CCGR174_TOG) #define CCM_CCGR175_REG(base) ((base)->CCGR175) #define CCM_CCGR175_SET_REG(base) ((base)->CCGR175_SET) #define CCM_CCGR175_CLR_REG(base) ((base)->CCGR175_CLR) #define CCM_CCGR175_TOG_REG(base) ((base)->CCGR175_TOG) #define CCM_CCGR176_REG(base) ((base)->CCGR176) #define CCM_CCGR176_SET_REG(base) ((base)->CCGR176_SET) #define CCM_CCGR176_CLR_REG(base) ((base)->CCGR176_CLR) #define CCM_CCGR176_TOG_REG(base) ((base)->CCGR176_TOG) #define CCM_CCGR177_REG(base) ((base)->CCGR177) #define CCM_CCGR177_SET_REG(base) ((base)->CCGR177_SET) #define CCM_CCGR177_CLR_REG(base) ((base)->CCGR177_CLR) #define CCM_CCGR177_TOG_REG(base) ((base)->CCGR177_TOG) #define CCM_CCGR178_REG(base) ((base)->CCGR178) #define CCM_CCGR178_SET_REG(base) ((base)->CCGR178_SET) #define CCM_CCGR178_CLR_REG(base) ((base)->CCGR178_CLR) #define CCM_CCGR178_TOG_REG(base) ((base)->CCGR178_TOG) #define CCM_CCGR179_REG(base) ((base)->CCGR179) #define CCM_CCGR179_SET_REG(base) ((base)->CCGR179_SET) #define CCM_CCGR179_CLR_REG(base) ((base)->CCGR179_CLR) #define CCM_CCGR179_TOG_REG(base) ((base)->CCGR179_TOG) #define CCM_CCGR180_REG(base) ((base)->CCGR180) #define CCM_CCGR180_SET_REG(base) ((base)->CCGR180_SET) #define CCM_CCGR180_CLR_REG(base) ((base)->CCGR180_CLR) #define CCM_CCGR180_TOG_REG(base) ((base)->CCGR180_TOG) #define CCM_CCGR181_REG(base) ((base)->CCGR181) #define CCM_CCGR181_SET_REG(base) ((base)->CCGR181_SET) #define CCM_CCGR181_CLR_REG(base) ((base)->CCGR181_CLR) #define CCM_CCGR181_TOG_REG(base) ((base)->CCGR181_TOG) #define CCM_CCGR182_REG(base) ((base)->CCGR182) #define CCM_CCGR182_SET_REG(base) ((base)->CCGR182_SET) #define CCM_CCGR182_CLR_REG(base) ((base)->CCGR182_CLR) #define CCM_CCGR182_TOG_REG(base) ((base)->CCGR182_TOG) #define CCM_CCGR183_REG(base) ((base)->CCGR183) #define CCM_CCGR183_SET_REG(base) ((base)->CCGR183_SET) #define CCM_CCGR183_CLR_REG(base) ((base)->CCGR183_CLR) #define CCM_CCGR183_TOG_REG(base) ((base)->CCGR183_TOG) #define CCM_CCGR184_REG(base) ((base)->CCGR184) #define CCM_CCGR184_SET_REG(base) ((base)->CCGR184_SET) #define CCM_CCGR184_CLR_REG(base) ((base)->CCGR184_CLR) #define CCM_CCGR184_TOG_REG(base) ((base)->CCGR184_TOG) #define CCM_CCGR185_REG(base) ((base)->CCGR185) #define CCM_CCGR185_SET_REG(base) ((base)->CCGR185_SET) #define CCM_CCGR185_CLR_REG(base) ((base)->CCGR185_CLR) #define CCM_CCGR185_TOG_REG(base) ((base)->CCGR185_TOG) #define CCM_CCGR186_REG(base) ((base)->CCGR186) #define CCM_CCGR186_SET_REG(base) ((base)->CCGR186_SET) #define CCM_CCGR186_CLR_REG(base) ((base)->CCGR186_CLR) #define CCM_CCGR186_TOG_REG(base) ((base)->CCGR186_TOG) #define CCM_CCGR187_REG(base) ((base)->CCGR187) #define CCM_CCGR187_SET_REG(base) ((base)->CCGR187_SET) #define CCM_CCGR187_CLR_REG(base) ((base)->CCGR187_CLR) #define CCM_CCGR187_TOG_REG(base) ((base)->CCGR187_TOG) #define CCM_CCGR188_REG(base) ((base)->CCGR188) #define CCM_CCGR188_SET_REG(base) ((base)->CCGR188_SET) #define CCM_CCGR188_CLR_REG(base) ((base)->CCGR188_CLR) #define CCM_CCGR188_TOG_REG(base) ((base)->CCGR188_TOG) #define CCM_CCGR189_REG(base) ((base)->CCGR189) #define CCM_CCGR189_SET_REG(base) ((base)->CCGR189_SET) #define CCM_CCGR189_CLR_REG(base) ((base)->CCGR189_CLR) #define CCM_CCGR189_TOG_REG(base) ((base)->CCGR189_TOG) #define CCM_CCGR190_REG(base) ((base)->CCGR190) #define CCM_CCGR190_SET_REG(base) ((base)->CCGR190_SET) #define CCM_CCGR190_CLR_REG(base) ((base)->CCGR190_CLR) #define CCM_CCGR190_TOG_REG(base) ((base)->CCGR190_TOG) #define CCM_TARGET_ROOT0_REG(base) ((base)->TARGET_ROOT0) #define CCM_TARGET_ROOT0_SET_REG(base) ((base)->TARGET_ROOT0_SET) #define CCM_TARGET_ROOT0_CLR_REG(base) ((base)->TARGET_ROOT0_CLR) #define CCM_TARGET_ROOT0_TOG_REG(base) ((base)->TARGET_ROOT0_TOG) #define CCM_POST0_REG(base) ((base)->POST0) #define CCM_POST_ROOT0_SET_REG(base) ((base)->POST_ROOT0_SET) #define CCM_POST_ROOT0_CLR_REG(base) ((base)->POST_ROOT0_CLR) #define CCM_POST_ROOT0_TOG_REG(base) ((base)->POST_ROOT0_TOG) #define CCM_PRE0_REG(base) ((base)->PRE0) #define CCM_PRE_ROOT0_SET_REG(base) ((base)->PRE_ROOT0_SET) #define CCM_PRE_ROOT0_CLR_REG(base) ((base)->PRE_ROOT0_CLR) #define CCM_PRE_ROOT0_TOG_REG(base) ((base)->PRE_ROOT0_TOG) #define CCM_ACCESS_CTRL0_REG(base) ((base)->ACCESS_CTRL0) #define CCM_ACCESS_CTRL0_ROOT_SET_REG(base) ((base)->ACCESS_CTRL0_ROOT_SET) #define CCM_ACCESS_CTRL0_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL0_ROOT_CLR) #define CCM_ACCESS_CTRL0_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL0_ROOT_TOG) #define CCM_TARGET_ROOT1_REG(base) ((base)->TARGET_ROOT1) #define CCM_TARGET_ROOT1_SET_REG(base) ((base)->TARGET_ROOT1_SET) #define CCM_TARGET_ROOT1_CLR_REG(base) ((base)->TARGET_ROOT1_CLR) #define CCM_TARGET_ROOT1_TOG_REG(base) ((base)->TARGET_ROOT1_TOG) #define CCM_POST1_REG(base) ((base)->POST1) #define CCM_POST_ROOT1_SET_REG(base) ((base)->POST_ROOT1_SET) #define CCM_POST_ROOT1_CLR_REG(base) ((base)->POST_ROOT1_CLR) #define CCM_POST_ROOT1_TOG_REG(base) ((base)->POST_ROOT1_TOG) #define CCM_PRE1_REG(base) ((base)->PRE1) #define CCM_PRE_ROOT1_SET_REG(base) ((base)->PRE_ROOT1_SET) #define CCM_PRE_ROOT1_CLR_REG(base) ((base)->PRE_ROOT1_CLR) #define CCM_PRE_ROOT1_TOG_REG(base) ((base)->PRE_ROOT1_TOG) #define CCM_ACCESS_CTRL1_REG(base) ((base)->ACCESS_CTRL1) #define CCM_ACCESS_CTRL1_ROOT_SET_REG(base) ((base)->ACCESS_CTRL1_ROOT_SET) #define CCM_ACCESS_CTRL1_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL1_ROOT_CLR) #define CCM_ACCESS_CTRL1_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL1_ROOT_TOG) #define CCM_TARGET_ROOT2_REG(base) ((base)->TARGET_ROOT2) #define CCM_TARGET_ROOT2_SET_REG(base) ((base)->TARGET_ROOT2_SET) #define CCM_TARGET_ROOT2_CLR_REG(base) ((base)->TARGET_ROOT2_CLR) #define CCM_TARGET_ROOT2_TOG_REG(base) ((base)->TARGET_ROOT2_TOG) #define CCM_POST2_REG(base) ((base)->POST2) #define CCM_POST_ROOT2_SET_REG(base) ((base)->POST_ROOT2_SET) #define CCM_POST_ROOT2_CLR_REG(base) ((base)->POST_ROOT2_CLR) #define CCM_POST_ROOT2_TOG_REG(base) ((base)->POST_ROOT2_TOG) #define CCM_PRE2_REG(base) ((base)->PRE2) #define CCM_PRE_ROOT2_SET_REG(base) ((base)->PRE_ROOT2_SET) #define CCM_PRE_ROOT2_CLR_REG(base) ((base)->PRE_ROOT2_CLR) #define CCM_PRE_ROOT2_TOG_REG(base) ((base)->PRE_ROOT2_TOG) #define CCM_ACCESS_CTRL2_REG(base) ((base)->ACCESS_CTRL2) #define CCM_ACCESS_CTRL2_ROOT_SET_REG(base) ((base)->ACCESS_CTRL2_ROOT_SET) #define CCM_ACCESS_CTRL2_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL2_ROOT_CLR) #define CCM_ACCESS_CTRL2_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL2_ROOT_TOG) #define CCM_TARGET_ROOT3_REG(base) ((base)->TARGET_ROOT3) #define CCM_TARGET_ROOT3_SET_REG(base) ((base)->TARGET_ROOT3_SET) #define CCM_TARGET_ROOT3_CLR_REG(base) ((base)->TARGET_ROOT3_CLR) #define CCM_TARGET_ROOT3_TOG_REG(base) ((base)->TARGET_ROOT3_TOG) #define CCM_POST3_REG(base) ((base)->POST3) #define CCM_POST_ROOT3_SET_REG(base) ((base)->POST_ROOT3_SET) #define CCM_POST_ROOT3_CLR_REG(base) ((base)->POST_ROOT3_CLR) #define CCM_POST_ROOT3_TOG_REG(base) ((base)->POST_ROOT3_TOG) #define CCM_PRE3_REG(base) ((base)->PRE3) #define CCM_PRE_ROOT3_SET_REG(base) ((base)->PRE_ROOT3_SET) #define CCM_PRE_ROOT3_CLR_REG(base) ((base)->PRE_ROOT3_CLR) #define CCM_PRE_ROOT3_TOG_REG(base) ((base)->PRE_ROOT3_TOG) #define CCM_ACCESS_CTRL3_REG(base) ((base)->ACCESS_CTRL3) #define CCM_ACCESS_CTRL3_ROOT_SET_REG(base) ((base)->ACCESS_CTRL3_ROOT_SET) #define CCM_ACCESS_CTRL3_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL3_ROOT_CLR) #define CCM_ACCESS_CTRL3_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL3_ROOT_TOG) #define CCM_TARGET_ROOT4_REG(base) ((base)->TARGET_ROOT4) #define CCM_TARGET_ROOT4_SET_REG(base) ((base)->TARGET_ROOT4_SET) #define CCM_TARGET_ROOT4_CLR_REG(base) ((base)->TARGET_ROOT4_CLR) #define CCM_TARGET_ROOT4_TOG_REG(base) ((base)->TARGET_ROOT4_TOG) #define CCM_POST4_REG(base) ((base)->POST4) #define CCM_POST_ROOT4_SET_REG(base) ((base)->POST_ROOT4_SET) #define CCM_POST_ROOT4_CLR_REG(base) ((base)->POST_ROOT4_CLR) #define CCM_POST_ROOT4_TOG_REG(base) ((base)->POST_ROOT4_TOG) #define CCM_PRE4_REG(base) ((base)->PRE4) #define CCM_PRE_ROOT4_SET_REG(base) ((base)->PRE_ROOT4_SET) #define CCM_PRE_ROOT4_CLR_REG(base) ((base)->PRE_ROOT4_CLR) #define CCM_PRE_ROOT4_TOG_REG(base) ((base)->PRE_ROOT4_TOG) #define CCM_ACCESS_CTRL4_REG(base) ((base)->ACCESS_CTRL4) #define CCM_ACCESS_CTRL4_ROOT_SET_REG(base) ((base)->ACCESS_CTRL4_ROOT_SET) #define CCM_ACCESS_CTRL4_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL4_ROOT_CLR) #define CCM_ACCESS_CTRL4_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL4_ROOT_TOG) #define CCM_TARGET_ROOT5_REG(base) ((base)->TARGET_ROOT5) #define CCM_TARGET_ROOT5_SET_REG(base) ((base)->TARGET_ROOT5_SET) #define CCM_TARGET_ROOT5_CLR_REG(base) ((base)->TARGET_ROOT5_CLR) #define CCM_TARGET_ROOT5_TOG_REG(base) ((base)->TARGET_ROOT5_TOG) #define CCM_POST5_REG(base) ((base)->POST5) #define CCM_POST_ROOT5_SET_REG(base) ((base)->POST_ROOT5_SET) #define CCM_POST_ROOT5_CLR_REG(base) ((base)->POST_ROOT5_CLR) #define CCM_POST_ROOT5_TOG_REG(base) ((base)->POST_ROOT5_TOG) #define CCM_PRE5_REG(base) ((base)->PRE5) #define CCM_PRE_ROOT5_SET_REG(base) ((base)->PRE_ROOT5_SET) #define CCM_PRE_ROOT5_CLR_REG(base) ((base)->PRE_ROOT5_CLR) #define CCM_PRE_ROOT5_TOG_REG(base) ((base)->PRE_ROOT5_TOG) #define CCM_ACCESS_CTRL5_REG(base) ((base)->ACCESS_CTRL5) #define CCM_ACCESS_CTRL5_ROOT_SET_REG(base) ((base)->ACCESS_CTRL5_ROOT_SET) #define CCM_ACCESS_CTRL5_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL5_ROOT_CLR) #define CCM_ACCESS_CTRL5_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL5_ROOT_TOG) #define CCM_TARGET_ROOT6_REG(base) ((base)->TARGET_ROOT6) #define CCM_TARGET_ROOT6_SET_REG(base) ((base)->TARGET_ROOT6_SET) #define CCM_TARGET_ROOT6_CLR_REG(base) ((base)->TARGET_ROOT6_CLR) #define CCM_TARGET_ROOT6_TOG_REG(base) ((base)->TARGET_ROOT6_TOG) #define CCM_POST6_REG(base) ((base)->POST6) #define CCM_POST_ROOT6_SET_REG(base) ((base)->POST_ROOT6_SET) #define CCM_POST_ROOT6_CLR_REG(base) ((base)->POST_ROOT6_CLR) #define CCM_POST_ROOT6_TOG_REG(base) ((base)->POST_ROOT6_TOG) #define CCM_PRE6_REG(base) ((base)->PRE6) #define CCM_PRE_ROOT6_SET_REG(base) ((base)->PRE_ROOT6_SET) #define CCM_PRE_ROOT6_CLR_REG(base) ((base)->PRE_ROOT6_CLR) #define CCM_PRE_ROOT6_TOG_REG(base) ((base)->PRE_ROOT6_TOG) #define CCM_ACCESS_CTRL6_REG(base) ((base)->ACCESS_CTRL6) #define CCM_ACCESS_CTRL6_ROOT_SET_REG(base) ((base)->ACCESS_CTRL6_ROOT_SET) #define CCM_ACCESS_CTRL6_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL6_ROOT_CLR) #define CCM_ACCESS_CTRL6_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL6_ROOT_TOG) #define CCM_TARGET_ROOT7_REG(base) ((base)->TARGET_ROOT7) #define CCM_TARGET_ROOT7_SET_REG(base) ((base)->TARGET_ROOT7_SET) #define CCM_TARGET_ROOT7_CLR_REG(base) ((base)->TARGET_ROOT7_CLR) #define CCM_TARGET_ROOT7_TOG_REG(base) ((base)->TARGET_ROOT7_TOG) #define CCM_POST7_REG(base) ((base)->POST7) #define CCM_POST_ROOT7_SET_REG(base) ((base)->POST_ROOT7_SET) #define CCM_POST_ROOT7_CLR_REG(base) ((base)->POST_ROOT7_CLR) #define CCM_POST_ROOT7_TOG_REG(base) ((base)->POST_ROOT7_TOG) #define CCM_PRE7_REG(base) ((base)->PRE7) #define CCM_PRE_ROOT7_SET_REG(base) ((base)->PRE_ROOT7_SET) #define CCM_PRE_ROOT7_CLR_REG(base) ((base)->PRE_ROOT7_CLR) #define CCM_PRE_ROOT7_TOG_REG(base) ((base)->PRE_ROOT7_TOG) #define CCM_ACCESS_CTRL7_REG(base) ((base)->ACCESS_CTRL7) #define CCM_ACCESS_CTRL7_ROOT_SET_REG(base) ((base)->ACCESS_CTRL7_ROOT_SET) #define CCM_ACCESS_CTRL7_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL7_ROOT_CLR) #define CCM_ACCESS_CTRL7_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL7_ROOT_TOG) #define CCM_TARGET_ROOT8_REG(base) ((base)->TARGET_ROOT8) #define CCM_TARGET_ROOT8_SET_REG(base) ((base)->TARGET_ROOT8_SET) #define CCM_TARGET_ROOT8_CLR_REG(base) ((base)->TARGET_ROOT8_CLR) #define CCM_TARGET_ROOT8_TOG_REG(base) ((base)->TARGET_ROOT8_TOG) #define CCM_POST8_REG(base) ((base)->POST8) #define CCM_POST_ROOT8_SET_REG(base) ((base)->POST_ROOT8_SET) #define CCM_POST_ROOT8_CLR_REG(base) ((base)->POST_ROOT8_CLR) #define CCM_POST_ROOT8_TOG_REG(base) ((base)->POST_ROOT8_TOG) #define CCM_PRE8_REG(base) ((base)->PRE8) #define CCM_PRE_ROOT8_SET_REG(base) ((base)->PRE_ROOT8_SET) #define CCM_PRE_ROOT8_CLR_REG(base) ((base)->PRE_ROOT8_CLR) #define CCM_PRE_ROOT8_TOG_REG(base) ((base)->PRE_ROOT8_TOG) #define CCM_ACCESS_CTRL8_REG(base) ((base)->ACCESS_CTRL8) #define CCM_ACCESS_CTRL8_ROOT_SET_REG(base) ((base)->ACCESS_CTRL8_ROOT_SET) #define CCM_ACCESS_CTRL8_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL8_ROOT_CLR) #define CCM_ACCESS_CTRL8_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL8_ROOT_TOG) #define CCM_TARGET_ROOT9_REG(base) ((base)->TARGET_ROOT9) #define CCM_TARGET_ROOT9_SET_REG(base) ((base)->TARGET_ROOT9_SET) #define CCM_TARGET_ROOT9_CLR_REG(base) ((base)->TARGET_ROOT9_CLR) #define CCM_TARGET_ROOT9_TOG_REG(base) ((base)->TARGET_ROOT9_TOG) #define CCM_POST9_REG(base) ((base)->POST9) #define CCM_POST_ROOT9_SET_REG(base) ((base)->POST_ROOT9_SET) #define CCM_POST_ROOT9_CLR_REG(base) ((base)->POST_ROOT9_CLR) #define CCM_POST_ROOT9_TOG_REG(base) ((base)->POST_ROOT9_TOG) #define CCM_PRE9_REG(base) ((base)->PRE9) #define CCM_PRE_ROOT9_SET_REG(base) ((base)->PRE_ROOT9_SET) #define CCM_PRE_ROOT9_CLR_REG(base) ((base)->PRE_ROOT9_CLR) #define CCM_PRE_ROOT9_TOG_REG(base) ((base)->PRE_ROOT9_TOG) #define CCM_ACCESS_CTRL9_REG(base) ((base)->ACCESS_CTRL9) #define CCM_ACCESS_CTRL9_ROOT_SET_REG(base) ((base)->ACCESS_CTRL9_ROOT_SET) #define CCM_ACCESS_CTRL9_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL9_ROOT_CLR) #define CCM_ACCESS_CTRL9_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL9_ROOT_TOG) #define CCM_TARGET_ROOT10_REG(base) ((base)->TARGET_ROOT10) #define CCM_TARGET_ROOT10_SET_REG(base) ((base)->TARGET_ROOT10_SET) #define CCM_TARGET_ROOT10_CLR_REG(base) ((base)->TARGET_ROOT10_CLR) #define CCM_TARGET_ROOT10_TOG_REG(base) ((base)->TARGET_ROOT10_TOG) #define CCM_POST10_REG(base) ((base)->POST10) #define CCM_POST_ROOT10_SET_REG(base) ((base)->POST_ROOT10_SET) #define CCM_POST_ROOT10_CLR_REG(base) ((base)->POST_ROOT10_CLR) #define CCM_POST_ROOT10_TOG_REG(base) ((base)->POST_ROOT10_TOG) #define CCM_PRE10_REG(base) ((base)->PRE10) #define CCM_PRE_ROOT10_SET_REG(base) ((base)->PRE_ROOT10_SET) #define CCM_PRE_ROOT10_CLR_REG(base) ((base)->PRE_ROOT10_CLR) #define CCM_PRE_ROOT10_TOG_REG(base) ((base)->PRE_ROOT10_TOG) #define CCM_ACCESS_CTRL10_REG(base) ((base)->ACCESS_CTRL10) #define CCM_ACCESS_CTRL10_ROOT_SET_REG(base) ((base)->ACCESS_CTRL10_ROOT_SET) #define CCM_ACCESS_CTRL10_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL10_ROOT_CLR) #define CCM_ACCESS_CTRL10_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL10_ROOT_TOG) #define CCM_TARGET_ROOT11_REG(base) ((base)->TARGET_ROOT11) #define CCM_TARGET_ROOT11_SET_REG(base) ((base)->TARGET_ROOT11_SET) #define CCM_TARGET_ROOT11_CLR_REG(base) ((base)->TARGET_ROOT11_CLR) #define CCM_TARGET_ROOT11_TOG_REG(base) ((base)->TARGET_ROOT11_TOG) #define CCM_POST11_REG(base) ((base)->POST11) #define CCM_POST_ROOT11_SET_REG(base) ((base)->POST_ROOT11_SET) #define CCM_POST_ROOT11_CLR_REG(base) ((base)->POST_ROOT11_CLR) #define CCM_POST_ROOT11_TOG_REG(base) ((base)->POST_ROOT11_TOG) #define CCM_PRE11_REG(base) ((base)->PRE11) #define CCM_PRE_ROOT11_SET_REG(base) ((base)->PRE_ROOT11_SET) #define CCM_PRE_ROOT11_CLR_REG(base) ((base)->PRE_ROOT11_CLR) #define CCM_PRE_ROOT11_TOG_REG(base) ((base)->PRE_ROOT11_TOG) #define CCM_ACCESS_CTRL11_REG(base) ((base)->ACCESS_CTRL11) #define CCM_ACCESS_CTRL11_ROOT_SET_REG(base) ((base)->ACCESS_CTRL11_ROOT_SET) #define CCM_ACCESS_CTRL11_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL11_ROOT_CLR) #define CCM_ACCESS_CTRL11_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL11_ROOT_TOG) #define CCM_TARGET_ROOT12_REG(base) ((base)->TARGET_ROOT12) #define CCM_TARGET_ROOT12_SET_REG(base) ((base)->TARGET_ROOT12_SET) #define CCM_TARGET_ROOT12_CLR_REG(base) ((base)->TARGET_ROOT12_CLR) #define CCM_TARGET_ROOT12_TOG_REG(base) ((base)->TARGET_ROOT12_TOG) #define CCM_POST12_REG(base) ((base)->POST12) #define CCM_POST_ROOT12_SET_REG(base) ((base)->POST_ROOT12_SET) #define CCM_POST_ROOT12_CLR_REG(base) ((base)->POST_ROOT12_CLR) #define CCM_POST_ROOT12_TOG_REG(base) ((base)->POST_ROOT12_TOG) #define CCM_PRE12_REG(base) ((base)->PRE12) #define CCM_PRE_ROOT12_SET_REG(base) ((base)->PRE_ROOT12_SET) #define CCM_PRE_ROOT12_CLR_REG(base) ((base)->PRE_ROOT12_CLR) #define CCM_PRE_ROOT12_TOG_REG(base) ((base)->PRE_ROOT12_TOG) #define CCM_ACCESS_CTRL12_REG(base) ((base)->ACCESS_CTRL12) #define CCM_ACCESS_CTRL12_ROOT_SET_REG(base) ((base)->ACCESS_CTRL12_ROOT_SET) #define CCM_ACCESS_CTRL12_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL12_ROOT_CLR) #define CCM_ACCESS_CTRL12_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL12_ROOT_TOG) #define CCM_TARGET_ROOT13_REG(base) ((base)->TARGET_ROOT13) #define CCM_TARGET_ROOT13_SET_REG(base) ((base)->TARGET_ROOT13_SET) #define CCM_TARGET_ROOT13_CLR_REG(base) ((base)->TARGET_ROOT13_CLR) #define CCM_TARGET_ROOT13_TOG_REG(base) ((base)->TARGET_ROOT13_TOG) #define CCM_POST13_REG(base) ((base)->POST13) #define CCM_POST_ROOT13_SET_REG(base) ((base)->POST_ROOT13_SET) #define CCM_POST_ROOT13_CLR_REG(base) ((base)->POST_ROOT13_CLR) #define CCM_POST_ROOT13_TOG_REG(base) ((base)->POST_ROOT13_TOG) #define CCM_PRE13_REG(base) ((base)->PRE13) #define CCM_PRE_ROOT13_SET_REG(base) ((base)->PRE_ROOT13_SET) #define CCM_PRE_ROOT13_CLR_REG(base) ((base)->PRE_ROOT13_CLR) #define CCM_PRE_ROOT13_TOG_REG(base) ((base)->PRE_ROOT13_TOG) #define CCM_ACCESS_CTRL13_REG(base) ((base)->ACCESS_CTRL13) #define CCM_ACCESS_CTRL13_ROOT_SET_REG(base) ((base)->ACCESS_CTRL13_ROOT_SET) #define CCM_ACCESS_CTRL13_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL13_ROOT_CLR) #define CCM_ACCESS_CTRL13_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL13_ROOT_TOG) #define CCM_TARGET_ROOT14_REG(base) ((base)->TARGET_ROOT14) #define CCM_TARGET_ROOT14_SET_REG(base) ((base)->TARGET_ROOT14_SET) #define CCM_TARGET_ROOT14_CLR_REG(base) ((base)->TARGET_ROOT14_CLR) #define CCM_TARGET_ROOT14_TOG_REG(base) ((base)->TARGET_ROOT14_TOG) #define CCM_POST14_REG(base) ((base)->POST14) #define CCM_POST_ROOT14_SET_REG(base) ((base)->POST_ROOT14_SET) #define CCM_POST_ROOT14_CLR_REG(base) ((base)->POST_ROOT14_CLR) #define CCM_POST_ROOT14_TOG_REG(base) ((base)->POST_ROOT14_TOG) #define CCM_PRE14_REG(base) ((base)->PRE14) #define CCM_PRE_ROOT14_SET_REG(base) ((base)->PRE_ROOT14_SET) #define CCM_PRE_ROOT14_CLR_REG(base) ((base)->PRE_ROOT14_CLR) #define CCM_PRE_ROOT14_TOG_REG(base) ((base)->PRE_ROOT14_TOG) #define CCM_ACCESS_CTRL14_REG(base) ((base)->ACCESS_CTRL14) #define CCM_ACCESS_CTRL14_ROOT_SET_REG(base) ((base)->ACCESS_CTRL14_ROOT_SET) #define CCM_ACCESS_CTRL14_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL14_ROOT_CLR) #define CCM_ACCESS_CTRL14_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL14_ROOT_TOG) #define CCM_TARGET_ROOT15_REG(base) ((base)->TARGET_ROOT15) #define CCM_TARGET_ROOT15_SET_REG(base) ((base)->TARGET_ROOT15_SET) #define CCM_TARGET_ROOT15_CLR_REG(base) ((base)->TARGET_ROOT15_CLR) #define CCM_TARGET_ROOT15_TOG_REG(base) ((base)->TARGET_ROOT15_TOG) #define CCM_POST15_REG(base) ((base)->POST15) #define CCM_POST_ROOT15_SET_REG(base) ((base)->POST_ROOT15_SET) #define CCM_POST_ROOT15_CLR_REG(base) ((base)->POST_ROOT15_CLR) #define CCM_POST_ROOT15_TOG_REG(base) ((base)->POST_ROOT15_TOG) #define CCM_PRE15_REG(base) ((base)->PRE15) #define CCM_PRE_ROOT15_SET_REG(base) ((base)->PRE_ROOT15_SET) #define CCM_PRE_ROOT15_CLR_REG(base) ((base)->PRE_ROOT15_CLR) #define CCM_PRE_ROOT15_TOG_REG(base) ((base)->PRE_ROOT15_TOG) #define CCM_ACCESS_CTRL15_REG(base) ((base)->ACCESS_CTRL15) #define CCM_ACCESS_CTRL15_ROOT_SET_REG(base) ((base)->ACCESS_CTRL15_ROOT_SET) #define CCM_ACCESS_CTRL15_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL15_ROOT_CLR) #define CCM_ACCESS_CTRL15_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL15_ROOT_TOG) #define CCM_TARGET_ROOT16_REG(base) ((base)->TARGET_ROOT16) #define CCM_TARGET_ROOT16_SET_REG(base) ((base)->TARGET_ROOT16_SET) #define CCM_TARGET_ROOT16_CLR_REG(base) ((base)->TARGET_ROOT16_CLR) #define CCM_TARGET_ROOT16_TOG_REG(base) ((base)->TARGET_ROOT16_TOG) #define CCM_POST16_REG(base) ((base)->POST16) #define CCM_POST_ROOT16_SET_REG(base) ((base)->POST_ROOT16_SET) #define CCM_POST_ROOT16_CLR_REG(base) ((base)->POST_ROOT16_CLR) #define CCM_POST_ROOT16_TOG_REG(base) ((base)->POST_ROOT16_TOG) #define CCM_PRE16_REG(base) ((base)->PRE16) #define CCM_PRE_ROOT16_SET_REG(base) ((base)->PRE_ROOT16_SET) #define CCM_PRE_ROOT16_CLR_REG(base) ((base)->PRE_ROOT16_CLR) #define CCM_PRE_ROOT16_TOG_REG(base) ((base)->PRE_ROOT16_TOG) #define CCM_ACCESS_CTRL16_REG(base) ((base)->ACCESS_CTRL16) #define CCM_ACCESS_CTRL16_ROOT_SET_REG(base) ((base)->ACCESS_CTRL16_ROOT_SET) #define CCM_ACCESS_CTRL16_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL16_ROOT_CLR) #define CCM_ACCESS_CTRL16_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL16_ROOT_TOG) #define CCM_TARGET_ROOT17_REG(base) ((base)->TARGET_ROOT17) #define CCM_TARGET_ROOT17_SET_REG(base) ((base)->TARGET_ROOT17_SET) #define CCM_TARGET_ROOT17_CLR_REG(base) ((base)->TARGET_ROOT17_CLR) #define CCM_TARGET_ROOT17_TOG_REG(base) ((base)->TARGET_ROOT17_TOG) #define CCM_POST17_REG(base) ((base)->POST17) #define CCM_POST_ROOT17_SET_REG(base) ((base)->POST_ROOT17_SET) #define CCM_POST_ROOT17_CLR_REG(base) ((base)->POST_ROOT17_CLR) #define CCM_POST_ROOT17_TOG_REG(base) ((base)->POST_ROOT17_TOG) #define CCM_PRE17_REG(base) ((base)->PRE17) #define CCM_PRE_ROOT17_SET_REG(base) ((base)->PRE_ROOT17_SET) #define CCM_PRE_ROOT17_CLR_REG(base) ((base)->PRE_ROOT17_CLR) #define CCM_PRE_ROOT17_TOG_REG(base) ((base)->PRE_ROOT17_TOG) #define CCM_ACCESS_CTRL17_REG(base) ((base)->ACCESS_CTRL17) #define CCM_ACCESS_CTRL17_ROOT_SET_REG(base) ((base)->ACCESS_CTRL17_ROOT_SET) #define CCM_ACCESS_CTRL17_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL17_ROOT_CLR) #define CCM_ACCESS_CTRL17_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL17_ROOT_TOG) #define CCM_TARGET_ROOT18_REG(base) ((base)->TARGET_ROOT18) #define CCM_TARGET_ROOT18_SET_REG(base) ((base)->TARGET_ROOT18_SET) #define CCM_TARGET_ROOT18_CLR_REG(base) ((base)->TARGET_ROOT18_CLR) #define CCM_TARGET_ROOT18_TOG_REG(base) ((base)->TARGET_ROOT18_TOG) #define CCM_POST18_REG(base) ((base)->POST18) #define CCM_POST_ROOT18_SET_REG(base) ((base)->POST_ROOT18_SET) #define CCM_POST_ROOT18_CLR_REG(base) ((base)->POST_ROOT18_CLR) #define CCM_POST_ROOT18_TOG_REG(base) ((base)->POST_ROOT18_TOG) #define CCM_PRE18_REG(base) ((base)->PRE18) #define CCM_PRE_ROOT18_SET_REG(base) ((base)->PRE_ROOT18_SET) #define CCM_PRE_ROOT18_CLR_REG(base) ((base)->PRE_ROOT18_CLR) #define CCM_PRE_ROOT18_TOG_REG(base) ((base)->PRE_ROOT18_TOG) #define CCM_ACCESS_CTRL18_REG(base) ((base)->ACCESS_CTRL18) #define CCM_ACCESS_CTRL18_ROOT_SET_REG(base) ((base)->ACCESS_CTRL18_ROOT_SET) #define CCM_ACCESS_CTRL18_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL18_ROOT_CLR) #define CCM_ACCESS_CTRL18_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL18_ROOT_TOG) #define CCM_TARGET_ROOT19_REG(base) ((base)->TARGET_ROOT19) #define CCM_TARGET_ROOT19_SET_REG(base) ((base)->TARGET_ROOT19_SET) #define CCM_TARGET_ROOT19_CLR_REG(base) ((base)->TARGET_ROOT19_CLR) #define CCM_TARGET_ROOT19_TOG_REG(base) ((base)->TARGET_ROOT19_TOG) #define CCM_POST19_REG(base) ((base)->POST19) #define CCM_POST_ROOT19_SET_REG(base) ((base)->POST_ROOT19_SET) #define CCM_POST_ROOT19_CLR_REG(base) ((base)->POST_ROOT19_CLR) #define CCM_POST_ROOT19_TOG_REG(base) ((base)->POST_ROOT19_TOG) #define CCM_PRE19_REG(base) ((base)->PRE19) #define CCM_PRE_ROOT19_SET_REG(base) ((base)->PRE_ROOT19_SET) #define CCM_PRE_ROOT19_CLR_REG(base) ((base)->PRE_ROOT19_CLR) #define CCM_PRE_ROOT19_TOG_REG(base) ((base)->PRE_ROOT19_TOG) #define CCM_ACCESS_CTRL19_REG(base) ((base)->ACCESS_CTRL19) #define CCM_ACCESS_CTRL19_ROOT_SET_REG(base) ((base)->ACCESS_CTRL19_ROOT_SET) #define CCM_ACCESS_CTRL19_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL19_ROOT_CLR) #define CCM_ACCESS_CTRL19_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL19_ROOT_TOG) #define CCM_TARGET_ROOT20_REG(base) ((base)->TARGET_ROOT20) #define CCM_TARGET_ROOT20_SET_REG(base) ((base)->TARGET_ROOT20_SET) #define CCM_TARGET_ROOT20_CLR_REG(base) ((base)->TARGET_ROOT20_CLR) #define CCM_TARGET_ROOT20_TOG_REG(base) ((base)->TARGET_ROOT20_TOG) #define CCM_POST20_REG(base) ((base)->POST20) #define CCM_POST_ROOT20_SET_REG(base) ((base)->POST_ROOT20_SET) #define CCM_POST_ROOT20_CLR_REG(base) ((base)->POST_ROOT20_CLR) #define CCM_POST_ROOT20_TOG_REG(base) ((base)->POST_ROOT20_TOG) #define CCM_PRE20_REG(base) ((base)->PRE20) #define CCM_PRE_ROOT20_SET_REG(base) ((base)->PRE_ROOT20_SET) #define CCM_PRE_ROOT20_CLR_REG(base) ((base)->PRE_ROOT20_CLR) #define CCM_PRE_ROOT20_TOG_REG(base) ((base)->PRE_ROOT20_TOG) #define CCM_ACCESS_CTRL20_REG(base) ((base)->ACCESS_CTRL20) #define CCM_ACCESS_CTRL20_ROOT_SET_REG(base) ((base)->ACCESS_CTRL20_ROOT_SET) #define CCM_ACCESS_CTRL20_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL20_ROOT_CLR) #define CCM_ACCESS_CTRL20_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL20_ROOT_TOG) #define CCM_TARGET_ROOT21_REG(base) ((base)->TARGET_ROOT21) #define CCM_TARGET_ROOT21_SET_REG(base) ((base)->TARGET_ROOT21_SET) #define CCM_TARGET_ROOT21_CLR_REG(base) ((base)->TARGET_ROOT21_CLR) #define CCM_TARGET_ROOT21_TOG_REG(base) ((base)->TARGET_ROOT21_TOG) #define CCM_POST21_REG(base) ((base)->POST21) #define CCM_POST_ROOT21_SET_REG(base) ((base)->POST_ROOT21_SET) #define CCM_POST_ROOT21_CLR_REG(base) ((base)->POST_ROOT21_CLR) #define CCM_POST_ROOT21_TOG_REG(base) ((base)->POST_ROOT21_TOG) #define CCM_PRE21_REG(base) ((base)->PRE21) #define CCM_PRE_ROOT21_SET_REG(base) ((base)->PRE_ROOT21_SET) #define CCM_PRE_ROOT21_CLR_REG(base) ((base)->PRE_ROOT21_CLR) #define CCM_PRE_ROOT21_TOG_REG(base) ((base)->PRE_ROOT21_TOG) #define CCM_ACCESS_CTRL21_REG(base) ((base)->ACCESS_CTRL21) #define CCM_ACCESS_CTRL21_ROOT_SET_REG(base) ((base)->ACCESS_CTRL21_ROOT_SET) #define CCM_ACCESS_CTRL21_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL21_ROOT_CLR) #define CCM_ACCESS_CTRL21_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL21_ROOT_TOG) #define CCM_TARGET_ROOT22_REG(base) ((base)->TARGET_ROOT22) #define CCM_TARGET_ROOT22_SET_REG(base) ((base)->TARGET_ROOT22_SET) #define CCM_TARGET_ROOT22_CLR_REG(base) ((base)->TARGET_ROOT22_CLR) #define CCM_TARGET_ROOT22_TOG_REG(base) ((base)->TARGET_ROOT22_TOG) #define CCM_POST22_REG(base) ((base)->POST22) #define CCM_POST_ROOT22_SET_REG(base) ((base)->POST_ROOT22_SET) #define CCM_POST_ROOT22_CLR_REG(base) ((base)->POST_ROOT22_CLR) #define CCM_POST_ROOT22_TOG_REG(base) ((base)->POST_ROOT22_TOG) #define CCM_PRE22_REG(base) ((base)->PRE22) #define CCM_PRE_ROOT22_SET_REG(base) ((base)->PRE_ROOT22_SET) #define CCM_PRE_ROOT22_CLR_REG(base) ((base)->PRE_ROOT22_CLR) #define CCM_PRE_ROOT22_TOG_REG(base) ((base)->PRE_ROOT22_TOG) #define CCM_ACCESS_CTRL22_REG(base) ((base)->ACCESS_CTRL22) #define CCM_ACCESS_CTRL22_ROOT_SET_REG(base) ((base)->ACCESS_CTRL22_ROOT_SET) #define CCM_ACCESS_CTRL22_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL22_ROOT_CLR) #define CCM_ACCESS_CTRL22_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL22_ROOT_TOG) #define CCM_TARGET_ROOT23_REG(base) ((base)->TARGET_ROOT23) #define CCM_TARGET_ROOT23_SET_REG(base) ((base)->TARGET_ROOT23_SET) #define CCM_TARGET_ROOT23_CLR_REG(base) ((base)->TARGET_ROOT23_CLR) #define CCM_TARGET_ROOT23_TOG_REG(base) ((base)->TARGET_ROOT23_TOG) #define CCM_POST23_REG(base) ((base)->POST23) #define CCM_POST_ROOT23_SET_REG(base) ((base)->POST_ROOT23_SET) #define CCM_POST_ROOT23_CLR_REG(base) ((base)->POST_ROOT23_CLR) #define CCM_POST_ROOT23_TOG_REG(base) ((base)->POST_ROOT23_TOG) #define CCM_PRE23_REG(base) ((base)->PRE23) #define CCM_PRE_ROOT23_SET_REG(base) ((base)->PRE_ROOT23_SET) #define CCM_PRE_ROOT23_CLR_REG(base) ((base)->PRE_ROOT23_CLR) #define CCM_PRE_ROOT23_TOG_REG(base) ((base)->PRE_ROOT23_TOG) #define CCM_ACCESS_CTRL23_REG(base) ((base)->ACCESS_CTRL23) #define CCM_ACCESS_CTRL23_ROOT_SET_REG(base) ((base)->ACCESS_CTRL23_ROOT_SET) #define CCM_ACCESS_CTRL23_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL23_ROOT_CLR) #define CCM_ACCESS_CTRL23_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL23_ROOT_TOG) #define CCM_TARGET_ROOT24_REG(base) ((base)->TARGET_ROOT24) #define CCM_TARGET_ROOT24_SET_REG(base) ((base)->TARGET_ROOT24_SET) #define CCM_TARGET_ROOT24_CLR_REG(base) ((base)->TARGET_ROOT24_CLR) #define CCM_TARGET_ROOT24_TOG_REG(base) ((base)->TARGET_ROOT24_TOG) #define CCM_POST24_REG(base) ((base)->POST24) #define CCM_POST_ROOT24_SET_REG(base) ((base)->POST_ROOT24_SET) #define CCM_POST_ROOT24_CLR_REG(base) ((base)->POST_ROOT24_CLR) #define CCM_POST_ROOT24_TOG_REG(base) ((base)->POST_ROOT24_TOG) #define CCM_PRE24_REG(base) ((base)->PRE24) #define CCM_PRE_ROOT24_SET_REG(base) ((base)->PRE_ROOT24_SET) #define CCM_PRE_ROOT24_CLR_REG(base) ((base)->PRE_ROOT24_CLR) #define CCM_PRE_ROOT24_TOG_REG(base) ((base)->PRE_ROOT24_TOG) #define CCM_ACCESS_CTRL24_REG(base) ((base)->ACCESS_CTRL24) #define CCM_ACCESS_CTRL24_ROOT_SET_REG(base) ((base)->ACCESS_CTRL24_ROOT_SET) #define CCM_ACCESS_CTRL24_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL24_ROOT_CLR) #define CCM_ACCESS_CTRL24_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL24_ROOT_TOG) #define CCM_TARGET_ROOT25_REG(base) ((base)->TARGET_ROOT25) #define CCM_TARGET_ROOT25_SET_REG(base) ((base)->TARGET_ROOT25_SET) #define CCM_TARGET_ROOT25_CLR_REG(base) ((base)->TARGET_ROOT25_CLR) #define CCM_TARGET_ROOT25_TOG_REG(base) ((base)->TARGET_ROOT25_TOG) #define CCM_POST25_REG(base) ((base)->POST25) #define CCM_POST_ROOT25_SET_REG(base) ((base)->POST_ROOT25_SET) #define CCM_POST_ROOT25_CLR_REG(base) ((base)->POST_ROOT25_CLR) #define CCM_POST_ROOT25_TOG_REG(base) ((base)->POST_ROOT25_TOG) #define CCM_PRE25_REG(base) ((base)->PRE25) #define CCM_PRE_ROOT25_SET_REG(base) ((base)->PRE_ROOT25_SET) #define CCM_PRE_ROOT25_CLR_REG(base) ((base)->PRE_ROOT25_CLR) #define CCM_PRE_ROOT25_TOG_REG(base) ((base)->PRE_ROOT25_TOG) #define CCM_ACCESS_CTRL25_REG(base) ((base)->ACCESS_CTRL25) #define CCM_ACCESS_CTRL25_ROOT_SET_REG(base) ((base)->ACCESS_CTRL25_ROOT_SET) #define CCM_ACCESS_CTRL25_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL25_ROOT_CLR) #define CCM_ACCESS_CTRL25_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL25_ROOT_TOG) #define CCM_TARGET_ROOT26_REG(base) ((base)->TARGET_ROOT26) #define CCM_TARGET_ROOT26_SET_REG(base) ((base)->TARGET_ROOT26_SET) #define CCM_TARGET_ROOT26_CLR_REG(base) ((base)->TARGET_ROOT26_CLR) #define CCM_TARGET_ROOT26_TOG_REG(base) ((base)->TARGET_ROOT26_TOG) #define CCM_POST26_REG(base) ((base)->POST26) #define CCM_POST_ROOT26_SET_REG(base) ((base)->POST_ROOT26_SET) #define CCM_POST_ROOT26_CLR_REG(base) ((base)->POST_ROOT26_CLR) #define CCM_POST_ROOT26_TOG_REG(base) ((base)->POST_ROOT26_TOG) #define CCM_PRE26_REG(base) ((base)->PRE26) #define CCM_PRE_ROOT26_SET_REG(base) ((base)->PRE_ROOT26_SET) #define CCM_PRE_ROOT26_CLR_REG(base) ((base)->PRE_ROOT26_CLR) #define CCM_PRE_ROOT26_TOG_REG(base) ((base)->PRE_ROOT26_TOG) #define CCM_ACCESS_CTRL26_REG(base) ((base)->ACCESS_CTRL26) #define CCM_ACCESS_CTRL26_ROOT_SET_REG(base) ((base)->ACCESS_CTRL26_ROOT_SET) #define CCM_ACCESS_CTRL26_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL26_ROOT_CLR) #define CCM_ACCESS_CTRL26_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL26_ROOT_TOG) #define CCM_TARGET_ROOT27_REG(base) ((base)->TARGET_ROOT27) #define CCM_TARGET_ROOT27_SET_REG(base) ((base)->TARGET_ROOT27_SET) #define CCM_TARGET_ROOT27_CLR_REG(base) ((base)->TARGET_ROOT27_CLR) #define CCM_TARGET_ROOT27_TOG_REG(base) ((base)->TARGET_ROOT27_TOG) #define CCM_POST27_REG(base) ((base)->POST27) #define CCM_POST_ROOT27_SET_REG(base) ((base)->POST_ROOT27_SET) #define CCM_POST_ROOT27_CLR_REG(base) ((base)->POST_ROOT27_CLR) #define CCM_POST_ROOT27_TOG_REG(base) ((base)->POST_ROOT27_TOG) #define CCM_PRE27_REG(base) ((base)->PRE27) #define CCM_PRE_ROOT27_SET_REG(base) ((base)->PRE_ROOT27_SET) #define CCM_PRE_ROOT27_CLR_REG(base) ((base)->PRE_ROOT27_CLR) #define CCM_PRE_ROOT27_TOG_REG(base) ((base)->PRE_ROOT27_TOG) #define CCM_ACCESS_CTRL27_REG(base) ((base)->ACCESS_CTRL27) #define CCM_ACCESS_CTRL27_ROOT_SET_REG(base) ((base)->ACCESS_CTRL27_ROOT_SET) #define CCM_ACCESS_CTRL27_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL27_ROOT_CLR) #define CCM_ACCESS_CTRL27_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL27_ROOT_TOG) #define CCM_TARGET_ROOT28_REG(base) ((base)->TARGET_ROOT28) #define CCM_TARGET_ROOT28_SET_REG(base) ((base)->TARGET_ROOT28_SET) #define CCM_TARGET_ROOT28_CLR_REG(base) ((base)->TARGET_ROOT28_CLR) #define CCM_TARGET_ROOT28_TOG_REG(base) ((base)->TARGET_ROOT28_TOG) #define CCM_POST28_REG(base) ((base)->POST28) #define CCM_POST_ROOT28_SET_REG(base) ((base)->POST_ROOT28_SET) #define CCM_POST_ROOT28_CLR_REG(base) ((base)->POST_ROOT28_CLR) #define CCM_POST_ROOT28_TOG_REG(base) ((base)->POST_ROOT28_TOG) #define CCM_PRE28_REG(base) ((base)->PRE28) #define CCM_PRE_ROOT28_SET_REG(base) ((base)->PRE_ROOT28_SET) #define CCM_PRE_ROOT28_CLR_REG(base) ((base)->PRE_ROOT28_CLR) #define CCM_PRE_ROOT28_TOG_REG(base) ((base)->PRE_ROOT28_TOG) #define CCM_ACCESS_CTRL28_REG(base) ((base)->ACCESS_CTRL28) #define CCM_ACCESS_CTRL28_ROOT_SET_REG(base) ((base)->ACCESS_CTRL28_ROOT_SET) #define CCM_ACCESS_CTRL28_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL28_ROOT_CLR) #define CCM_ACCESS_CTRL28_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL28_ROOT_TOG) #define CCM_TARGET_ROOT29_REG(base) ((base)->TARGET_ROOT29) #define CCM_TARGET_ROOT29_SET_REG(base) ((base)->TARGET_ROOT29_SET) #define CCM_TARGET_ROOT29_CLR_REG(base) ((base)->TARGET_ROOT29_CLR) #define CCM_TARGET_ROOT29_TOG_REG(base) ((base)->TARGET_ROOT29_TOG) #define CCM_POST29_REG(base) ((base)->POST29) #define CCM_POST_ROOT29_SET_REG(base) ((base)->POST_ROOT29_SET) #define CCM_POST_ROOT29_CLR_REG(base) ((base)->POST_ROOT29_CLR) #define CCM_POST_ROOT29_TOG_REG(base) ((base)->POST_ROOT29_TOG) #define CCM_PRE29_REG(base) ((base)->PRE29) #define CCM_PRE_ROOT29_SET_REG(base) ((base)->PRE_ROOT29_SET) #define CCM_PRE_ROOT29_CLR_REG(base) ((base)->PRE_ROOT29_CLR) #define CCM_PRE_ROOT29_TOG_REG(base) ((base)->PRE_ROOT29_TOG) #define CCM_ACCESS_CTRL29_REG(base) ((base)->ACCESS_CTRL29) #define CCM_ACCESS_CTRL29_ROOT_SET_REG(base) ((base)->ACCESS_CTRL29_ROOT_SET) #define CCM_ACCESS_CTRL29_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL29_ROOT_CLR) #define CCM_ACCESS_CTRL29_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL29_ROOT_TOG) #define CCM_TARGET_ROOT30_REG(base) ((base)->TARGET_ROOT30) #define CCM_TARGET_ROOT30_SET_REG(base) ((base)->TARGET_ROOT30_SET) #define CCM_TARGET_ROOT30_CLR_REG(base) ((base)->TARGET_ROOT30_CLR) #define CCM_TARGET_ROOT30_TOG_REG(base) ((base)->TARGET_ROOT30_TOG) #define CCM_POST30_REG(base) ((base)->POST30) #define CCM_POST_ROOT30_SET_REG(base) ((base)->POST_ROOT30_SET) #define CCM_POST_ROOT30_CLR_REG(base) ((base)->POST_ROOT30_CLR) #define CCM_POST_ROOT30_TOG_REG(base) ((base)->POST_ROOT30_TOG) #define CCM_PRE30_REG(base) ((base)->PRE30) #define CCM_PRE_ROOT30_SET_REG(base) ((base)->PRE_ROOT30_SET) #define CCM_PRE_ROOT30_CLR_REG(base) ((base)->PRE_ROOT30_CLR) #define CCM_PRE_ROOT30_TOG_REG(base) ((base)->PRE_ROOT30_TOG) #define CCM_ACCESS_CTRL30_REG(base) ((base)->ACCESS_CTRL30) #define CCM_ACCESS_CTRL30_ROOT_SET_REG(base) ((base)->ACCESS_CTRL30_ROOT_SET) #define CCM_ACCESS_CTRL30_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL30_ROOT_CLR) #define CCM_ACCESS_CTRL30_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL30_ROOT_TOG) #define CCM_TARGET_ROOT31_REG(base) ((base)->TARGET_ROOT31) #define CCM_TARGET_ROOT31_SET_REG(base) ((base)->TARGET_ROOT31_SET) #define CCM_TARGET_ROOT31_CLR_REG(base) ((base)->TARGET_ROOT31_CLR) #define CCM_TARGET_ROOT31_TOG_REG(base) ((base)->TARGET_ROOT31_TOG) #define CCM_POST31_REG(base) ((base)->POST31) #define CCM_POST_ROOT31_SET_REG(base) ((base)->POST_ROOT31_SET) #define CCM_POST_ROOT31_CLR_REG(base) ((base)->POST_ROOT31_CLR) #define CCM_POST_ROOT31_TOG_REG(base) ((base)->POST_ROOT31_TOG) #define CCM_PRE31_REG(base) ((base)->PRE31) #define CCM_PRE_ROOT31_SET_REG(base) ((base)->PRE_ROOT31_SET) #define CCM_PRE_ROOT31_CLR_REG(base) ((base)->PRE_ROOT31_CLR) #define CCM_PRE_ROOT31_TOG_REG(base) ((base)->PRE_ROOT31_TOG) #define CCM_ACCESS_CTRL31_REG(base) ((base)->ACCESS_CTRL31) #define CCM_ACCESS_CTRL31_ROOT_SET_REG(base) ((base)->ACCESS_CTRL31_ROOT_SET) #define CCM_ACCESS_CTRL31_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL31_ROOT_CLR) #define CCM_ACCESS_CTRL31_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL31_ROOT_TOG) #define CCM_TARGET_ROOT32_REG(base) ((base)->TARGET_ROOT32) #define CCM_TARGET_ROOT32_SET_REG(base) ((base)->TARGET_ROOT32_SET) #define CCM_TARGET_ROOT32_CLR_REG(base) ((base)->TARGET_ROOT32_CLR) #define CCM_TARGET_ROOT32_TOG_REG(base) ((base)->TARGET_ROOT32_TOG) #define CCM_POST32_REG(base) ((base)->POST32) #define CCM_POST_ROOT32_SET_REG(base) ((base)->POST_ROOT32_SET) #define CCM_POST_ROOT32_CLR_REG(base) ((base)->POST_ROOT32_CLR) #define CCM_POST_ROOT32_TOG_REG(base) ((base)->POST_ROOT32_TOG) #define CCM_PRE32_REG(base) ((base)->PRE32) #define CCM_PRE_ROOT32_SET_REG(base) ((base)->PRE_ROOT32_SET) #define CCM_PRE_ROOT32_CLR_REG(base) ((base)->PRE_ROOT32_CLR) #define CCM_PRE_ROOT32_TOG_REG(base) ((base)->PRE_ROOT32_TOG) #define CCM_ACCESS_CTRL32_REG(base) ((base)->ACCESS_CTRL32) #define CCM_ACCESS_CTRL32_ROOT_SET_REG(base) ((base)->ACCESS_CTRL32_ROOT_SET) #define CCM_ACCESS_CTRL32_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL32_ROOT_CLR) #define CCM_ACCESS_CTRL32_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL32_ROOT_TOG) #define CCM_TARGET_ROOT33_REG(base) ((base)->TARGET_ROOT33) #define CCM_TARGET_ROOT33_SET_REG(base) ((base)->TARGET_ROOT33_SET) #define CCM_TARGET_ROOT33_CLR_REG(base) ((base)->TARGET_ROOT33_CLR) #define CCM_TARGET_ROOT33_TOG_REG(base) ((base)->TARGET_ROOT33_TOG) #define CCM_POST33_REG(base) ((base)->POST33) #define CCM_POST_ROOT33_SET_REG(base) ((base)->POST_ROOT33_SET) #define CCM_POST_ROOT33_CLR_REG(base) ((base)->POST_ROOT33_CLR) #define CCM_POST_ROOT33_TOG_REG(base) ((base)->POST_ROOT33_TOG) #define CCM_PRE33_REG(base) ((base)->PRE33) #define CCM_PRE_ROOT33_SET_REG(base) ((base)->PRE_ROOT33_SET) #define CCM_PRE_ROOT33_CLR_REG(base) ((base)->PRE_ROOT33_CLR) #define CCM_PRE_ROOT33_TOG_REG(base) ((base)->PRE_ROOT33_TOG) #define CCM_ACCESS_CTRL33_REG(base) ((base)->ACCESS_CTRL33) #define CCM_ACCESS_CTRL33_ROOT_SET_REG(base) ((base)->ACCESS_CTRL33_ROOT_SET) #define CCM_ACCESS_CTRL33_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL33_ROOT_CLR) #define CCM_ACCESS_CTRL33_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL33_ROOT_TOG) #define CCM_TARGET_ROOT34_REG(base) ((base)->TARGET_ROOT34) #define CCM_TARGET_ROOT34_SET_REG(base) ((base)->TARGET_ROOT34_SET) #define CCM_TARGET_ROOT34_CLR_REG(base) ((base)->TARGET_ROOT34_CLR) #define CCM_TARGET_ROOT34_TOG_REG(base) ((base)->TARGET_ROOT34_TOG) #define CCM_POST34_REG(base) ((base)->POST34) #define CCM_POST_ROOT34_SET_REG(base) ((base)->POST_ROOT34_SET) #define CCM_POST_ROOT34_CLR_REG(base) ((base)->POST_ROOT34_CLR) #define CCM_POST_ROOT34_TOG_REG(base) ((base)->POST_ROOT34_TOG) #define CCM_PRE34_REG(base) ((base)->PRE34) #define CCM_PRE_ROOT34_SET_REG(base) ((base)->PRE_ROOT34_SET) #define CCM_PRE_ROOT34_CLR_REG(base) ((base)->PRE_ROOT34_CLR) #define CCM_PRE_ROOT34_TOG_REG(base) ((base)->PRE_ROOT34_TOG) #define CCM_ACCESS_CTRL34_REG(base) ((base)->ACCESS_CTRL34) #define CCM_ACCESS_CTRL34_ROOT_SET_REG(base) ((base)->ACCESS_CTRL34_ROOT_SET) #define CCM_ACCESS_CTRL34_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL34_ROOT_CLR) #define CCM_ACCESS_CTRL34_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL34_ROOT_TOG) #define CCM_TARGET_ROOT35_REG(base) ((base)->TARGET_ROOT35) #define CCM_TARGET_ROOT35_SET_REG(base) ((base)->TARGET_ROOT35_SET) #define CCM_TARGET_ROOT35_CLR_REG(base) ((base)->TARGET_ROOT35_CLR) #define CCM_TARGET_ROOT35_TOG_REG(base) ((base)->TARGET_ROOT35_TOG) #define CCM_POST35_REG(base) ((base)->POST35) #define CCM_POST_ROOT35_SET_REG(base) ((base)->POST_ROOT35_SET) #define CCM_POST_ROOT35_CLR_REG(base) ((base)->POST_ROOT35_CLR) #define CCM_POST_ROOT35_TOG_REG(base) ((base)->POST_ROOT35_TOG) #define CCM_PRE35_REG(base) ((base)->PRE35) #define CCM_PRE_ROOT35_SET_REG(base) ((base)->PRE_ROOT35_SET) #define CCM_PRE_ROOT35_CLR_REG(base) ((base)->PRE_ROOT35_CLR) #define CCM_PRE_ROOT35_TOG_REG(base) ((base)->PRE_ROOT35_TOG) #define CCM_ACCESS_CTRL35_REG(base) ((base)->ACCESS_CTRL35) #define CCM_ACCESS_CTRL35_ROOT_SET_REG(base) ((base)->ACCESS_CTRL35_ROOT_SET) #define CCM_ACCESS_CTRL35_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL35_ROOT_CLR) #define CCM_ACCESS_CTRL35_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL35_ROOT_TOG) #define CCM_TARGET_ROOT36_REG(base) ((base)->TARGET_ROOT36) #define CCM_TARGET_ROOT36_SET_REG(base) ((base)->TARGET_ROOT36_SET) #define CCM_TARGET_ROOT36_CLR_REG(base) ((base)->TARGET_ROOT36_CLR) #define CCM_TARGET_ROOT36_TOG_REG(base) ((base)->TARGET_ROOT36_TOG) #define CCM_POST36_REG(base) ((base)->POST36) #define CCM_POST_ROOT36_SET_REG(base) ((base)->POST_ROOT36_SET) #define CCM_POST_ROOT36_CLR_REG(base) ((base)->POST_ROOT36_CLR) #define CCM_POST_ROOT36_TOG_REG(base) ((base)->POST_ROOT36_TOG) #define CCM_PRE36_REG(base) ((base)->PRE36) #define CCM_PRE_ROOT36_SET_REG(base) ((base)->PRE_ROOT36_SET) #define CCM_PRE_ROOT36_CLR_REG(base) ((base)->PRE_ROOT36_CLR) #define CCM_PRE_ROOT36_TOG_REG(base) ((base)->PRE_ROOT36_TOG) #define CCM_ACCESS_CTRL36_REG(base) ((base)->ACCESS_CTRL36) #define CCM_ACCESS_CTRL36_ROOT_SET_REG(base) ((base)->ACCESS_CTRL36_ROOT_SET) #define CCM_ACCESS_CTRL36_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL36_ROOT_CLR) #define CCM_ACCESS_CTRL36_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL36_ROOT_TOG) #define CCM_TARGET_ROOT37_REG(base) ((base)->TARGET_ROOT37) #define CCM_TARGET_ROOT37_SET_REG(base) ((base)->TARGET_ROOT37_SET) #define CCM_TARGET_ROOT37_CLR_REG(base) ((base)->TARGET_ROOT37_CLR) #define CCM_TARGET_ROOT37_TOG_REG(base) ((base)->TARGET_ROOT37_TOG) #define CCM_POST37_REG(base) ((base)->POST37) #define CCM_POST_ROOT37_SET_REG(base) ((base)->POST_ROOT37_SET) #define CCM_POST_ROOT37_CLR_REG(base) ((base)->POST_ROOT37_CLR) #define CCM_POST_ROOT37_TOG_REG(base) ((base)->POST_ROOT37_TOG) #define CCM_PRE37_REG(base) ((base)->PRE37) #define CCM_PRE_ROOT37_SET_REG(base) ((base)->PRE_ROOT37_SET) #define CCM_PRE_ROOT37_CLR_REG(base) ((base)->PRE_ROOT37_CLR) #define CCM_PRE_ROOT37_TOG_REG(base) ((base)->PRE_ROOT37_TOG) #define CCM_ACCESS_CTRL37_REG(base) ((base)->ACCESS_CTRL37) #define CCM_ACCESS_CTRL37_ROOT_SET_REG(base) ((base)->ACCESS_CTRL37_ROOT_SET) #define CCM_ACCESS_CTRL37_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL37_ROOT_CLR) #define CCM_ACCESS_CTRL37_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL37_ROOT_TOG) #define CCM_TARGET_ROOT38_REG(base) ((base)->TARGET_ROOT38) #define CCM_TARGET_ROOT38_SET_REG(base) ((base)->TARGET_ROOT38_SET) #define CCM_TARGET_ROOT38_CLR_REG(base) ((base)->TARGET_ROOT38_CLR) #define CCM_TARGET_ROOT38_TOG_REG(base) ((base)->TARGET_ROOT38_TOG) #define CCM_POST38_REG(base) ((base)->POST38) #define CCM_POST_ROOT38_SET_REG(base) ((base)->POST_ROOT38_SET) #define CCM_POST_ROOT38_CLR_REG(base) ((base)->POST_ROOT38_CLR) #define CCM_POST_ROOT38_TOG_REG(base) ((base)->POST_ROOT38_TOG) #define CCM_PRE38_REG(base) ((base)->PRE38) #define CCM_PRE_ROOT38_SET_REG(base) ((base)->PRE_ROOT38_SET) #define CCM_PRE_ROOT38_CLR_REG(base) ((base)->PRE_ROOT38_CLR) #define CCM_PRE_ROOT38_TOG_REG(base) ((base)->PRE_ROOT38_TOG) #define CCM_ACCESS_CTRL38_REG(base) ((base)->ACCESS_CTRL38) #define CCM_ACCESS_CTRL38_ROOT_SET_REG(base) ((base)->ACCESS_CTRL38_ROOT_SET) #define CCM_ACCESS_CTRL38_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL38_ROOT_CLR) #define CCM_ACCESS_CTRL38_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL38_ROOT_TOG) #define CCM_TARGET_ROOT39_REG(base) ((base)->TARGET_ROOT39) #define CCM_TARGET_ROOT39_SET_REG(base) ((base)->TARGET_ROOT39_SET) #define CCM_TARGET_ROOT39_CLR_REG(base) ((base)->TARGET_ROOT39_CLR) #define CCM_TARGET_ROOT39_TOG_REG(base) ((base)->TARGET_ROOT39_TOG) #define CCM_POST39_REG(base) ((base)->POST39) #define CCM_POST_ROOT39_SET_REG(base) ((base)->POST_ROOT39_SET) #define CCM_POST_ROOT39_CLR_REG(base) ((base)->POST_ROOT39_CLR) #define CCM_POST_ROOT39_TOG_REG(base) ((base)->POST_ROOT39_TOG) #define CCM_PRE39_REG(base) ((base)->PRE39) #define CCM_PRE_ROOT39_SET_REG(base) ((base)->PRE_ROOT39_SET) #define CCM_PRE_ROOT39_CLR_REG(base) ((base)->PRE_ROOT39_CLR) #define CCM_PRE_ROOT39_TOG_REG(base) ((base)->PRE_ROOT39_TOG) #define CCM_ACCESS_CTRL39_REG(base) ((base)->ACCESS_CTRL39) #define CCM_ACCESS_CTRL39_ROOT_SET_REG(base) ((base)->ACCESS_CTRL39_ROOT_SET) #define CCM_ACCESS_CTRL39_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL39_ROOT_CLR) #define CCM_ACCESS_CTRL39_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL39_ROOT_TOG) #define CCM_TARGET_ROOT40_REG(base) ((base)->TARGET_ROOT40) #define CCM_TARGET_ROOT40_SET_REG(base) ((base)->TARGET_ROOT40_SET) #define CCM_TARGET_ROOT40_CLR_REG(base) ((base)->TARGET_ROOT40_CLR) #define CCM_TARGET_ROOT40_TOG_REG(base) ((base)->TARGET_ROOT40_TOG) #define CCM_POST40_REG(base) ((base)->POST40) #define CCM_POST_ROOT40_SET_REG(base) ((base)->POST_ROOT40_SET) #define CCM_POST_ROOT40_CLR_REG(base) ((base)->POST_ROOT40_CLR) #define CCM_POST_ROOT40_TOG_REG(base) ((base)->POST_ROOT40_TOG) #define CCM_PRE40_REG(base) ((base)->PRE40) #define CCM_PRE_ROOT40_SET_REG(base) ((base)->PRE_ROOT40_SET) #define CCM_PRE_ROOT40_CLR_REG(base) ((base)->PRE_ROOT40_CLR) #define CCM_PRE_ROOT40_TOG_REG(base) ((base)->PRE_ROOT40_TOG) #define CCM_ACCESS_CTRL40_REG(base) ((base)->ACCESS_CTRL40) #define CCM_ACCESS_CTRL40_ROOT_SET_REG(base) ((base)->ACCESS_CTRL40_ROOT_SET) #define CCM_ACCESS_CTRL40_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL40_ROOT_CLR) #define CCM_ACCESS_CTRL40_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL40_ROOT_TOG) #define CCM_TARGET_ROOT41_REG(base) ((base)->TARGET_ROOT41) #define CCM_TARGET_ROOT41_SET_REG(base) ((base)->TARGET_ROOT41_SET) #define CCM_TARGET_ROOT41_CLR_REG(base) ((base)->TARGET_ROOT41_CLR) #define CCM_TARGET_ROOT41_TOG_REG(base) ((base)->TARGET_ROOT41_TOG) #define CCM_POST41_REG(base) ((base)->POST41) #define CCM_POST_ROOT41_SET_REG(base) ((base)->POST_ROOT41_SET) #define CCM_POST_ROOT41_CLR_REG(base) ((base)->POST_ROOT41_CLR) #define CCM_POST_ROOT41_TOG_REG(base) ((base)->POST_ROOT41_TOG) #define CCM_PRE41_REG(base) ((base)->PRE41) #define CCM_PRE_ROOT41_SET_REG(base) ((base)->PRE_ROOT41_SET) #define CCM_PRE_ROOT41_CLR_REG(base) ((base)->PRE_ROOT41_CLR) #define CCM_PRE_ROOT41_TOG_REG(base) ((base)->PRE_ROOT41_TOG) #define CCM_ACCESS_CTRL41_REG(base) ((base)->ACCESS_CTRL41) #define CCM_ACCESS_CTRL41_ROOT_SET_REG(base) ((base)->ACCESS_CTRL41_ROOT_SET) #define CCM_ACCESS_CTRL41_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL41_ROOT_CLR) #define CCM_ACCESS_CTRL41_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL41_ROOT_TOG) #define CCM_TARGET_ROOT42_REG(base) ((base)->TARGET_ROOT42) #define CCM_TARGET_ROOT42_SET_REG(base) ((base)->TARGET_ROOT42_SET) #define CCM_TARGET_ROOT42_CLR_REG(base) ((base)->TARGET_ROOT42_CLR) #define CCM_TARGET_ROOT42_TOG_REG(base) ((base)->TARGET_ROOT42_TOG) #define CCM_POST42_REG(base) ((base)->POST42) #define CCM_POST_ROOT42_SET_REG(base) ((base)->POST_ROOT42_SET) #define CCM_POST_ROOT42_CLR_REG(base) ((base)->POST_ROOT42_CLR) #define CCM_POST_ROOT42_TOG_REG(base) ((base)->POST_ROOT42_TOG) #define CCM_PRE42_REG(base) ((base)->PRE42) #define CCM_PRE_ROOT42_SET_REG(base) ((base)->PRE_ROOT42_SET) #define CCM_PRE_ROOT42_CLR_REG(base) ((base)->PRE_ROOT42_CLR) #define CCM_PRE_ROOT42_TOG_REG(base) ((base)->PRE_ROOT42_TOG) #define CCM_ACCESS_CTRL42_REG(base) ((base)->ACCESS_CTRL42) #define CCM_ACCESS_CTRL42_ROOT_SET_REG(base) ((base)->ACCESS_CTRL42_ROOT_SET) #define CCM_ACCESS_CTRL42_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL42_ROOT_CLR) #define CCM_ACCESS_CTRL42_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL42_ROOT_TOG) #define CCM_TARGET_ROOT43_REG(base) ((base)->TARGET_ROOT43) #define CCM_TARGET_ROOT43_SET_REG(base) ((base)->TARGET_ROOT43_SET) #define CCM_TARGET_ROOT43_CLR_REG(base) ((base)->TARGET_ROOT43_CLR) #define CCM_TARGET_ROOT43_TOG_REG(base) ((base)->TARGET_ROOT43_TOG) #define CCM_POST43_REG(base) ((base)->POST43) #define CCM_POST_ROOT43_SET_REG(base) ((base)->POST_ROOT43_SET) #define CCM_POST_ROOT43_CLR_REG(base) ((base)->POST_ROOT43_CLR) #define CCM_POST_ROOT43_TOG_REG(base) ((base)->POST_ROOT43_TOG) #define CCM_PRE43_REG(base) ((base)->PRE43) #define CCM_PRE_ROOT43_SET_REG(base) ((base)->PRE_ROOT43_SET) #define CCM_PRE_ROOT43_CLR_REG(base) ((base)->PRE_ROOT43_CLR) #define CCM_PRE_ROOT43_TOG_REG(base) ((base)->PRE_ROOT43_TOG) #define CCM_ACCESS_CTRL43_REG(base) ((base)->ACCESS_CTRL43) #define CCM_ACCESS_CTRL43_ROOT_SET_REG(base) ((base)->ACCESS_CTRL43_ROOT_SET) #define CCM_ACCESS_CTRL43_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL43_ROOT_CLR) #define CCM_ACCESS_CTRL43_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL43_ROOT_TOG) #define CCM_TARGET_ROOT44_REG(base) ((base)->TARGET_ROOT44) #define CCM_TARGET_ROOT44_SET_REG(base) ((base)->TARGET_ROOT44_SET) #define CCM_TARGET_ROOT44_CLR_REG(base) ((base)->TARGET_ROOT44_CLR) #define CCM_TARGET_ROOT44_TOG_REG(base) ((base)->TARGET_ROOT44_TOG) #define CCM_POST44_REG(base) ((base)->POST44) #define CCM_POST_ROOT44_SET_REG(base) ((base)->POST_ROOT44_SET) #define CCM_POST_ROOT44_CLR_REG(base) ((base)->POST_ROOT44_CLR) #define CCM_POST_ROOT44_TOG_REG(base) ((base)->POST_ROOT44_TOG) #define CCM_PRE44_REG(base) ((base)->PRE44) #define CCM_PRE_ROOT44_SET_REG(base) ((base)->PRE_ROOT44_SET) #define CCM_PRE_ROOT44_CLR_REG(base) ((base)->PRE_ROOT44_CLR) #define CCM_PRE_ROOT44_TOG_REG(base) ((base)->PRE_ROOT44_TOG) #define CCM_ACCESS_CTRL44_REG(base) ((base)->ACCESS_CTRL44) #define CCM_ACCESS_CTRL44_ROOT_SET_REG(base) ((base)->ACCESS_CTRL44_ROOT_SET) #define CCM_ACCESS_CTRL44_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL44_ROOT_CLR) #define CCM_ACCESS_CTRL44_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL44_ROOT_TOG) #define CCM_TARGET_ROOT45_REG(base) ((base)->TARGET_ROOT45) #define CCM_TARGET_ROOT45_SET_REG(base) ((base)->TARGET_ROOT45_SET) #define CCM_TARGET_ROOT45_CLR_REG(base) ((base)->TARGET_ROOT45_CLR) #define CCM_TARGET_ROOT45_TOG_REG(base) ((base)->TARGET_ROOT45_TOG) #define CCM_POST45_REG(base) ((base)->POST45) #define CCM_POST_ROOT45_SET_REG(base) ((base)->POST_ROOT45_SET) #define CCM_POST_ROOT45_CLR_REG(base) ((base)->POST_ROOT45_CLR) #define CCM_POST_ROOT45_TOG_REG(base) ((base)->POST_ROOT45_TOG) #define CCM_PRE45_REG(base) ((base)->PRE45) #define CCM_PRE_ROOT45_SET_REG(base) ((base)->PRE_ROOT45_SET) #define CCM_PRE_ROOT45_CLR_REG(base) ((base)->PRE_ROOT45_CLR) #define CCM_PRE_ROOT45_TOG_REG(base) ((base)->PRE_ROOT45_TOG) #define CCM_ACCESS_CTRL45_REG(base) ((base)->ACCESS_CTRL45) #define CCM_ACCESS_CTRL45_ROOT_SET_REG(base) ((base)->ACCESS_CTRL45_ROOT_SET) #define CCM_ACCESS_CTRL45_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL45_ROOT_CLR) #define CCM_ACCESS_CTRL45_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL45_ROOT_TOG) #define CCM_TARGET_ROOT46_REG(base) ((base)->TARGET_ROOT46) #define CCM_TARGET_ROOT46_SET_REG(base) ((base)->TARGET_ROOT46_SET) #define CCM_TARGET_ROOT46_CLR_REG(base) ((base)->TARGET_ROOT46_CLR) #define CCM_TARGET_ROOT46_TOG_REG(base) ((base)->TARGET_ROOT46_TOG) #define CCM_POST46_REG(base) ((base)->POST46) #define CCM_POST_ROOT46_SET_REG(base) ((base)->POST_ROOT46_SET) #define CCM_POST_ROOT46_CLR_REG(base) ((base)->POST_ROOT46_CLR) #define CCM_POST_ROOT46_TOG_REG(base) ((base)->POST_ROOT46_TOG) #define CCM_PRE46_REG(base) ((base)->PRE46) #define CCM_PRE_ROOT46_SET_REG(base) ((base)->PRE_ROOT46_SET) #define CCM_PRE_ROOT46_CLR_REG(base) ((base)->PRE_ROOT46_CLR) #define CCM_PRE_ROOT46_TOG_REG(base) ((base)->PRE_ROOT46_TOG) #define CCM_ACCESS_CTRL46_REG(base) ((base)->ACCESS_CTRL46) #define CCM_ACCESS_CTRL46_ROOT_SET_REG(base) ((base)->ACCESS_CTRL46_ROOT_SET) #define CCM_ACCESS_CTRL46_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL46_ROOT_CLR) #define CCM_ACCESS_CTRL46_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL46_ROOT_TOG) #define CCM_TARGET_ROOT47_REG(base) ((base)->TARGET_ROOT47) #define CCM_TARGET_ROOT47_SET_REG(base) ((base)->TARGET_ROOT47_SET) #define CCM_TARGET_ROOT47_CLR_REG(base) ((base)->TARGET_ROOT47_CLR) #define CCM_TARGET_ROOT47_TOG_REG(base) ((base)->TARGET_ROOT47_TOG) #define CCM_POST47_REG(base) ((base)->POST47) #define CCM_POST_ROOT47_SET_REG(base) ((base)->POST_ROOT47_SET) #define CCM_POST_ROOT47_CLR_REG(base) ((base)->POST_ROOT47_CLR) #define CCM_POST_ROOT47_TOG_REG(base) ((base)->POST_ROOT47_TOG) #define CCM_PRE47_REG(base) ((base)->PRE47) #define CCM_PRE_ROOT47_SET_REG(base) ((base)->PRE_ROOT47_SET) #define CCM_PRE_ROOT47_CLR_REG(base) ((base)->PRE_ROOT47_CLR) #define CCM_PRE_ROOT47_TOG_REG(base) ((base)->PRE_ROOT47_TOG) #define CCM_ACCESS_CTRL47_REG(base) ((base)->ACCESS_CTRL47) #define CCM_ACCESS_CTRL47_ROOT_SET_REG(base) ((base)->ACCESS_CTRL47_ROOT_SET) #define CCM_ACCESS_CTRL47_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL47_ROOT_CLR) #define CCM_ACCESS_CTRL47_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL47_ROOT_TOG) #define CCM_TARGET_ROOT48_REG(base) ((base)->TARGET_ROOT48) #define CCM_TARGET_ROOT48_SET_REG(base) ((base)->TARGET_ROOT48_SET) #define CCM_TARGET_ROOT48_CLR_REG(base) ((base)->TARGET_ROOT48_CLR) #define CCM_TARGET_ROOT48_TOG_REG(base) ((base)->TARGET_ROOT48_TOG) #define CCM_POST48_REG(base) ((base)->POST48) #define CCM_POST_ROOT48_SET_REG(base) ((base)->POST_ROOT48_SET) #define CCM_POST_ROOT48_CLR_REG(base) ((base)->POST_ROOT48_CLR) #define CCM_POST_ROOT48_TOG_REG(base) ((base)->POST_ROOT48_TOG) #define CCM_PRE48_REG(base) ((base)->PRE48) #define CCM_PRE_ROOT48_SET_REG(base) ((base)->PRE_ROOT48_SET) #define CCM_PRE_ROOT48_CLR_REG(base) ((base)->PRE_ROOT48_CLR) #define CCM_PRE_ROOT48_TOG_REG(base) ((base)->PRE_ROOT48_TOG) #define CCM_ACCESS_CTRL48_REG(base) ((base)->ACCESS_CTRL48) #define CCM_ACCESS_CTRL48_ROOT_SET_REG(base) ((base)->ACCESS_CTRL48_ROOT_SET) #define CCM_ACCESS_CTRL48_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL48_ROOT_CLR) #define CCM_ACCESS_CTRL48_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL48_ROOT_TOG) #define CCM_TARGET_ROOT49_REG(base) ((base)->TARGET_ROOT49) #define CCM_TARGET_ROOT49_SET_REG(base) ((base)->TARGET_ROOT49_SET) #define CCM_TARGET_ROOT49_CLR_REG(base) ((base)->TARGET_ROOT49_CLR) #define CCM_TARGET_ROOT49_TOG_REG(base) ((base)->TARGET_ROOT49_TOG) #define CCM_POST49_REG(base) ((base)->POST49) #define CCM_POST_ROOT49_SET_REG(base) ((base)->POST_ROOT49_SET) #define CCM_POST_ROOT49_CLR_REG(base) ((base)->POST_ROOT49_CLR) #define CCM_POST_ROOT49_TOG_REG(base) ((base)->POST_ROOT49_TOG) #define CCM_PRE49_REG(base) ((base)->PRE49) #define CCM_PRE_ROOT49_SET_REG(base) ((base)->PRE_ROOT49_SET) #define CCM_PRE_ROOT49_CLR_REG(base) ((base)->PRE_ROOT49_CLR) #define CCM_PRE_ROOT49_TOG_REG(base) ((base)->PRE_ROOT49_TOG) #define CCM_ACCESS_CTRL49_REG(base) ((base)->ACCESS_CTRL49) #define CCM_ACCESS_CTRL49_ROOT_SET_REG(base) ((base)->ACCESS_CTRL49_ROOT_SET) #define CCM_ACCESS_CTRL49_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL49_ROOT_CLR) #define CCM_ACCESS_CTRL49_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL49_ROOT_TOG) #define CCM_TARGET_ROOT50_REG(base) ((base)->TARGET_ROOT50) #define CCM_TARGET_ROOT50_SET_REG(base) ((base)->TARGET_ROOT50_SET) #define CCM_TARGET_ROOT50_CLR_REG(base) ((base)->TARGET_ROOT50_CLR) #define CCM_TARGET_ROOT50_TOG_REG(base) ((base)->TARGET_ROOT50_TOG) #define CCM_POST50_REG(base) ((base)->POST50) #define CCM_POST_ROOT50_SET_REG(base) ((base)->POST_ROOT50_SET) #define CCM_POST_ROOT50_CLR_REG(base) ((base)->POST_ROOT50_CLR) #define CCM_POST_ROOT50_TOG_REG(base) ((base)->POST_ROOT50_TOG) #define CCM_PRE50_REG(base) ((base)->PRE50) #define CCM_PRE_ROOT50_SET_REG(base) ((base)->PRE_ROOT50_SET) #define CCM_PRE_ROOT50_CLR_REG(base) ((base)->PRE_ROOT50_CLR) #define CCM_PRE_ROOT50_TOG_REG(base) ((base)->PRE_ROOT50_TOG) #define CCM_ACCESS_CTRL50_REG(base) ((base)->ACCESS_CTRL50) #define CCM_ACCESS_CTRL50_ROOT_SET_REG(base) ((base)->ACCESS_CTRL50_ROOT_SET) #define CCM_ACCESS_CTRL50_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL50_ROOT_CLR) #define CCM_ACCESS_CTRL50_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL50_ROOT_TOG) #define CCM_TARGET_ROOT51_REG(base) ((base)->TARGET_ROOT51) #define CCM_TARGET_ROOT51_SET_REG(base) ((base)->TARGET_ROOT51_SET) #define CCM_TARGET_ROOT51_CLR_REG(base) ((base)->TARGET_ROOT51_CLR) #define CCM_TARGET_ROOT51_TOG_REG(base) ((base)->TARGET_ROOT51_TOG) #define CCM_POST51_REG(base) ((base)->POST51) #define CCM_POST_ROOT51_SET_REG(base) ((base)->POST_ROOT51_SET) #define CCM_POST_ROOT51_CLR_REG(base) ((base)->POST_ROOT51_CLR) #define CCM_POST_ROOT51_TOG_REG(base) ((base)->POST_ROOT51_TOG) #define CCM_PRE51_REG(base) ((base)->PRE51) #define CCM_PRE_ROOT51_SET_REG(base) ((base)->PRE_ROOT51_SET) #define CCM_PRE_ROOT51_CLR_REG(base) ((base)->PRE_ROOT51_CLR) #define CCM_PRE_ROOT51_TOG_REG(base) ((base)->PRE_ROOT51_TOG) #define CCM_ACCESS_CTRL51_REG(base) ((base)->ACCESS_CTRL51) #define CCM_ACCESS_CTRL51_ROOT_SET_REG(base) ((base)->ACCESS_CTRL51_ROOT_SET) #define CCM_ACCESS_CTRL51_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL51_ROOT_CLR) #define CCM_ACCESS_CTRL51_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL51_ROOT_TOG) #define CCM_TARGET_ROOT52_REG(base) ((base)->TARGET_ROOT52) #define CCM_TARGET_ROOT52_SET_REG(base) ((base)->TARGET_ROOT52_SET) #define CCM_TARGET_ROOT52_CLR_REG(base) ((base)->TARGET_ROOT52_CLR) #define CCM_TARGET_ROOT52_TOG_REG(base) ((base)->TARGET_ROOT52_TOG) #define CCM_POST52_REG(base) ((base)->POST52) #define CCM_POST_ROOT52_SET_REG(base) ((base)->POST_ROOT52_SET) #define CCM_POST_ROOT52_CLR_REG(base) ((base)->POST_ROOT52_CLR) #define CCM_POST_ROOT52_TOG_REG(base) ((base)->POST_ROOT52_TOG) #define CCM_PRE52_REG(base) ((base)->PRE52) #define CCM_PRE_ROOT52_SET_REG(base) ((base)->PRE_ROOT52_SET) #define CCM_PRE_ROOT52_CLR_REG(base) ((base)->PRE_ROOT52_CLR) #define CCM_PRE_ROOT52_TOG_REG(base) ((base)->PRE_ROOT52_TOG) #define CCM_ACCESS_CTRL52_REG(base) ((base)->ACCESS_CTRL52) #define CCM_ACCESS_CTRL52_ROOT_SET_REG(base) ((base)->ACCESS_CTRL52_ROOT_SET) #define CCM_ACCESS_CTRL52_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL52_ROOT_CLR) #define CCM_ACCESS_CTRL52_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL52_ROOT_TOG) #define CCM_TARGET_ROOT53_REG(base) ((base)->TARGET_ROOT53) #define CCM_TARGET_ROOT53_SET_REG(base) ((base)->TARGET_ROOT53_SET) #define CCM_TARGET_ROOT53_CLR_REG(base) ((base)->TARGET_ROOT53_CLR) #define CCM_TARGET_ROOT53_TOG_REG(base) ((base)->TARGET_ROOT53_TOG) #define CCM_POST53_REG(base) ((base)->POST53) #define CCM_POST_ROOT53_SET_REG(base) ((base)->POST_ROOT53_SET) #define CCM_POST_ROOT53_CLR_REG(base) ((base)->POST_ROOT53_CLR) #define CCM_POST_ROOT53_TOG_REG(base) ((base)->POST_ROOT53_TOG) #define CCM_PRE53_REG(base) ((base)->PRE53) #define CCM_PRE_ROOT53_SET_REG(base) ((base)->PRE_ROOT53_SET) #define CCM_PRE_ROOT53_CLR_REG(base) ((base)->PRE_ROOT53_CLR) #define CCM_PRE_ROOT53_TOG_REG(base) ((base)->PRE_ROOT53_TOG) #define CCM_ACCESS_CTRL53_REG(base) ((base)->ACCESS_CTRL53) #define CCM_ACCESS_CTRL53_ROOT_SET_REG(base) ((base)->ACCESS_CTRL53_ROOT_SET) #define CCM_ACCESS_CTRL53_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL53_ROOT_CLR) #define CCM_ACCESS_CTRL53_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL53_ROOT_TOG) #define CCM_TARGET_ROOT54_REG(base) ((base)->TARGET_ROOT54) #define CCM_TARGET_ROOT54_SET_REG(base) ((base)->TARGET_ROOT54_SET) #define CCM_TARGET_ROOT54_CLR_REG(base) ((base)->TARGET_ROOT54_CLR) #define CCM_TARGET_ROOT54_TOG_REG(base) ((base)->TARGET_ROOT54_TOG) #define CCM_POST54_REG(base) ((base)->POST54) #define CCM_POST_ROOT54_SET_REG(base) ((base)->POST_ROOT54_SET) #define CCM_POST_ROOT54_CLR_REG(base) ((base)->POST_ROOT54_CLR) #define CCM_POST_ROOT54_TOG_REG(base) ((base)->POST_ROOT54_TOG) #define CCM_PRE54_REG(base) ((base)->PRE54) #define CCM_PRE_ROOT54_SET_REG(base) ((base)->PRE_ROOT54_SET) #define CCM_PRE_ROOT54_CLR_REG(base) ((base)->PRE_ROOT54_CLR) #define CCM_PRE_ROOT54_TOG_REG(base) ((base)->PRE_ROOT54_TOG) #define CCM_ACCESS_CTRL54_REG(base) ((base)->ACCESS_CTRL54) #define CCM_ACCESS_CTRL54_ROOT_SET_REG(base) ((base)->ACCESS_CTRL54_ROOT_SET) #define CCM_ACCESS_CTRL54_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL54_ROOT_CLR) #define CCM_ACCESS_CTRL54_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL54_ROOT_TOG) #define CCM_TARGET_ROOT55_REG(base) ((base)->TARGET_ROOT55) #define CCM_TARGET_ROOT55_SET_REG(base) ((base)->TARGET_ROOT55_SET) #define CCM_TARGET_ROOT55_CLR_REG(base) ((base)->TARGET_ROOT55_CLR) #define CCM_TARGET_ROOT55_TOG_REG(base) ((base)->TARGET_ROOT55_TOG) #define CCM_POST55_REG(base) ((base)->POST55) #define CCM_POST_ROOT55_SET_REG(base) ((base)->POST_ROOT55_SET) #define CCM_POST_ROOT55_CLR_REG(base) ((base)->POST_ROOT55_CLR) #define CCM_POST_ROOT55_TOG_REG(base) ((base)->POST_ROOT55_TOG) #define CCM_PRE55_REG(base) ((base)->PRE55) #define CCM_PRE_ROOT55_SET_REG(base) ((base)->PRE_ROOT55_SET) #define CCM_PRE_ROOT55_CLR_REG(base) ((base)->PRE_ROOT55_CLR) #define CCM_PRE_ROOT55_TOG_REG(base) ((base)->PRE_ROOT55_TOG) #define CCM_ACCESS_CTRL55_REG(base) ((base)->ACCESS_CTRL55) #define CCM_ACCESS_CTRL55_ROOT_SET_REG(base) ((base)->ACCESS_CTRL55_ROOT_SET) #define CCM_ACCESS_CTRL55_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL55_ROOT_CLR) #define CCM_ACCESS_CTRL55_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL55_ROOT_TOG) #define CCM_TARGET_ROOT56_REG(base) ((base)->TARGET_ROOT56) #define CCM_TARGET_ROOT56_SET_REG(base) ((base)->TARGET_ROOT56_SET) #define CCM_TARGET_ROOT56_CLR_REG(base) ((base)->TARGET_ROOT56_CLR) #define CCM_TARGET_ROOT56_TOG_REG(base) ((base)->TARGET_ROOT56_TOG) #define CCM_POST56_REG(base) ((base)->POST56) #define CCM_POST_ROOT56_SET_REG(base) ((base)->POST_ROOT56_SET) #define CCM_POST_ROOT56_CLR_REG(base) ((base)->POST_ROOT56_CLR) #define CCM_POST_ROOT56_TOG_REG(base) ((base)->POST_ROOT56_TOG) #define CCM_PRE56_REG(base) ((base)->PRE56) #define CCM_PRE_ROOT56_SET_REG(base) ((base)->PRE_ROOT56_SET) #define CCM_PRE_ROOT56_CLR_REG(base) ((base)->PRE_ROOT56_CLR) #define CCM_PRE_ROOT56_TOG_REG(base) ((base)->PRE_ROOT56_TOG) #define CCM_ACCESS_CTRL56_REG(base) ((base)->ACCESS_CTRL56) #define CCM_ACCESS_CTRL56_ROOT_SET_REG(base) ((base)->ACCESS_CTRL56_ROOT_SET) #define CCM_ACCESS_CTRL56_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL56_ROOT_CLR) #define CCM_ACCESS_CTRL56_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL56_ROOT_TOG) #define CCM_TARGET_ROOT57_REG(base) ((base)->TARGET_ROOT57) #define CCM_TARGET_ROOT57_SET_REG(base) ((base)->TARGET_ROOT57_SET) #define CCM_TARGET_ROOT57_CLR_REG(base) ((base)->TARGET_ROOT57_CLR) #define CCM_TARGET_ROOT57_TOG_REG(base) ((base)->TARGET_ROOT57_TOG) #define CCM_POST57_REG(base) ((base)->POST57) #define CCM_POST_ROOT57_SET_REG(base) ((base)->POST_ROOT57_SET) #define CCM_POST_ROOT57_CLR_REG(base) ((base)->POST_ROOT57_CLR) #define CCM_POST_ROOT57_TOG_REG(base) ((base)->POST_ROOT57_TOG) #define CCM_PRE57_REG(base) ((base)->PRE57) #define CCM_PRE_ROOT57_SET_REG(base) ((base)->PRE_ROOT57_SET) #define CCM_PRE_ROOT57_CLR_REG(base) ((base)->PRE_ROOT57_CLR) #define CCM_PRE_ROOT57_TOG_REG(base) ((base)->PRE_ROOT57_TOG) #define CCM_ACCESS_CTRL57_REG(base) ((base)->ACCESS_CTRL57) #define CCM_ACCESS_CTRL57_ROOT_SET_REG(base) ((base)->ACCESS_CTRL57_ROOT_SET) #define CCM_ACCESS_CTRL57_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL57_ROOT_CLR) #define CCM_ACCESS_CTRL57_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL57_ROOT_TOG) #define CCM_TARGET_ROOT58_REG(base) ((base)->TARGET_ROOT58) #define CCM_TARGET_ROOT58_SET_REG(base) ((base)->TARGET_ROOT58_SET) #define CCM_TARGET_ROOT58_CLR_REG(base) ((base)->TARGET_ROOT58_CLR) #define CCM_TARGET_ROOT58_TOG_REG(base) ((base)->TARGET_ROOT58_TOG) #define CCM_POST58_REG(base) ((base)->POST58) #define CCM_POST_ROOT58_SET_REG(base) ((base)->POST_ROOT58_SET) #define CCM_POST_ROOT58_CLR_REG(base) ((base)->POST_ROOT58_CLR) #define CCM_POST_ROOT58_TOG_REG(base) ((base)->POST_ROOT58_TOG) #define CCM_PRE58_REG(base) ((base)->PRE58) #define CCM_PRE_ROOT58_SET_REG(base) ((base)->PRE_ROOT58_SET) #define CCM_PRE_ROOT58_CLR_REG(base) ((base)->PRE_ROOT58_CLR) #define CCM_PRE_ROOT58_TOG_REG(base) ((base)->PRE_ROOT58_TOG) #define CCM_ACCESS_CTRL58_REG(base) ((base)->ACCESS_CTRL58) #define CCM_ACCESS_CTRL58_ROOT_SET_REG(base) ((base)->ACCESS_CTRL58_ROOT_SET) #define CCM_ACCESS_CTRL58_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL58_ROOT_CLR) #define CCM_ACCESS_CTRL58_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL58_ROOT_TOG) #define CCM_TARGET_ROOT59_REG(base) ((base)->TARGET_ROOT59) #define CCM_TARGET_ROOT59_SET_REG(base) ((base)->TARGET_ROOT59_SET) #define CCM_TARGET_ROOT59_CLR_REG(base) ((base)->TARGET_ROOT59_CLR) #define CCM_TARGET_ROOT59_TOG_REG(base) ((base)->TARGET_ROOT59_TOG) #define CCM_POST59_REG(base) ((base)->POST59) #define CCM_POST_ROOT59_SET_REG(base) ((base)->POST_ROOT59_SET) #define CCM_POST_ROOT59_CLR_REG(base) ((base)->POST_ROOT59_CLR) #define CCM_POST_ROOT59_TOG_REG(base) ((base)->POST_ROOT59_TOG) #define CCM_PRE59_REG(base) ((base)->PRE59) #define CCM_PRE_ROOT59_SET_REG(base) ((base)->PRE_ROOT59_SET) #define CCM_PRE_ROOT59_CLR_REG(base) ((base)->PRE_ROOT59_CLR) #define CCM_PRE_ROOT59_TOG_REG(base) ((base)->PRE_ROOT59_TOG) #define CCM_ACCESS_CTRL59_REG(base) ((base)->ACCESS_CTRL59) #define CCM_ACCESS_CTRL59_ROOT_SET_REG(base) ((base)->ACCESS_CTRL59_ROOT_SET) #define CCM_ACCESS_CTRL59_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL59_ROOT_CLR) #define CCM_ACCESS_CTRL59_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL59_ROOT_TOG) #define CCM_TARGET_ROOT60_REG(base) ((base)->TARGET_ROOT60) #define CCM_TARGET_ROOT60_SET_REG(base) ((base)->TARGET_ROOT60_SET) #define CCM_TARGET_ROOT60_CLR_REG(base) ((base)->TARGET_ROOT60_CLR) #define CCM_TARGET_ROOT60_TOG_REG(base) ((base)->TARGET_ROOT60_TOG) #define CCM_POST60_REG(base) ((base)->POST60) #define CCM_POST_ROOT60_SET_REG(base) ((base)->POST_ROOT60_SET) #define CCM_POST_ROOT60_CLR_REG(base) ((base)->POST_ROOT60_CLR) #define CCM_POST_ROOT60_TOG_REG(base) ((base)->POST_ROOT60_TOG) #define CCM_PRE60_REG(base) ((base)->PRE60) #define CCM_PRE_ROOT60_SET_REG(base) ((base)->PRE_ROOT60_SET) #define CCM_PRE_ROOT60_CLR_REG(base) ((base)->PRE_ROOT60_CLR) #define CCM_PRE_ROOT60_TOG_REG(base) ((base)->PRE_ROOT60_TOG) #define CCM_ACCESS_CTRL60_REG(base) ((base)->ACCESS_CTRL60) #define CCM_ACCESS_CTRL60_ROOT_SET_REG(base) ((base)->ACCESS_CTRL60_ROOT_SET) #define CCM_ACCESS_CTRL60_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL60_ROOT_CLR) #define CCM_ACCESS_CTRL60_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL60_ROOT_TOG) #define CCM_TARGET_ROOT61_REG(base) ((base)->TARGET_ROOT61) #define CCM_TARGET_ROOT61_SET_REG(base) ((base)->TARGET_ROOT61_SET) #define CCM_TARGET_ROOT61_CLR_REG(base) ((base)->TARGET_ROOT61_CLR) #define CCM_TARGET_ROOT61_TOG_REG(base) ((base)->TARGET_ROOT61_TOG) #define CCM_POST61_REG(base) ((base)->POST61) #define CCM_POST_ROOT61_SET_REG(base) ((base)->POST_ROOT61_SET) #define CCM_POST_ROOT61_CLR_REG(base) ((base)->POST_ROOT61_CLR) #define CCM_POST_ROOT61_TOG_REG(base) ((base)->POST_ROOT61_TOG) #define CCM_PRE61_REG(base) ((base)->PRE61) #define CCM_PRE_ROOT61_SET_REG(base) ((base)->PRE_ROOT61_SET) #define CCM_PRE_ROOT61_CLR_REG(base) ((base)->PRE_ROOT61_CLR) #define CCM_PRE_ROOT61_TOG_REG(base) ((base)->PRE_ROOT61_TOG) #define CCM_ACCESS_CTRL61_REG(base) ((base)->ACCESS_CTRL61) #define CCM_ACCESS_CTRL61_ROOT_SET_REG(base) ((base)->ACCESS_CTRL61_ROOT_SET) #define CCM_ACCESS_CTRL61_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL61_ROOT_CLR) #define CCM_ACCESS_CTRL61_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL61_ROOT_TOG) #define CCM_TARGET_ROOT62_REG(base) ((base)->TARGET_ROOT62) #define CCM_TARGET_ROOT62_SET_REG(base) ((base)->TARGET_ROOT62_SET) #define CCM_TARGET_ROOT62_CLR_REG(base) ((base)->TARGET_ROOT62_CLR) #define CCM_TARGET_ROOT62_TOG_REG(base) ((base)->TARGET_ROOT62_TOG) #define CCM_POST62_REG(base) ((base)->POST62) #define CCM_POST_ROOT62_SET_REG(base) ((base)->POST_ROOT62_SET) #define CCM_POST_ROOT62_CLR_REG(base) ((base)->POST_ROOT62_CLR) #define CCM_POST_ROOT62_TOG_REG(base) ((base)->POST_ROOT62_TOG) #define CCM_PRE62_REG(base) ((base)->PRE62) #define CCM_PRE_ROOT62_SET_REG(base) ((base)->PRE_ROOT62_SET) #define CCM_PRE_ROOT62_CLR_REG(base) ((base)->PRE_ROOT62_CLR) #define CCM_PRE_ROOT62_TOG_REG(base) ((base)->PRE_ROOT62_TOG) #define CCM_ACCESS_CTRL62_REG(base) ((base)->ACCESS_CTRL62) #define CCM_ACCESS_CTRL62_ROOT_SET_REG(base) ((base)->ACCESS_CTRL62_ROOT_SET) #define CCM_ACCESS_CTRL62_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL62_ROOT_CLR) #define CCM_ACCESS_CTRL62_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL62_ROOT_TOG) #define CCM_TARGET_ROOT63_REG(base) ((base)->TARGET_ROOT63) #define CCM_TARGET_ROOT63_SET_REG(base) ((base)->TARGET_ROOT63_SET) #define CCM_TARGET_ROOT63_CLR_REG(base) ((base)->TARGET_ROOT63_CLR) #define CCM_TARGET_ROOT63_TOG_REG(base) ((base)->TARGET_ROOT63_TOG) #define CCM_POST63_REG(base) ((base)->POST63) #define CCM_POST_ROOT63_SET_REG(base) ((base)->POST_ROOT63_SET) #define CCM_POST_ROOT63_CLR_REG(base) ((base)->POST_ROOT63_CLR) #define CCM_POST_ROOT63_TOG_REG(base) ((base)->POST_ROOT63_TOG) #define CCM_PRE63_REG(base) ((base)->PRE63) #define CCM_PRE_ROOT63_SET_REG(base) ((base)->PRE_ROOT63_SET) #define CCM_PRE_ROOT63_CLR_REG(base) ((base)->PRE_ROOT63_CLR) #define CCM_PRE_ROOT63_TOG_REG(base) ((base)->PRE_ROOT63_TOG) #define CCM_ACCESS_CTRL63_REG(base) ((base)->ACCESS_CTRL63) #define CCM_ACCESS_CTRL63_ROOT_SET_REG(base) ((base)->ACCESS_CTRL63_ROOT_SET) #define CCM_ACCESS_CTRL63_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL63_ROOT_CLR) #define CCM_ACCESS_CTRL63_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL63_ROOT_TOG) #define CCM_TARGET_ROOT64_REG(base) ((base)->TARGET_ROOT64) #define CCM_TARGET_ROOT64_SET_REG(base) ((base)->TARGET_ROOT64_SET) #define CCM_TARGET_ROOT64_CLR_REG(base) ((base)->TARGET_ROOT64_CLR) #define CCM_TARGET_ROOT64_TOG_REG(base) ((base)->TARGET_ROOT64_TOG) #define CCM_POST64_REG(base) ((base)->POST64) #define CCM_POST_ROOT64_SET_REG(base) ((base)->POST_ROOT64_SET) #define CCM_POST_ROOT64_CLR_REG(base) ((base)->POST_ROOT64_CLR) #define CCM_POST_ROOT64_TOG_REG(base) ((base)->POST_ROOT64_TOG) #define CCM_PRE64_REG(base) ((base)->PRE64) #define CCM_PRE_ROOT64_SET_REG(base) ((base)->PRE_ROOT64_SET) #define CCM_PRE_ROOT64_CLR_REG(base) ((base)->PRE_ROOT64_CLR) #define CCM_PRE_ROOT64_TOG_REG(base) ((base)->PRE_ROOT64_TOG) #define CCM_ACCESS_CTRL64_REG(base) ((base)->ACCESS_CTRL64) #define CCM_ACCESS_CTRL64_ROOT_SET_REG(base) ((base)->ACCESS_CTRL64_ROOT_SET) #define CCM_ACCESS_CTRL64_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL64_ROOT_CLR) #define CCM_ACCESS_CTRL64_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL64_ROOT_TOG) #define CCM_TARGET_ROOT65_REG(base) ((base)->TARGET_ROOT65) #define CCM_TARGET_ROOT65_SET_REG(base) ((base)->TARGET_ROOT65_SET) #define CCM_TARGET_ROOT65_CLR_REG(base) ((base)->TARGET_ROOT65_CLR) #define CCM_TARGET_ROOT65_TOG_REG(base) ((base)->TARGET_ROOT65_TOG) #define CCM_POST65_REG(base) ((base)->POST65) #define CCM_POST_ROOT65_SET_REG(base) ((base)->POST_ROOT65_SET) #define CCM_POST_ROOT65_CLR_REG(base) ((base)->POST_ROOT65_CLR) #define CCM_POST_ROOT65_TOG_REG(base) ((base)->POST_ROOT65_TOG) #define CCM_PRE65_REG(base) ((base)->PRE65) #define CCM_PRE_ROOT65_SET_REG(base) ((base)->PRE_ROOT65_SET) #define CCM_PRE_ROOT65_CLR_REG(base) ((base)->PRE_ROOT65_CLR) #define CCM_PRE_ROOT65_TOG_REG(base) ((base)->PRE_ROOT65_TOG) #define CCM_ACCESS_CTRL65_REG(base) ((base)->ACCESS_CTRL65) #define CCM_ACCESS_CTRL65_ROOT_SET_REG(base) ((base)->ACCESS_CTRL65_ROOT_SET) #define CCM_ACCESS_CTRL65_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL65_ROOT_CLR) #define CCM_ACCESS_CTRL65_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL65_ROOT_TOG) #define CCM_TARGET_ROOT66_REG(base) ((base)->TARGET_ROOT66) #define CCM_TARGET_ROOT66_SET_REG(base) ((base)->TARGET_ROOT66_SET) #define CCM_TARGET_ROOT66_CLR_REG(base) ((base)->TARGET_ROOT66_CLR) #define CCM_TARGET_ROOT66_TOG_REG(base) ((base)->TARGET_ROOT66_TOG) #define CCM_POST66_REG(base) ((base)->POST66) #define CCM_POST_ROOT66_SET_REG(base) ((base)->POST_ROOT66_SET) #define CCM_POST_ROOT66_CLR_REG(base) ((base)->POST_ROOT66_CLR) #define CCM_POST_ROOT66_TOG_REG(base) ((base)->POST_ROOT66_TOG) #define CCM_PRE66_REG(base) ((base)->PRE66) #define CCM_PRE_ROOT66_SET_REG(base) ((base)->PRE_ROOT66_SET) #define CCM_PRE_ROOT66_CLR_REG(base) ((base)->PRE_ROOT66_CLR) #define CCM_PRE_ROOT66_TOG_REG(base) ((base)->PRE_ROOT66_TOG) #define CCM_ACCESS_CTRL66_REG(base) ((base)->ACCESS_CTRL66) #define CCM_ACCESS_CTRL66_ROOT_SET_REG(base) ((base)->ACCESS_CTRL66_ROOT_SET) #define CCM_ACCESS_CTRL66_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL66_ROOT_CLR) #define CCM_ACCESS_CTRL66_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL66_ROOT_TOG) #define CCM_TARGET_ROOT67_REG(base) ((base)->TARGET_ROOT67) #define CCM_TARGET_ROOT67_SET_REG(base) ((base)->TARGET_ROOT67_SET) #define CCM_TARGET_ROOT67_CLR_REG(base) ((base)->TARGET_ROOT67_CLR) #define CCM_TARGET_ROOT67_TOG_REG(base) ((base)->TARGET_ROOT67_TOG) #define CCM_POST67_REG(base) ((base)->POST67) #define CCM_POST_ROOT67_SET_REG(base) ((base)->POST_ROOT67_SET) #define CCM_POST_ROOT67_CLR_REG(base) ((base)->POST_ROOT67_CLR) #define CCM_POST_ROOT67_TOG_REG(base) ((base)->POST_ROOT67_TOG) #define CCM_PRE67_REG(base) ((base)->PRE67) #define CCM_PRE_ROOT67_SET_REG(base) ((base)->PRE_ROOT67_SET) #define CCM_PRE_ROOT67_CLR_REG(base) ((base)->PRE_ROOT67_CLR) #define CCM_PRE_ROOT67_TOG_REG(base) ((base)->PRE_ROOT67_TOG) #define CCM_ACCESS_CTRL67_REG(base) ((base)->ACCESS_CTRL67) #define CCM_ACCESS_CTRL67_ROOT_SET_REG(base) ((base)->ACCESS_CTRL67_ROOT_SET) #define CCM_ACCESS_CTRL67_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL67_ROOT_CLR) #define CCM_ACCESS_CTRL67_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL67_ROOT_TOG) #define CCM_TARGET_ROOT68_REG(base) ((base)->TARGET_ROOT68) #define CCM_TARGET_ROOT68_SET_REG(base) ((base)->TARGET_ROOT68_SET) #define CCM_TARGET_ROOT68_CLR_REG(base) ((base)->TARGET_ROOT68_CLR) #define CCM_TARGET_ROOT68_TOG_REG(base) ((base)->TARGET_ROOT68_TOG) #define CCM_POST68_REG(base) ((base)->POST68) #define CCM_POST_ROOT68_SET_REG(base) ((base)->POST_ROOT68_SET) #define CCM_POST_ROOT68_CLR_REG(base) ((base)->POST_ROOT68_CLR) #define CCM_POST_ROOT68_TOG_REG(base) ((base)->POST_ROOT68_TOG) #define CCM_PRE68_REG(base) ((base)->PRE68) #define CCM_PRE_ROOT68_SET_REG(base) ((base)->PRE_ROOT68_SET) #define CCM_PRE_ROOT68_CLR_REG(base) ((base)->PRE_ROOT68_CLR) #define CCM_PRE_ROOT68_TOG_REG(base) ((base)->PRE_ROOT68_TOG) #define CCM_ACCESS_CTRL68_REG(base) ((base)->ACCESS_CTRL68) #define CCM_ACCESS_CTRL68_ROOT_SET_REG(base) ((base)->ACCESS_CTRL68_ROOT_SET) #define CCM_ACCESS_CTRL68_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL68_ROOT_CLR) #define CCM_ACCESS_CTRL68_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL68_ROOT_TOG) #define CCM_TARGET_ROOT69_REG(base) ((base)->TARGET_ROOT69) #define CCM_TARGET_ROOT69_SET_REG(base) ((base)->TARGET_ROOT69_SET) #define CCM_TARGET_ROOT69_CLR_REG(base) ((base)->TARGET_ROOT69_CLR) #define CCM_TARGET_ROOT69_TOG_REG(base) ((base)->TARGET_ROOT69_TOG) #define CCM_POST69_REG(base) ((base)->POST69) #define CCM_POST_ROOT69_SET_REG(base) ((base)->POST_ROOT69_SET) #define CCM_POST_ROOT69_CLR_REG(base) ((base)->POST_ROOT69_CLR) #define CCM_POST_ROOT69_TOG_REG(base) ((base)->POST_ROOT69_TOG) #define CCM_PRE69_REG(base) ((base)->PRE69) #define CCM_PRE_ROOT69_SET_REG(base) ((base)->PRE_ROOT69_SET) #define CCM_PRE_ROOT69_CLR_REG(base) ((base)->PRE_ROOT69_CLR) #define CCM_PRE_ROOT69_TOG_REG(base) ((base)->PRE_ROOT69_TOG) #define CCM_ACCESS_CTRL69_REG(base) ((base)->ACCESS_CTRL69) #define CCM_ACCESS_CTRL69_ROOT_SET_REG(base) ((base)->ACCESS_CTRL69_ROOT_SET) #define CCM_ACCESS_CTRL69_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL69_ROOT_CLR) #define CCM_ACCESS_CTRL69_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL69_ROOT_TOG) #define CCM_TARGET_ROOT70_REG(base) ((base)->TARGET_ROOT70) #define CCM_TARGET_ROOT70_SET_REG(base) ((base)->TARGET_ROOT70_SET) #define CCM_TARGET_ROOT70_CLR_REG(base) ((base)->TARGET_ROOT70_CLR) #define CCM_TARGET_ROOT70_TOG_REG(base) ((base)->TARGET_ROOT70_TOG) #define CCM_POST70_REG(base) ((base)->POST70) #define CCM_POST_ROOT70_SET_REG(base) ((base)->POST_ROOT70_SET) #define CCM_POST_ROOT70_CLR_REG(base) ((base)->POST_ROOT70_CLR) #define CCM_POST_ROOT70_TOG_REG(base) ((base)->POST_ROOT70_TOG) #define CCM_PRE70_REG(base) ((base)->PRE70) #define CCM_PRE_ROOT70_SET_REG(base) ((base)->PRE_ROOT70_SET) #define CCM_PRE_ROOT70_CLR_REG(base) ((base)->PRE_ROOT70_CLR) #define CCM_PRE_ROOT70_TOG_REG(base) ((base)->PRE_ROOT70_TOG) #define CCM_ACCESS_CTRL70_REG(base) ((base)->ACCESS_CTRL70) #define CCM_ACCESS_CTRL70_ROOT_SET_REG(base) ((base)->ACCESS_CTRL70_ROOT_SET) #define CCM_ACCESS_CTRL70_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL70_ROOT_CLR) #define CCM_ACCESS_CTRL70_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL70_ROOT_TOG) #define CCM_TARGET_ROOT71_REG(base) ((base)->TARGET_ROOT71) #define CCM_TARGET_ROOT71_SET_REG(base) ((base)->TARGET_ROOT71_SET) #define CCM_TARGET_ROOT71_CLR_REG(base) ((base)->TARGET_ROOT71_CLR) #define CCM_TARGET_ROOT71_TOG_REG(base) ((base)->TARGET_ROOT71_TOG) #define CCM_POST71_REG(base) ((base)->POST71) #define CCM_POST_ROOT71_SET_REG(base) ((base)->POST_ROOT71_SET) #define CCM_POST_ROOT71_CLR_REG(base) ((base)->POST_ROOT71_CLR) #define CCM_POST_ROOT71_TOG_REG(base) ((base)->POST_ROOT71_TOG) #define CCM_PRE71_REG(base) ((base)->PRE71) #define CCM_PRE_ROOT71_SET_REG(base) ((base)->PRE_ROOT71_SET) #define CCM_PRE_ROOT71_CLR_REG(base) ((base)->PRE_ROOT71_CLR) #define CCM_PRE_ROOT71_TOG_REG(base) ((base)->PRE_ROOT71_TOG) #define CCM_ACCESS_CTRL71_REG(base) ((base)->ACCESS_CTRL71) #define CCM_ACCESS_CTRL71_ROOT_SET_REG(base) ((base)->ACCESS_CTRL71_ROOT_SET) #define CCM_ACCESS_CTRL71_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL71_ROOT_CLR) #define CCM_ACCESS_CTRL71_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL71_ROOT_TOG) #define CCM_TARGET_ROOT72_REG(base) ((base)->TARGET_ROOT72) #define CCM_TARGET_ROOT72_SET_REG(base) ((base)->TARGET_ROOT72_SET) #define CCM_TARGET_ROOT72_CLR_REG(base) ((base)->TARGET_ROOT72_CLR) #define CCM_TARGET_ROOT72_TOG_REG(base) ((base)->TARGET_ROOT72_TOG) #define CCM_POST72_REG(base) ((base)->POST72) #define CCM_POST_ROOT72_SET_REG(base) ((base)->POST_ROOT72_SET) #define CCM_POST_ROOT72_CLR_REG(base) ((base)->POST_ROOT72_CLR) #define CCM_POST_ROOT72_TOG_REG(base) ((base)->POST_ROOT72_TOG) #define CCM_PRE72_REG(base) ((base)->PRE72) #define CCM_PRE_ROOT72_SET_REG(base) ((base)->PRE_ROOT72_SET) #define CCM_PRE_ROOT72_CLR_REG(base) ((base)->PRE_ROOT72_CLR) #define CCM_PRE_ROOT72_TOG_REG(base) ((base)->PRE_ROOT72_TOG) #define CCM_ACCESS_CTRL72_REG(base) ((base)->ACCESS_CTRL72) #define CCM_ACCESS_CTRL72_ROOT_SET_REG(base) ((base)->ACCESS_CTRL72_ROOT_SET) #define CCM_ACCESS_CTRL72_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL72_ROOT_CLR) #define CCM_ACCESS_CTRL72_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL72_ROOT_TOG) #define CCM_TARGET_ROOT73_REG(base) ((base)->TARGET_ROOT73) #define CCM_TARGET_ROOT73_SET_REG(base) ((base)->TARGET_ROOT73_SET) #define CCM_TARGET_ROOT73_CLR_REG(base) ((base)->TARGET_ROOT73_CLR) #define CCM_TARGET_ROOT73_TOG_REG(base) ((base)->TARGET_ROOT73_TOG) #define CCM_POST73_REG(base) ((base)->POST73) #define CCM_POST_ROOT73_SET_REG(base) ((base)->POST_ROOT73_SET) #define CCM_POST_ROOT73_CLR_REG(base) ((base)->POST_ROOT73_CLR) #define CCM_POST_ROOT73_TOG_REG(base) ((base)->POST_ROOT73_TOG) #define CCM_PRE73_REG(base) ((base)->PRE73) #define CCM_PRE_ROOT73_SET_REG(base) ((base)->PRE_ROOT73_SET) #define CCM_PRE_ROOT73_CLR_REG(base) ((base)->PRE_ROOT73_CLR) #define CCM_PRE_ROOT73_TOG_REG(base) ((base)->PRE_ROOT73_TOG) #define CCM_ACCESS_CTRL73_REG(base) ((base)->ACCESS_CTRL73) #define CCM_ACCESS_CTRL73_ROOT_SET_REG(base) ((base)->ACCESS_CTRL73_ROOT_SET) #define CCM_ACCESS_CTRL73_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL73_ROOT_CLR) #define CCM_ACCESS_CTRL73_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL73_ROOT_TOG) #define CCM_TARGET_ROOT74_REG(base) ((base)->TARGET_ROOT74) #define CCM_TARGET_ROOT74_SET_REG(base) ((base)->TARGET_ROOT74_SET) #define CCM_TARGET_ROOT74_CLR_REG(base) ((base)->TARGET_ROOT74_CLR) #define CCM_TARGET_ROOT74_TOG_REG(base) ((base)->TARGET_ROOT74_TOG) #define CCM_POST74_REG(base) ((base)->POST74) #define CCM_POST_ROOT74_SET_REG(base) ((base)->POST_ROOT74_SET) #define CCM_POST_ROOT74_CLR_REG(base) ((base)->POST_ROOT74_CLR) #define CCM_POST_ROOT74_TOG_REG(base) ((base)->POST_ROOT74_TOG) #define CCM_PRE74_REG(base) ((base)->PRE74) #define CCM_PRE_ROOT74_SET_REG(base) ((base)->PRE_ROOT74_SET) #define CCM_PRE_ROOT74_CLR_REG(base) ((base)->PRE_ROOT74_CLR) #define CCM_PRE_ROOT74_TOG_REG(base) ((base)->PRE_ROOT74_TOG) #define CCM_ACCESS_CTRL74_REG(base) ((base)->ACCESS_CTRL74) #define CCM_ACCESS_CTRL74_ROOT_SET_REG(base) ((base)->ACCESS_CTRL74_ROOT_SET) #define CCM_ACCESS_CTRL74_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL74_ROOT_CLR) #define CCM_ACCESS_CTRL74_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL74_ROOT_TOG) #define CCM_TARGET_ROOT75_REG(base) ((base)->TARGET_ROOT75) #define CCM_TARGET_ROOT75_SET_REG(base) ((base)->TARGET_ROOT75_SET) #define CCM_TARGET_ROOT75_CLR_REG(base) ((base)->TARGET_ROOT75_CLR) #define CCM_TARGET_ROOT75_TOG_REG(base) ((base)->TARGET_ROOT75_TOG) #define CCM_POST75_REG(base) ((base)->POST75) #define CCM_POST_ROOT75_SET_REG(base) ((base)->POST_ROOT75_SET) #define CCM_POST_ROOT75_CLR_REG(base) ((base)->POST_ROOT75_CLR) #define CCM_POST_ROOT75_TOG_REG(base) ((base)->POST_ROOT75_TOG) #define CCM_PRE75_REG(base) ((base)->PRE75) #define CCM_PRE_ROOT75_SET_REG(base) ((base)->PRE_ROOT75_SET) #define CCM_PRE_ROOT75_CLR_REG(base) ((base)->PRE_ROOT75_CLR) #define CCM_PRE_ROOT75_TOG_REG(base) ((base)->PRE_ROOT75_TOG) #define CCM_ACCESS_CTRL75_REG(base) ((base)->ACCESS_CTRL75) #define CCM_ACCESS_CTRL75_ROOT_SET_REG(base) ((base)->ACCESS_CTRL75_ROOT_SET) #define CCM_ACCESS_CTRL75_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL75_ROOT_CLR) #define CCM_ACCESS_CTRL75_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL75_ROOT_TOG) #define CCM_TARGET_ROOT76_REG(base) ((base)->TARGET_ROOT76) #define CCM_TARGET_ROOT76_SET_REG(base) ((base)->TARGET_ROOT76_SET) #define CCM_TARGET_ROOT76_CLR_REG(base) ((base)->TARGET_ROOT76_CLR) #define CCM_TARGET_ROOT76_TOG_REG(base) ((base)->TARGET_ROOT76_TOG) #define CCM_POST76_REG(base) ((base)->POST76) #define CCM_POST_ROOT76_SET_REG(base) ((base)->POST_ROOT76_SET) #define CCM_POST_ROOT76_CLR_REG(base) ((base)->POST_ROOT76_CLR) #define CCM_POST_ROOT76_TOG_REG(base) ((base)->POST_ROOT76_TOG) #define CCM_PRE76_REG(base) ((base)->PRE76) #define CCM_PRE_ROOT76_SET_REG(base) ((base)->PRE_ROOT76_SET) #define CCM_PRE_ROOT76_CLR_REG(base) ((base)->PRE_ROOT76_CLR) #define CCM_PRE_ROOT76_TOG_REG(base) ((base)->PRE_ROOT76_TOG) #define CCM_ACCESS_CTRL76_REG(base) ((base)->ACCESS_CTRL76) #define CCM_ACCESS_CTRL76_ROOT_SET_REG(base) ((base)->ACCESS_CTRL76_ROOT_SET) #define CCM_ACCESS_CTRL76_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL76_ROOT_CLR) #define CCM_ACCESS_CTRL76_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL76_ROOT_TOG) #define CCM_TARGET_ROOT77_REG(base) ((base)->TARGET_ROOT77) #define CCM_TARGET_ROOT77_SET_REG(base) ((base)->TARGET_ROOT77_SET) #define CCM_TARGET_ROOT77_CLR_REG(base) ((base)->TARGET_ROOT77_CLR) #define CCM_TARGET_ROOT77_TOG_REG(base) ((base)->TARGET_ROOT77_TOG) #define CCM_POST77_REG(base) ((base)->POST77) #define CCM_POST_ROOT77_SET_REG(base) ((base)->POST_ROOT77_SET) #define CCM_POST_ROOT77_CLR_REG(base) ((base)->POST_ROOT77_CLR) #define CCM_POST_ROOT77_TOG_REG(base) ((base)->POST_ROOT77_TOG) #define CCM_PRE77_REG(base) ((base)->PRE77) #define CCM_PRE_ROOT77_SET_REG(base) ((base)->PRE_ROOT77_SET) #define CCM_PRE_ROOT77_CLR_REG(base) ((base)->PRE_ROOT77_CLR) #define CCM_PRE_ROOT77_TOG_REG(base) ((base)->PRE_ROOT77_TOG) #define CCM_ACCESS_CTRL77_REG(base) ((base)->ACCESS_CTRL77) #define CCM_ACCESS_CTRL77_ROOT_SET_REG(base) ((base)->ACCESS_CTRL77_ROOT_SET) #define CCM_ACCESS_CTRL77_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL77_ROOT_CLR) #define CCM_ACCESS_CTRL77_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL77_ROOT_TOG) #define CCM_TARGET_ROOT78_REG(base) ((base)->TARGET_ROOT78) #define CCM_TARGET_ROOT78_SET_REG(base) ((base)->TARGET_ROOT78_SET) #define CCM_TARGET_ROOT78_CLR_REG(base) ((base)->TARGET_ROOT78_CLR) #define CCM_TARGET_ROOT78_TOG_REG(base) ((base)->TARGET_ROOT78_TOG) #define CCM_POST78_REG(base) ((base)->POST78) #define CCM_POST_ROOT78_SET_REG(base) ((base)->POST_ROOT78_SET) #define CCM_POST_ROOT78_CLR_REG(base) ((base)->POST_ROOT78_CLR) #define CCM_POST_ROOT78_TOG_REG(base) ((base)->POST_ROOT78_TOG) #define CCM_PRE78_REG(base) ((base)->PRE78) #define CCM_PRE_ROOT78_SET_REG(base) ((base)->PRE_ROOT78_SET) #define CCM_PRE_ROOT78_CLR_REG(base) ((base)->PRE_ROOT78_CLR) #define CCM_PRE_ROOT78_TOG_REG(base) ((base)->PRE_ROOT78_TOG) #define CCM_ACCESS_CTRL78_REG(base) ((base)->ACCESS_CTRL78) #define CCM_ACCESS_CTRL78_ROOT_SET_REG(base) ((base)->ACCESS_CTRL78_ROOT_SET) #define CCM_ACCESS_CTRL78_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL78_ROOT_CLR) #define CCM_ACCESS_CTRL78_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL78_ROOT_TOG) #define CCM_TARGET_ROOT79_REG(base) ((base)->TARGET_ROOT79) #define CCM_TARGET_ROOT79_SET_REG(base) ((base)->TARGET_ROOT79_SET) #define CCM_TARGET_ROOT79_CLR_REG(base) ((base)->TARGET_ROOT79_CLR) #define CCM_TARGET_ROOT79_TOG_REG(base) ((base)->TARGET_ROOT79_TOG) #define CCM_POST79_REG(base) ((base)->POST79) #define CCM_POST_ROOT79_SET_REG(base) ((base)->POST_ROOT79_SET) #define CCM_POST_ROOT79_CLR_REG(base) ((base)->POST_ROOT79_CLR) #define CCM_POST_ROOT79_TOG_REG(base) ((base)->POST_ROOT79_TOG) #define CCM_PRE79_REG(base) ((base)->PRE79) #define CCM_PRE_ROOT79_SET_REG(base) ((base)->PRE_ROOT79_SET) #define CCM_PRE_ROOT79_CLR_REG(base) ((base)->PRE_ROOT79_CLR) #define CCM_PRE_ROOT79_TOG_REG(base) ((base)->PRE_ROOT79_TOG) #define CCM_ACCESS_CTRL79_REG(base) ((base)->ACCESS_CTRL79) #define CCM_ACCESS_CTRL79_ROOT_SET_REG(base) ((base)->ACCESS_CTRL79_ROOT_SET) #define CCM_ACCESS_CTRL79_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL79_ROOT_CLR) #define CCM_ACCESS_CTRL79_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL79_ROOT_TOG) #define CCM_TARGET_ROOT80_REG(base) ((base)->TARGET_ROOT80) #define CCM_TARGET_ROOT80_SET_REG(base) ((base)->TARGET_ROOT80_SET) #define CCM_TARGET_ROOT80_CLR_REG(base) ((base)->TARGET_ROOT80_CLR) #define CCM_TARGET_ROOT80_TOG_REG(base) ((base)->TARGET_ROOT80_TOG) #define CCM_POST80_REG(base) ((base)->POST80) #define CCM_POST_ROOT80_SET_REG(base) ((base)->POST_ROOT80_SET) #define CCM_POST_ROOT80_CLR_REG(base) ((base)->POST_ROOT80_CLR) #define CCM_POST_ROOT80_TOG_REG(base) ((base)->POST_ROOT80_TOG) #define CCM_PRE80_REG(base) ((base)->PRE80) #define CCM_PRE_ROOT80_SET_REG(base) ((base)->PRE_ROOT80_SET) #define CCM_PRE_ROOT80_CLR_REG(base) ((base)->PRE_ROOT80_CLR) #define CCM_PRE_ROOT80_TOG_REG(base) ((base)->PRE_ROOT80_TOG) #define CCM_ACCESS_CTRL80_REG(base) ((base)->ACCESS_CTRL80) #define CCM_ACCESS_CTRL80_ROOT_SET_REG(base) ((base)->ACCESS_CTRL80_ROOT_SET) #define CCM_ACCESS_CTRL80_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL80_ROOT_CLR) #define CCM_ACCESS_CTRL80_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL80_ROOT_TOG) #define CCM_TARGET_ROOT81_REG(base) ((base)->TARGET_ROOT81) #define CCM_TARGET_ROOT81_SET_REG(base) ((base)->TARGET_ROOT81_SET) #define CCM_TARGET_ROOT81_CLR_REG(base) ((base)->TARGET_ROOT81_CLR) #define CCM_TARGET_ROOT81_TOG_REG(base) ((base)->TARGET_ROOT81_TOG) #define CCM_POST81_REG(base) ((base)->POST81) #define CCM_POST_ROOT81_SET_REG(base) ((base)->POST_ROOT81_SET) #define CCM_POST_ROOT81_CLR_REG(base) ((base)->POST_ROOT81_CLR) #define CCM_POST_ROOT81_TOG_REG(base) ((base)->POST_ROOT81_TOG) #define CCM_PRE81_REG(base) ((base)->PRE81) #define CCM_PRE_ROOT81_SET_REG(base) ((base)->PRE_ROOT81_SET) #define CCM_PRE_ROOT81_CLR_REG(base) ((base)->PRE_ROOT81_CLR) #define CCM_PRE_ROOT81_TOG_REG(base) ((base)->PRE_ROOT81_TOG) #define CCM_ACCESS_CTRL81_REG(base) ((base)->ACCESS_CTRL81) #define CCM_ACCESS_CTRL81_ROOT_SET_REG(base) ((base)->ACCESS_CTRL81_ROOT_SET) #define CCM_ACCESS_CTRL81_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL81_ROOT_CLR) #define CCM_ACCESS_CTRL81_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL81_ROOT_TOG) #define CCM_TARGET_ROOT82_REG(base) ((base)->TARGET_ROOT82) #define CCM_TARGET_ROOT82_SET_REG(base) ((base)->TARGET_ROOT82_SET) #define CCM_TARGET_ROOT82_CLR_REG(base) ((base)->TARGET_ROOT82_CLR) #define CCM_TARGET_ROOT82_TOG_REG(base) ((base)->TARGET_ROOT82_TOG) #define CCM_POST82_REG(base) ((base)->POST82) #define CCM_POST_ROOT82_SET_REG(base) ((base)->POST_ROOT82_SET) #define CCM_POST_ROOT82_CLR_REG(base) ((base)->POST_ROOT82_CLR) #define CCM_POST_ROOT82_TOG_REG(base) ((base)->POST_ROOT82_TOG) #define CCM_PRE82_REG(base) ((base)->PRE82) #define CCM_PRE_ROOT82_SET_REG(base) ((base)->PRE_ROOT82_SET) #define CCM_PRE_ROOT82_CLR_REG(base) ((base)->PRE_ROOT82_CLR) #define CCM_PRE_ROOT82_TOG_REG(base) ((base)->PRE_ROOT82_TOG) #define CCM_ACCESS_CTRL82_REG(base) ((base)->ACCESS_CTRL82) #define CCM_ACCESS_CTRL82_ROOT_SET_REG(base) ((base)->ACCESS_CTRL82_ROOT_SET) #define CCM_ACCESS_CTRL82_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL82_ROOT_CLR) #define CCM_ACCESS_CTRL82_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL82_ROOT_TOG) #define CCM_TARGET_ROOT83_REG(base) ((base)->TARGET_ROOT83) #define CCM_TARGET_ROOT83_SET_REG(base) ((base)->TARGET_ROOT83_SET) #define CCM_TARGET_ROOT83_CLR_REG(base) ((base)->TARGET_ROOT83_CLR) #define CCM_TARGET_ROOT83_TOG_REG(base) ((base)->TARGET_ROOT83_TOG) #define CCM_POST83_REG(base) ((base)->POST83) #define CCM_POST_ROOT83_SET_REG(base) ((base)->POST_ROOT83_SET) #define CCM_POST_ROOT83_CLR_REG(base) ((base)->POST_ROOT83_CLR) #define CCM_POST_ROOT83_TOG_REG(base) ((base)->POST_ROOT83_TOG) #define CCM_PRE83_REG(base) ((base)->PRE83) #define CCM_PRE_ROOT83_SET_REG(base) ((base)->PRE_ROOT83_SET) #define CCM_PRE_ROOT83_CLR_REG(base) ((base)->PRE_ROOT83_CLR) #define CCM_PRE_ROOT83_TOG_REG(base) ((base)->PRE_ROOT83_TOG) #define CCM_ACCESS_CTRL83_REG(base) ((base)->ACCESS_CTRL83) #define CCM_ACCESS_CTRL83_ROOT_SET_REG(base) ((base)->ACCESS_CTRL83_ROOT_SET) #define CCM_ACCESS_CTRL83_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL83_ROOT_CLR) #define CCM_ACCESS_CTRL83_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL83_ROOT_TOG) #define CCM_TARGET_ROOT84_REG(base) ((base)->TARGET_ROOT84) #define CCM_TARGET_ROOT84_SET_REG(base) ((base)->TARGET_ROOT84_SET) #define CCM_TARGET_ROOT84_CLR_REG(base) ((base)->TARGET_ROOT84_CLR) #define CCM_TARGET_ROOT84_TOG_REG(base) ((base)->TARGET_ROOT84_TOG) #define CCM_POST84_REG(base) ((base)->POST84) #define CCM_POST_ROOT84_SET_REG(base) ((base)->POST_ROOT84_SET) #define CCM_POST_ROOT84_CLR_REG(base) ((base)->POST_ROOT84_CLR) #define CCM_POST_ROOT84_TOG_REG(base) ((base)->POST_ROOT84_TOG) #define CCM_PRE84_REG(base) ((base)->PRE84) #define CCM_PRE_ROOT84_SET_REG(base) ((base)->PRE_ROOT84_SET) #define CCM_PRE_ROOT84_CLR_REG(base) ((base)->PRE_ROOT84_CLR) #define CCM_PRE_ROOT84_TOG_REG(base) ((base)->PRE_ROOT84_TOG) #define CCM_ACCESS_CTRL84_REG(base) ((base)->ACCESS_CTRL84) #define CCM_ACCESS_CTRL84_ROOT_SET_REG(base) ((base)->ACCESS_CTRL84_ROOT_SET) #define CCM_ACCESS_CTRL84_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL84_ROOT_CLR) #define CCM_ACCESS_CTRL84_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL84_ROOT_TOG) #define CCM_TARGET_ROOT85_REG(base) ((base)->TARGET_ROOT85) #define CCM_TARGET_ROOT85_SET_REG(base) ((base)->TARGET_ROOT85_SET) #define CCM_TARGET_ROOT85_CLR_REG(base) ((base)->TARGET_ROOT85_CLR) #define CCM_TARGET_ROOT85_TOG_REG(base) ((base)->TARGET_ROOT85_TOG) #define CCM_POST85_REG(base) ((base)->POST85) #define CCM_POST_ROOT85_SET_REG(base) ((base)->POST_ROOT85_SET) #define CCM_POST_ROOT85_CLR_REG(base) ((base)->POST_ROOT85_CLR) #define CCM_POST_ROOT85_TOG_REG(base) ((base)->POST_ROOT85_TOG) #define CCM_PRE85_REG(base) ((base)->PRE85) #define CCM_PRE_ROOT85_SET_REG(base) ((base)->PRE_ROOT85_SET) #define CCM_PRE_ROOT85_CLR_REG(base) ((base)->PRE_ROOT85_CLR) #define CCM_PRE_ROOT85_TOG_REG(base) ((base)->PRE_ROOT85_TOG) #define CCM_ACCESS_CTRL85_REG(base) ((base)->ACCESS_CTRL85) #define CCM_ACCESS_CTRL85_ROOT_SET_REG(base) ((base)->ACCESS_CTRL85_ROOT_SET) #define CCM_ACCESS_CTRL85_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL85_ROOT_CLR) #define CCM_ACCESS_CTRL85_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL85_ROOT_TOG) #define CCM_TARGET_ROOT86_REG(base) ((base)->TARGET_ROOT86) #define CCM_TARGET_ROOT86_SET_REG(base) ((base)->TARGET_ROOT86_SET) #define CCM_TARGET_ROOT86_CLR_REG(base) ((base)->TARGET_ROOT86_CLR) #define CCM_TARGET_ROOT86_TOG_REG(base) ((base)->TARGET_ROOT86_TOG) #define CCM_POST86_REG(base) ((base)->POST86) #define CCM_POST_ROOT86_SET_REG(base) ((base)->POST_ROOT86_SET) #define CCM_POST_ROOT86_CLR_REG(base) ((base)->POST_ROOT86_CLR) #define CCM_POST_ROOT86_TOG_REG(base) ((base)->POST_ROOT86_TOG) #define CCM_PRE86_REG(base) ((base)->PRE86) #define CCM_PRE_ROOT86_SET_REG(base) ((base)->PRE_ROOT86_SET) #define CCM_PRE_ROOT86_CLR_REG(base) ((base)->PRE_ROOT86_CLR) #define CCM_PRE_ROOT86_TOG_REG(base) ((base)->PRE_ROOT86_TOG) #define CCM_ACCESS_CTRL86_REG(base) ((base)->ACCESS_CTRL86) #define CCM_ACCESS_CTRL86_ROOT_SET_REG(base) ((base)->ACCESS_CTRL86_ROOT_SET) #define CCM_ACCESS_CTRL86_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL86_ROOT_CLR) #define CCM_ACCESS_CTRL86_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL86_ROOT_TOG) #define CCM_TARGET_ROOT87_REG(base) ((base)->TARGET_ROOT87) #define CCM_TARGET_ROOT87_SET_REG(base) ((base)->TARGET_ROOT87_SET) #define CCM_TARGET_ROOT87_CLR_REG(base) ((base)->TARGET_ROOT87_CLR) #define CCM_TARGET_ROOT87_TOG_REG(base) ((base)->TARGET_ROOT87_TOG) #define CCM_POST87_REG(base) ((base)->POST87) #define CCM_POST_ROOT87_SET_REG(base) ((base)->POST_ROOT87_SET) #define CCM_POST_ROOT87_CLR_REG(base) ((base)->POST_ROOT87_CLR) #define CCM_POST_ROOT87_TOG_REG(base) ((base)->POST_ROOT87_TOG) #define CCM_PRE87_REG(base) ((base)->PRE87) #define CCM_PRE_ROOT87_SET_REG(base) ((base)->PRE_ROOT87_SET) #define CCM_PRE_ROOT87_CLR_REG(base) ((base)->PRE_ROOT87_CLR) #define CCM_PRE_ROOT87_TOG_REG(base) ((base)->PRE_ROOT87_TOG) #define CCM_ACCESS_CTRL87_REG(base) ((base)->ACCESS_CTRL87) #define CCM_ACCESS_CTRL87_ROOT_SET_REG(base) ((base)->ACCESS_CTRL87_ROOT_SET) #define CCM_ACCESS_CTRL87_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL87_ROOT_CLR) #define CCM_ACCESS_CTRL87_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL87_ROOT_TOG) #define CCM_TARGET_ROOT88_REG(base) ((base)->TARGET_ROOT88) #define CCM_TARGET_ROOT88_SET_REG(base) ((base)->TARGET_ROOT88_SET) #define CCM_TARGET_ROOT88_CLR_REG(base) ((base)->TARGET_ROOT88_CLR) #define CCM_TARGET_ROOT88_TOG_REG(base) ((base)->TARGET_ROOT88_TOG) #define CCM_POST88_REG(base) ((base)->POST88) #define CCM_POST_ROOT88_SET_REG(base) ((base)->POST_ROOT88_SET) #define CCM_POST_ROOT88_CLR_REG(base) ((base)->POST_ROOT88_CLR) #define CCM_POST_ROOT88_TOG_REG(base) ((base)->POST_ROOT88_TOG) #define CCM_PRE88_REG(base) ((base)->PRE88) #define CCM_PRE_ROOT88_SET_REG(base) ((base)->PRE_ROOT88_SET) #define CCM_PRE_ROOT88_CLR_REG(base) ((base)->PRE_ROOT88_CLR) #define CCM_PRE_ROOT88_TOG_REG(base) ((base)->PRE_ROOT88_TOG) #define CCM_ACCESS_CTRL88_REG(base) ((base)->ACCESS_CTRL88) #define CCM_ACCESS_CTRL88_ROOT_SET_REG(base) ((base)->ACCESS_CTRL88_ROOT_SET) #define CCM_ACCESS_CTRL88_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL88_ROOT_CLR) #define CCM_ACCESS_CTRL88_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL88_ROOT_TOG) #define CCM_TARGET_ROOT89_REG(base) ((base)->TARGET_ROOT89) #define CCM_TARGET_ROOT89_SET_REG(base) ((base)->TARGET_ROOT89_SET) #define CCM_TARGET_ROOT89_CLR_REG(base) ((base)->TARGET_ROOT89_CLR) #define CCM_TARGET_ROOT89_TOG_REG(base) ((base)->TARGET_ROOT89_TOG) #define CCM_POST89_REG(base) ((base)->POST89) #define CCM_POST_ROOT89_SET_REG(base) ((base)->POST_ROOT89_SET) #define CCM_POST_ROOT89_CLR_REG(base) ((base)->POST_ROOT89_CLR) #define CCM_POST_ROOT89_TOG_REG(base) ((base)->POST_ROOT89_TOG) #define CCM_PRE89_REG(base) ((base)->PRE89) #define CCM_PRE_ROOT89_SET_REG(base) ((base)->PRE_ROOT89_SET) #define CCM_PRE_ROOT89_CLR_REG(base) ((base)->PRE_ROOT89_CLR) #define CCM_PRE_ROOT89_TOG_REG(base) ((base)->PRE_ROOT89_TOG) #define CCM_ACCESS_CTRL89_REG(base) ((base)->ACCESS_CTRL89) #define CCM_ACCESS_CTRL89_ROOT_SET_REG(base) ((base)->ACCESS_CTRL89_ROOT_SET) #define CCM_ACCESS_CTRL89_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL89_ROOT_CLR) #define CCM_ACCESS_CTRL89_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL89_ROOT_TOG) #define CCM_TARGET_ROOT90_REG(base) ((base)->TARGET_ROOT90) #define CCM_TARGET_ROOT90_SET_REG(base) ((base)->TARGET_ROOT90_SET) #define CCM_TARGET_ROOT90_CLR_REG(base) ((base)->TARGET_ROOT90_CLR) #define CCM_TARGET_ROOT90_TOG_REG(base) ((base)->TARGET_ROOT90_TOG) #define CCM_POST90_REG(base) ((base)->POST90) #define CCM_POST_ROOT90_SET_REG(base) ((base)->POST_ROOT90_SET) #define CCM_POST_ROOT90_CLR_REG(base) ((base)->POST_ROOT90_CLR) #define CCM_POST_ROOT90_TOG_REG(base) ((base)->POST_ROOT90_TOG) #define CCM_PRE90_REG(base) ((base)->PRE90) #define CCM_PRE_ROOT90_SET_REG(base) ((base)->PRE_ROOT90_SET) #define CCM_PRE_ROOT90_CLR_REG(base) ((base)->PRE_ROOT90_CLR) #define CCM_PRE_ROOT90_TOG_REG(base) ((base)->PRE_ROOT90_TOG) #define CCM_ACCESS_CTRL90_REG(base) ((base)->ACCESS_CTRL90) #define CCM_ACCESS_CTRL90_ROOT_SET_REG(base) ((base)->ACCESS_CTRL90_ROOT_SET) #define CCM_ACCESS_CTRL90_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL90_ROOT_CLR) #define CCM_ACCESS_CTRL90_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL90_ROOT_TOG) #define CCM_TARGET_ROOT91_REG(base) ((base)->TARGET_ROOT91) #define CCM_TARGET_ROOT91_SET_REG(base) ((base)->TARGET_ROOT91_SET) #define CCM_TARGET_ROOT91_CLR_REG(base) ((base)->TARGET_ROOT91_CLR) #define CCM_TARGET_ROOT91_TOG_REG(base) ((base)->TARGET_ROOT91_TOG) #define CCM_POST91_REG(base) ((base)->POST91) #define CCM_POST_ROOT91_SET_REG(base) ((base)->POST_ROOT91_SET) #define CCM_POST_ROOT91_CLR_REG(base) ((base)->POST_ROOT91_CLR) #define CCM_POST_ROOT91_TOG_REG(base) ((base)->POST_ROOT91_TOG) #define CCM_PRE91_REG(base) ((base)->PRE91) #define CCM_PRE_ROOT91_SET_REG(base) ((base)->PRE_ROOT91_SET) #define CCM_PRE_ROOT91_CLR_REG(base) ((base)->PRE_ROOT91_CLR) #define CCM_PRE_ROOT91_TOG_REG(base) ((base)->PRE_ROOT91_TOG) #define CCM_ACCESS_CTRL91_REG(base) ((base)->ACCESS_CTRL91) #define CCM_ACCESS_CTRL91_ROOT_SET_REG(base) ((base)->ACCESS_CTRL91_ROOT_SET) #define CCM_ACCESS_CTRL91_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL91_ROOT_CLR) #define CCM_ACCESS_CTRL91_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL91_ROOT_TOG) #define CCM_TARGET_ROOT92_REG(base) ((base)->TARGET_ROOT92) #define CCM_TARGET_ROOT92_SET_REG(base) ((base)->TARGET_ROOT92_SET) #define CCM_TARGET_ROOT92_CLR_REG(base) ((base)->TARGET_ROOT92_CLR) #define CCM_TARGET_ROOT92_TOG_REG(base) ((base)->TARGET_ROOT92_TOG) #define CCM_POST92_REG(base) ((base)->POST92) #define CCM_POST_ROOT92_SET_REG(base) ((base)->POST_ROOT92_SET) #define CCM_POST_ROOT92_CLR_REG(base) ((base)->POST_ROOT92_CLR) #define CCM_POST_ROOT92_TOG_REG(base) ((base)->POST_ROOT92_TOG) #define CCM_PRE92_REG(base) ((base)->PRE92) #define CCM_PRE_ROOT92_SET_REG(base) ((base)->PRE_ROOT92_SET) #define CCM_PRE_ROOT92_CLR_REG(base) ((base)->PRE_ROOT92_CLR) #define CCM_PRE_ROOT92_TOG_REG(base) ((base)->PRE_ROOT92_TOG) #define CCM_ACCESS_CTRL92_REG(base) ((base)->ACCESS_CTRL92) #define CCM_ACCESS_CTRL92_ROOT_SET_REG(base) ((base)->ACCESS_CTRL92_ROOT_SET) #define CCM_ACCESS_CTRL92_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL92_ROOT_CLR) #define CCM_ACCESS_CTRL92_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL92_ROOT_TOG) #define CCM_TARGET_ROOT93_REG(base) ((base)->TARGET_ROOT93) #define CCM_TARGET_ROOT93_SET_REG(base) ((base)->TARGET_ROOT93_SET) #define CCM_TARGET_ROOT93_CLR_REG(base) ((base)->TARGET_ROOT93_CLR) #define CCM_TARGET_ROOT93_TOG_REG(base) ((base)->TARGET_ROOT93_TOG) #define CCM_POST93_REG(base) ((base)->POST93) #define CCM_POST_ROOT93_SET_REG(base) ((base)->POST_ROOT93_SET) #define CCM_POST_ROOT93_CLR_REG(base) ((base)->POST_ROOT93_CLR) #define CCM_POST_ROOT93_TOG_REG(base) ((base)->POST_ROOT93_TOG) #define CCM_PRE93_REG(base) ((base)->PRE93) #define CCM_PRE_ROOT93_SET_REG(base) ((base)->PRE_ROOT93_SET) #define CCM_PRE_ROOT93_CLR_REG(base) ((base)->PRE_ROOT93_CLR) #define CCM_PRE_ROOT93_TOG_REG(base) ((base)->PRE_ROOT93_TOG) #define CCM_ACCESS_CTRL93_REG(base) ((base)->ACCESS_CTRL93) #define CCM_ACCESS_CTRL93_ROOT_SET_REG(base) ((base)->ACCESS_CTRL93_ROOT_SET) #define CCM_ACCESS_CTRL93_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL93_ROOT_CLR) #define CCM_ACCESS_CTRL93_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL93_ROOT_TOG) #define CCM_TARGET_ROOT94_REG(base) ((base)->TARGET_ROOT94) #define CCM_TARGET_ROOT94_SET_REG(base) ((base)->TARGET_ROOT94_SET) #define CCM_TARGET_ROOT94_CLR_REG(base) ((base)->TARGET_ROOT94_CLR) #define CCM_TARGET_ROOT94_TOG_REG(base) ((base)->TARGET_ROOT94_TOG) #define CCM_POST94_REG(base) ((base)->POST94) #define CCM_POST_ROOT94_SET_REG(base) ((base)->POST_ROOT94_SET) #define CCM_POST_ROOT94_CLR_REG(base) ((base)->POST_ROOT94_CLR) #define CCM_POST_ROOT94_TOG_REG(base) ((base)->POST_ROOT94_TOG) #define CCM_PRE94_REG(base) ((base)->PRE94) #define CCM_PRE_ROOT94_SET_REG(base) ((base)->PRE_ROOT94_SET) #define CCM_PRE_ROOT94_CLR_REG(base) ((base)->PRE_ROOT94_CLR) #define CCM_PRE_ROOT94_TOG_REG(base) ((base)->PRE_ROOT94_TOG) #define CCM_ACCESS_CTRL94_REG(base) ((base)->ACCESS_CTRL94) #define CCM_ACCESS_CTRL94_ROOT_SET_REG(base) ((base)->ACCESS_CTRL94_ROOT_SET) #define CCM_ACCESS_CTRL94_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL94_ROOT_CLR) #define CCM_ACCESS_CTRL94_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL94_ROOT_TOG) #define CCM_TARGET_ROOT95_REG(base) ((base)->TARGET_ROOT95) #define CCM_TARGET_ROOT95_SET_REG(base) ((base)->TARGET_ROOT95_SET) #define CCM_TARGET_ROOT95_CLR_REG(base) ((base)->TARGET_ROOT95_CLR) #define CCM_TARGET_ROOT95_TOG_REG(base) ((base)->TARGET_ROOT95_TOG) #define CCM_POST95_REG(base) ((base)->POST95) #define CCM_POST_ROOT95_SET_REG(base) ((base)->POST_ROOT95_SET) #define CCM_POST_ROOT95_CLR_REG(base) ((base)->POST_ROOT95_CLR) #define CCM_POST_ROOT95_TOG_REG(base) ((base)->POST_ROOT95_TOG) #define CCM_PRE95_REG(base) ((base)->PRE95) #define CCM_PRE_ROOT95_SET_REG(base) ((base)->PRE_ROOT95_SET) #define CCM_PRE_ROOT95_CLR_REG(base) ((base)->PRE_ROOT95_CLR) #define CCM_PRE_ROOT95_TOG_REG(base) ((base)->PRE_ROOT95_TOG) #define CCM_ACCESS_CTRL95_REG(base) ((base)->ACCESS_CTRL95) #define CCM_ACCESS_CTRL95_ROOT_SET_REG(base) ((base)->ACCESS_CTRL95_ROOT_SET) #define CCM_ACCESS_CTRL95_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL95_ROOT_CLR) #define CCM_ACCESS_CTRL95_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL95_ROOT_TOG) #define CCM_TARGET_ROOT96_REG(base) ((base)->TARGET_ROOT96) #define CCM_TARGET_ROOT96_SET_REG(base) ((base)->TARGET_ROOT96_SET) #define CCM_TARGET_ROOT96_CLR_REG(base) ((base)->TARGET_ROOT96_CLR) #define CCM_TARGET_ROOT96_TOG_REG(base) ((base)->TARGET_ROOT96_TOG) #define CCM_POST96_REG(base) ((base)->POST96) #define CCM_POST_ROOT96_SET_REG(base) ((base)->POST_ROOT96_SET) #define CCM_POST_ROOT96_CLR_REG(base) ((base)->POST_ROOT96_CLR) #define CCM_POST_ROOT96_TOG_REG(base) ((base)->POST_ROOT96_TOG) #define CCM_PRE96_REG(base) ((base)->PRE96) #define CCM_PRE_ROOT96_SET_REG(base) ((base)->PRE_ROOT96_SET) #define CCM_PRE_ROOT96_CLR_REG(base) ((base)->PRE_ROOT96_CLR) #define CCM_PRE_ROOT96_TOG_REG(base) ((base)->PRE_ROOT96_TOG) #define CCM_ACCESS_CTRL96_REG(base) ((base)->ACCESS_CTRL96) #define CCM_ACCESS_CTRL96_ROOT_SET_REG(base) ((base)->ACCESS_CTRL96_ROOT_SET) #define CCM_ACCESS_CTRL96_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL96_ROOT_CLR) #define CCM_ACCESS_CTRL96_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL96_ROOT_TOG) #define CCM_TARGET_ROOT97_REG(base) ((base)->TARGET_ROOT97) #define CCM_TARGET_ROOT97_SET_REG(base) ((base)->TARGET_ROOT97_SET) #define CCM_TARGET_ROOT97_CLR_REG(base) ((base)->TARGET_ROOT97_CLR) #define CCM_TARGET_ROOT97_TOG_REG(base) ((base)->TARGET_ROOT97_TOG) #define CCM_POST97_REG(base) ((base)->POST97) #define CCM_POST_ROOT97_SET_REG(base) ((base)->POST_ROOT97_SET) #define CCM_POST_ROOT97_CLR_REG(base) ((base)->POST_ROOT97_CLR) #define CCM_POST_ROOT97_TOG_REG(base) ((base)->POST_ROOT97_TOG) #define CCM_PRE97_REG(base) ((base)->PRE97) #define CCM_PRE_ROOT97_SET_REG(base) ((base)->PRE_ROOT97_SET) #define CCM_PRE_ROOT97_CLR_REG(base) ((base)->PRE_ROOT97_CLR) #define CCM_PRE_ROOT97_TOG_REG(base) ((base)->PRE_ROOT97_TOG) #define CCM_ACCESS_CTRL97_REG(base) ((base)->ACCESS_CTRL97) #define CCM_ACCESS_CTRL97_ROOT_SET_REG(base) ((base)->ACCESS_CTRL97_ROOT_SET) #define CCM_ACCESS_CTRL97_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL97_ROOT_CLR) #define CCM_ACCESS_CTRL97_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL97_ROOT_TOG) #define CCM_TARGET_ROOT98_REG(base) ((base)->TARGET_ROOT98) #define CCM_TARGET_ROOT98_SET_REG(base) ((base)->TARGET_ROOT98_SET) #define CCM_TARGET_ROOT98_CLR_REG(base) ((base)->TARGET_ROOT98_CLR) #define CCM_TARGET_ROOT98_TOG_REG(base) ((base)->TARGET_ROOT98_TOG) #define CCM_POST98_REG(base) ((base)->POST98) #define CCM_POST_ROOT98_SET_REG(base) ((base)->POST_ROOT98_SET) #define CCM_POST_ROOT98_CLR_REG(base) ((base)->POST_ROOT98_CLR) #define CCM_POST_ROOT98_TOG_REG(base) ((base)->POST_ROOT98_TOG) #define CCM_PRE98_REG(base) ((base)->PRE98) #define CCM_PRE_ROOT98_SET_REG(base) ((base)->PRE_ROOT98_SET) #define CCM_PRE_ROOT98_CLR_REG(base) ((base)->PRE_ROOT98_CLR) #define CCM_PRE_ROOT98_TOG_REG(base) ((base)->PRE_ROOT98_TOG) #define CCM_ACCESS_CTRL98_REG(base) ((base)->ACCESS_CTRL98) #define CCM_ACCESS_CTRL98_ROOT_SET_REG(base) ((base)->ACCESS_CTRL98_ROOT_SET) #define CCM_ACCESS_CTRL98_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL98_ROOT_CLR) #define CCM_ACCESS_CTRL98_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL98_ROOT_TOG) #define CCM_TARGET_ROOT99_REG(base) ((base)->TARGET_ROOT99) #define CCM_TARGET_ROOT99_SET_REG(base) ((base)->TARGET_ROOT99_SET) #define CCM_TARGET_ROOT99_CLR_REG(base) ((base)->TARGET_ROOT99_CLR) #define CCM_TARGET_ROOT99_TOG_REG(base) ((base)->TARGET_ROOT99_TOG) #define CCM_POST99_REG(base) ((base)->POST99) #define CCM_POST_ROOT99_SET_REG(base) ((base)->POST_ROOT99_SET) #define CCM_POST_ROOT99_CLR_REG(base) ((base)->POST_ROOT99_CLR) #define CCM_POST_ROOT99_TOG_REG(base) ((base)->POST_ROOT99_TOG) #define CCM_PRE99_REG(base) ((base)->PRE99) #define CCM_PRE_ROOT99_SET_REG(base) ((base)->PRE_ROOT99_SET) #define CCM_PRE_ROOT99_CLR_REG(base) ((base)->PRE_ROOT99_CLR) #define CCM_PRE_ROOT99_TOG_REG(base) ((base)->PRE_ROOT99_TOG) #define CCM_ACCESS_CTRL99_REG(base) ((base)->ACCESS_CTRL99) #define CCM_ACCESS_CTRL99_ROOT_SET_REG(base) ((base)->ACCESS_CTRL99_ROOT_SET) #define CCM_ACCESS_CTRL99_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL99_ROOT_CLR) #define CCM_ACCESS_CTRL99_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL99_ROOT_TOG) #define CCM_TARGET_ROOT100_REG(base) ((base)->TARGET_ROOT100) #define CCM_TARGET_ROOT100_SET_REG(base) ((base)->TARGET_ROOT100_SET) #define CCM_TARGET_ROOT100_CLR_REG(base) ((base)->TARGET_ROOT100_CLR) #define CCM_TARGET_ROOT100_TOG_REG(base) ((base)->TARGET_ROOT100_TOG) #define CCM_POST100_REG(base) ((base)->POST100) #define CCM_POST_ROOT100_SET_REG(base) ((base)->POST_ROOT100_SET) #define CCM_POST_ROOT100_CLR_REG(base) ((base)->POST_ROOT100_CLR) #define CCM_POST_ROOT100_TOG_REG(base) ((base)->POST_ROOT100_TOG) #define CCM_PRE100_REG(base) ((base)->PRE100) #define CCM_PRE_ROOT100_SET_REG(base) ((base)->PRE_ROOT100_SET) #define CCM_PRE_ROOT100_CLR_REG(base) ((base)->PRE_ROOT100_CLR) #define CCM_PRE_ROOT100_TOG_REG(base) ((base)->PRE_ROOT100_TOG) #define CCM_ACCESS_CTRL100_REG(base) ((base)->ACCESS_CTRL100) #define CCM_ACCESS_CTRL100_ROOT_SET_REG(base) ((base)->ACCESS_CTRL100_ROOT_SET) #define CCM_ACCESS_CTRL100_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL100_ROOT_CLR) #define CCM_ACCESS_CTRL100_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL100_ROOT_TOG) #define CCM_TARGET_ROOT101_REG(base) ((base)->TARGET_ROOT101) #define CCM_TARGET_ROOT101_SET_REG(base) ((base)->TARGET_ROOT101_SET) #define CCM_TARGET_ROOT101_CLR_REG(base) ((base)->TARGET_ROOT101_CLR) #define CCM_TARGET_ROOT101_TOG_REG(base) ((base)->TARGET_ROOT101_TOG) #define CCM_POST101_REG(base) ((base)->POST101) #define CCM_POST_ROOT101_SET_REG(base) ((base)->POST_ROOT101_SET) #define CCM_POST_ROOT101_CLR_REG(base) ((base)->POST_ROOT101_CLR) #define CCM_POST_ROOT101_TOG_REG(base) ((base)->POST_ROOT101_TOG) #define CCM_PRE101_REG(base) ((base)->PRE101) #define CCM_PRE_ROOT101_SET_REG(base) ((base)->PRE_ROOT101_SET) #define CCM_PRE_ROOT101_CLR_REG(base) ((base)->PRE_ROOT101_CLR) #define CCM_PRE_ROOT101_TOG_REG(base) ((base)->PRE_ROOT101_TOG) #define CCM_ACCESS_CTRL101_REG(base) ((base)->ACCESS_CTRL101) #define CCM_ACCESS_CTRL101_ROOT_SET_REG(base) ((base)->ACCESS_CTRL101_ROOT_SET) #define CCM_ACCESS_CTRL101_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL101_ROOT_CLR) #define CCM_ACCESS_CTRL101_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL101_ROOT_TOG) #define CCM_TARGET_ROOT102_REG(base) ((base)->TARGET_ROOT102) #define CCM_TARGET_ROOT102_SET_REG(base) ((base)->TARGET_ROOT102_SET) #define CCM_TARGET_ROOT102_CLR_REG(base) ((base)->TARGET_ROOT102_CLR) #define CCM_TARGET_ROOT102_TOG_REG(base) ((base)->TARGET_ROOT102_TOG) #define CCM_POST102_REG(base) ((base)->POST102) #define CCM_POST_ROOT102_SET_REG(base) ((base)->POST_ROOT102_SET) #define CCM_POST_ROOT102_CLR_REG(base) ((base)->POST_ROOT102_CLR) #define CCM_POST_ROOT102_TOG_REG(base) ((base)->POST_ROOT102_TOG) #define CCM_PRE102_REG(base) ((base)->PRE102) #define CCM_PRE_ROOT102_SET_REG(base) ((base)->PRE_ROOT102_SET) #define CCM_PRE_ROOT102_CLR_REG(base) ((base)->PRE_ROOT102_CLR) #define CCM_PRE_ROOT102_TOG_REG(base) ((base)->PRE_ROOT102_TOG) #define CCM_ACCESS_CTRL102_REG(base) ((base)->ACCESS_CTRL102) #define CCM_ACCESS_CTRL102_ROOT_SET_REG(base) ((base)->ACCESS_CTRL102_ROOT_SET) #define CCM_ACCESS_CTRL102_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL102_ROOT_CLR) #define CCM_ACCESS_CTRL102_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL102_ROOT_TOG) #define CCM_TARGET_ROOT103_REG(base) ((base)->TARGET_ROOT103) #define CCM_TARGET_ROOT103_SET_REG(base) ((base)->TARGET_ROOT103_SET) #define CCM_TARGET_ROOT103_CLR_REG(base) ((base)->TARGET_ROOT103_CLR) #define CCM_TARGET_ROOT103_TOG_REG(base) ((base)->TARGET_ROOT103_TOG) #define CCM_POST103_REG(base) ((base)->POST103) #define CCM_POST_ROOT103_SET_REG(base) ((base)->POST_ROOT103_SET) #define CCM_POST_ROOT103_CLR_REG(base) ((base)->POST_ROOT103_CLR) #define CCM_POST_ROOT103_TOG_REG(base) ((base)->POST_ROOT103_TOG) #define CCM_PRE103_REG(base) ((base)->PRE103) #define CCM_PRE_ROOT103_SET_REG(base) ((base)->PRE_ROOT103_SET) #define CCM_PRE_ROOT103_CLR_REG(base) ((base)->PRE_ROOT103_CLR) #define CCM_PRE_ROOT103_TOG_REG(base) ((base)->PRE_ROOT103_TOG) #define CCM_ACCESS_CTRL103_REG(base) ((base)->ACCESS_CTRL103) #define CCM_ACCESS_CTRL103_ROOT_SET_REG(base) ((base)->ACCESS_CTRL103_ROOT_SET) #define CCM_ACCESS_CTRL103_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL103_ROOT_CLR) #define CCM_ACCESS_CTRL103_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL103_ROOT_TOG) #define CCM_TARGET_ROOT104_REG(base) ((base)->TARGET_ROOT104) #define CCM_TARGET_ROOT104_SET_REG(base) ((base)->TARGET_ROOT104_SET) #define CCM_TARGET_ROOT104_CLR_REG(base) ((base)->TARGET_ROOT104_CLR) #define CCM_TARGET_ROOT104_TOG_REG(base) ((base)->TARGET_ROOT104_TOG) #define CCM_POST104_REG(base) ((base)->POST104) #define CCM_POST_ROOT104_SET_REG(base) ((base)->POST_ROOT104_SET) #define CCM_POST_ROOT104_CLR_REG(base) ((base)->POST_ROOT104_CLR) #define CCM_POST_ROOT104_TOG_REG(base) ((base)->POST_ROOT104_TOG) #define CCM_PRE104_REG(base) ((base)->PRE104) #define CCM_PRE_ROOT104_SET_REG(base) ((base)->PRE_ROOT104_SET) #define CCM_PRE_ROOT104_CLR_REG(base) ((base)->PRE_ROOT104_CLR) #define CCM_PRE_ROOT104_TOG_REG(base) ((base)->PRE_ROOT104_TOG) #define CCM_ACCESS_CTRL104_REG(base) ((base)->ACCESS_CTRL104) #define CCM_ACCESS_CTRL104_ROOT_SET_REG(base) ((base)->ACCESS_CTRL104_ROOT_SET) #define CCM_ACCESS_CTRL104_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL104_ROOT_CLR) #define CCM_ACCESS_CTRL104_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL104_ROOT_TOG) #define CCM_TARGET_ROOT105_REG(base) ((base)->TARGET_ROOT105) #define CCM_TARGET_ROOT105_SET_REG(base) ((base)->TARGET_ROOT105_SET) #define CCM_TARGET_ROOT105_CLR_REG(base) ((base)->TARGET_ROOT105_CLR) #define CCM_TARGET_ROOT105_TOG_REG(base) ((base)->TARGET_ROOT105_TOG) #define CCM_POST105_REG(base) ((base)->POST105) #define CCM_POST_ROOT105_SET_REG(base) ((base)->POST_ROOT105_SET) #define CCM_POST_ROOT105_CLR_REG(base) ((base)->POST_ROOT105_CLR) #define CCM_POST_ROOT105_TOG_REG(base) ((base)->POST_ROOT105_TOG) #define CCM_PRE105_REG(base) ((base)->PRE105) #define CCM_PRE_ROOT105_SET_REG(base) ((base)->PRE_ROOT105_SET) #define CCM_PRE_ROOT105_CLR_REG(base) ((base)->PRE_ROOT105_CLR) #define CCM_PRE_ROOT105_TOG_REG(base) ((base)->PRE_ROOT105_TOG) #define CCM_ACCESS_CTRL105_REG(base) ((base)->ACCESS_CTRL105) #define CCM_ACCESS_CTRL105_ROOT_SET_REG(base) ((base)->ACCESS_CTRL105_ROOT_SET) #define CCM_ACCESS_CTRL105_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL105_ROOT_CLR) #define CCM_ACCESS_CTRL105_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL105_ROOT_TOG) #define CCM_TARGET_ROOT106_REG(base) ((base)->TARGET_ROOT106) #define CCM_TARGET_ROOT106_SET_REG(base) ((base)->TARGET_ROOT106_SET) #define CCM_TARGET_ROOT106_CLR_REG(base) ((base)->TARGET_ROOT106_CLR) #define CCM_TARGET_ROOT106_TOG_REG(base) ((base)->TARGET_ROOT106_TOG) #define CCM_POST106_REG(base) ((base)->POST106) #define CCM_POST_ROOT106_SET_REG(base) ((base)->POST_ROOT106_SET) #define CCM_POST_ROOT106_CLR_REG(base) ((base)->POST_ROOT106_CLR) #define CCM_POST_ROOT106_TOG_REG(base) ((base)->POST_ROOT106_TOG) #define CCM_PRE106_REG(base) ((base)->PRE106) #define CCM_PRE_ROOT106_SET_REG(base) ((base)->PRE_ROOT106_SET) #define CCM_PRE_ROOT106_CLR_REG(base) ((base)->PRE_ROOT106_CLR) #define CCM_PRE_ROOT106_TOG_REG(base) ((base)->PRE_ROOT106_TOG) #define CCM_ACCESS_CTRL106_REG(base) ((base)->ACCESS_CTRL106) #define CCM_ACCESS_CTRL106_ROOT_SET_REG(base) ((base)->ACCESS_CTRL106_ROOT_SET) #define CCM_ACCESS_CTRL106_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL106_ROOT_CLR) #define CCM_ACCESS_CTRL106_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL106_ROOT_TOG) #define CCM_TARGET_ROOT107_REG(base) ((base)->TARGET_ROOT107) #define CCM_TARGET_ROOT107_SET_REG(base) ((base)->TARGET_ROOT107_SET) #define CCM_TARGET_ROOT107_CLR_REG(base) ((base)->TARGET_ROOT107_CLR) #define CCM_TARGET_ROOT107_TOG_REG(base) ((base)->TARGET_ROOT107_TOG) #define CCM_POST107_REG(base) ((base)->POST107) #define CCM_POST_ROOT107_SET_REG(base) ((base)->POST_ROOT107_SET) #define CCM_POST_ROOT107_CLR_REG(base) ((base)->POST_ROOT107_CLR) #define CCM_POST_ROOT107_TOG_REG(base) ((base)->POST_ROOT107_TOG) #define CCM_PRE107_REG(base) ((base)->PRE107) #define CCM_PRE_ROOT107_SET_REG(base) ((base)->PRE_ROOT107_SET) #define CCM_PRE_ROOT107_CLR_REG(base) ((base)->PRE_ROOT107_CLR) #define CCM_PRE_ROOT107_TOG_REG(base) ((base)->PRE_ROOT107_TOG) #define CCM_ACCESS_CTRL107_REG(base) ((base)->ACCESS_CTRL107) #define CCM_ACCESS_CTRL107_ROOT_SET_REG(base) ((base)->ACCESS_CTRL107_ROOT_SET) #define CCM_ACCESS_CTRL107_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL107_ROOT_CLR) #define CCM_ACCESS_CTRL107_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL107_ROOT_TOG) #define CCM_TARGET_ROOT108_REG(base) ((base)->TARGET_ROOT108) #define CCM_TARGET_ROOT108_SET_REG(base) ((base)->TARGET_ROOT108_SET) #define CCM_TARGET_ROOT108_CLR_REG(base) ((base)->TARGET_ROOT108_CLR) #define CCM_TARGET_ROOT108_TOG_REG(base) ((base)->TARGET_ROOT108_TOG) #define CCM_POST108_REG(base) ((base)->POST108) #define CCM_POST_ROOT108_SET_REG(base) ((base)->POST_ROOT108_SET) #define CCM_POST_ROOT108_CLR_REG(base) ((base)->POST_ROOT108_CLR) #define CCM_POST_ROOT108_TOG_REG(base) ((base)->POST_ROOT108_TOG) #define CCM_PRE108_REG(base) ((base)->PRE108) #define CCM_PRE_ROOT108_SET_REG(base) ((base)->PRE_ROOT108_SET) #define CCM_PRE_ROOT108_CLR_REG(base) ((base)->PRE_ROOT108_CLR) #define CCM_PRE_ROOT108_TOG_REG(base) ((base)->PRE_ROOT108_TOG) #define CCM_ACCESS_CTRL108_REG(base) ((base)->ACCESS_CTRL108) #define CCM_ACCESS_CTRL108_ROOT_SET_REG(base) ((base)->ACCESS_CTRL108_ROOT_SET) #define CCM_ACCESS_CTRL108_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL108_ROOT_CLR) #define CCM_ACCESS_CTRL108_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL108_ROOT_TOG) #define CCM_TARGET_ROOT109_REG(base) ((base)->TARGET_ROOT109) #define CCM_TARGET_ROOT109_SET_REG(base) ((base)->TARGET_ROOT109_SET) #define CCM_TARGET_ROOT109_CLR_REG(base) ((base)->TARGET_ROOT109_CLR) #define CCM_TARGET_ROOT109_TOG_REG(base) ((base)->TARGET_ROOT109_TOG) #define CCM_POST109_REG(base) ((base)->POST109) #define CCM_POST_ROOT109_SET_REG(base) ((base)->POST_ROOT109_SET) #define CCM_POST_ROOT109_CLR_REG(base) ((base)->POST_ROOT109_CLR) #define CCM_POST_ROOT109_TOG_REG(base) ((base)->POST_ROOT109_TOG) #define CCM_PRE109_REG(base) ((base)->PRE109) #define CCM_PRE_ROOT109_SET_REG(base) ((base)->PRE_ROOT109_SET) #define CCM_PRE_ROOT109_CLR_REG(base) ((base)->PRE_ROOT109_CLR) #define CCM_PRE_ROOT109_TOG_REG(base) ((base)->PRE_ROOT109_TOG) #define CCM_ACCESS_CTRL109_REG(base) ((base)->ACCESS_CTRL109) #define CCM_ACCESS_CTRL109_ROOT_SET_REG(base) ((base)->ACCESS_CTRL109_ROOT_SET) #define CCM_ACCESS_CTRL109_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL109_ROOT_CLR) #define CCM_ACCESS_CTRL109_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL109_ROOT_TOG) #define CCM_TARGET_ROOT110_REG(base) ((base)->TARGET_ROOT110) #define CCM_TARGET_ROOT110_SET_REG(base) ((base)->TARGET_ROOT110_SET) #define CCM_TARGET_ROOT110_CLR_REG(base) ((base)->TARGET_ROOT110_CLR) #define CCM_TARGET_ROOT110_TOG_REG(base) ((base)->TARGET_ROOT110_TOG) #define CCM_POST110_REG(base) ((base)->POST110) #define CCM_POST_ROOT110_SET_REG(base) ((base)->POST_ROOT110_SET) #define CCM_POST_ROOT110_CLR_REG(base) ((base)->POST_ROOT110_CLR) #define CCM_POST_ROOT110_TOG_REG(base) ((base)->POST_ROOT110_TOG) #define CCM_PRE110_REG(base) ((base)->PRE110) #define CCM_PRE_ROOT110_SET_REG(base) ((base)->PRE_ROOT110_SET) #define CCM_PRE_ROOT110_CLR_REG(base) ((base)->PRE_ROOT110_CLR) #define CCM_PRE_ROOT110_TOG_REG(base) ((base)->PRE_ROOT110_TOG) #define CCM_ACCESS_CTRL110_REG(base) ((base)->ACCESS_CTRL110) #define CCM_ACCESS_CTRL110_ROOT_SET_REG(base) ((base)->ACCESS_CTRL110_ROOT_SET) #define CCM_ACCESS_CTRL110_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL110_ROOT_CLR) #define CCM_ACCESS_CTRL110_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL110_ROOT_TOG) #define CCM_TARGET_ROOT111_REG(base) ((base)->TARGET_ROOT111) #define CCM_TARGET_ROOT111_SET_REG(base) ((base)->TARGET_ROOT111_SET) #define CCM_TARGET_ROOT111_CLR_REG(base) ((base)->TARGET_ROOT111_CLR) #define CCM_TARGET_ROOT111_TOG_REG(base) ((base)->TARGET_ROOT111_TOG) #define CCM_POST111_REG(base) ((base)->POST111) #define CCM_POST_ROOT111_SET_REG(base) ((base)->POST_ROOT111_SET) #define CCM_POST_ROOT111_CLR_REG(base) ((base)->POST_ROOT111_CLR) #define CCM_POST_ROOT111_TOG_REG(base) ((base)->POST_ROOT111_TOG) #define CCM_PRE111_REG(base) ((base)->PRE111) #define CCM_PRE_ROOT111_SET_REG(base) ((base)->PRE_ROOT111_SET) #define CCM_PRE_ROOT111_CLR_REG(base) ((base)->PRE_ROOT111_CLR) #define CCM_PRE_ROOT111_TOG_REG(base) ((base)->PRE_ROOT111_TOG) #define CCM_ACCESS_CTRL111_REG(base) ((base)->ACCESS_CTRL111) #define CCM_ACCESS_CTRL111_ROOT_SET_REG(base) ((base)->ACCESS_CTRL111_ROOT_SET) #define CCM_ACCESS_CTRL111_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL111_ROOT_CLR) #define CCM_ACCESS_CTRL111_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL111_ROOT_TOG) #define CCM_TARGET_ROOT112_REG(base) ((base)->TARGET_ROOT112) #define CCM_TARGET_ROOT112_SET_REG(base) ((base)->TARGET_ROOT112_SET) #define CCM_TARGET_ROOT112_CLR_REG(base) ((base)->TARGET_ROOT112_CLR) #define CCM_TARGET_ROOT112_TOG_REG(base) ((base)->TARGET_ROOT112_TOG) #define CCM_POST112_REG(base) ((base)->POST112) #define CCM_POST_ROOT112_SET_REG(base) ((base)->POST_ROOT112_SET) #define CCM_POST_ROOT112_CLR_REG(base) ((base)->POST_ROOT112_CLR) #define CCM_POST_ROOT112_TOG_REG(base) ((base)->POST_ROOT112_TOG) #define CCM_PRE112_REG(base) ((base)->PRE112) #define CCM_PRE_ROOT112_SET_REG(base) ((base)->PRE_ROOT112_SET) #define CCM_PRE_ROOT112_CLR_REG(base) ((base)->PRE_ROOT112_CLR) #define CCM_PRE_ROOT112_TOG_REG(base) ((base)->PRE_ROOT112_TOG) #define CCM_ACCESS_CTRL112_REG(base) ((base)->ACCESS_CTRL112) #define CCM_ACCESS_CTRL112_ROOT_SET_REG(base) ((base)->ACCESS_CTRL112_ROOT_SET) #define CCM_ACCESS_CTRL112_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL112_ROOT_CLR) #define CCM_ACCESS_CTRL112_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL112_ROOT_TOG) #define CCM_TARGET_ROOT113_REG(base) ((base)->TARGET_ROOT113) #define CCM_TARGET_ROOT113_SET_REG(base) ((base)->TARGET_ROOT113_SET) #define CCM_TARGET_ROOT113_CLR_REG(base) ((base)->TARGET_ROOT113_CLR) #define CCM_TARGET_ROOT113_TOG_REG(base) ((base)->TARGET_ROOT113_TOG) #define CCM_POST113_REG(base) ((base)->POST113) #define CCM_POST_ROOT113_SET_REG(base) ((base)->POST_ROOT113_SET) #define CCM_POST_ROOT113_CLR_REG(base) ((base)->POST_ROOT113_CLR) #define CCM_POST_ROOT113_TOG_REG(base) ((base)->POST_ROOT113_TOG) #define CCM_PRE113_REG(base) ((base)->PRE113) #define CCM_PRE_ROOT113_SET_REG(base) ((base)->PRE_ROOT113_SET) #define CCM_PRE_ROOT113_CLR_REG(base) ((base)->PRE_ROOT113_CLR) #define CCM_PRE_ROOT113_TOG_REG(base) ((base)->PRE_ROOT113_TOG) #define CCM_ACCESS_CTRL113_REG(base) ((base)->ACCESS_CTRL113) #define CCM_ACCESS_CTRL113_ROOT_SET_REG(base) ((base)->ACCESS_CTRL113_ROOT_SET) #define CCM_ACCESS_CTRL113_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL113_ROOT_CLR) #define CCM_ACCESS_CTRL113_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL113_ROOT_TOG) #define CCM_TARGET_ROOT114_REG(base) ((base)->TARGET_ROOT114) #define CCM_TARGET_ROOT114_SET_REG(base) ((base)->TARGET_ROOT114_SET) #define CCM_TARGET_ROOT114_CLR_REG(base) ((base)->TARGET_ROOT114_CLR) #define CCM_TARGET_ROOT114_TOG_REG(base) ((base)->TARGET_ROOT114_TOG) #define CCM_POST114_REG(base) ((base)->POST114) #define CCM_POST_ROOT114_SET_REG(base) ((base)->POST_ROOT114_SET) #define CCM_POST_ROOT114_CLR_REG(base) ((base)->POST_ROOT114_CLR) #define CCM_POST_ROOT114_TOG_REG(base) ((base)->POST_ROOT114_TOG) #define CCM_PRE114_REG(base) ((base)->PRE114) #define CCM_PRE_ROOT114_SET_REG(base) ((base)->PRE_ROOT114_SET) #define CCM_PRE_ROOT114_CLR_REG(base) ((base)->PRE_ROOT114_CLR) #define CCM_PRE_ROOT114_TOG_REG(base) ((base)->PRE_ROOT114_TOG) #define CCM_ACCESS_CTRL114_REG(base) ((base)->ACCESS_CTRL114) #define CCM_ACCESS_CTRL114_ROOT_SET_REG(base) ((base)->ACCESS_CTRL114_ROOT_SET) #define CCM_ACCESS_CTRL114_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL114_ROOT_CLR) #define CCM_ACCESS_CTRL114_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL114_ROOT_TOG) #define CCM_TARGET_ROOT115_REG(base) ((base)->TARGET_ROOT115) #define CCM_TARGET_ROOT115_SET_REG(base) ((base)->TARGET_ROOT115_SET) #define CCM_TARGET_ROOT115_CLR_REG(base) ((base)->TARGET_ROOT115_CLR) #define CCM_TARGET_ROOT115_TOG_REG(base) ((base)->TARGET_ROOT115_TOG) #define CCM_POST115_REG(base) ((base)->POST115) #define CCM_POST_ROOT115_SET_REG(base) ((base)->POST_ROOT115_SET) #define CCM_POST_ROOT115_CLR_REG(base) ((base)->POST_ROOT115_CLR) #define CCM_POST_ROOT115_TOG_REG(base) ((base)->POST_ROOT115_TOG) #define CCM_PRE115_REG(base) ((base)->PRE115) #define CCM_PRE_ROOT115_SET_REG(base) ((base)->PRE_ROOT115_SET) #define CCM_PRE_ROOT115_CLR_REG(base) ((base)->PRE_ROOT115_CLR) #define CCM_PRE_ROOT115_TOG_REG(base) ((base)->PRE_ROOT115_TOG) #define CCM_ACCESS_CTRL115_REG(base) ((base)->ACCESS_CTRL115) #define CCM_ACCESS_CTRL115_ROOT_SET_REG(base) ((base)->ACCESS_CTRL115_ROOT_SET) #define CCM_ACCESS_CTRL115_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL115_ROOT_CLR) #define CCM_ACCESS_CTRL115_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL115_ROOT_TOG) #define CCM_TARGET_ROOT116_REG(base) ((base)->TARGET_ROOT116) #define CCM_TARGET_ROOT116_SET_REG(base) ((base)->TARGET_ROOT116_SET) #define CCM_TARGET_ROOT116_CLR_REG(base) ((base)->TARGET_ROOT116_CLR) #define CCM_TARGET_ROOT116_TOG_REG(base) ((base)->TARGET_ROOT116_TOG) #define CCM_POST116_REG(base) ((base)->POST116) #define CCM_POST_ROOT116_SET_REG(base) ((base)->POST_ROOT116_SET) #define CCM_POST_ROOT116_CLR_REG(base) ((base)->POST_ROOT116_CLR) #define CCM_POST_ROOT116_TOG_REG(base) ((base)->POST_ROOT116_TOG) #define CCM_PRE116_REG(base) ((base)->PRE116) #define CCM_PRE_ROOT116_SET_REG(base) ((base)->PRE_ROOT116_SET) #define CCM_PRE_ROOT116_CLR_REG(base) ((base)->PRE_ROOT116_CLR) #define CCM_PRE_ROOT116_TOG_REG(base) ((base)->PRE_ROOT116_TOG) #define CCM_ACCESS_CTRL116_REG(base) ((base)->ACCESS_CTRL116) #define CCM_ACCESS_CTRL116_ROOT_SET_REG(base) ((base)->ACCESS_CTRL116_ROOT_SET) #define CCM_ACCESS_CTRL116_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL116_ROOT_CLR) #define CCM_ACCESS_CTRL116_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL116_ROOT_TOG) #define CCM_TARGET_ROOT117_REG(base) ((base)->TARGET_ROOT117) #define CCM_TARGET_ROOT117_SET_REG(base) ((base)->TARGET_ROOT117_SET) #define CCM_TARGET_ROOT117_CLR_REG(base) ((base)->TARGET_ROOT117_CLR) #define CCM_TARGET_ROOT117_TOG_REG(base) ((base)->TARGET_ROOT117_TOG) #define CCM_POST117_REG(base) ((base)->POST117) #define CCM_POST_ROOT117_SET_REG(base) ((base)->POST_ROOT117_SET) #define CCM_POST_ROOT117_CLR_REG(base) ((base)->POST_ROOT117_CLR) #define CCM_POST_ROOT117_TOG_REG(base) ((base)->POST_ROOT117_TOG) #define CCM_PRE117_REG(base) ((base)->PRE117) #define CCM_PRE_ROOT117_SET_REG(base) ((base)->PRE_ROOT117_SET) #define CCM_PRE_ROOT117_CLR_REG(base) ((base)->PRE_ROOT117_CLR) #define CCM_PRE_ROOT117_TOG_REG(base) ((base)->PRE_ROOT117_TOG) #define CCM_ACCESS_CTRL117_REG(base) ((base)->ACCESS_CTRL117) #define CCM_ACCESS_CTRL117_ROOT_SET_REG(base) ((base)->ACCESS_CTRL117_ROOT_SET) #define CCM_ACCESS_CTRL117_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL117_ROOT_CLR) #define CCM_ACCESS_CTRL117_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL117_ROOT_TOG) #define CCM_TARGET_ROOT118_REG(base) ((base)->TARGET_ROOT118) #define CCM_TARGET_ROOT118_SET_REG(base) ((base)->TARGET_ROOT118_SET) #define CCM_TARGET_ROOT118_CLR_REG(base) ((base)->TARGET_ROOT118_CLR) #define CCM_TARGET_ROOT118_TOG_REG(base) ((base)->TARGET_ROOT118_TOG) #define CCM_POST118_REG(base) ((base)->POST118) #define CCM_POST_ROOT118_SET_REG(base) ((base)->POST_ROOT118_SET) #define CCM_POST_ROOT118_CLR_REG(base) ((base)->POST_ROOT118_CLR) #define CCM_POST_ROOT118_TOG_REG(base) ((base)->POST_ROOT118_TOG) #define CCM_PRE118_REG(base) ((base)->PRE118) #define CCM_PRE_ROOT118_SET_REG(base) ((base)->PRE_ROOT118_SET) #define CCM_PRE_ROOT118_CLR_REG(base) ((base)->PRE_ROOT118_CLR) #define CCM_PRE_ROOT118_TOG_REG(base) ((base)->PRE_ROOT118_TOG) #define CCM_ACCESS_CTRL118_REG(base) ((base)->ACCESS_CTRL118) #define CCM_ACCESS_CTRL118_ROOT_SET_REG(base) ((base)->ACCESS_CTRL118_ROOT_SET) #define CCM_ACCESS_CTRL118_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL118_ROOT_CLR) #define CCM_ACCESS_CTRL118_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL118_ROOT_TOG) #define CCM_TARGET_ROOT119_REG(base) ((base)->TARGET_ROOT119) #define CCM_TARGET_ROOT119_SET_REG(base) ((base)->TARGET_ROOT119_SET) #define CCM_TARGET_ROOT119_CLR_REG(base) ((base)->TARGET_ROOT119_CLR) #define CCM_TARGET_ROOT119_TOG_REG(base) ((base)->TARGET_ROOT119_TOG) #define CCM_POST119_REG(base) ((base)->POST119) #define CCM_POST_ROOT119_SET_REG(base) ((base)->POST_ROOT119_SET) #define CCM_POST_ROOT119_CLR_REG(base) ((base)->POST_ROOT119_CLR) #define CCM_POST_ROOT119_TOG_REG(base) ((base)->POST_ROOT119_TOG) #define CCM_PRE119_REG(base) ((base)->PRE119) #define CCM_PRE_ROOT119_SET_REG(base) ((base)->PRE_ROOT119_SET) #define CCM_PRE_ROOT119_CLR_REG(base) ((base)->PRE_ROOT119_CLR) #define CCM_PRE_ROOT119_TOG_REG(base) ((base)->PRE_ROOT119_TOG) #define CCM_ACCESS_CTRL119_REG(base) ((base)->ACCESS_CTRL119) #define CCM_ACCESS_CTRL119_ROOT_SET_REG(base) ((base)->ACCESS_CTRL119_ROOT_SET) #define CCM_ACCESS_CTRL119_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL119_ROOT_CLR) #define CCM_ACCESS_CTRL119_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL119_ROOT_TOG) #define CCM_TARGET_ROOT120_REG(base) ((base)->TARGET_ROOT120) #define CCM_TARGET_ROOT120_SET_REG(base) ((base)->TARGET_ROOT120_SET) #define CCM_TARGET_ROOT120_CLR_REG(base) ((base)->TARGET_ROOT120_CLR) #define CCM_TARGET_ROOT120_TOG_REG(base) ((base)->TARGET_ROOT120_TOG) #define CCM_POST120_REG(base) ((base)->POST120) #define CCM_POST_ROOT120_SET_REG(base) ((base)->POST_ROOT120_SET) #define CCM_POST_ROOT120_CLR_REG(base) ((base)->POST_ROOT120_CLR) #define CCM_POST_ROOT120_TOG_REG(base) ((base)->POST_ROOT120_TOG) #define CCM_PRE120_REG(base) ((base)->PRE120) #define CCM_PRE_ROOT120_SET_REG(base) ((base)->PRE_ROOT120_SET) #define CCM_PRE_ROOT120_CLR_REG(base) ((base)->PRE_ROOT120_CLR) #define CCM_PRE_ROOT120_TOG_REG(base) ((base)->PRE_ROOT120_TOG) #define CCM_ACCESS_CTRL120_REG(base) ((base)->ACCESS_CTRL120) #define CCM_ACCESS_CTRL120_ROOT_SET_REG(base) ((base)->ACCESS_CTRL120_ROOT_SET) #define CCM_ACCESS_CTRL120_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL120_ROOT_CLR) #define CCM_ACCESS_CTRL120_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL120_ROOT_TOG) /*! * @} */ /* end of group CCM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CCM_Register_Masks CCM Register Masks * @{ */ /* GPR0 Bit Fields */ #define CCM_GPR0_GP0_MASK 0xFFFFFFFFu #define CCM_GPR0_GP0_SHIFT 0 #define CCM_GPR0_GP0(x) (((uint32_t)(((uint32_t)(x))<PLL_ARM) #define CCM_ANALOG_PLL_ARM_SET_REG(base) ((base)->PLL_ARM_SET) #define CCM_ANALOG_PLL_ARM_CLR_REG(base) ((base)->PLL_ARM_CLR) #define CCM_ANALOG_PLL_ARM_TOG_REG(base) ((base)->PLL_ARM_TOG) #define CCM_ANALOG_PLL_DDR_REG(base) ((base)->PLL_DDR) #define CCM_ANALOG_PLL_DDR_SET_REG(base) ((base)->PLL_DDR_SET) #define CCM_ANALOG_PLL_DDR_CLR_REG(base) ((base)->PLL_DDR_CLR) #define CCM_ANALOG_PLL_DDR_TOG_REG(base) ((base)->PLL_DDR_TOG) #define CCM_ANALOG_PLL_DDR_SS_REG(base) ((base)->PLL_DDR_SS) #define CCM_ANALOG_PLL_DDR_NUM_REG(base) ((base)->PLL_DDR_NUM) #define CCM_ANALOG_PLL_DDR_DENOM_REG(base) ((base)->PLL_DDR_DENOM) #define CCM_ANALOG_PLL_480_REG(base) ((base)->PLL_480) #define CCM_ANALOG_PLL_480_SET_REG(base) ((base)->PLL_480_SET) #define CCM_ANALOG_PLL_480_CLR_REG(base) ((base)->PLL_480_CLR) #define CCM_ANALOG_PLL_480_TOG_REG(base) ((base)->PLL_480_TOG) #define CCM_ANALOG_PFD_480A_REG(base) ((base)->PFD_480A) #define CCM_ANALOG_PFD_480A_SET_REG(base) ((base)->PFD_480A_SET) #define CCM_ANALOG_PFD_480A_CLR_REG(base) ((base)->PFD_480A_CLR) #define CCM_ANALOG_PFD_480A_TOG_REG(base) ((base)->PFD_480A_TOG) #define CCM_ANALOG_PFD_480B_REG(base) ((base)->PFD_480B) #define CCM_ANALOG_PFD_480B_SET_REG(base) ((base)->PFD_480B_SET) #define CCM_ANALOG_PFD_480B_CLR_REG(base) ((base)->PFD_480B_CLR) #define CCM_ANALOG_PFD_480B_TOG_REG(base) ((base)->PFD_480B_TOG) #define CCM_ANALOG_PLL_ENET_REG(base) ((base)->PLL_ENET) #define CCM_ANALOG_PLL_ENET_SET_REG(base) ((base)->PLL_ENET_SET) #define CCM_ANALOG_PLL_ENET_CLR_REG(base) ((base)->PLL_ENET_CLR) #define CCM_ANALOG_PLL_ENET_TOG_REG(base) ((base)->PLL_ENET_TOG) #define CCM_ANALOG_PLL_AUDIO_REG(base) ((base)->PLL_AUDIO) #define CCM_ANALOG_PLL_AUDIO_SET_REG(base) ((base)->PLL_AUDIO_SET) #define CCM_ANALOG_PLL_AUDIO_CLR_REG(base) ((base)->PLL_AUDIO_CLR) #define CCM_ANALOG_PLL_AUDIO_TOG_REG(base) ((base)->PLL_AUDIO_TOG) #define CCM_ANALOG_PLL_AUDIO_SS_REG(base) ((base)->PLL_AUDIO_SS) #define CCM_ANALOG_PLL_AUDIO_NUM_REG(base) ((base)->PLL_AUDIO_NUM) #define CCM_ANALOG_PLL_AUDIO_DENOM_REG(base) ((base)->PLL_AUDIO_DENOM) #define CCM_ANALOG_PLL_VIDEO_REG(base) ((base)->PLL_VIDEO) #define CCM_ANALOG_PLL_VIDEO_SET_REG(base) ((base)->PLL_VIDEO_SET) #define CCM_ANALOG_PLL_VIDEO_CLR_REG(base) ((base)->PLL_VIDEO_CLR) #define CCM_ANALOG_PLL_VIDEO_TOG_REG(base) ((base)->PLL_VIDEO_TOG) #define CCM_ANALOG_PLL_VIDEO_SS_REG(base) ((base)->PLL_VIDEO_SS) #define CCM_ANALOG_PLL_VIDEO_NUM_REG(base) ((base)->PLL_VIDEO_NUM) #define CCM_ANALOG_PLL_VIDEO_DENOM_REG(base) ((base)->PLL_VIDEO_DENOM) #define CCM_ANALOG_CLK_MISC0_REG(base) ((base)->CLK_MISC0) #define CCM_ANALOG_CLK_MISC0_SET_REG(base) ((base)->CLK_MISC0_SET) #define CCM_ANALOG_CLK_MISC0_CLR_REG(base) ((base)->CLK_MISC0_CLR) #define CCM_ANALOG_CLK_MISC0_TOG_REG(base) ((base)->CLK_MISC0_TOG) /*! * @} */ /* end of group CCM_ANALOG_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CCM_ANALOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks * @{ */ /* PLL_ARM Bit Fields */ #define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7Fu #define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0 #define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<CSICR1) #define CSI_CSICR2_REG(base) ((base)->CSICR2) #define CSI_CSICR3_REG(base) ((base)->CSICR3) #define CSI_CSISTATFIFO_REG(base) ((base)->CSISTATFIFO) #define CSI_CSIRFIFO_REG(base) ((base)->CSIRFIFO) #define CSI_CSIRXCNT_REG(base) ((base)->CSIRXCNT) #define CSI_CSISR_REG(base) ((base)->CSISR) #define CSI_CSIDMASA_STATFIFO_REG(base) ((base)->CSIDMASA_STATFIFO) #define CSI_CSIDMATS_STATFIFO_REG(base) ((base)->CSIDMATS_STATFIFO) #define CSI_CSIDMASA_FB1_REG(base) ((base)->CSIDMASA_FB1) #define CSI_CSIDMASA_FB2_REG(base) ((base)->CSIDMASA_FB2) #define CSI_CSIFBUF_PARA_REG(base) ((base)->CSIFBUF_PARA) #define CSI_CSIIMAG_PARA_REG(base) ((base)->CSIIMAG_PARA) #define CSI_CSICR18_REG(base) ((base)->CSICR18) #define CSI_CSICR19_REG(base) ((base)->CSICR19) /*! * @} */ /* end of group CSI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CSI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CSI_Register_Masks CSI Register Masks * @{ */ /* CSICR1 Bit Fields */ #define CSI_CSICR1_PIXEL_BIT_MASK 0x1u #define CSI_CSICR1_PIXEL_BIT_SHIFT 0 #define CSI_CSICR1_REDGE_MASK 0x2u #define CSI_CSICR1_REDGE_SHIFT 1 #define CSI_CSICR1_INV_PCLK_MASK 0x4u #define CSI_CSICR1_INV_PCLK_SHIFT 2 #define CSI_CSICR1_INV_DATA_MASK 0x8u #define CSI_CSICR1_INV_DATA_SHIFT 3 #define CSI_CSICR1_GCLK_MODE_MASK 0x10u #define CSI_CSICR1_GCLK_MODE_SHIFT 4 #define CSI_CSICR1_CLR_RXFIFO_MASK 0x20u #define CSI_CSICR1_CLR_RXFIFO_SHIFT 5 #define CSI_CSICR1_CLR_STATFIFO_MASK 0x40u #define CSI_CSICR1_CLR_STATFIFO_SHIFT 6 #define CSI_CSICR1_PACK_DIR_MASK 0x80u #define CSI_CSICR1_PACK_DIR_SHIFT 7 #define CSI_CSICR1_FCC_MASK 0x100u #define CSI_CSICR1_FCC_SHIFT 8 #define CSI_CSICR1_CCIR_EN_MASK 0x400u #define CSI_CSICR1_CCIR_EN_SHIFT 10 #define CSI_CSICR1_HSYNC_POL_MASK 0x800u #define CSI_CSICR1_HSYNC_POL_SHIFT 11 #define CSI_CSICR1_SOF_INTEN_MASK 0x10000u #define CSI_CSICR1_SOF_INTEN_SHIFT 16 #define CSI_CSICR1_SOF_POL_MASK 0x20000u #define CSI_CSICR1_SOF_POL_SHIFT 17 #define CSI_CSICR1_RXFF_INTEN_MASK 0x40000u #define CSI_CSICR1_RXFF_INTEN_SHIFT 18 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK 0x80000u #define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT 19 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK 0x100000u #define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT 20 #define CSI_CSICR1_STATFF_INTEN_MASK 0x200000u #define CSI_CSICR1_STATFF_INTEN_SHIFT 21 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK 0x400000u #define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT 22 #define CSI_CSICR1_RF_OR_INTEN_MASK 0x1000000u #define CSI_CSICR1_RF_OR_INTEN_SHIFT 24 #define CSI_CSICR1_SF_OR_INTEN_MASK 0x2000000u #define CSI_CSICR1_SF_OR_INTEN_SHIFT 25 #define CSI_CSICR1_COF_INT_EN_MASK 0x4000000u #define CSI_CSICR1_COF_INT_EN_SHIFT 26 #define CSI_CSICR1_VIDEO_MODE_MASK 0x8000000u #define CSI_CSICR1_VIDEO_MODE_SHIFT 27 #define CSI_CSICR1_PrP_IF_EN_MASK 0x10000000u #define CSI_CSICR1_PrP_IF_EN_SHIFT 28 #define CSI_CSICR1_EOF_INT_EN_MASK 0x20000000u #define CSI_CSICR1_EOF_INT_EN_SHIFT 29 #define CSI_CSICR1_EXT_VSYNC_MASK 0x40000000u #define CSI_CSICR1_EXT_VSYNC_SHIFT 30 #define CSI_CSICR1_SWAP16_EN_MASK 0x80000000u #define CSI_CSICR1_SWAP16_EN_SHIFT 31 /* CSICR2 Bit Fields */ #define CSI_CSICR2_HSC_MASK 0xFFu #define CSI_CSICR2_HSC_SHIFT 0 #define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x))<MSTR) #define DDRC_STAT_REG(base) ((base)->STAT) #define DDRC_MRCTRL0_REG(base) ((base)->MRCTRL0) #define DDRC_MRCTRL1_REG(base) ((base)->MRCTRL1) #define DDRC_MRSTAT_REG(base) ((base)->MRSTAT) #define DDRC_DERATEEN_REG(base) ((base)->DERATEEN) #define DDRC_DERATEINT_REG(base) ((base)->DERATEINT) #define DDRC_PWRCTL_REG(base) ((base)->PWRCTL) #define DDRC_PWRTMG_REG(base) ((base)->PWRTMG) #define DDRC_HWLPCTL_REG(base) ((base)->HWLPCTL) #define DDRC_RFSHCTL0_REG(base) ((base)->RFSHCTL0) #define DDRC_RFSHCTL1_REG(base) ((base)->RFSHCTL1) #define DDRC_RFSHCTL3_REG(base) ((base)->RFSHCTL3) #define DDRC_RFSHTMG_REG(base) ((base)->RFSHTMG) #define DDRC_INIT0_REG(base) ((base)->INIT0) #define DDRC_INIT1_REG(base) ((base)->INIT1) #define DDRC_INIT2_REG(base) ((base)->INIT2) #define DDRC_INIT3_REG(base) ((base)->INIT3) #define DDRC_INIT4_REG(base) ((base)->INIT4) #define DDRC_INIT5_REG(base) ((base)->INIT5) #define DDRC_DRAMTMG0_REG(base) ((base)->DRAMTMG0) #define DDRC_DRAMTMG1_REG(base) ((base)->DRAMTMG1) #define DDRC_DRAMTMG2_REG(base) ((base)->DRAMTMG2) #define DDRC_DRAMTMG3_REG(base) ((base)->DRAMTMG3) #define DDRC_DRAMTMG4_REG(base) ((base)->DRAMTMG4) #define DDRC_DRAMTMG5_REG(base) ((base)->DRAMTMG5) #define DDRC_DRAMTMG6_REG(base) ((base)->DRAMTMG6) #define DDRC_DRAMTMG7_REG(base) ((base)->DRAMTMG7) #define DDRC_DRAMTMG8_REG(base) ((base)->DRAMTMG8) #define DDRC_ZQCTL0_REG(base) ((base)->ZQCTL0) #define DDRC_ZQCTL1_REG(base) ((base)->ZQCTL1) #define DDRC_ZQCTL2_REG(base) ((base)->ZQCTL2) #define DDRC_ZQSTAT_REG(base) ((base)->ZQSTAT) #define DDRC_DFITMG0_REG(base) ((base)->DFITMG0) #define DDRC_DFITMG1_REG(base) ((base)->DFITMG1) #define DDRC_DFILPCFG0_REG(base) ((base)->DFILPCFG0) #define DDRC_DFIUPD0_REG(base) ((base)->DFIUPD0) #define DDRC_DFIUPD1_REG(base) ((base)->DFIUPD1) #define DDRC_DFIUPD2_REG(base) ((base)->DFIUPD2) #define DDRC_DFIUPD3_REG(base) ((base)->DFIUPD3) #define DDRC_DFIMISC_REG(base) ((base)->DFIMISC) #define DDRC_ADDRMAP0_REG(base) ((base)->ADDRMAP0) #define DDRC_ADDRMAP1_REG(base) ((base)->ADDRMAP1) #define DDRC_ADDRMAP2_REG(base) ((base)->ADDRMAP2) #define DDRC_ADDRMAP3_REG(base) ((base)->ADDRMAP3) #define DDRC_ADDRMAP4_REG(base) ((base)->ADDRMAP4) #define DDRC_ADDRMAP5_REG(base) ((base)->ADDRMAP5) #define DDRC_ADDRMAP6_REG(base) ((base)->ADDRMAP6) #define DDRC_ODTCFG_REG(base) ((base)->ODTCFG) #define DDRC_ODTMAP_REG(base) ((base)->ODTMAP) #define DDRC_SCHED_REG(base) ((base)->SCHED) #define DDRC_SCHED1_REG(base) ((base)->SCHED1) #define DDRC_PERFHPR1_REG(base) ((base)->PERFHPR1) #define DDRC_PERFLPR1_REG(base) ((base)->PERFLPR1) #define DDRC_PERFWR1_REG(base) ((base)->PERFWR1) #define DDRC_PERFVPR1_REG(base) ((base)->PERFVPR1) #define DDRC_PERFVPW1_REG(base) ((base)->PERFVPW1) #define DDRC_DBG0_REG(base) ((base)->DBG0) #define DDRC_DBG1_REG(base) ((base)->DBG1) #define DDRC_DBGCAM_REG(base) ((base)->DBGCAM) #define DDRC_DBGCMD_REG(base) ((base)->DBGCMD) #define DDRC_DBGSTAT_REG(base) ((base)->DBGSTAT) #define DDRC_SWCTL_REG(base) ((base)->SWCTL) #define DDRC_SWSTAT_REG(base) ((base)->SWSTAT) /*! * @} */ /* end of group DDRC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DDRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DDRC_Register_Masks DDRC Register Masks * @{ */ /* MSTR Bit Fields */ #define DDRC_MSTR_DDR3_MASK 0x1u #define DDRC_MSTR_DDR3_SHIFT 0 #define DDRC_MSTR_LPDDR2_MASK 0x4u #define DDRC_MSTR_LPDDR2_SHIFT 2 #define DDRC_MSTR_LPDDR3_MASK 0x8u #define DDRC_MSTR_LPDDR3_SHIFT 3 #define DDRC_MSTR_BURST_MODE_MASK 0x100u #define DDRC_MSTR_BURST_MODE_SHIFT 8 #define DDRC_MSTR_BURSTCHOP_MASK 0x200u #define DDRC_MSTR_BURSTCHOP_SHIFT 9 #define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x3000u #define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12 #define DDRC_MSTR_DATA_BUS_WIDTH(x) (((uint32_t)(((uint32_t)(x))<PSTAT) #define DDRC_MP_PCCFG_REG(base) ((base)->PCCFG) #define DDRC_MP_PCFGR_0_REG(base) ((base)->PCFGR_0) #define DDRC_MP_PCFGW_0_REG(base) ((base)->PCFGW_0) #define DDRC_MP_PCFGIDMASKCH_0_REG(base,index) ((base)->PCFGID[index].PCFGIDMASKCH_0) #define DDRC_MP_PCFGIDVALUECH_0_REG(base,index) ((base)->PCFGID[index].PCFGIDVALUECH_0) #define DDRC_MP_PCTRL_0_REG(base) ((base)->PCTRL_0) #define DDRC_MP_PCFGQOS0_0_REG(base) ((base)->PCFGQOS0_0) #define DDRC_MP_PCFGQOS1_0_REG(base) ((base)->PCFGQOS1_0) #define DDRC_MP_PCFGWQOS0_0_REG(base) ((base)->PCFGWQOS0_0) #define DDRC_MP_PCFGWQOS1_0_REG(base) ((base)->PCFGWQOS1_0) #define DDRC_MP_SARBASE_REG(base,index) ((base)->SAR[index].SARBASE) #define DDRC_MP_SARSIZE_REG(base,index) ((base)->SAR[index].SARSIZE) /*! * @} */ /* end of group DDRC_MP_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DDRC_MP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DDRC_MP_Register_Masks DDRC_MP Register Masks * @{ */ /* PSTAT Bit Fields */ #define DDRC_MP_PSTAT_RD_PORT_BUSY_0_MASK 0x1u #define DDRC_MP_PSTAT_RD_PORT_BUSY_0_SHIFT 0 /* PCCFG Bit Fields */ #define DDRC_MP_PCCFG_GO2CRITICAL_EN_MASK 0x1u #define DDRC_MP_PCCFG_GO2CRITICAL_EN_SHIFT 0 #define DDRC_MP_PCCFG_PAGEMATCH_LIMIT_MASK 0x10u #define DDRC_MP_PCCFG_PAGEMATCH_LIMIT_SHIFT 4 /* PCFGR_0 Bit Fields */ #define DDRC_MP_PCFGR_0_RD_PORT_PRIORITY_MASK 0x3FFu #define DDRC_MP_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0 #define DDRC_MP_PCFGR_0_RD_PORT_PRIORITY(x) (((uint32_t)(((uint32_t)(x))<PHY_CON0) #define DDR_PHY_PHY_CON1_REG(base) ((base)->PHY_CON1) #define DDR_PHY_PHY_CON2_REG(base) ((base)->PHY_CON2) #define DDR_PHY_PHY_CON3_REG(base) ((base)->PHY_CON3) #define DDR_PHY_CON4_REG(base) ((base)->CON4) #define DDR_PHY_PHY_CON5_REG(base) ((base)->PHY_CON5) #define DDR_PHY_LP_CON0_REG(base) ((base)->LP_CON0) #define DDR_PHY_RODT_CON0_REG(base) ((base)->RODT_CON0) #define DDR_PHY_OFFSET_RD_CON0_REG(base) ((base)->OFFSET_RD_CON0) #define DDR_PHY_OFFSET_WR_CON0_REG(base) ((base)->OFFSET_WR_CON0) #define DDR_PHY_GATE_CODE_CON0_REG(base) ((base)->GATE_CODE_CON0) #define DDR_PHY_SHIFTC_CON0_REG(base) ((base)->SHIFTC_CON0) #define DDR_PHY_CMD_SDLL_CON0_REG(base) ((base)->CMD_SDLL_CON0) #define DDR_PHY_LVL_CON0_REG(base) ((base)->LVL_CON0) #define DDR_PHY_LVL_CON3_REG(base) ((base)->LVL_CON3) #define DDR_PHY_CMD_DESKEW_CON0_REG(base) ((base)->CMD_DESKEW_CON0) #define DDR_PHY_CMD_DESKEW_CON1_REG(base) ((base)->CMD_DESKEW_CON1) #define DDR_PHY_CMD_DESKEW_CON2_REG(base) ((base)->CMD_DESKEW_CON2) #define DDR_PHY_CMD_DESKEW_CON3_REG(base) ((base)->CMD_DESKEW_CON3) #define DDR_PHY_CMD_DESKEW_CON4_REG(base) ((base)->CMD_DESKEW_CON4) #define DDR_PHY_DRVDS_CON0_REG(base) ((base)->DRVDS_CON0) #define DDR_PHY_MDLL_CON0_REG(base) ((base)->MDLL_CON0) #define DDR_PHY_MDLL_CON1_REG(base) ((base)->MDLL_CON1) #define DDR_PHY_ZQ_CON0_REG(base) ((base)->ZQ_CON0) #define DDR_PHY_ZQ_CON1_REG(base) ((base)->ZQ_CON1) #define DDR_PHY_ZQ_CON2_REG(base) ((base)->ZQ_CON2) #define DDR_PHY_RD_DESKEW_CON0_REG(base) ((base)->RD_DESKEW_CON0) #define DDR_PHY_RD_DESKEW_CON3_REG(base) ((base)->RD_DESKEW_CON3) #define DDR_PHY_RD_DESKEW_CON6_REG(base) ((base)->RD_DESKEW_CON6) #define DDR_PHY_RD_DESKEW_CON9_REG(base) ((base)->RD_DESKEW_CON9) #define DDR_PHY_RD_DESKEW_CON12_REG(base) ((base)->RD_DESKEW_CON12) #define DDR_PHY_RD_DESKEW_CON15_REG(base) ((base)->RD_DESKEW_CON15) #define DDR_PHY_RD_DESKEW_CON18_REG(base) ((base)->RD_DESKEW_CON18) #define DDR_PHY_RD_DESKEW_CON21_REG(base) ((base)->RD_DESKEW_CON21) #define DDR_PHY_WR_DESKEW_CON0_REG(base) ((base)->WR_DESKEW_CON0) #define DDR_PHY_WR_DESKEW_CON3_REG(base) ((base)->WR_DESKEW_CON3) #define DDR_PHY_WR_DESKEW_CON6_REG(base) ((base)->WR_DESKEW_CON6) #define DDR_PHY_WR_DESKEW_CON9_REG(base) ((base)->WR_DESKEW_CON9) #define DDR_PHY_WR_DESKEW_CON12_REG(base) ((base)->WR_DESKEW_CON12) #define DDR_PHY_WR_DESKEW_CON15_REG(base) ((base)->WR_DESKEW_CON15) #define DDR_PHY_WR_DESKEW_CON18_REG(base) ((base)->WR_DESKEW_CON18) #define DDR_PHY_WR_DESKEW_CON21_REG(base) ((base)->WR_DESKEW_CON21) #define DDR_PHY_DM_DESKEW_CON_REG(base) ((base)->DM_DESKEW_CON) #define DDR_PHY_RDATA0_REG(base) ((base)->RDATA0) #define DDR_PHY_STAT0_REG(base) ((base)->STAT0) /*! * @} */ /* end of group DDR_PHY_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DDR_PHY Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DDR_PHY_Register_Masks DDR_PHY Register Masks * @{ */ /* PHY_CON0 Bit Fields */ #define DDR_PHY_PHY_CON0_CTRL_FNC_FB_MASK 0x7u #define DDR_PHY_PHY_CON0_CTRL_FNC_FB_SHIFT 0 #define DDR_PHY_PHY_CON0_CTRL_FNC_FB(x) (((uint32_t)(((uint32_t)(x))<RXDATA) #define ECSPI_TXDATA_REG(base) ((base)->TXDATA) #define ECSPI_CONREG_REG(base) ((base)->CONREG) #define ECSPI_CONFIGREG_REG(base) ((base)->CONFIGREG) #define ECSPI_INTREG_REG(base) ((base)->INTREG) #define ECSPI_DMAREG_REG(base) ((base)->DMAREG) #define ECSPI_STATREG_REG(base) ((base)->STATREG) #define ECSPI_PERIODREG_REG(base) ((base)->PERIODREG) #define ECSPI_TESTREG_REG(base) ((base)->TESTREG) #define ECSPI_MSGDATA_REG(base) ((base)->MSGDATA) /*! * @} */ /* end of group ECSPI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ECSPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ECSPI_Register_Masks ECSPI Register Masks * @{ */ /* RXDATA Bit Fields */ #define ECSPI_RXDATA_ECSPI_RXDATA_MASK 0xFFFFFFFFu #define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT 0 #define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x))<CSCR[index].CSGCR1) #define EIM_CSGCR2_REG(base,index) ((base)->CSCR[index].CSGCR2) #define EIM_CSRCR1_REG(base,index) ((base)->CSCR[index].CSRCR1) #define EIM_CSRCR2_REG(base,index) ((base)->CSCR[index].CSRCR2) #define EIM_CSWCR1_REG(base,index) ((base)->CSCR[index].CSWCR1) #define EIM_CSWCR2_REG(base,index) ((base)->CSCR[index].CSWCR2) #define EIM_WCR_REG(base) ((base)->WCR) #define EIM_DCR_REG(base) ((base)->DCR) #define EIM_DSR_REG(base) ((base)->DSR) #define EIM_WIAR_REG(base) ((base)->WIAR) #define EIM_EAR_REG(base) ((base)->EAR) /*! * @} */ /* end of group EIM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- EIM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup EIM_Register_Masks EIM Register Masks * @{ */ /* CSGCR1 Bit Fields */ #define EIM_CSGCR1_CSEN_MASK 0x1u #define EIM_CSGCR1_CSEN_SHIFT 0 #define EIM_CSGCR1_SWR_MASK 0x2u #define EIM_CSGCR1_SWR_SHIFT 1 #define EIM_CSGCR1_SRD_MASK 0x4u #define EIM_CSGCR1_SRD_SHIFT 2 #define EIM_CSGCR1_MUM_MASK 0x8u #define EIM_CSGCR1_MUM_SHIFT 3 #define EIM_CSGCR1_WFL_MASK 0x10u #define EIM_CSGCR1_WFL_SHIFT 4 #define EIM_CSGCR1_RFL_MASK 0x20u #define EIM_CSGCR1_RFL_SHIFT 5 #define EIM_CSGCR1_CRE_MASK 0x40u #define EIM_CSGCR1_CRE_SHIFT 6 #define EIM_CSGCR1_CREP_MASK 0x80u #define EIM_CSGCR1_CREP_SHIFT 7 #define EIM_CSGCR1_BL_MASK 0x700u #define EIM_CSGCR1_BL_SHIFT 8 #define EIM_CSGCR1_BL(x) (((uint32_t)(((uint32_t)(x))<VER_ID) #define EMVSIM_PARAM_REG(base) ((base)->PARAM) #define EMVSIM_CLKCFG_REG(base) ((base)->CLKCFG) #define EMVSIM_DIVISOR_REG(base) ((base)->DIVISOR) #define EMVSIM_CTRL_REG(base) ((base)->CTRL) #define EMVSIM_INT_MASK_REG(base) ((base)->INT_MASK) #define EMVSIM_RX_THD_REG(base) ((base)->RX_THD) #define EMVSIM_TX_THD_REG(base) ((base)->TX_THD) #define EMVSIM_RX_STATUS_REG(base) ((base)->RX_STATUS) #define EMVSIM_TX_STATUS_REG(base) ((base)->TX_STATUS) #define EMVSIM_PCSR_REG(base) ((base)->PCSR) #define EMVSIM_RX_BUF_REG(base) ((base)->RX_BUF) #define EMVSIM_TX_BUF_REG(base) ((base)->TX_BUF) #define EMVSIM_TX_GETU_REG(base) ((base)->TX_GETU) #define EMVSIM_CWT_VAL_REG(base) ((base)->CWT_VAL) #define EMVSIM_BWT_VAL_REG(base) ((base)->BWT_VAL) #define EMVSIM_BGT_VAL_REG(base) ((base)->BGT_VAL) #define EMVSIM_GPCNT0_VAL_REG(base) ((base)->GPCNT0_VAL) #define EMVSIM_GPCNT1_VAL_REG(base) ((base)->GPCNT1_VAL) /*! * @} */ /* end of group EMVSIM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- EMVSIM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks * @{ */ /* VER_ID Bit Fields */ #define EMVSIM_VER_ID_VER_MASK 0xFFFFFFFFu #define EMVSIM_VER_ID_VER_SHIFT 0 #define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x))<EIR) #define ENET_EIMR_REG(base) ((base)->EIMR) #define ENET_RDAR_REG(base) ((base)->RDAR) #define ENET_TDAR_REG(base) ((base)->TDAR) #define ENET_ECR_REG(base) ((base)->ECR) #define ENET_MMFR_REG(base) ((base)->MMFR) #define ENET_MSCR_REG(base) ((base)->MSCR) #define ENET_MIBC_REG(base) ((base)->MIBC) #define ENET_RCR_REG(base) ((base)->RCR) #define ENET_TCR_REG(base) ((base)->TCR) #define ENET_PALR_REG(base) ((base)->PALR) #define ENET_PAUR_REG(base) ((base)->PAUR) #define ENET_OPD_REG(base) ((base)->OPD) #define ENET_TXIC_REG(base,index) ((base)->TXIC[index]) #define ENET_RXIC_REG(base,index) ((base)->RXIC[index]) #define ENET_IAUR_REG(base) ((base)->IAUR) #define ENET_IALR_REG(base) ((base)->IALR) #define ENET_GAUR_REG(base) ((base)->GAUR) #define ENET_GALR_REG(base) ((base)->GALR) #define ENET_TFWR_REG(base) ((base)->TFWR) #define ENET_RDSR1_REG(base) ((base)->RDSR1) #define ENET_TDSR1_REG(base) ((base)->TDSR1) #define ENET_MRBR1_REG(base) ((base)->MRBR1) #define ENET_RDSR2_REG(base) ((base)->RDSR2) #define ENET_TDSR2_REG(base) ((base)->TDSR2) #define ENET_MRBR2_REG(base) ((base)->MRBR2) #define ENET_RDSR_REG(base) ((base)->RDSR) #define ENET_TDSR_REG(base) ((base)->TDSR) #define ENET_MRBR_REG(base) ((base)->MRBR) #define ENET_RSFL_REG(base) ((base)->RSFL) #define ENET_RSEM_REG(base) ((base)->RSEM) #define ENET_RAEM_REG(base) ((base)->RAEM) #define ENET_RAFL_REG(base) ((base)->RAFL) #define ENET_TSEM_REG(base) ((base)->TSEM) #define ENET_TAEM_REG(base) ((base)->TAEM) #define ENET_TAFL_REG(base) ((base)->TAFL) #define ENET_TIPG_REG(base) ((base)->TIPG) #define ENET_FTRL_REG(base) ((base)->FTRL) #define ENET_TACC_REG(base) ((base)->TACC) #define ENET_RACC_REG(base) ((base)->RACC) #define ENET_RCMR_REG(base,index) ((base)->RCMR[index]) #define ENET_DMACFG_REG(base,index) ((base)->DMACFG[index]) #define ENET_RDAR1_REG(base) ((base)->RDAR1) #define ENET_TDAR1_REG(base) ((base)->TDAR1) #define ENET_RDAR2_REG(base) ((base)->RDAR2) #define ENET_TDAR2_REG(base) ((base)->TDAR2) #define ENET_QOS_REG(base) ((base)->QOS) #define ENET_RMON_T_DROP_REG(base) ((base)->RMON_T_DROP) #define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS) #define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT) #define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT) #define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN) #define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE) #define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE) #define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG) #define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB) #define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL) #define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64) #define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127) #define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255) #define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511) #define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023) #define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047) #define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048) #define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS) #define ENET_IEEE_T_DROP_REG(base) ((base)->IEEE_T_DROP) #define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK) #define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL) #define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL) #define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF) #define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL) #define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL) #define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR) #define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR) #define ENET_IEEE_T_SQE_REG(base) ((base)->IEEE_T_SQE) #define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC) #define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK) #define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS) #define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT) #define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT) #define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN) #define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE) #define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE) #define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG) #define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB) #define ENET_RMON_R_RESVD_0_REG(base) ((base)->RMON_R_RESVD_0) #define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64) #define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127) #define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255) #define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511) #define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023) #define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047) #define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048) #define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS) #define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP) #define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK) #define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC) #define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN) #define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR) #define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC) #define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK) #define ENET_ATCR_REG(base) ((base)->ATCR) #define ENET_ATVR_REG(base) ((base)->ATVR) #define ENET_ATOFF_REG(base) ((base)->ATOFF) #define ENET_ATPER_REG(base) ((base)->ATPER) #define ENET_ATCOR_REG(base) ((base)->ATCOR) #define ENET_ATINC_REG(base) ((base)->ATINC) #define ENET_ATSTMP_REG(base) ((base)->ATSTMP) #define ENET_TGSR_REG(base) ((base)->TGSR) #define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR) #define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR) /*! * @} */ /* end of group ENET_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ENET Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_Register_Masks ENET Register Masks * @{ */ /* EIR Bit Fields */ #define ENET_EIR_RXB1_MASK 0x1u #define ENET_EIR_RXB1_SHIFT 0 #define ENET_EIR_RXF1_MASK 0x2u #define ENET_EIR_RXF1_SHIFT 1 #define ENET_EIR_TXB1_MASK 0x4u #define ENET_EIR_TXB1_SHIFT 2 #define ENET_EIR_TXF1_MASK 0x8u #define ENET_EIR_TXF1_SHIFT 3 #define ENET_EIR_RXB2_MASK 0x10u #define ENET_EIR_RXB2_SHIFT 4 #define ENET_EIR_RXF2_MASK 0x20u #define ENET_EIR_RXF2_SHIFT 5 #define ENET_EIR_TXB2_MASK 0x40u #define ENET_EIR_TXB2_SHIFT 6 #define ENET_EIR_TXF2_MASK 0x80u #define ENET_EIR_TXF2_SHIFT 7 #define ENET_EIR_RXFLUSH_0_MASK 0x1000u #define ENET_EIR_RXFLUSH_0_SHIFT 12 #define ENET_EIR_RXFLUSH_1_MASK 0x2000u #define ENET_EIR_RXFLUSH_1_SHIFT 13 #define ENET_EIR_RXFLUSH_2_MASK 0x4000u #define ENET_EIR_RXFLUSH_2_SHIFT 14 #define ENET_EIR_TS_TIMER_MASK 0x8000u #define ENET_EIR_TS_TIMER_SHIFT 15 #define ENET_EIR_TS_AVAIL_MASK 0x10000u #define ENET_EIR_TS_AVAIL_SHIFT 16 #define ENET_EIR_WAKEUP_MASK 0x20000u #define ENET_EIR_WAKEUP_SHIFT 17 #define ENET_EIR_PLR_MASK 0x40000u #define ENET_EIR_PLR_SHIFT 18 #define ENET_EIR_UN_MASK 0x80000u #define ENET_EIR_UN_SHIFT 19 #define ENET_EIR_RL_MASK 0x100000u #define ENET_EIR_RL_SHIFT 20 #define ENET_EIR_LC_MASK 0x200000u #define ENET_EIR_LC_SHIFT 21 #define ENET_EIR_EBERR_MASK 0x400000u #define ENET_EIR_EBERR_SHIFT 22 #define ENET_EIR_MII_MASK 0x800000u #define ENET_EIR_MII_SHIFT 23 #define ENET_EIR_RXB_MASK 0x1000000u #define ENET_EIR_RXB_SHIFT 24 #define ENET_EIR_RXF_MASK 0x2000000u #define ENET_EIR_RXF_SHIFT 25 #define ENET_EIR_TXB_MASK 0x4000000u #define ENET_EIR_TXB_SHIFT 26 #define ENET_EIR_TXF_MASK 0x8000000u #define ENET_EIR_TXF_SHIFT 27 #define ENET_EIR_GRA_MASK 0x10000000u #define ENET_EIR_GRA_SHIFT 28 #define ENET_EIR_BABT_MASK 0x20000000u #define ENET_EIR_BABT_SHIFT 29 #define ENET_EIR_BABR_MASK 0x40000000u #define ENET_EIR_BABR_SHIFT 30 /* EIMR Bit Fields */ #define ENET_EIMR_RXB1_MASK 0x1u #define ENET_EIMR_RXB1_SHIFT 0 #define ENET_EIMR_RXF1_MASK 0x2u #define ENET_EIMR_RXF1_SHIFT 1 #define ENET_EIMR_TXB1_MASK 0x4u #define ENET_EIMR_TXB1_SHIFT 2 #define ENET_EIMR_TXF1_MASK 0x8u #define ENET_EIMR_TXF1_SHIFT 3 #define ENET_EIMR_RXB2_MASK 0x10u #define ENET_EIMR_RXB2_SHIFT 4 #define ENET_EIMR_RXF2_MASK 0x20u #define ENET_EIMR_RXF2_SHIFT 5 #define ENET_EIMR_TXB2_MASK 0x40u #define ENET_EIMR_TXB2_SHIFT 6 #define ENET_EIMR_TXF2_MASK 0x80u #define ENET_EIMR_TXF2_SHIFT 7 #define ENET_EIMR_RXFLUSH_0_MASK 0x1000u #define ENET_EIMR_RXFLUSH_0_SHIFT 12 #define ENET_EIMR_RXFLUSH_1_MASK 0x2000u #define ENET_EIMR_RXFLUSH_1_SHIFT 13 #define ENET_EIMR_RXFLUSH_2_MASK 0x4000u #define ENET_EIMR_RXFLUSH_2_SHIFT 14 #define ENET_EIMR_TS_TIMER_MASK 0x8000u #define ENET_EIMR_TS_TIMER_SHIFT 15 #define ENET_EIMR_TS_AVAIL_MASK 0x10000u #define ENET_EIMR_TS_AVAIL_SHIFT 16 #define ENET_EIMR_WAKEUP_MASK 0x20000u #define ENET_EIMR_WAKEUP_SHIFT 17 #define ENET_EIMR_PLR_MASK 0x40000u #define ENET_EIMR_PLR_SHIFT 18 #define ENET_EIMR_UN_MASK 0x80000u #define ENET_EIMR_UN_SHIFT 19 #define ENET_EIMR_RL_MASK 0x100000u #define ENET_EIMR_RL_SHIFT 20 #define ENET_EIMR_LC_MASK 0x200000u #define ENET_EIMR_LC_SHIFT 21 #define ENET_EIMR_EBERR_MASK 0x400000u #define ENET_EIMR_EBERR_SHIFT 22 #define ENET_EIMR_MII_MASK 0x800000u #define ENET_EIMR_MII_SHIFT 23 #define ENET_EIMR_RXB_MASK 0x1000000u #define ENET_EIMR_RXB_SHIFT 24 #define ENET_EIMR_RXF_MASK 0x2000000u #define ENET_EIMR_RXF_SHIFT 25 #define ENET_EIMR_TXB_MASK 0x4000000u #define ENET_EIMR_TXB_SHIFT 26 #define ENET_EIMR_TXF_MASK 0x8000000u #define ENET_EIMR_TXF_SHIFT 27 #define ENET_EIMR_GRA_MASK 0x10000000u #define ENET_EIMR_GRA_SHIFT 28 #define ENET_EIMR_BABT_MASK 0x20000000u #define ENET_EIMR_BABT_SHIFT 29 #define ENET_EIMR_BABR_MASK 0x40000000u #define ENET_EIMR_BABR_SHIFT 30 /* RDAR Bit Fields */ #define ENET_RDAR_RDAR_MASK 0x1000000u #define ENET_RDAR_RDAR_SHIFT 24 /* TDAR Bit Fields */ #define ENET_TDAR_TDAR_MASK 0x1000000u #define ENET_TDAR_TDAR_SHIFT 24 /* ECR Bit Fields */ #define ENET_ECR_RESET_MASK 0x1u #define ENET_ECR_RESET_SHIFT 0 #define ENET_ECR_ETHEREN_MASK 0x2u #define ENET_ECR_ETHEREN_SHIFT 1 #define ENET_ECR_MAGICEN_MASK 0x4u #define ENET_ECR_MAGICEN_SHIFT 2 #define ENET_ECR_SLEEP_MASK 0x8u #define ENET_ECR_SLEEP_SHIFT 3 #define ENET_ECR_EN1588_MASK 0x10u #define ENET_ECR_EN1588_SHIFT 4 #define ENET_ECR_SPEED_MASK 0x20u #define ENET_ECR_SPEED_SHIFT 5 #define ENET_ECR_DBGEN_MASK 0x40u #define ENET_ECR_DBGEN_SHIFT 6 #define ENET_ECR_DBSWP_MASK 0x100u #define ENET_ECR_DBSWP_SHIFT 8 #define ENET_ECR_SVLANEN_MASK 0x200u #define ENET_ECR_SVLANEN_SHIFT 9 #define ENET_ECR_VLANUSE2ND_MASK 0x400u #define ENET_ECR_VLANUSE2ND_SHIFT 10 #define ENET_ECR_SVLANDBL_MASK 0x800u #define ENET_ECR_SVLANDBL_SHIFT 11 /* MMFR Bit Fields */ #define ENET_MMFR_DATA_MASK 0xFFFFu #define ENET_MMFR_DATA_SHIFT 0 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<CTRL) #define EPDC_CTRL_SET_REG(base) ((base)->CTRL_SET) #define EPDC_CTRL_CLR_REG(base) ((base)->CTRL_CLR) #define EPDC_CTRL_TOG_REG(base) ((base)->CTRL_TOG) #define EPDC_WVADDR_REG(base) ((base)->WVADDR) #define EPDC_WB_ADDR_REG(base) ((base)->WB_ADDR) #define EPDC_RES_REG(base) ((base)->RES) #define EPDC_FORMAT_REG(base) ((base)->FORMAT) #define EPDC_FORMAT_SET_REG(base) ((base)->FORMAT_SET) #define EPDC_FORMAT_CLR_REG(base) ((base)->FORMAT_CLR) #define EPDC_FORMAT_TOG_REG(base) ((base)->FORMAT_TOG) #define EPDC_FIFOCTRL_REG(base) ((base)->FIFOCTRL) #define EPDC_FIFOCTRL_SET_REG(base) ((base)->FIFOCTRL_SET) #define EPDC_FIFOCTRL_CLR_REG(base) ((base)->FIFOCTRL_CLR) #define EPDC_FIFOCTRL_TOG_REG(base) ((base)->FIFOCTRL_TOG) #define EPDC_UPD_ADDR_REG(base) ((base)->UPD_ADDR) #define EPDC_UPD_STRIDE_REG(base) ((base)->UPD_STRIDE) #define EPDC_UPD_CORD_REG(base) ((base)->UPD_CORD) #define EPDC_UPD_SIZE_REG(base) ((base)->UPD_SIZE) #define EPDC_UPD_CTRL_REG(base) ((base)->UPD_CTRL) #define EPDC_UPD_CTRL_SET_REG(base) ((base)->UPD_CTRL_SET) #define EPDC_UPD_CTRL_CLR_REG(base) ((base)->UPD_CTRL_CLR) #define EPDC_UPD_CTRL_TOG_REG(base) ((base)->UPD_CTRL_TOG) #define EPDC_UPD_FIXED_REG(base) ((base)->UPD_FIXED) #define EPDC_UPD_FIXED_SET_REG(base) ((base)->UPD_FIXED_SET) #define EPDC_UPD_FIXED_CLR_REG(base) ((base)->UPD_FIXED_CLR) #define EPDC_UPD_FIXED_TOG_REG(base) ((base)->UPD_FIXED_TOG) #define EPDC_TEMP_REG(base) ((base)->TEMP) #define EPDC_AUTOWV_LUT_REG(base) ((base)->AUTOWV_LUT) #define EPDC_TCE_CTRL_REG(base) ((base)->TCE_CTRL) #define EPDC_TCE_CTRL_SET_REG(base) ((base)->TCE_CTRL_SET) #define EPDC_TCE_CTRL_CLR_REG(base) ((base)->TCE_CTRL_CLR) #define EPDC_TCE_CTRL_TOG_REG(base) ((base)->TCE_CTRL_TOG) #define EPDC_TCE_SDCFG_REG(base) ((base)->TCE_SDCFG) #define EPDC_TCE_SDCFG_SET_REG(base) ((base)->TCE_SDCFG_SET) #define EPDC_TCE_SDCFG_CLR_REG(base) ((base)->TCE_SDCFG_CLR) #define EPDC_TCE_SDCFG_TOG_REG(base) ((base)->TCE_SDCFG_TOG) #define EPDC_TCE_GDCFG_REG(base) ((base)->TCE_GDCFG) #define EPDC_TCE_GDCFG_SET_REG(base) ((base)->TCE_GDCFG_SET) #define EPDC_TCE_GDCFG_CLR_REG(base) ((base)->TCE_GDCFG_CLR) #define EPDC_TCE_GDCFG_TOG_REG(base) ((base)->TCE_GDCFG_TOG) #define EPDC_TCE_HSCAN1_REG(base) ((base)->TCE_HSCAN1) #define EPDC_TCE_HSCAN1_SET_REG(base) ((base)->TCE_HSCAN1_SET) #define EPDC_TCE_HSCAN1_CLR_REG(base) ((base)->TCE_HSCAN1_CLR) #define EPDC_TCE_HSCAN1_TOG_REG(base) ((base)->TCE_HSCAN1_TOG) #define EPDC_TCE_HSCAN2_REG(base) ((base)->TCE_HSCAN2) #define EPDC_TCE_HSCAN2_SET_REG(base) ((base)->TCE_HSCAN2_SET) #define EPDC_TCE_HSCAN2_CLR_REG(base) ((base)->TCE_HSCAN2_CLR) #define EPDC_TCE_HSCAN2_TOG_REG(base) ((base)->TCE_HSCAN2_TOG) #define EPDC_TCE_VSCAN_REG(base) ((base)->TCE_VSCAN) #define EPDC_TCE_VSCAN_SET_REG(base) ((base)->TCE_VSCAN_SET) #define EPDC_TCE_VSCAN_CLR_REG(base) ((base)->TCE_VSCAN_CLR) #define EPDC_TCE_VSCAN_TOG_REG(base) ((base)->TCE_VSCAN_TOG) #define EPDC_TCE_OE_REG(base) ((base)->TCE_OE) #define EPDC_TCE_OE_SET_REG(base) ((base)->TCE_OE_SET) #define EPDC_TCE_OE_CLR_REG(base) ((base)->TCE_OE_CLR) #define EPDC_TCE_OE_TOG_REG(base) ((base)->TCE_OE_TOG) #define EPDC_TCE_POLARITY_REG(base) ((base)->TCE_POLARITY) #define EPDC_TCE_POLARITY_SET_REG(base) ((base)->TCE_POLARITY_SET) #define EPDC_TCE_POLARITY_CLR_REG(base) ((base)->TCE_POLARITY_CLR) #define EPDC_TCE_POLARITY_TOG_REG(base) ((base)->TCE_POLARITY_TOG) #define EPDC_TCE_TIMING1_REG(base) ((base)->TCE_TIMING1) #define EPDC_TCE_TIMING1_SET_REG(base) ((base)->TCE_TIMING1_SET) #define EPDC_TCE_TIMING1_CLR_REG(base) ((base)->TCE_TIMING1_CLR) #define EPDC_TCE_TIMING1_TOG_REG(base) ((base)->TCE_TIMING1_TOG) #define EPDC_TCE_TIMING2_REG(base) ((base)->TCE_TIMING2) #define EPDC_TCE_TIMING2_SET_REG(base) ((base)->TCE_TIMING2_SET) #define EPDC_TCE_TIMING2_CLR_REG(base) ((base)->TCE_TIMING2_CLR) #define EPDC_TCE_TIMING2_TOG_REG(base) ((base)->TCE_TIMING2_TOG) #define EPDC_TCE_TIMING3_REG(base) ((base)->TCE_TIMING3) #define EPDC_TCE_TIMING3_SET_REG(base) ((base)->TCE_TIMING3_SET) #define EPDC_TCE_TIMING3_CLR_REG(base) ((base)->TCE_TIMING3_CLR) #define EPDC_TCE_TIMING3_TOG_REG(base) ((base)->TCE_TIMING3_TOG) #define EPDC_PIGEON_CTRL0_REG(base) ((base)->PIGEON_CTRL0) #define EPDC_PIGEON_CTRL0_SET_REG(base) ((base)->PIGEON_CTRL0_SET) #define EPDC_PIGEON_CTRL0_CLR_REG(base) ((base)->PIGEON_CTRL0_CLR) #define EPDC_PIGEON_CTRL0_TOG_REG(base) ((base)->PIGEON_CTRL0_TOG) #define EPDC_PIGEON_CTRL1_REG(base) ((base)->PIGEON_CTRL1) #define EPDC_PIGEON_CTRL1_SET_REG(base) ((base)->PIGEON_CTRL1_SET) #define EPDC_PIGEON_CTRL1_CLR_REG(base) ((base)->PIGEON_CTRL1_CLR) #define EPDC_PIGEON_CTRL1_TOG_REG(base) ((base)->PIGEON_CTRL1_TOG) #define EPDC_IRQ_MASK1_REG(base) ((base)->IRQ_MASK1) #define EPDC_IRQ_MASK1_SET_REG(base) ((base)->IRQ_MASK1_SET) #define EPDC_IRQ_MASK1_CLR_REG(base) ((base)->IRQ_MASK1_CLR) #define EPDC_IRQ_MASK1_TOG_REG(base) ((base)->IRQ_MASK1_TOG) #define EPDC_IRQ_MASK2_REG(base) ((base)->IRQ_MASK2) #define EPDC_IRQ_MASK2_SET_REG(base) ((base)->IRQ_MASK2_SET) #define EPDC_IRQ_MASK2_CLR_REG(base) ((base)->IRQ_MASK2_CLR) #define EPDC_IRQ_MASK2_TOG_REG(base) ((base)->IRQ_MASK2_TOG) #define EPDC_IRQ1_REG(base) ((base)->IRQ1) #define EPDC_IRQ1_SET_REG(base) ((base)->IRQ1_SET) #define EPDC_IRQ1_CLR_REG(base) ((base)->IRQ1_CLR) #define EPDC_IRQ1_TOG_REG(base) ((base)->IRQ1_TOG) #define EPDC_IRQ2_REG(base) ((base)->IRQ2) #define EPDC_IRQ2_SET_REG(base) ((base)->IRQ2_SET) #define EPDC_IRQ2_CLR_REG(base) ((base)->IRQ2_CLR) #define EPDC_IRQ2_TOG_REG(base) ((base)->IRQ2_TOG) #define EPDC_IRQ_MASK_REG(base) ((base)->IRQ_MASK) #define EPDC_IRQ_MASK_SET_REG(base) ((base)->IRQ_MASK_SET) #define EPDC_IRQ_MASK_CLR_REG(base) ((base)->IRQ_MASK_CLR) #define EPDC_IRQ_MASK_TOG_REG(base) ((base)->IRQ_MASK_TOG) #define EPDC_IRQ_REG(base) ((base)->IRQ) #define EPDC_IRQ_SET_REG(base) ((base)->IRQ_SET) #define EPDC_IRQ_CLR_REG(base) ((base)->IRQ_CLR) #define EPDC_IRQ_TOG_REG(base) ((base)->IRQ_TOG) #define EPDC_STATUS_LUTS1_REG(base) ((base)->STATUS_LUTS1) #define EPDC_STATUS_LUTS1_SET_REG(base) ((base)->STATUS_LUTS1_SET) #define EPDC_STATUS_LUTS1_CLR_REG(base) ((base)->STATUS_LUTS1_CLR) #define EPDC_STATUS_LUTS1_TOG_REG(base) ((base)->STATUS_LUTS1_TOG) #define EPDC_STATUS_LUTS2_REG(base) ((base)->STATUS_LUTS2) #define EPDC_STATUS_LUTS2_SET_REG(base) ((base)->STATUS_LUTS2_SET) #define EPDC_STATUS_LUTS2_CLR_REG(base) ((base)->STATUS_LUTS2_CLR) #define EPDC_STATUS_LUTS2_TOG_REG(base) ((base)->STATUS_LUTS2_TOG) #define EPDC_STATUS_NEXTLUT_REG(base) ((base)->STATUS_NEXTLUT) #define EPDC_STATUS_COL1_REG(base) ((base)->STATUS_COL1) #define EPDC_STATUS_COL1_SET_REG(base) ((base)->STATUS_COL1_SET) #define EPDC_STATUS_COL1_CLR_REG(base) ((base)->STATUS_COL1_CLR) #define EPDC_STATUS_COL1_TOG_REG(base) ((base)->STATUS_COL1_TOG) #define EPDC_STATUS_COL2_REG(base) ((base)->STATUS_COL2) #define EPDC_STATUS_COL2_SET_REG(base) ((base)->STATUS_COL2_SET) #define EPDC_STATUS_COL2_CLR_REG(base) ((base)->STATUS_COL2_CLR) #define EPDC_STATUS_COL2_TOG_REG(base) ((base)->STATUS_COL2_TOG) #define EPDC_STATUS_REG(base) ((base)->STATUS) #define EPDC_STATUS_SET_REG(base) ((base)->STATUS_SET) #define EPDC_STATUS_CLR_REG(base) ((base)->STATUS_CLR) #define EPDC_STATUS_TOG_REG(base) ((base)->STATUS_TOG) #define EPDC_UPD_COL_CORD_REG(base) ((base)->UPD_COL_CORD) #define EPDC_UPD_COL_SIZE_REG(base) ((base)->UPD_COL_SIZE) #define EPDC_HIST1_PARAM_REG(base) ((base)->HIST1_PARAM) #define EPDC_HIST2_PARAM_REG(base) ((base)->HIST2_PARAM) #define EPDC_HIST4_PARAM_REG(base) ((base)->HIST4_PARAM) #define EPDC_HIST8_PARAM0_REG(base) ((base)->HIST8_PARAM0) #define EPDC_HIST8_PARAM1_REG(base) ((base)->HIST8_PARAM1) #define EPDC_HIST16_PARAM0_REG(base) ((base)->HIST16_PARAM0) #define EPDC_HIST16_PARAM1_REG(base) ((base)->HIST16_PARAM1) #define EPDC_HIST16_PARAM2_REG(base) ((base)->HIST16_PARAM2) #define EPDC_HIST16_PARAM3_REG(base) ((base)->HIST16_PARAM3) #define EPDC_GPIO_REG(base) ((base)->GPIO) #define EPDC_GPIO_SET_REG(base) ((base)->GPIO_SET) #define EPDC_GPIO_CLR_REG(base) ((base)->GPIO_CLR) #define EPDC_GPIO_TOG_REG(base) ((base)->GPIO_TOG) #define EPDC_VERSION_REG(base) ((base)->VERSION) #define EPDC_PIGEON_0_0_REG(base) ((base)->PIGEON_0_0) #define EPDC_PIGEON_0_1_REG(base) ((base)->PIGEON_0_1) #define EPDC_PIGEON_0_2_REG(base) ((base)->PIGEON_0_2) #define EPDC_PIGEON_1_0_REG(base) ((base)->PIGEON_1_0) #define EPDC_PIGEON_1_1_REG(base) ((base)->PIGEON_1_1) #define EPDC_PIGEON_1_2_REG(base) ((base)->PIGEON_1_2) #define EPDC_PIGEON_2_0_REG(base) ((base)->PIGEON_2_0) #define EPDC_PIGEON_2_1_REG(base) ((base)->PIGEON_2_1) #define EPDC_PIGEON_2_2_REG(base) ((base)->PIGEON_2_2) #define EPDC_PIGEON_3_0_REG(base) ((base)->PIGEON_3_0) #define EPDC_PIGEON_3_1_REG(base) ((base)->PIGEON_3_1) #define EPDC_PIGEON_3_2_REG(base) ((base)->PIGEON_3_2) #define EPDC_PIGEON_4_0_REG(base) ((base)->PIGEON_4_0) #define EPDC_PIGEON_4_1_REG(base) ((base)->PIGEON_4_1) #define EPDC_PIGEON_4_2_REG(base) ((base)->PIGEON_4_2) #define EPDC_PIGEON_5_0_REG(base) ((base)->PIGEON_5_0) #define EPDC_PIGEON_5_1_REG(base) ((base)->PIGEON_5_1) #define EPDC_PIGEON_5_2_REG(base) ((base)->PIGEON_5_2) #define EPDC_PIGEON_6_0_REG(base) ((base)->PIGEON_6_0) #define EPDC_PIGEON_6_1_REG(base) ((base)->PIGEON_6_1) #define EPDC_PIGEON_6_2_REG(base) ((base)->PIGEON_6_2) #define EPDC_PIGEON_7_0_REG(base) ((base)->PIGEON_7_0) #define EPDC_PIGEON_7_1_REG(base) ((base)->PIGEON_7_1) #define EPDC_PIGEON_7_2_REG(base) ((base)->PIGEON_7_2) #define EPDC_PIGEON_8_0_REG(base) ((base)->PIGEON_8_0) #define EPDC_PIGEON_8_1_REG(base) ((base)->PIGEON_8_1) #define EPDC_PIGEON_8_2_REG(base) ((base)->PIGEON_8_2) #define EPDC_PIGEON_9_0_REG(base) ((base)->PIGEON_9_0) #define EPDC_PIGEON_9_1_REG(base) ((base)->PIGEON_9_1) #define EPDC_PIGEON_9_2_REG(base) ((base)->PIGEON_9_2) #define EPDC_PIGEON_10_0_REG(base) ((base)->PIGEON_10_0) #define EPDC_PIGEON_10_1_REG(base) ((base)->PIGEON_10_1) #define EPDC_PIGEON_10_2_REG(base) ((base)->PIGEON_10_2) #define EPDC_PIGEON_11_0_REG(base) ((base)->PIGEON_11_0) #define EPDC_PIGEON_11_1_REG(base) ((base)->PIGEON_11_1) #define EPDC_PIGEON_11_2_REG(base) ((base)->PIGEON_11_2) #define EPDC_PIGEON_12_0_REG(base) ((base)->PIGEON_12_0) #define EPDC_PIGEON_12_1_REG(base) ((base)->PIGEON_12_1) #define EPDC_PIGEON_12_2_REG(base) ((base)->PIGEON_12_2) #define EPDC_PIGEON_13_0_REG(base) ((base)->PIGEON_13_0) #define EPDC_PIGEON_13_1_REG(base) ((base)->PIGEON_13_1) #define EPDC_PIGEON_13_2_REG(base) ((base)->PIGEON_13_2) #define EPDC_PIGEON_14_0_REG(base) ((base)->PIGEON_14_0) #define EPDC_PIGEON_14_1_REG(base) ((base)->PIGEON_14_1) #define EPDC_PIGEON_14_2_REG(base) ((base)->PIGEON_14_2) #define EPDC_PIGEON_15_0_REG(base) ((base)->PIGEON_15_0) #define EPDC_PIGEON_15_1_REG(base) ((base)->PIGEON_15_1) #define EPDC_PIGEON_15_2_REG(base) ((base)->PIGEON_15_2) #define EPDC_PIGEON_16_0_REG(base) ((base)->PIGEON_16_0) #define EPDC_PIGEON_16_1_REG(base) ((base)->PIGEON_16_1) #define EPDC_WB_ADDR_TCE_REG(base) ((base)->WB_ADDR_TCE) #define EPDC_PIGEON_16_2_REG(base) ((base)->PIGEON_16_2) /*! * @} */ /* end of group EPDC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- EPDC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup EPDC_Register_Masks EPDC Register Masks * @{ */ /* CTRL Bit Fields */ #define EPDC_CTRL_BURST_LEN_8_MASK 0x1u #define EPDC_CTRL_BURST_LEN_8_SHIFT 0 #define EPDC_CTRL_LUT_DATA_SWIZZLE_MASK 0x30u #define EPDC_CTRL_LUT_DATA_SWIZZLE_SHIFT 4 #define EPDC_CTRL_LUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<SC) #define FTM_CNT_REG(base) ((base)->CNT) #define FTM_MOD_REG(base) ((base)->MOD) #define FTM_CSC_REG(base,index) ((base)->C[index].CSC) #define FTM_CV_REG(base,index) ((base)->C[index].CV) #define FTM_CNTIN_REG(base) ((base)->CNTIN) #define FTM_STATUS_REG(base) ((base)->STATUS) #define FTM_MODE_REG(base) ((base)->MODE) #define FTM_SYNC_REG(base) ((base)->SYNC) #define FTM_OUTINIT_REG(base) ((base)->OUTINIT) #define FTM_OUTMASK_REG(base) ((base)->OUTMASK) #define FTM_COMBINE_REG(base) ((base)->COMBINE) #define FTM_DEADTIME_REG(base) ((base)->DEADTIME) #define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) #define FTM_POL_REG(base) ((base)->POL) #define FTM_FMS_REG(base) ((base)->FMS) #define FTM_FILTER_REG(base) ((base)->FILTER) #define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) #define FTM_QDCTRL_REG(base) ((base)->QDCTRL) #define FTM_CONF_REG(base) ((base)->CONF) #define FTM_FLTPOL_REG(base) ((base)->FLTPOL) #define FTM_SYNCONF_REG(base) ((base)->SYNCONF) #define FTM_INVCTRL_REG(base) ((base)->INVCTRL) #define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) #define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) /*! * @} */ /* end of group FTM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- FTM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FTM_Register_Masks FTM Register Masks * @{ */ /* SC Bit Fields */ #define FTM_SC_PS_MASK 0x7u #define FTM_SC_PS_SHIFT 0 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<CNTR) #define GPC_PGR_REG(base) ((base)->PGR) #define GPC_IMR1_REG(base) ((base)->IMR1) #define GPC_IMR2_REG(base) ((base)->IMR2) #define GPC_IMR3_REG(base) ((base)->IMR3) #define GPC_IMR4_REG(base) ((base)->IMR4) #define GPC_ISR1_REG(base) ((base)->ISR1) #define GPC_ISR2_REG(base) ((base)->ISR2) #define GPC_ISR3_REG(base) ((base)->ISR3) #define GPC_ISR4_REG(base) ((base)->ISR4) #define GPC_A9_LPSR_REG(base) ((base)->A9_LPSR) #define GPC_M4_LPSR_REG(base) ((base)->M4_LPSR) #define GPC_DR_REG(base) ((base)->DR) /*! * @} */ /* end of group GPC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- GPC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPC_Register_Masks GPC Register Masks * @{ */ /* CNTR Bit Fields */ #define GPC_CNTR_gpu_vpu_pdn_req_MASK 0x1u #define GPC_CNTR_gpu_vpu_pdn_req_SHIFT 0 #define GPC_CNTR_gpu_vpu_pup_req_MASK 0x2u #define GPC_CNTR_gpu_vpu_pup_req_SHIFT 1 #define GPC_CNTR_MEGA_PDN_REQ_MASK 0x4u #define GPC_CNTR_MEGA_PDN_REQ_SHIFT 2 #define GPC_CNTR_MEGA_PUP_REQ_MASK 0x8u #define GPC_CNTR_MEGA_PUP_REQ_SHIFT 3 #define GPC_CNTR_DISPLAY_PDN_REQ_MASK 0x10u #define GPC_CNTR_DISPLAY_PDN_REQ_SHIFT 4 #define GPC_CNTR_DISPLAY_PUP_REQ_MASK 0x20u #define GPC_CNTR_DISPLAY_PUP_REQ_SHIFT 5 #define GPC_CNTR_PCIE_PHY_PDN_REQ_MASK 0x40u #define GPC_CNTR_PCIE_PHY_PDN_REQ_SHIFT 6 #define GPC_CNTR_PCIE_PHY_PUP_REQ_MASK 0x80u #define GPC_CNTR_PCIE_PHY_PUP_REQ_SHIFT 7 #define GPC_CNTR_DVFS0CR_MASK 0x10000u #define GPC_CNTR_DVFS0CR_SHIFT 16 #define GPC_CNTR_VADC_ANALOG_OFF_MASK 0x20000u #define GPC_CNTR_VADC_ANALOG_OFF_SHIFT 17 #define GPC_CNTR_VADC_EXT_PWD_N_MASK 0x40000u #define GPC_CNTR_VADC_EXT_PWD_N_SHIFT 18 #define GPC_CNTR_GPCIRQM_MASK 0x200000u #define GPC_CNTR_GPCIRQM_SHIFT 21 #define GPC_CNTR_L2_PGE_MASK 0x400000u #define GPC_CNTR_L2_PGE_SHIFT 22 /* PGR Bit Fields */ #define GPC_PGR_DRCIC_MASK 0x60000000u #define GPC_PGR_DRCIC_SHIFT 29 #define GPC_PGR_DRCIC(x) (((uint32_t)(((uint32_t)(x))<DR) #define GPIO_GDIR_REG(base) ((base)->GDIR) #define GPIO_PSR_REG(base) ((base)->PSR) #define GPIO_ICR1_REG(base) ((base)->ICR1) #define GPIO_ICR2_REG(base) ((base)->ICR2) #define GPIO_IMR_REG(base) ((base)->IMR) #define GPIO_ISR_REG(base) ((base)->ISR) #define GPIO_EDGE_SEL_REG(base) ((base)->EDGE_SEL) /*! * @} */ /* end of group GPIO_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- GPIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Register_Masks GPIO Register Masks * @{ */ /* DR Bit Fields */ #define GPIO_DR_DR_MASK 0xFFFFFFFFu #define GPIO_DR_DR_SHIFT 0 #define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x))<CTRL0) #define GPMI_CTRL0_SET_REG(base) ((base)->CTRL0_SET) #define GPMI_CTRL0_CLR_REG(base) ((base)->CTRL0_CLR) #define GPMI_CTRL0_TOG_REG(base) ((base)->CTRL0_TOG) #define GPMI_COMPARE_REG(base) ((base)->COMPARE) #define GPMI_ECCCTRL_REG(base) ((base)->ECCCTRL) #define GPMI_ECCCTRL_SET_REG(base) ((base)->ECCCTRL_SET) #define GPMI_ECCCTRL_CLR_REG(base) ((base)->ECCCTRL_CLR) #define GPMI_ECCCTRL_TOG_REG(base) ((base)->ECCCTRL_TOG) #define GPMI_ECCCOUNT_REG(base) ((base)->ECCCOUNT) #define GPMI_PAYLOAD_REG(base) ((base)->PAYLOAD) #define GPMI_AUXILIARY_REG(base) ((base)->AUXILIARY) #define GPMI_CTRL1_REG(base) ((base)->CTRL1) #define GPMI_CTRL1_SET_REG(base) ((base)->CTRL1_SET) #define GPMI_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) #define GPMI_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) #define GPMI_TIMING0_REG(base) ((base)->TIMING0) #define GPMI_TIMING1_REG(base) ((base)->TIMING1) #define GPMI_TIMING2_REG(base) ((base)->TIMING2) #define GPMI_DATA_REG(base) ((base)->DATA) #define GPMI_STAT_REG(base) ((base)->STAT) #define GPMI_DEBUG_REG(base) ((base)->DEBUG) #define GPMI_VERSION_REG(base) ((base)->VERSION) #define GPMI_DEBUG2_REG(base) ((base)->DEBUG2) #define GPMI_DEBUG3_REG(base) ((base)->DEBUG3) #define GPMI_READ_DDR_DLL_CTRL_REG(base) ((base)->READ_DDR_DLL_CTRL) #define GPMI_READ_DDR_DLL_STS_REG(base) ((base)->READ_DDR_DLL_STS) /*! * @} */ /* end of group GPMI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- GPMI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPMI_Register_Masks GPMI Register Masks * @{ */ /* CTRL0 Bit Fields */ #define GPMI_CTRL0_XFER_COUNT_MASK 0xFFFFu #define GPMI_CTRL0_XFER_COUNT_SHIFT 0 #define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x))<CR) #define GPT_PR_REG(base) ((base)->PR) #define GPT_SR_REG(base) ((base)->SR) #define GPT_IR_REG(base) ((base)->IR) #define GPT_OCR1_REG(base) ((base)->OCR1) #define GPT_OCR2_REG(base) ((base)->OCR2) #define GPT_OCR3_REG(base) ((base)->OCR3) #define GPT_ICR1_REG(base) ((base)->ICR1) #define GPT_ICR2_REG(base) ((base)->ICR2) #define GPT_CNT_REG(base) ((base)->CNT) /*! * @} */ /* end of group GPT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- GPT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPT_Register_Masks GPT Register Masks * @{ */ /* CR Bit Fields */ #define GPT_CR_EN_MASK 0x1u #define GPT_CR_EN_SHIFT 0 #define GPT_CR_ENMOD_MASK 0x2u #define GPT_CR_ENMOD_SHIFT 1 #define GPT_CR_DBGEN_MASK 0x4u #define GPT_CR_DBGEN_SHIFT 2 #define GPT_CR_WAITEN_MASK 0x8u #define GPT_CR_WAITEN_SHIFT 3 #define GPT_CR_DOZEEN_MASK 0x10u #define GPT_CR_DOZEEN_SHIFT 4 #define GPT_CR_STOPEN_MASK 0x20u #define GPT_CR_STOPEN_SHIFT 5 #define GPT_CR_CLKSRC_MASK 0x1C0u #define GPT_CR_CLKSRC_SHIFT 6 #define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<IADR) #define I2C_IFDR_REG(base) ((base)->IFDR) #define I2C_I2CR_REG(base) ((base)->I2CR) #define I2C_I2SR_REG(base) ((base)->I2SR) #define I2C_I2DR_REG(base) ((base)->I2DR) /*! * @} */ /* end of group I2C_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- I2C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2C_Register_Masks I2C Register Masks * @{ */ /* IADR Bit Fields */ #define I2C_IADR_ADR_MASK 0xFEu #define I2C_IADR_ADR_SHIFT 1 #define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x))<TCSR) #define I2S_TCR1_REG(base) ((base)->TCR1) #define I2S_TCR2_REG(base) ((base)->TCR2) #define I2S_TCR3_REG(base) ((base)->TCR3) #define I2S_TCR4_REG(base) ((base)->TCR4) #define I2S_TCR5_REG(base) ((base)->TCR5) #define I2S_TDR_REG(base,index) ((base)->TDR[index]) #define I2S_TFR_REG(base,index) ((base)->TFR[index]) #define I2S_TMR_REG(base) ((base)->TMR) #define I2S_RCSR_REG(base) ((base)->RCSR) #define I2S_RCR1_REG(base) ((base)->RCR1) #define I2S_RCR2_REG(base) ((base)->RCR2) #define I2S_RCR3_REG(base) ((base)->RCR3) #define I2S_RCR4_REG(base) ((base)->RCR4) #define I2S_RCR5_REG(base) ((base)->RCR5) #define I2S_RDR_REG(base,index) ((base)->RDR[index]) #define I2S_RFR_REG(base,index) ((base)->RFR[index]) #define I2S_RMR_REG(base) ((base)->RMR) /*! * @} */ /* end of group I2S_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- I2S Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Register_Masks I2S Register Masks * @{ */ /* TCSR Bit Fields */ #define I2S_TCSR_FRDE_MASK 0x1u #define I2S_TCSR_FRDE_SHIFT 0 #define I2S_TCSR_FWDE_MASK 0x2u #define I2S_TCSR_FWDE_SHIFT 1 #define I2S_TCSR_FRIE_MASK 0x100u #define I2S_TCSR_FRIE_SHIFT 8 #define I2S_TCSR_FWIE_MASK 0x200u #define I2S_TCSR_FWIE_SHIFT 9 #define I2S_TCSR_FEIE_MASK 0x400u #define I2S_TCSR_FEIE_SHIFT 10 #define I2S_TCSR_SEIE_MASK 0x800u #define I2S_TCSR_SEIE_SHIFT 11 #define I2S_TCSR_WSIE_MASK 0x1000u #define I2S_TCSR_WSIE_SHIFT 12 #define I2S_TCSR_FRF_MASK 0x10000u #define I2S_TCSR_FRF_SHIFT 16 #define I2S_TCSR_FWF_MASK 0x20000u #define I2S_TCSR_FWF_SHIFT 17 #define I2S_TCSR_FEF_MASK 0x40000u #define I2S_TCSR_FEF_SHIFT 18 #define I2S_TCSR_SEF_MASK 0x80000u #define I2S_TCSR_SEF_SHIFT 19 #define I2S_TCSR_WSF_MASK 0x100000u #define I2S_TCSR_WSF_SHIFT 20 #define I2S_TCSR_SR_MASK 0x1000000u #define I2S_TCSR_SR_SHIFT 24 #define I2S_TCSR_FR_MASK 0x2000000u #define I2S_TCSR_FR_SHIFT 25 #define I2S_TCSR_BCE_MASK 0x10000000u #define I2S_TCSR_BCE_SHIFT 28 #define I2S_TCSR_DBGE_MASK 0x20000000u #define I2S_TCSR_DBGE_SHIFT 29 #define I2S_TCSR_STOPE_MASK 0x40000000u #define I2S_TCSR_STOPE_SHIFT 30 #define I2S_TCSR_TE_MASK 0x80000000u #define I2S_TCSR_TE_SHIFT 31 /* TCR1 Bit Fields */ #define I2S_TCR1_TFW_MASK 0x1Fu #define I2S_TCR1_TFW_SHIFT 0 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<SW_MUX_CTL_PAD_GPIO1_IO08) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO09) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO10) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO11) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO12) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO13) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO14) #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO15) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA00) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA01) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA02) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA03) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA04) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA05) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA06) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA07) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA08) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA09) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA10) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA11) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA12) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA13) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA14) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA15) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCLK) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDLE) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDOE) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDSHR) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE0) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE1) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE2) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE3) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDCLK) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDOE) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDRL) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDSP) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_BDR0) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_BDR1) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_PWR_COM) #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_PWR_STAT) #define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_CLK) #define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_ENABLE) #define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_HSYNC) #define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_VSYNC) #define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_RESET) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA00) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA01) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA02) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA03) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA04) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA05) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA06) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA07) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA08) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA09) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA10) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA11) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA12) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA13) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA14) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA15) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA16) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA17) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA18) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA19) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA20) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA21) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA22) #define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA23) #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART1_RX_DATA) #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART1_TX_DATA) #define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART2_RX_DATA) #define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART2_TX_DATA) #define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_RX_DATA) #define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_TX_DATA) #define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_RTS_B) #define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_CTS_B) #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C1_SCL) #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C1_SDA) #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C2_SCL) #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C2_SDA) #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C3_SCL) #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C3_SDA) #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C4_SCL) #define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C4_SDA) #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_SCLK) #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_MOSI) #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_MISO) #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_SS0) #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_SCLK) #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_MOSI) #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_MISO) #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_SS0) #define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CD_B) #define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_WP) #define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_RESET_B) #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CLK) #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CMD) #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA0) #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA1) #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA2) #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA3) #define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CD_B) #define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_WP) #define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_RESET_B) #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CLK) #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CMD) #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA0) #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA1) #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA2) #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA3) #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_CLK) #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_CMD) #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA0) #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA1) #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA2) #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA3) #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA4) #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA5) #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA6) #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA7) #define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_STROBE) #define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_RESET_B) #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_RX_DATA) #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_TX_BCLK) #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_TX_SYNC) #define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_TX_DATA) #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_RX_SYNC) #define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_RX_BCLK) #define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_MCLK) #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_TX_SYNC) #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_TX_BCLK) #define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_RX_DATA) #define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_TX_DATA) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD0) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD1) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD2) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD3) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RXC) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD0) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD1) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD2) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD3) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TXC) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_TX_CLK) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RX_CLK) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_CRS) #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_COL) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO08) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO09) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO10) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO11) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO12) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO13) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO14) #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO15) #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_MOD) #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TCK) #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDI) #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDO) #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TMS) #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TRST_B) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA00) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA01) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA02) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA03) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA04) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA05) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA06) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA07) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA08) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA09) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA10) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA11) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA12) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA13) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA14) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA15) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCLK) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDLE) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDOE) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDSHR) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE0) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE1) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE2) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE3) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDCLK) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDOE) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDRL) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDSP) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_BDR0) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_BDR1) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_PWR_COM) #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_PWR_STAT) #define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_CLK) #define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_ENABLE) #define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_HSYNC) #define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_VSYNC) #define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_RESET) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA00) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA01) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA02) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA03) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA04) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA05) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA06) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA07) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA08) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA09) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA10) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA11) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA12) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA13) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA14) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA15) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA16) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA17) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA18) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA19) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA20) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA21) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA22) #define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA23) #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART1_RX_DATA) #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART1_TX_DATA) #define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART2_RX_DATA) #define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART2_TX_DATA) #define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_RX_DATA) #define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_TX_DATA) #define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_RTS) #define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_CTS) #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C1_SCL) #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C1_SDA) #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C2_SCL) #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C2_SDA) #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C3_SCL) #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C3_SDA) #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C4_SCL) #define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C4_SDA) #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_SCLK) #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_MOSI) #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_MISO) #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_SS0) #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_SCLK) #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_MOSI) #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_MISO) #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_SS0) #define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CD_B) #define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_WP) #define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_RESET_B) #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CLK) #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CMD) #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA0) #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA1) #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA2) #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA3) #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CD_B) #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_WP) #define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_RESET_B) #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CLK) #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CMD) #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA0) #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA1) #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA2) #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA3) #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_CLK) #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_CMD) #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA0) #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA1) #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA2) #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA3) #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA4) #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA5) #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA6) #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA7) #define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_STROBE) #define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_RESET_B) #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_RX_DATA) #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_TX_BCLK) #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_TX_SYNC) #define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_TX_DATA) #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_RX_SYNC) #define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_RX_BCLK) #define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_MCLK) #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_TX_SYNC) #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_TX_BCLK) #define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_RX_DATA) #define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_TX_DATA) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD0) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD1) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD2) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD3) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RXC) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD0) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD1) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD2) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD3) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TXC) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_TX_CLK) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RX_CLK) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_CRS) #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_COL) #define IOMUXC_FLEXCAN1_RX_SELECT_INPUT_REG(base) ((base)->FLEXCAN1_RX_SELECT_INPUT) #define IOMUXC_FLEXCAN2_RX_SELECT_INPUT_REG(base) ((base)->FLEXCAN2_RX_SELECT_INPUT) #define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_1_SELECT_INPUT) #define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_2_SELECT_INPUT) #define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_3_SELECT_INPUT) #define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_4_SELECT_INPUT) #define IOMUXC_CCM_PMIC_READY_SELECT_INPUT_REG(base) ((base)->CCM_PMIC_READY_SELECT_INPUT) #define IOMUXC_CSI_DATA2_SELECT_INPUT_REG(base) ((base)->CSI_DATA2_SELECT_INPUT) #define IOMUXC_CSI_DATA3_SELECT_INPUT_REG(base) ((base)->CSI_DATA3_SELECT_INPUT) #define IOMUXC_CSI_DATA4_SELECT_INPUT_REG(base) ((base)->CSI_DATA4_SELECT_INPUT) #define IOMUXC_CSI_DATA5_SELECT_INPUT_REG(base) ((base)->CSI_DATA5_SELECT_INPUT) #define IOMUXC_CSI_DATA6_SELECT_INPUT_REG(base) ((base)->CSI_DATA6_SELECT_INPUT) #define IOMUXC_CSI_DATA7_SELECT_INPUT_REG(base) ((base)->CSI_DATA7_SELECT_INPUT) #define IOMUXC_CSI_DATA8_SELECT_INPUT_REG(base) ((base)->CSI_DATA8_SELECT_INPUT) #define IOMUXC_CSI_DATA9_SELECT_INPUT_REG(base) ((base)->CSI_DATA9_SELECT_INPUT) #define IOMUXC_CSI_HSYNC_SELECT_INPUT_REG(base) ((base)->CSI_HSYNC_SELECT_INPUT) #define IOMUXC_CSI_PIXCLK_SELECT_INPUT_REG(base) ((base)->CSI_PIXCLK_SELECT_INPUT) #define IOMUXC_CSI_VSYNC_SELECT_INPUT_REG(base) ((base)->CSI_VSYNC_SELECT_INPUT) #define IOMUXC_ECSPI1_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI1_SCLK_SELECT_INPUT) #define IOMUXC_ECSPI1_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI1_MISO_SELECT_INPUT) #define IOMUXC_ECSPI1_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI1_MOSI_SELECT_INPUT) #define IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI1_SS0_B_SELECT_INPUT) #define IOMUXC_ECSPI2_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI2_SCLK_SELECT_INPUT) #define IOMUXC_ECSPI2_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI2_MISO_SELECT_INPUT) #define IOMUXC_ECSPI2_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI2_MOSI_SELECT_INPUT) #define IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI2_SS0_B_SELECT_INPUT) #define IOMUXC_ECSPI3_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI3_SCLK_SELECT_INPUT) #define IOMUXC_ECSPI3_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI3_MISO_SELECT_INPUT) #define IOMUXC_ECSPI3_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI3_MOSI_SELECT_INPUT) #define IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI3_SS0_B_SELECT_INPUT) #define IOMUXC_ECSPI4_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI4_SCLK_SELECT_INPUT) #define IOMUXC_ECSPI4_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI4_MISO_SELECT_INPUT) #define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI4_MOSI_SELECT_INPUT) #define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI4_SS0_B_SELECT_INPUT) #define IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT_REG(base) ((base)->CCM_ENET_REF_CLK1_SELECT_INPUT) #define IOMUXC_ENET1_MDIO_SELECT_INPUT_REG(base) ((base)->ENET1_MDIO_SELECT_INPUT) #define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_REG(base) ((base)->ENET1_RX_CLK_SELECT_INPUT) #define IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT_REG(base) ((base)->CCM_ENET_REF_CLK2_SELECT_INPUT) #define IOMUXC_ENET2_MDIO_SELECT_INPUT_REG(base) ((base)->ENET2_MDIO_SELECT_INPUT) #define IOMUXC_ENET2_RX_CLK_SELECT_INPUT_REG(base) ((base)->ENET2_RX_CLK_SELECT_INPUT) #define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_REG(base) ((base)->EPDC_PWR_IRQ_SELECT_INPUT) #define IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_REG(base) ((base)->EPDC_PWR_STAT_SELECT_INPUT) #define IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH0_SELECT_INPUT) #define IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH1_SELECT_INPUT) #define IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH2_SELECT_INPUT) #define IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH3_SELECT_INPUT) #define IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH4_SELECT_INPUT) #define IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH5_SELECT_INPUT) #define IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH6_SELECT_INPUT) #define IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH7_SELECT_INPUT) #define IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_PHA_SELECT_INPUT) #define IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_PHB_SELECT_INPUT) #define IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH0_SELECT_INPUT) #define IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH1_SELECT_INPUT) #define IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH2_SELECT_INPUT) #define IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH3_SELECT_INPUT) #define IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH4_SELECT_INPUT) #define IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH5_SELECT_INPUT) #define IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH6_SELECT_INPUT) #define IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH7_SELECT_INPUT) #define IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_PHA_SELECT_INPUT) #define IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_PHB_SELECT_INPUT) #define IOMUXC_I2C1_SCL_SELECT_INPUT_REG(base) ((base)->I2C1_SCL_SELECT_INPUT) #define IOMUXC_I2C1_SDA_SELECT_INPUT_REG(base) ((base)->I2C1_SDA_SELECT_INPUT) #define IOMUXC_I2C2_SCL_SELECT_INPUT_REG(base) ((base)->I2C2_SCL_SELECT_INPUT) #define IOMUXC_I2C2_SDA_SELECT_INPUT_REG(base) ((base)->I2C2_SDA_SELECT_INPUT) #define IOMUXC_I2C3_SCL_SELECT_INPUT_REG(base) ((base)->I2C3_SCL_SELECT_INPUT) #define IOMUXC_I2C3_SDA_SELECT_INPUT_REG(base) ((base)->I2C3_SDA_SELECT_INPUT) #define IOMUXC_I2C4_SCL_SELECT_INPUT_REG(base) ((base)->I2C4_SCL_SELECT_INPUT) #define IOMUXC_I2C4_SDA_SELECT_INPUT_REG(base) ((base)->I2C4_SDA_SELECT_INPUT) #define IOMUXC_KPP_COL0_SELECT_INPUT_REG(base) ((base)->KPP_COL0_SELECT_INPUT) #define IOMUXC_KPP_COL1_SELECT_INPUT_REG(base) ((base)->KPP_COL1_SELECT_INPUT) #define IOMUXC_KPP_COL2_SELECT_INPUT_REG(base) ((base)->KPP_COL2_SELECT_INPUT) #define IOMUXC_KPP_COL3_SELECT_INPUT_REG(base) ((base)->KPP_COL3_SELECT_INPUT) #define IOMUXC_KPP_COL4_SELECT_INPUT_REG(base) ((base)->KPP_COL4_SELECT_INPUT) #define IOMUXC_KPP_COL5_SELECT_INPUT_REG(base) ((base)->KPP_COL5_SELECT_INPUT) #define IOMUXC_KPP_COL6_SELECT_INPUT_REG(base) ((base)->KPP_COL6_SELECT_INPUT) #define IOMUXC_KPP_COL7_SELECT_INPUT_REG(base) ((base)->KPP_COL7_SELECT_INPUT) #define IOMUXC_KPP_ROW0_SELECT_INPUT_REG(base) ((base)->KPP_ROW0_SELECT_INPUT) #define IOMUXC_KPP_ROW1_SELECT_INPUT_REG(base) ((base)->KPP_ROW1_SELECT_INPUT) #define IOMUXC_KPP_ROW2_SELECT_INPUT_REG(base) ((base)->KPP_ROW2_SELECT_INPUT) #define IOMUXC_KPP_ROW3_SELECT_INPUT_REG(base) ((base)->KPP_ROW3_SELECT_INPUT) #define IOMUXC_KPP_ROW4_SELECT_INPUT_REG(base) ((base)->KPP_ROW4_SELECT_INPUT) #define IOMUXC_KPP_ROW5_SELECT_INPUT_REG(base) ((base)->KPP_ROW5_SELECT_INPUT) #define IOMUXC_KPP_ROW6_SELECT_INPUT_REG(base) ((base)->KPP_ROW6_SELECT_INPUT) #define IOMUXC_KPP_ROW7_SELECT_INPUT_REG(base) ((base)->KPP_ROW7_SELECT_INPUT) #define IOMUXC_LCD_BUSY_SELECT_INPUT_REG(base) ((base)->LCD_BUSY_SELECT_INPUT) #define IOMUXC_LCD_DATA00_SELECT_INPUT_REG(base) ((base)->LCD_DATA00_SELECT_INPUT) #define IOMUXC_LCD_DATA01_SELECT_INPUT_REG(base) ((base)->LCD_DATA01_SELECT_INPUT) #define IOMUXC_LCD_DATA02_SELECT_INPUT_REG(base) ((base)->LCD_DATA02_SELECT_INPUT) #define IOMUXC_LCD_DATA03_SELECT_INPUT_REG(base) ((base)->LCD_DATA03_SELECT_INPUT) #define IOMUXC_LCD_DATA04_SELECT_INPUT_REG(base) ((base)->LCD_DATA04_SELECT_INPUT) #define IOMUXC_LCD_DATA05_SELECT_INPUT_REG(base) ((base)->LCD_DATA05_SELECT_INPUT) #define IOMUXC_LCD_DATA06_SELECT_INPUT_REG(base) ((base)->LCD_DATA06_SELECT_INPUT) #define IOMUXC_LCD_DATA07_SELECT_INPUT_REG(base) ((base)->LCD_DATA07_SELECT_INPUT) #define IOMUXC_LCD_DATA08_SELECT_INPUT_REG(base) ((base)->LCD_DATA08_SELECT_INPUT) #define IOMUXC_LCD_DATA09_SELECT_INPUT_REG(base) ((base)->LCD_DATA09_SELECT_INPUT) #define IOMUXC_LCD_DATA10_SELECT_INPUT_REG(base) ((base)->LCD_DATA10_SELECT_INPUT) #define IOMUXC_LCD_DATA11_SELECT_INPUT_REG(base) ((base)->LCD_DATA11_SELECT_INPUT) #define IOMUXC_LCD_DATA12_SELECT_INPUT_REG(base) ((base)->LCD_DATA12_SELECT_INPUT) #define IOMUXC_LCD_DATA13_SELECT_INPUT_REG(base) ((base)->LCD_DATA13_SELECT_INPUT) #define IOMUXC_LCD_DATA14_SELECT_INPUT_REG(base) ((base)->LCD_DATA14_SELECT_INPUT) #define IOMUXC_LCD_DATA15_SELECT_INPUT_REG(base) ((base)->LCD_DATA15_SELECT_INPUT) #define IOMUXC_LCD_DATA16_SELECT_INPUT_REG(base) ((base)->LCD_DATA16_SELECT_INPUT) #define IOMUXC_LCD_DATA17_SELECT_INPUT_REG(base) ((base)->LCD_DATA17_SELECT_INPUT) #define IOMUXC_LCD_DATA18_SELECT_INPUT_REG(base) ((base)->LCD_DATA18_SELECT_INPUT) #define IOMUXC_LCD_DATA19_SELECT_INPUT_REG(base) ((base)->LCD_DATA19_SELECT_INPUT) #define IOMUXC_LCD_DATA20_SELECT_INPUT_REG(base) ((base)->LCD_DATA20_SELECT_INPUT) #define IOMUXC_LCD_DATA21_SELECT_INPUT_REG(base) ((base)->LCD_DATA21_SELECT_INPUT) #define IOMUXC_LCD_DATA22_SELECT_INPUT_REG(base) ((base)->LCD_DATA22_SELECT_INPUT) #define IOMUXC_LCD_DATA23_SELECT_INPUT_REG(base) ((base)->LCD_DATA23_SELECT_INPUT) #define IOMUXC_LCD_VSYNC_SELECT_INPUT_REG(base) ((base)->LCD_VSYNC_SELECT_INPUT) #define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI1_RX_BCLK_SELECT_INPUT) #define IOMUXC_SAI1_RX_DATA_SELECT_INPUT_REG(base) ((base)->SAI1_RX_DATA_SELECT_INPUT) #define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI1_RX_SYNC_SELECT_INPUT) #define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI1_TX_BCLK_SELECT_INPUT) #define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI1_TX_SYNC_SELECT_INPUT) #define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI2_RX_BCLK_SELECT_INPUT) #define IOMUXC_SAI2_RX_DATA_SELECT_INPUT_REG(base) ((base)->SAI2_RX_DATA_SELECT_INPUT) #define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI2_RX_SYNC_SELECT_INPUT) #define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI2_TX_BCLK_SELECT_INPUT) #define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI2_TX_SYNC_SELECT_INPUT) #define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI3_RX_BCLK_SELECT_INPUT) #define IOMUXC_SAI3_RX_DATA_SELECT_INPUT_REG(base) ((base)->SAI3_RX_DATA_SELECT_INPUT) #define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI3_RX_SYNC_SELECT_INPUT) #define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI3_TX_BCLK_SELECT_INPUT) #define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI3_TX_SYNC_SELECT_INPUT) #define IOMUXC_SDMA_EVENTS0_SELECT_INPUT_REG(base) ((base)->SDMA_EVENTS0_SELECT_INPUT) #define IOMUXC_SDMA_EVENTS1_SELECT_INPUT_REG(base) ((base)->SDMA_EVENTS1_SELECT_INPUT) #define IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_REG(base) ((base)->SIM1_PORT1_PD_SELECT_INPUT) #define IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_REG(base) ((base)->SIM1_PORT1_TRXD_SELECT_INPUT) #define IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_REG(base) ((base)->SIM2_PORT1_PD_SELECT_INPUT) #define IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_REG(base) ((base)->SIM2_PORT1_TRXD_SELECT_INPUT) #define IOMUXC_UART1_RTS_B_SELECT_INPUT_REG(base) ((base)->UART1_RTS_B_SELECT_INPUT) #define IOMUXC_UART1_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART1_RX_DATA_SELECT_INPUT) #define IOMUXC_UART2_RTS_B_SELECT_INPUT_REG(base) ((base)->UART2_RTS_B_SELECT_INPUT) #define IOMUXC_UART2_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART2_RX_DATA_SELECT_INPUT) #define IOMUXC_UART3_RTS_B_SELECT_INPUT_REG(base) ((base)->UART3_RTS_B_SELECT_INPUT) #define IOMUXC_UART3_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART3_RX_DATA_SELECT_INPUT) #define IOMUXC_UART4_RTS_B_SELECT_INPUT_REG(base) ((base)->UART4_RTS_B_SELECT_INPUT) #define IOMUXC_UART4_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART4_RX_DATA_SELECT_INPUT) #define IOMUXC_UART5_RTS_B_SELECT_INPUT_REG(base) ((base)->UART5_RTS_B_SELECT_INPUT) #define IOMUXC_UART5_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART5_RX_DATA_SELECT_INPUT) #define IOMUXC_UART6_RTS_B_SELECT_INPUT_REG(base) ((base)->UART6_RTS_B_SELECT_INPUT) #define IOMUXC_UART6_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART6_RX_DATA_SELECT_INPUT) #define IOMUXC_UART7_RTS_B_SELECT_INPUT_REG(base) ((base)->UART7_RTS_B_SELECT_INPUT) #define IOMUXC_UART7_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART7_RX_DATA_SELECT_INPUT) #define IOMUXC_USB_OTG2_OC_SELECT_INPUT_REG(base) ((base)->USB_OTG2_OC_SELECT_INPUT) #define IOMUXC_USB_OTG1_OC_SELECT_INPUT_REG(base) ((base)->USB_OTG1_OC_SELECT_INPUT) #define IOMUXC_USB_OTG2_ID_SELECT_INPUT_REG(base) ((base)->USB_OTG2_ID_SELECT_INPUT) #define IOMUXC_USB_OTG1_ID_SELECT_INPUT_REG(base) ((base)->USB_OTG1_ID_SELECT_INPUT) #define IOMUXC_SD3_CD_B_SELECT_INPUT_REG(base) ((base)->SD3_CD_B_SELECT_INPUT) #define IOMUXC_SD3_WP_SELECT_INPUT_REG(base) ((base)->SD3_WP_SELECT_INPUT) /*! * @} */ /* end of group IOMUXC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- IOMUXC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks * @{ */ /* SW_MUX_CTL_PAD_GPIO1_IO08 Bit Fields */ #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_MASK 0x7u #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_SHIFT 0 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<GPR0) #define IOMUXC_GPR_GPR1_REG(base) ((base)->GPR1) #define IOMUXC_GPR_GPR2_REG(base) ((base)->GPR2) #define IOMUXC_GPR_GPR3_REG(base) ((base)->GPR3) #define IOMUXC_GPR_GPR4_REG(base) ((base)->GPR4) #define IOMUXC_GPR_GPR5_REG(base) ((base)->GPR5) #define IOMUXC_GPR_GPR6_REG(base) ((base)->GPR6) #define IOMUXC_GPR_GPR7_REG(base) ((base)->GPR7) #define IOMUXC_GPR_GPR8_REG(base) ((base)->GPR8) #define IOMUXC_GPR_GPR9_REG(base) ((base)->GPR9) #define IOMUXC_GPR_GPR10_REG(base) ((base)->GPR10) #define IOMUXC_GPR_GPR11_REG(base) ((base)->GPR11) #define IOMUXC_GPR_GPR12_REG(base) ((base)->GPR12) #define IOMUXC_GPR_GPR13_REG(base) ((base)->GPR13) #define IOMUXC_GPR_GPR14_REG(base) ((base)->GPR14) #define IOMUXC_GPR_GPR15_REG(base) ((base)->GPR15) #define IOMUXC_GPR_GPR16_REG(base) ((base)->GPR16) #define IOMUXC_GPR_GPR17_REG(base) ((base)->GPR17) #define IOMUXC_GPR_GPR18_REG(base) ((base)->GPR18) #define IOMUXC_GPR_GPR19_REG(base) ((base)->GPR19) #define IOMUXC_GPR_GPR20_REG(base) ((base)->GPR20) #define IOMUXC_GPR_GPR21_REG(base) ((base)->GPR21) #define IOMUXC_GPR_GPR22_REG(base) ((base)->GPR22) /*! * @} */ /* end of group IOMUXC_GPR_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- IOMUXC_GPR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks * @{ */ /* GPR0 Bit Fields */ #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 /* GPR1 Bit Fields */ #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT 1 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<SW_MUX_CTL_PAD_GPIO1_IO00) #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO01) #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO02) #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO03) #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO04) #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO05) #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO06) #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO07) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_REG(base) ((base)->SW_PAD_CTL_PAD_TEST_MODE) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_REG(base) ((base)->SW_PAD_CTL_PAD_SRC_POR_B) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_REG(base) ((base)->SW_PAD_CTL_PAD_BOOT_MODE0) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_REG(base) ((base)->SW_PAD_CTL_PAD_BOOT_MODE1) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO00) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO01) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO02) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO03) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO04) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO05) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO06) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO07) /*! * @} */ /* end of group IOMUXC_LPSR_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- IOMUXC_LPSR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC_LPSR_Register_Masks IOMUXC_LPSR Register Masks * @{ */ /* SW_MUX_CTL_PAD_GPIO1_IO00 Bit Fields */ #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_MASK 0x7u #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_SHIFT 0 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<KPCR) #define KPP_KPSR_REG(base) ((base)->KPSR) #define KPP_KDDR_REG(base) ((base)->KDDR) #define KPP_KPDR_REG(base) ((base)->KPDR) /*! * @} */ /* end of group KPP_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- KPP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup KPP_Register_Masks KPP Register Masks * @{ */ /* KPCR Bit Fields */ #define KPP_KPCR_KRE_MASK 0xFFu #define KPP_KPCR_KRE_SHIFT 0 #define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x))<RL) #define LCDIF_RL_SET_REG(base) ((base)->RL_SET) #define LCDIF_RL_CLR_REG(base) ((base)->RL_CLR) #define LCDIF_RL_TOG_REG(base) ((base)->RL_TOG) #define LCDIF_CTRL1_REG(base) ((base)->CTRL1) #define LCDIF_CTRL1_SET_REG(base) ((base)->CTRL1_SET) #define LCDIF_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) #define LCDIF_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) #define LCDIF_CTRL2_REG(base) ((base)->CTRL2) #define LCDIF_CTRL2_SET_REG(base) ((base)->CTRL2_SET) #define LCDIF_CTRL2_CLR_REG(base) ((base)->CTRL2_CLR) #define LCDIF_CTRL2_TOG_REG(base) ((base)->CTRL2_TOG) #define LCDIF_TRANSFER_COUNT_REG(base) ((base)->TRANSFER_COUNT) #define LCDIF_CUR_BUF_REG(base) ((base)->CUR_BUF) #define LCDIF_NEXT_BUF_REG(base) ((base)->NEXT_BUF) #define LCDIF_TIMING_REG(base) ((base)->TIMING) #define LCDIF_VDCTRL0_REG(base) ((base)->VDCTRL0) #define LCDIF_VDCTRL0_SET_REG(base) ((base)->VDCTRL0_SET) #define LCDIF_VDCTRL0_CLR_REG(base) ((base)->VDCTRL0_CLR) #define LCDIF_VDCTRL0_TOG_REG(base) ((base)->VDCTRL0_TOG) #define LCDIF_VDCTRL1_REG(base) ((base)->VDCTRL1) #define LCDIF_VDCTRL2_REG(base) ((base)->VDCTRL2) #define LCDIF_VDCTRL3_REG(base) ((base)->VDCTRL3) #define LCDIF_VDCTRL4_REG(base) ((base)->VDCTRL4) #define LCDIF_DVICTRL0_REG(base) ((base)->DVICTRL0) #define LCDIF_DVICTRL1_REG(base) ((base)->DVICTRL1) #define LCDIF_DVICTRL2_REG(base) ((base)->DVICTRL2) #define LCDIF_DVICTRL3_REG(base) ((base)->DVICTRL3) #define LCDIF_DVICTRL4_REG(base) ((base)->DVICTRL4) #define LCDIF_CSC_COEFF0_REG(base) ((base)->CSC_COEFF0) #define LCDIF_CSC_COEFF1_REG(base) ((base)->CSC_COEFF1) #define LCDIF_CSC_COEFF2_REG(base) ((base)->CSC_COEFF2) #define LCDIF_CSC_COEFF3_REG(base) ((base)->CSC_COEFF3) #define LCDIF_CSC_COEFF4_REG(base) ((base)->CSC_COEFF4) #define LCDIF_CSC_OFFSET_REG(base) ((base)->CSC_OFFSET) #define LCDIF_CSC_LIMIT_REG(base) ((base)->CSC_LIMIT) #define LCDIF_DATA_REG(base) ((base)->DATA) #define LCDIF_BM_ERROR_STAT_REG(base) ((base)->BM_ERROR_STAT) #define LCDIF_CRC_STAT_REG(base) ((base)->CRC_STAT) #define LCDIF_STAT_REG(base) ((base)->STAT) #define LCDIF_VERSION_REG(base) ((base)->VERSION) #define LCDIF_DEBUG0_REG(base) ((base)->DEBUG0) #define LCDIF_DEBUG1_REG(base) ((base)->DEBUG1) #define LCDIF_DEBUG2_REG(base) ((base)->DEBUG2) #define LCDIF_THRES_REG(base) ((base)->THRES) #define LCDIF_AS_CTRL_REG(base) ((base)->AS_CTRL) #define LCDIF_AS_BUF_REG(base) ((base)->AS_BUF) #define LCDIF_AS_NEXT_BUF_REG(base) ((base)->AS_NEXT_BUF) #define LCDIF_AS_CLRKEYLOW_REG(base) ((base)->AS_CLRKEYLOW) #define LCDIF_AS_CLRKEYHIGH_REG(base) ((base)->AS_CLRKEYHIGH) #define LCDIF_SYNC_DELAY_REG(base) ((base)->SYNC_DELAY) #define LCDIF_DEBUG3_REG(base) ((base)->DEBUG3) #define LCDIF_DEBUG4_REG(base) ((base)->DEBUG4) #define LCDIF_DEBUG5_REG(base) ((base)->DEBUG5) /*! * @} */ /* end of group LCDIF_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- LCDIF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LCDIF_Register_Masks LCDIF Register Masks * @{ */ /* RL Bit Fields */ #define LCDIF_RL_RUN_MASK 0x1u #define LCDIF_RL_RUN_SHIFT 0 #define LCDIF_RL_DATA_FORMAT_24_BIT_MASK 0x2u #define LCDIF_RL_DATA_FORMAT_24_BIT_SHIFT 1 #define LCDIF_RL_DATA_FORMAT_18_BIT_MASK 0x4u #define LCDIF_RL_DATA_FORMAT_18_BIT_SHIFT 2 #define LCDIF_RL_DATA_FORMAT_16_BIT_MASK 0x8u #define LCDIF_RL_DATA_FORMAT_16_BIT_SHIFT 3 #define LCDIF_RL_RSRVD0_MASK 0x10u #define LCDIF_RL_RSRVD0_SHIFT 4 #define LCDIF_RL_MASTER_MASK 0x20u #define LCDIF_RL_MASTER_SHIFT 5 #define LCDIF_RL_ENABLE_PXP_HANDSHAKE_MASK 0x40u #define LCDIF_RL_ENABLE_PXP_HANDSHAKE_SHIFT 6 #define LCDIF_RL_RGB_TO_YCBCR422_CSC_MASK 0x80u #define LCDIF_RL_RGB_TO_YCBCR422_CSC_SHIFT 7 #define LCDIF_RL_WORD_LENGTH_MASK 0x300u #define LCDIF_RL_WORD_LENGTH_SHIFT 8 #define LCDIF_RL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x))<PCCCR) #define LMEM_PCCLCR_REG(base) ((base)->PCCLCR) #define LMEM_PCCSAR_REG(base) ((base)->PCCSAR) #define LMEM_PCCCVR_REG(base) ((base)->PCCCVR) #define LMEM_PSCCR_REG(base) ((base)->PSCCR) #define LMEM_PSCLCR_REG(base) ((base)->PSCLCR) #define LMEM_PSCSAR_REG(base) ((base)->PSCSAR) #define LMEM_PSCCVR_REG(base) ((base)->PSCCVR) /*! * @} */ /* end of group LMEM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- LMEM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LMEM_Register_Masks LMEM Register Masks * @{ */ /* PCCCR Bit Fields */ #define LMEM_PCCCR_ENCACHE_MASK 0x1u #define LMEM_PCCCR_ENCACHE_SHIFT 0 #define LMEM_PCCCR_ENWRBUF_MASK 0x2u #define LMEM_PCCCR_ENWRBUF_SHIFT 1 #define LMEM_PCCCR_PCCR2_MASK 0x4u #define LMEM_PCCCR_PCCR2_SHIFT 2 #define LMEM_PCCCR_PCCR3_MASK 0x8u #define LMEM_PCCCR_PCCR3_SHIFT 3 #define LMEM_PCCCR_INVW0_MASK 0x1000000u #define LMEM_PCCCR_INVW0_SHIFT 24 #define LMEM_PCCCR_PUSHW0_MASK 0x2000000u #define LMEM_PCCCR_PUSHW0_SHIFT 25 #define LMEM_PCCCR_INVW1_MASK 0x4000000u #define LMEM_PCCCR_INVW1_SHIFT 26 #define LMEM_PCCCR_PUSHW1_MASK 0x8000000u #define LMEM_PCCCR_PUSHW1_SHIFT 27 #define LMEM_PCCCR_GO_MASK 0x80000000u #define LMEM_PCCCR_GO_SHIFT 31 /* PCCLCR Bit Fields */ #define LMEM_PCCLCR_LGO_MASK 0x1u #define LMEM_PCCLCR_LGO_SHIFT 0 #define LMEM_PCCLCR_CACHEADDR_MASK 0x1FFCu #define LMEM_PCCLCR_CACHEADDR_SHIFT 2 #define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<PLASC) #define MCM_PLAMC_REG(base) ((base)->PLAMC) #define MCM_FADR_REG(base) ((base)->FADR) #define MCM_FATR_REG(base) ((base)->FATR) #define MCM_FDR_REG(base) ((base)->FDR) /*! * @} */ /* end of group MCM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MCM_Register_Masks MCM Register Masks * @{ */ /* PLASC Bit Fields */ #define MCM_PLASC_ASC_MASK 0xFFu #define MCM_PLASC_ASC_SHIFT 0 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<VERSION) #define MIPI_DSI_STATUS_REG(base) ((base)->STATUS) #define MIPI_DSI_RGB_STATUS_REG(base) ((base)->RGB_STATUS) #define MIPI_DSI_SWRST_REG(base) ((base)->SWRST) #define MIPI_DSI_CLKCTRL_REG(base) ((base)->CLKCTRL) #define MIPI_DSI_TIMEOUT_REG(base) ((base)->TIMEOUT) #define MIPI_DSI_CONFIG_REG(base) ((base)->CONFIG) #define MIPI_DSI_ESCMODE_REG(base) ((base)->ESCMODE) #define MIPI_DSI_MDRESOL_REG(base) ((base)->MDRESOL) #define MIPI_DSI_MVPORCH_REG(base) ((base)->MVPORCH) #define MIPI_DSI_MHPORCH_REG(base) ((base)->MHPORCH) #define MIPI_DSI_MSYNC_REG(base) ((base)->MSYNC) #define MIPI_DSI_SDRESOL_REG(base) ((base)->SDRESOL) #define MIPI_DSI_INTSRC_REG(base) ((base)->INTSRC) #define MIPI_DSI_INTMSK_REG(base) ((base)->INTMSK) #define MIPI_DSI_PKTHDR_REG(base) ((base)->PKTHDR) #define MIPI_DSI_PAYLOAD_REG(base) ((base)->PAYLOAD) #define MIPI_DSI_RXFIFO_REG(base) ((base)->RXFIFO) #define MIPI_DSI_FIFOTHLD_REG(base) ((base)->FIFOTHLD) #define MIPI_DSI_FIFOCTRL_REG(base) ((base)->FIFOCTRL) #define MIPI_DSI_MEMACCHR_REG(base) ((base)->MEMACCHR) #define MIPI_DSI_MULTI_PKT_REG(base) ((base)->MULTI_PKT) #define MIPI_DSI_PLLCTRL_1G_REG(base) ((base)->PLLCTRL_1G) #define MIPI_DSI_PLLCTRL_REG(base) ((base)->PLLCTRL) #define MIPI_DSI_PLLCTRL1_REG(base) ((base)->PLLCTRL1) #define MIPI_DSI_PLLCTRL2_REG(base) ((base)->PLLCTRL2) #define MIPI_DSI_PLLTMR_REG(base) ((base)->PLLTMR) #define MIPI_DSI_PHYCTRL_B1_REG(base) ((base)->PHYCTRL_B.PHYCTRL_B1) #define MIPI_DSI_PHYCTRL_B2_REG(base) ((base)->PHYCTRL_B.PHYCTRL_B2) #define MIPI_DSI_PHYCTRL_M1_REG(base) ((base)->PHYCTRL_M.PHYCTRL_M1) #define MIPI_DSI_PHYCTRL_M2_REG(base) ((base)->PHYCTRL_M.PHYCTRL_M2) #define MIPI_DSI_PHYTIMING_REG(base) ((base)->PHYTIMING) #define MIPI_DSI_PHYTIMING1_REG(base) ((base)->PHYTIMING1) #define MIPI_DSI_PHYTIMING2_REG(base) ((base)->PHYTIMING2) /*! * @} */ /* end of group MIPI_DSI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MIPI_DSI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_Register_Masks MIPI_DSI Register Masks * @{ */ /* VERSION Bit Fields */ #define MIPI_DSI_VERSION_VERSION_MASK 0xFFFFFFFFu #define MIPI_DSI_VERSION_VERSION_SHIFT 0 #define MIPI_DSI_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x))<CSIS_CMN_CTRL) #define MIPI_HSI_CSIS_CLK_CTRL_REG(base) ((base)->CSIS_CLK_CTRL) #define MIPI_HSI_CSIS_INT_MSK_REG(base) ((base)->CSIS_INT_MSK) #define MIPI_HSI_CSIS_INT_SRC_REG(base) ((base)->CSIS_INT_SRC) #define MIPI_HSI_DPHY_STATUS_REG(base) ((base)->DPHY_STATUS) #define MIPI_HSI_DPHY_CMN_CTRL_REG(base) ((base)->DPHY_CMN_CTRL) #define MIPI_HSI_DPHY_BCTRL_L_REG(base) ((base)->DPHY_BCTRL_L) #define MIPI_HSI_DPHY_BCTRL_H_REG(base) ((base)->DPHY_BCTRL_H) #define MIPI_HSI_DPHY_SCTRL_L_REG(base) ((base)->DPHY_SCTRL_L) #define MIPI_HSI_DPHY_SCTRL_H_REG(base) ((base)->DPHY_SCTRL_H) #define MIPI_HSI_ISP_CONFIG_CH0_REG(base) ((base)->ISP_CONFIG_CH0) #define MIPI_HSI_ISP_RESOL_CH0_REG(base) ((base)->ISP_RESOL_CH0) #define MIPI_HSI_ISP_SYNC_CH0_REG(base) ((base)->ISP_SYNC_CH0) #define MIPI_HSI_SDW_CONFIG_CH0_REG(base) ((base)->SDW_CONFIG_CH0) #define MIPI_HSI_SDW_RESOL_CH0_REG(base) ((base)->SDW_RESOL_CH0) #define MIPI_HSI_SDW_SYNC_CH0_REG(base) ((base)->SDW_SYNC_CH0) #define MIPI_HSI_DBG_CTRL_REG(base) ((base)->DBG_CTRL) #define MIPI_HSI_DBG_INTR_MSK_REG(base) ((base)->DBG_INTR_MSK) #define MIPI_HSI_DBG_INTR_SRC_REG(base) ((base)->DBG_INTR_SRC) #define MIPI_HSI_NON_IMG_DATA_REG(base) ((base)->NON_IMG_DATA) /*! * @} */ /* end of group MIPI_HSI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MIPI_HSI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_HSI_Register_Masks MIPI_HSI Register Masks * @{ */ /* CSIS_CMN_CTRL Bit Fields */ #define MIPI_HSI_CSIS_CMN_CTRL_CSI_EN_MASK 0x1u #define MIPI_HSI_CSIS_CMN_CTRL_CSI_EN_SHIFT 0 #define MIPI_HSI_CSIS_CMN_CTRL_SW_REST_MASK 0x2u #define MIPI_HSI_CSIS_CMN_CTRL_SW_REST_SHIFT 1 #define MIPI_HSI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL_MASK 0x4u #define MIPI_HSI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL_SHIFT 2 #define MIPI_HSI_CSIS_CMN_CTRL_RSVD3_MASK 0xF8u #define MIPI_HSI_CSIS_CMN_CTRL_RSVD3_SHIFT 3 #define MIPI_HSI_CSIS_CMN_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x))<TR[index]) #define MU_TR_COUNT 4 #define MU_RR_REG(base,index) ((base)->RR[index]) #define MU_RR_COUNT 4 #define MU_SR_REG(base) ((base)->SR) #define MU_CR_REG(base) ((base)->CR) /*! * @} */ /* end of group MU_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MU_Register_Masks MU Register Masks * @{ */ /* TR Bit Fields */ #define MU_TR_DATA_MASK 0xFFFFFFFFu #define MU_TR_DATA_SHIFT 0 #define MU_TR_DATA_WIDTH 32 #define MU_TR_DATA(x) (((uint32_t)(((uint32_t)(x))<CTRL) #define OCOTP_CTRL_SET_REG(base) ((base)->CTRL_SET) #define OCOTP_CTRL_CLR_REG(base) ((base)->CTRL_CLR) #define OCOTP_CTRL_TOG_REG(base) ((base)->CTRL_TOG) #define OCOTP_TIMING_REG(base) ((base)->TIMING) #define OCOTP_DATA0_REG(base) ((base)->DATA0) #define OCOTP_DATA1_REG(base) ((base)->DATA1) #define OCOTP_DATA2_REG(base) ((base)->DATA2) #define OCOTP_DATA3_REG(base) ((base)->DATA3) #define OCOTP_READ_CTRL_REG(base) ((base)->READ_CTRL) #define OCOTP_READ_FUSE_DATA0_REG(base) ((base)->READ_FUSE_DATA0) #define OCOTP_READ_FUSE_DATA1_REG(base) ((base)->READ_FUSE_DATA1) #define OCOTP_READ_FUSE_DATA2_REG(base) ((base)->READ_FUSE_DATA2) #define OCOTP_READ_FUSE_DATA3_REG(base) ((base)->READ_FUSE_DATA3) #define OCOTP_SW_STICKY_REG(base) ((base)->SW_STICKY) #define OCOTP_SCS_REG(base) ((base)->SCS) #define OCOTP_SCS_SET_REG(base) ((base)->SCS_SET) #define OCOTP_SCS_CLR_REG(base) ((base)->SCS_CLR) #define OCOTP_SCS_TOG_REG(base) ((base)->SCS_TOG) #define OCOTP_CRC_ADDR_REG(base) ((base)->CRC_ADDR) #define OCOTP_CRC_VALUE_REG(base) ((base)->CRC_VALUE) #define OCOTP_VERSION_REG(base) ((base)->VERSION) #define OCOTP_LOCK_REG(base) ((base)->LOCK) #define OCOTP_TESTER0_REG(base) ((base)->TESTER0) #define OCOTP_TESTER1_REG(base) ((base)->TESTER1) #define OCOTP_TESTER2_REG(base) ((base)->TESTER2) #define OCOTP_TESTER3_REG(base) ((base)->TESTER3) #define OCOTP_TESTER4_REG(base) ((base)->TESTER4) #define OCOTP_TESTER5_REG(base) ((base)->TESTER5) #define OCOTP_BOOT_CFG0_REG(base) ((base)->BOOT_CFG0) #define OCOTP_BOOT_CFG1_REG(base) ((base)->BOOT_CFG1) #define OCOTP_BOOT_CFG2_REG(base) ((base)->BOOT_CFG2) #define OCOTP_BOOT_CFG3_REG(base) ((base)->BOOT_CFG3) #define OCOTP_BOOT_CFG4_REG(base) ((base)->BOOT_CFG4) #define OCOTP_MEM_TRIM0_REG(base) ((base)->MEM_TRIM0) #define OCOTP_MEM_TRIM1_REG(base) ((base)->MEM_TRIM1) #define OCOTP_ANA0_REG(base) ((base)->ANA0) #define OCOTP_ANA1_REG(base) ((base)->ANA1) #define OCOTP_OTPMK0_REG(base) ((base)->OTPMK0) #define OCOTP_OTPMK1_REG(base) ((base)->OTPMK1) #define OCOTP_OTPMK2_REG(base) ((base)->OTPMK2) #define OCOTP_OTPMK3_REG(base) ((base)->OTPMK3) #define OCOTP_OTPMK4_REG(base) ((base)->OTPMK4) #define OCOTP_OTPMK5_REG(base) ((base)->OTPMK5) #define OCOTP_OTPMK6_REG(base) ((base)->OTPMK6) #define OCOTP_OTPMK7_REG(base) ((base)->OTPMK7) #define OCOTP_SRK0_REG(base) ((base)->SRK0) #define OCOTP_SRK1_REG(base) ((base)->SRK1) #define OCOTP_SRK2_REG(base) ((base)->SRK2) #define OCOTP_SRK3_REG(base) ((base)->SRK3) #define OCOTP_SRK4_REG(base) ((base)->SRK4) #define OCOTP_SRK5_REG(base) ((base)->SRK5) #define OCOTP_SRK6_REG(base) ((base)->SRK6) #define OCOTP_SRK7_REG(base) ((base)->SRK7) #define OCOTP_SJC_RESP0_REG(base) ((base)->SJC_RESP0) #define OCOTP_SJC_RESP1_REG(base) ((base)->SJC_RESP1) #define OCOTP_USB_ID_REG(base) ((base)->USB_ID) #define OCOTP_FIELD_RETURN_REG(base) ((base)->FIELD_RETURN) #define OCOTP_MAC_ADDR0_REG(base) ((base)->MAC_ADDR0) #define OCOTP_MAC_ADDR1_REG(base) ((base)->MAC_ADDR1) #define OCOTP_MAC_ADDR2_REG(base) ((base)->MAC_ADDR2) #define OCOTP_SRK_REVOKE_REG(base) ((base)->SRK_REVOKE) #define OCOTP_MAU_KEY0_REG(base) ((base)->MAU_KEY0) #define OCOTP_MAU_KEY1_REG(base) ((base)->MAU_KEY1) #define OCOTP_MAU_KEY2_REG(base) ((base)->MAU_KEY2) #define OCOTP_MAU_KEY3_REG(base) ((base)->MAU_KEY3) #define OCOTP_MAU_KEY4_REG(base) ((base)->MAU_KEY4) #define OCOTP_MAU_KEY5_REG(base) ((base)->MAU_KEY5) #define OCOTP_MAU_KEY6_REG(base) ((base)->MAU_KEY6) #define OCOTP_MAU_KEY7_REG(base) ((base)->MAU_KEY7) #define OCOTP_ROM_PATCH0_REG(base) ((base)->ROM_PATCH0) #define OCOTP_ROM_PATCH1_REG(base) ((base)->ROM_PATCH1) #define OCOTP_ROM_PATCH2_REG(base) ((base)->ROM_PATCH2) #define OCOTP_ROM_PATCH3_REG(base) ((base)->ROM_PATCH3) #define OCOTP_ROM_PATCH4_REG(base) ((base)->ROM_PATCH4) #define OCOTP_ROM_PATCH5_REG(base) ((base)->ROM_PATCH5) #define OCOTP_ROM_PATCH6_REG(base) ((base)->ROM_PATCH6) #define OCOTP_ROM_PATCH7_REG(base) ((base)->ROM_PATCH7) #define OCOTP_GP10_REG(base) ((base)->GP10) #define OCOTP_GP11_REG(base) ((base)->GP11) #define OCOTP_GP20_REG(base) ((base)->GP20) #define OCOTP_GP21_REG(base) ((base)->GP21) #define OCOTP_CRC_GP10_REG(base) ((base)->CRC_GP10) #define OCOTP_CRC_GP11_REG(base) ((base)->CRC_GP11) #define OCOTP_CRC_GP20_REG(base) ((base)->CRC_GP20) #define OCOTP_CRC_GP21_REG(base) ((base)->CRC_GP21) /*! * @} */ /* end of group OCOTP_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- OCOTP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup OCOTP_Register_Masks OCOTP Register Masks * @{ */ /* CTRL Bit Fields */ #define OCOTP_CTRL_ADDR_MASK 0xFu #define OCOTP_CTRL_ADDR_SHIFT 0 #define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x))<REG01) #define PCIE_PHY_CMN_REG02_REG(base) ((base)->REG02) #define PCIE_PHY_CMN_REG03_REG(base) ((base)->REG03) #define PCIE_PHY_CMN_REG04_REG(base) ((base)->REG04) #define PCIE_PHY_CMN_REG05_REG(base) ((base)->REG05) #define PCIE_PHY_CMN_REG06_REG(base) ((base)->REG06) #define PCIE_PHY_CMN_REG07_REG(base) ((base)->REG07) #define PCIE_PHY_CMN_REG0B_REG(base) ((base)->REG0B) #define PCIE_PHY_CMN_REG08_REG(base) ((base)->REG08) #define PCIE_PHY_CMN_REG09_REG(base) ((base)->REG09) #define PCIE_PHY_CMN_REG11_REG(base) ((base)->REG11) #define PCIE_PHY_CMN_REG15_REG(base) ((base)->REG15) #define PCIE_PHY_CMN_REG16_REG(base) ((base)->REG16) #define PCIE_PHY_CMN_REG17_REG(base) ((base)->REG17) #define PCIE_PHY_CMN_REG18_REG(base) ((base)->REG18) #define PCIE_PHY_CMN_REG19_REG(base) ((base)->REG19) #define PCIE_PHY_CMN_REG1A_REG(base) ((base)->REG1A) /*! * @} */ /* end of group PCIE_PHY_CMN_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PCIE_PHY_CMN Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PCIE_PHY_CMN_Register_Masks PCIE_PHY_CMN Register Masks * @{ */ /* REG01 Bit Fields */ #define PCIE_PHY_CMN_REG01_TCODE_MASK 0xFu #define PCIE_PHY_CMN_REG01_TCODE_SHIFT 0 #define PCIE_PHY_CMN_REG01_TCODE(x) (((uint32_t)(((uint32_t)(x))<REG21) #define PCIE_PHY_TRSV_REG22_REG(base) ((base)->REG22) #define PCIE_PHY_TRSV_REG24_REG(base) ((base)->REG24) #define PCIE_PHY_TRSV_REG2B_REG(base) ((base)->REG2B) #define PCIE_PHY_TRSV_REG3A_REG(base) ((base)->REG3A) #define PCIE_PHY_TRSV_REG3E_REG(base) ((base)->REG3E) #define PCIE_PHY_TRSV_REG25_REG(base) ((base)->REG25) #define PCIE_PHY_TRSV_REG26_REG(base) ((base)->REG26) #define PCIE_PHY_TRSV_REG29_REG(base) ((base)->REG29) #define PCIE_PHY_TRSV_REG31_REG(base) ((base)->REG31) #define PCIE_PHY_TRSV_REG33_REG(base) ((base)->REG33) #define PCIE_PHY_TRSV_REG36_REG(base) ((base)->REG36) #define PCIE_PHY_TRSV_REG37_REG(base) ((base)->REG37) #define PCIE_PHY_TRSV_REG38_REG(base) ((base)->REG38) #define PCIE_PHY_TRSV_REG39_REG(base) ((base)->REG39) #define PCIE_PHY_TRSV_REG40_REG(base) ((base)->REG40) #define PCIE_PHY_TRSV_REG42_REG(base) ((base)->REG42) /*! * @} */ /* end of group PCIE_PHY_TRSV_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PCIE_PHY_TRSV Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PCIE_PHY_TRSV_Register_Masks PCIE_PHY_TRSV Register Masks * @{ */ /* REG21 Bit Fields */ #define PCIE_PHY_TRSV_REG21_EMP_LVL_MASK 0x1Fu #define PCIE_PHY_TRSV_REG21_EMP_LVL_SHIFT 0 #define PCIE_PHY_TRSV_REG21_EMP_LVL(x) (((uint32_t)(((uint32_t)(x))<GPU_CTRL) #define PGC_GPU_PUPSCR_REG(base) ((base)->GPU_PUPSCR) #define PGC_GPU_PDNSCR_REG(base) ((base)->GPU_PDNSCR) #define PGC_GPU_SR_REG(base) ((base)->GPU_SR) #define PGC_CPU_CTRL_REG(base) ((base)->CPU_CTRL) #define PGC_CPU_PUPSCR_REG(base) ((base)->CPU_PUPSCR) #define PGC_CPU_PDNSCR_REG(base) ((base)->CPU_PDNSCR) #define PGC_CPU_SR_REG(base) ((base)->CPU_SR) /*! * @} */ /* end of group PGC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PGC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PGC_Register_Masks PGC Register Masks * @{ */ /* GPU_CTRL Bit Fields */ #define PGC_GPU_CTRL_PCR_MASK 0x1u #define PGC_GPU_CTRL_PCR_SHIFT 0 /* GPU_PUPSCR Bit Fields */ #define PGC_GPU_PUPSCR_SW_MASK 0x3Fu #define PGC_GPU_PUPSCR_SW_SHIFT 0 #define PGC_GPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<REG_1P0A) #define PMU_REG_1P0A_SET_REG(base) ((base)->REG_1P0A_SET) #define PMU_REG_1P0A_CLR_REG(base) ((base)->REG_1P0A_CLR) #define PMU_REG_1P0A_TOG_REG(base) ((base)->REG_1P0A_TOG) #define PMU_REG_1P0D_REG(base) ((base)->REG_1P0D) #define PMU_REG_1P0D_SET_REG(base) ((base)->REG_1P0D_SET) #define PMU_REG_1P0D_CLR_REG(base) ((base)->REG_1P0D_CLR) #define PMU_REG_1P0D_TOG_REG(base) ((base)->REG_1P0D_TOG) #define PMU_REG_HSIC_1P2_REG(base) ((base)->REG_HSIC_1P2) #define PMU_REG_HSIC_1P2_SET_REG(base) ((base)->REG_HSIC_1P2_SET) #define PMU_REG_HSIC_1P2_CLR_REG(base) ((base)->REG_HSIC_1P2_CLR) #define PMU_REG_HSIC_1P2_TOG_REG(base) ((base)->REG_HSIC_1P2_TOG) #define PMU_REG_LPSR_1P0_REG(base) ((base)->REG_LPSR_1P0) #define PMU_REG_LPSR_1P0_SET_REG(base) ((base)->REG_LPSR_1P0_SET) #define PMU_REG_LPSR_1P0_CLR_REG(base) ((base)->REG_LPSR_1P0_CLR) #define PMU_REG_LPSR_1P0_TOG_REG(base) ((base)->REG_LPSR_1P0_TOG) #define PMU_REG_3P0_REG(base) ((base)->REG_3P0) #define PMU_REG_3P0_SET_REG(base) ((base)->REG_3P0_SET) #define PMU_REG_3P0_CLR_REG(base) ((base)->REG_3P0_CLR) #define PMU_REG_3P0_TOG_REG(base) ((base)->REG_3P0_TOG) #define PMU_REF_REG(base) ((base)->REF) #define PMU_REF_SET_REG(base) ((base)->REF_SET) #define PMU_REF_CLR_REG(base) ((base)->REF_CLR) #define PMU_REF_TOG_REG(base) ((base)->REF_TOG) #define PMU_LOWPWR_CTRL_REG(base) ((base)->LOWPWR_CTRL) #define PMU_LOWPWR_CTRL_SET_REG(base) ((base)->LOWPWR_CTRL_SET) #define PMU_LOWPWR_CTRL_CLR_REG(base) ((base)->LOWPWR_CTRL_CLR) #define PMU_LOWPWR_CTRL_TOG_REG(base) ((base)->LOWPWR_CTRL_TOG) /*! * @} */ /* end of group PMU_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PMU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PMU_Register_Masks PMU Register Masks * @{ */ /* REG_1P0A Bit Fields */ #define PMU_REG_1P0A_ENABLE_LINREG_MASK 0x1u #define PMU_REG_1P0A_ENABLE_LINREG_SHIFT 0 #define PMU_REG_1P0A_ENABLE_BO_MASK 0x2u #define PMU_REG_1P0A_ENABLE_BO_SHIFT 1 #define PMU_REG_1P0A_ENABLE_ILIMIT_MASK 0x4u #define PMU_REG_1P0A_ENABLE_ILIMIT_SHIFT 2 #define PMU_REG_1P0A_ENABLE_PULLDOWN_MASK 0x8u #define PMU_REG_1P0A_ENABLE_PULLDOWN_SHIFT 3 #define PMU_REG_1P0A_BO_OFFSET_MASK 0x70u #define PMU_REG_1P0A_BO_OFFSET_SHIFT 4 #define PMU_REG_1P0A_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<PWMCR) #define PWM_PWMSR_REG(base) ((base)->PWMSR) #define PWM_PWMIR_REG(base) ((base)->PWMIR) #define PWM_PWMSAR_REG(base) ((base)->PWMSAR) #define PWM_PWMPR_REG(base) ((base)->PWMPR) #define PWM_PWMCNR_REG(base) ((base)->PWMCNR) /*! * @} */ /* end of group PWM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PWM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PWM_Register_Masks PWM Register Masks * @{ */ /* PWMCR Bit Fields */ #define PWM_PWMCR_EN_MASK 0x1u #define PWM_PWMCR_EN_SHIFT 0 #define PWM_PWMCR_REPEAT_MASK 0x6u #define PWM_PWMCR_REPEAT_SHIFT 1 #define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x))<CTRL) #define PXP_STAT_REG(base) ((base)->STAT) #define PXP_OUT_CTRL_REG(base) ((base)->OUT_CTRL) #define PXP_OUT_BUF_REG(base) ((base)->OUT_BUF) #define PXP_OUT_BUF2_REG(base) ((base)->OUT_BUF2) #define PXP_OUT_PITCH_REG(base) ((base)->OUT_PITCH) #define PXP_OUT_LRC_REG(base) ((base)->OUT_LRC) #define PXP_OUT_PS_ULC_REG(base) ((base)->OUT_PS_ULC) #define PXP_OUT_PS_LRC_REG(base) ((base)->OUT_PS_LRC) #define PXP_OUT_AS_ULC_REG(base) ((base)->OUT_AS_ULC) #define PXP_OUT_AS_LRC_REG(base) ((base)->OUT_AS_LRC) #define PXP_PS_CTRL_REG(base) ((base)->PS_CTRL) #define PXP_PS_BUF_REG(base) ((base)->PS_BUF) #define PXP_PS_UBUF_REG(base) ((base)->PS_UBUF) #define PXP_PS_VBUF_REG(base) ((base)->PS_VBUF) #define PXP_PS_PITCH_REG(base) ((base)->PS_PITCH) #define PXP_HW_PXP_PS_BACKGROUND_0_REG(base) ((base)->HW_PXP_PS_BACKGROUND_0) #define PXP_PS_SCALE_REG(base) ((base)->PS_SCALE) #define PXP_PS_OFFSET_REG(base) ((base)->PS_OFFSET) #define PXP_HW_PXP_PS_CLRKEYLOW_0_REG(base) ((base)->HW_PXP_PS_CLRKEYLOW_0) #define PXP_HW_PXP_PS_CLRKEYHIGH_0_REG(base) ((base)->HW_PXP_PS_CLRKEYHIGH_0) #define PXP_AS_CTRL_REG(base) ((base)->AS_CTRL) #define PXP_AS_BUF_REG(base) ((base)->AS_BUF) #define PXP_AS_PITCH_REG(base) ((base)->AS_PITCH) #define PXP_HW_PXP_AS_CLRKEYLOW_0_REG(base) ((base)->HW_PXP_AS_CLRKEYLOW_0) #define PXP_HW_PXP_AS_CLRKEYHIGH_0_REG(base) ((base)->HW_PXP_AS_CLRKEYHIGH_0) #define PXP_CSC1_COEF0_REG(base) ((base)->CSC1_COEF0) #define PXP_CSC1_COEF1_REG(base) ((base)->CSC1_COEF1) #define PXP_CSC1_COEF2_REG(base) ((base)->CSC1_COEF2) #define PXP_CSC2_CTRL_REG(base) ((base)->CSC2_CTRL) #define PXP_CSC2_COEF0_REG(base) ((base)->CSC2_COEF0) #define PXP_CSC2_COEF1_REG(base) ((base)->CSC2_COEF1) #define PXP_CSC2_COEF2_REG(base) ((base)->CSC2_COEF2) #define PXP_CSC2_COEF3_REG(base) ((base)->CSC2_COEF3) #define PXP_CSC2_COEF4_REG(base) ((base)->CSC2_COEF4) #define PXP_CSC2_COEF5_REG(base) ((base)->CSC2_COEF5) #define PXP_LUT_CTRL_REG(base) ((base)->LUT_CTRL) #define PXP_LUT_ADDR_REG(base) ((base)->LUT_ADDR) #define PXP_LUT_DATA_REG(base) ((base)->LUT_DATA) #define PXP_LUT_EXTMEM_REG(base) ((base)->LUT_EXTMEM) #define PXP_CFA_REG(base) ((base)->CFA) #define PXP_HW_PXP_ALPHA_A_CTRL_REG(base) ((base)->HW_PXP_ALPHA_A_CTRL) #define PXP_HW_PXP_ALPHA_B_CTRL_REG(base) ((base)->HW_PXP_ALPHA_B_CTRL) #define PXP_HW_PXP_ALPHA_B_CTRL_1_REG(base) ((base)->HW_PXP_ALPHA_B_CTRL_1) #define PXP_HW_PXP_PS_BACKGROUND_1_REG(base) ((base)->HW_PXP_PS_BACKGROUND_1) #define PXP_HW_PXP_PS_CLRKEYLOW_1_REG(base) ((base)->HW_PXP_PS_CLRKEYLOW_1) #define PXP_HW_PXP_PS_CLRKEYHIGH_1_REG(base) ((base)->HW_PXP_PS_CLRKEYHIGH_1) #define PXP_HW_PXP_AS_CLRKEYLOW_1_REG(base) ((base)->HW_PXP_AS_CLRKEYLOW_1) #define PXP_HW_PXP_AS_CLRKEYHIGH_1_REG(base) ((base)->HW_PXP_AS_CLRKEYHIGH_1) #define PXP_HW_PXP_CTRL2_REG(base) ((base)->HW_PXP_CTRL2) #define PXP_HW_PXP_POWER_REG0_REG(base) ((base)->HW_PXP_POWER_REG0) #define PXP_HW_PXP_POWER_REG1_REG(base) ((base)->HW_PXP_POWER_REG1) #define PXP_HW_PXP_DATA_PATH_CTRL0_REG(base) ((base)->HW_PXP_DATA_PATH_CTRL0) #define PXP_HW_PXP_DATA_PATH_CTRL1_REG(base) ((base)->HW_PXP_DATA_PATH_CTRL1) #define PXP_HW_PXP_INIT_MEM_CTRL_REG(base) ((base)->HW_PXP_INIT_MEM_CTRL) #define PXP_HW_PXP_INIT_MEM_DATA_REG(base) ((base)->HW_PXP_INIT_MEM_DATA) #define PXP_HW_PXP_INIT_MEM_DATA_HIGH_REG(base) ((base)->HW_PXP_INIT_MEM_DATA_HIGH) #define PXP_HW_PXP_IRQ_MASK_REG(base) ((base)->HW_PXP_IRQ_MASK) #define PXP_HW_PXP_IRQ_REG(base) ((base)->HW_PXP_IRQ) #define PXP_NEXT_REG(base) ((base)->NEXT) #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_CTRL_CH0) #define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_CTRL_CH1) #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_STATUS_CH0) #define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_STATUS_CH1) #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0) #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0) #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1) #define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1) #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SIZE_CH0) #define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SIZE_CH1) #define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0) #define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1) #define PXP_HW_PXP_INPUT_FETCH_PITCH_REG(base) ((base)->HW_PXP_INPUT_FETCH_PITCH) #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0) #define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1) #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0) #define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1) #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0) #define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1) #define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_0_CH0) #define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_1_CH0) #define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_0_CH1) #define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_1_CH1) #define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_CTRL_CH0) #define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_CTRL_CH1) #define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_STATUS_CH0) #define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_STATUS_CH1) #define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_SIZE_CH0) #define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_SIZE_CH1) #define PXP_HW_PXP_INPUT_STORE_PITCH_REG(base) ((base)->HW_PXP_INPUT_STORE_PITCH) #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0) #define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1) #define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_0_CH0) #define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_1_CH0) #define PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_FILL_DATA_CH0) #define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_0_CH1) #define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_1_CH1) #define PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK0_H_CH0) #define PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK0_L_CH0) #define PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK1_H_CH0) #define PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK1_L_CH0) #define PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK2_H_CH0) #define PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK2_L_CH0) #define PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK3_H_CH0) #define PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK3_L_CH0) #define PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK4_H_CH0) #define PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK4_L_CH0) #define PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK5_H_CH0) #define PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK5_L_CH0) #define PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK6_H_CH0) #define PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK6_L_CH0) #define PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK7_H_CH0) #define PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK7_L_CH0) #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_SHIFT_L_CH0) #define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_SHIFT_H_CH0) #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_SHIFT_L_CH0) #define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_SHIFT_H_CH0) #define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_MASK_L_CH0) #define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_MASK_H_CH0) #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_CTRL_CH0) #define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_CTRL_CH1) #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_STATUS_CH0) #define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_STATUS_CH1) #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0) #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0) #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1) #define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1) #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SIZE_CH0) #define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SIZE_CH1) #define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0) #define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1) #define PXP_HW_PXP_DITHER_FETCH_PITCH_REG(base) ((base)->HW_PXP_DITHER_FETCH_PITCH) #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0) #define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1) #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0) #define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1) #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0) #define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1) #define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_0_CH0) #define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_1_CH0) #define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_0_CH1) #define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_1_CH1) #define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_CTRL_CH0) #define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_CTRL_CH1) #define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_STATUS_CH0) #define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_STATUS_CH1) #define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_SIZE_CH0) #define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_SIZE_CH1) #define PXP_HW_PXP_DITHER_STORE_PITCH_REG(base) ((base)->HW_PXP_DITHER_STORE_PITCH) #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0) #define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1) #define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_0_CH0) #define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_1_CH0) #define PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_FILL_DATA_CH0) #define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_0_CH1) #define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_1_CH1) #define PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK0_H_CH0) #define PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK0_L_CH0) #define PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK1_H_CH0) #define PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK1_L_CH0) #define PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK2_H_CH0) #define PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK2_L_CH0) #define PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK3_H_CH0) #define PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK3_L_CH0) #define PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK4_H_CH0) #define PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK4_L_CH0) #define PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK5_H_CH0) #define PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK5_L_CH0) #define PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK6_H_CH0) #define PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK6_L_CH0) #define PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK7_H_CH0) #define PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK7_L_CH0) #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_SHIFT_L_CH0) #define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_SHIFT_H_CH0) #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_SHIFT_L_CH0) #define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_SHIFT_H_CH0) #define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_MASK_L_CH0) #define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_MASK_H_CH0) #define PXP_HW_PXP_DITHER_CTRL_REG(base) ((base)->HW_PXP_DITHER_CTRL) #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA0) #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA1) #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA2) #define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA3) #define PXP_HW_PXP_HIST_A_CTRL_REG(base) ((base)->HW_PXP_HIST_A_CTRL) #define PXP_HW_PXP_HIST_A_MASK_REG(base) ((base)->HW_PXP_HIST_A_MASK) #define PXP_HW_PXP_HIST_A_BUF_SIZE_REG(base) ((base)->HW_PXP_HIST_A_BUF_SIZE) #define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_REG(base) ((base)->HW_PXP_HIST_A_TOTAL_PIXEL) #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_REG(base) ((base)->HW_PXP_HIST_A_ACTIVE_AREA_X) #define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_REG(base) ((base)->HW_PXP_HIST_A_ACTIVE_AREA_Y) #define PXP_HW_PXP_HIST_A_RAW_STAT0_REG(base) ((base)->HW_PXP_HIST_A_RAW_STAT0) #define PXP_HW_PXP_HIST_A_RAW_STAT1_REG(base) ((base)->HW_PXP_HIST_A_RAW_STAT1) #define PXP_HW_PXP_HIST_B_CTRL_REG(base) ((base)->HW_PXP_HIST_B_CTRL) #define PXP_HW_PXP_HIST_B_MASK_REG(base) ((base)->HW_PXP_HIST_B_MASK) #define PXP_HW_PXP_HIST_B_BUF_SIZE_REG(base) ((base)->HW_PXP_HIST_B_BUF_SIZE) #define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_REG(base) ((base)->HW_PXP_HIST_B_TOTAL_PIXEL) #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_REG(base) ((base)->HW_PXP_HIST_B_ACTIVE_AREA_X) #define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_REG(base) ((base)->HW_PXP_HIST_B_ACTIVE_AREA_Y) #define PXP_HW_PXP_HIST_B_RAW_STAT0_REG(base) ((base)->HW_PXP_HIST_B_RAW_STAT0) #define PXP_HW_PXP_HIST_B_RAW_STAT1_REG(base) ((base)->HW_PXP_HIST_B_RAW_STAT1) #define PXP_HIST2_PARAM_REG(base) ((base)->HIST2_PARAM) #define PXP_HIST4_PARAM_REG(base) ((base)->HIST4_PARAM) #define PXP_HIST8_PARAM0_REG(base) ((base)->HIST8_PARAM0) #define PXP_HIST8_PARAM1_REG(base) ((base)->HIST8_PARAM1) #define PXP_HIST16_PARAM0_REG(base) ((base)->HIST16_PARAM0) #define PXP_HIST16_PARAM1_REG(base) ((base)->HIST16_PARAM1) #define PXP_HIST16_PARAM2_REG(base) ((base)->HIST16_PARAM2) #define PXP_HIST16_PARAM3_REG(base) ((base)->HIST16_PARAM3) #define PXP_HW_PXP_HIST32_PARAM0_REG(base) ((base)->HW_PXP_HIST32_PARAM0) #define PXP_HW_PXP_HIST32_PARAM1_REG(base) ((base)->HW_PXP_HIST32_PARAM1) #define PXP_HW_PXP_HIST32_PARAM2_REG(base) ((base)->HW_PXP_HIST32_PARAM2) #define PXP_HW_PXP_HIST32_PARAM3_REG(base) ((base)->HW_PXP_HIST32_PARAM3) #define PXP_HW_PXP_HIST32_PARAM4_REG(base) ((base)->HW_PXP_HIST32_PARAM4) #define PXP_HW_PXP_HIST32_PARAM5_REG(base) ((base)->HW_PXP_HIST32_PARAM5) #define PXP_HW_PXP_HIST32_PARAM6_REG(base) ((base)->HW_PXP_HIST32_PARAM6) #define PXP_HW_PXP_HIST32_PARAM7_REG(base) ((base)->HW_PXP_HIST32_PARAM7) #define PXP_HW_PXP_COMP_CTRL_REG(base) ((base)->HW_PXP_COMP_CTRL) #define PXP_HW_PXP_COMP_FORMAT0_REG(base) ((base)->HW_PXP_COMP_FORMAT0) #define PXP_HW_PXP_COMP_FORMAT1_REG(base) ((base)->HW_PXP_COMP_FORMAT1) #define PXP_HW_PXP_COMP_FORMAT2_REG(base) ((base)->HW_PXP_COMP_FORMAT2) #define PXP_HW_PXP_COMP_MASK0_REG(base) ((base)->HW_PXP_COMP_MASK0) #define PXP_HW_PXP_COMP_MASK1_REG(base) ((base)->HW_PXP_COMP_MASK1) #define PXP_HW_PXP_COMP_BUFFER_SIZE_REG(base) ((base)->HW_PXP_COMP_BUFFER_SIZE) #define PXP_HW_PXP_COMP_SOURCE_REG(base) ((base)->HW_PXP_COMP_SOURCE) #define PXP_HW_PXP_COMP_TARGET_REG(base) ((base)->HW_PXP_COMP_TARGET) #define PXP_HW_PXP_COMP_BUFFER_A_REG(base) ((base)->HW_PXP_COMP_BUFFER_A) #define PXP_HW_PXP_COMP_BUFFER_B_REG(base) ((base)->HW_PXP_COMP_BUFFER_B) #define PXP_HW_PXP_COMP_BUFFER_C_REG(base) ((base)->HW_PXP_COMP_BUFFER_C) #define PXP_HW_PXP_COMP_BUFFER_D_REG(base) ((base)->HW_PXP_COMP_BUFFER_D) #define PXP_HW_PXP_COMP_DEBUG_REG(base) ((base)->HW_PXP_COMP_DEBUG) #define PXP_HW_PXP_BUS_MUX_REG(base) ((base)->HW_PXP_BUS_MUX) #define PXP_HW_PXP_HANDSHAKE_READY_MUX0_REG(base) ((base)->HW_PXP_HANDSHAKE_READY_MUX0) #define PXP_HW_PXP_HANDSHAKE_READY_MUX1_REG(base) ((base)->HW_PXP_HANDSHAKE_READY_MUX1) #define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_REG(base) ((base)->HW_PXP_HANDSHAKE_DONE_MUX0) #define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_REG(base) ((base)->HW_PXP_HANDSHAKE_DONE_MUX1) #define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_REG(base) ((base)->HW_PXP_HANDSHAKE_CPU_FETCH) #define PXP_HW_PXP_HANDSHAKE_CPU_STORE_REG(base) ((base)->HW_PXP_HANDSHAKE_CPU_STORE) /*! * @} */ /* end of group PXP_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PXP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PXP_Register_Masks PXP Register Masks * @{ */ /* CTRL Bit Fields */ #define PXP_CTRL_ENABLE_MASK 0x1u #define PXP_CTRL_ENABLE_SHIFT 0 #define PXP_CTRL_IRQ_ENABLE_MASK 0x2u #define PXP_CTRL_IRQ_ENABLE_SHIFT 1 #define PXP_CTRL_NEXT_IRQ_ENABLE_MASK 0x4u #define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT 2 #define PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK 0x8u #define PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT 3 #define PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK 0x10u #define PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT 4 #define PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK 0x20u #define PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT 5 #define PXP_CTRL_RSVD0_MASK 0xC0u #define PXP_CTRL_RSVD0_SHIFT 6 #define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<MCR) #define QuadSPI_IPCR_REG(base) ((base)->IPCR) #define QuadSPI_FLSHCR_REG(base) ((base)->FLSHCR) #define QuadSPI_BUF0CR_REG(base) ((base)->BUF0CR) #define QuadSPI_BUF1CR_REG(base) ((base)->BUF1CR) #define QuadSPI_BUF2CR_REG(base) ((base)->BUF2CR) #define QuadSPI_BUF3CR_REG(base) ((base)->BUF3CR) #define QuadSPI_BFGENCR_REG(base) ((base)->BFGENCR) #define QuadSPI_BUF0IND_REG(base) ((base)->BUF0IND) #define QuadSPI_BUF1IND_REG(base) ((base)->BUF1IND) #define QuadSPI_BUF2IND_REG(base) ((base)->BUF2IND) #define QuadSPI_SFAR_REG(base) ((base)->SFAR) #define QuadSPI_SMPR_REG(base) ((base)->SMPR) #define QuadSPI_RBSR_REG(base) ((base)->RBSR) #define QuadSPI_RBCT_REG(base) ((base)->RBCT) #define QuadSPI_TBSR_REG(base) ((base)->TBSR) #define QuadSPI_TBDR_REG(base) ((base)->TBDR) #define QuadSPI_SR_REG(base) ((base)->SR) #define QuadSPI_FR_REG(base) ((base)->FR) #define QuadSPI_RSER_REG(base) ((base)->RSER) #define QuadSPI_SPNDST_REG(base) ((base)->SPNDST) #define QuadSPI_SPTRCLR_REG(base) ((base)->SPTRCLR) #define QuadSPI_SFA1AD_REG(base) ((base)->SFA1AD) #define QuadSPI_SFA2AD_REG(base) ((base)->SFA2AD) #define QuadSPI_SFB1AD_REG(base) ((base)->SFB1AD) #define QuadSPI_SFB2AD_REG(base) ((base)->SFB2AD) #define QuadSPI_RBDR_REG(base,index) ((base)->RBDR[index]) #define QuadSPI_LUTKEY_REG(base) ((base)->LUTKEY) #define QuadSPI_LCKCR_REG(base) ((base)->LCKCR) #define QuadSPI_LUT_REG(base,index) ((base)->LUT[index]) /*! * @} */ /* end of group QuadSPI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- QuadSPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks * @{ */ /* MCR Bit Fields */ #define QuadSPI_MCR_SWRSTSD_MASK 0x1u #define QuadSPI_MCR_SWRSTSD_SHIFT 0 #define QuadSPI_MCR_SWRSTHD_MASK 0x2u #define QuadSPI_MCR_SWRSTHD_SHIFT 1 #define QuadSPI_MCR_END_CFG_MASK 0xCu #define QuadSPI_MCR_END_CFG_SHIFT 2 #define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x))<VIR) #define RDC_STAT_REG(base) ((base)->STAT) #define RDC_INTCTRL_REG(base) ((base)->INTCTRL) #define RDC_INTSTAT_REG(base) ((base)->INTSTAT) #define RDC_MDA_REG(base,index) ((base)->MDA[index]) #define RDC_PDAP_REG(base,index) ((base)->PDAP[index]) #define RDC_MRSA_REG(base,index) ((base)->MR[index].MRSA) #define RDC_MREA_REG(base,index) ((base)->MR[index].MREA) #define RDC_MRC_REG(base,index) ((base)->MR[index].MRC) #define RDC_MRVS_REG(base,index) ((base)->MR[index].MRVS) /*! * @} */ /* end of group RDC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- RDC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RDC_Register_Masks RDC Register Masks * @{ */ /* VIR Bit Fields */ #define RDC_VIR_NDID_MASK 0xFu #define RDC_VIR_NDID_SHIFT 0 #define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x))<GATE[index]) #define RDC_SEMAPHORE_RSTGT_R_REG(base) ((base)->RSTGT_R) #define RDC_SEMAPHORE_RSTGT_W_REG(base) ((base)->RSTGT_W) /*! * @} */ /* end of group RDC_SEMAPHORE_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- RDC_SEMAPHORE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks * @{ */ /* GATE Bit Fields */ #define RDC_SEMAPHORE_GATE_GTFSM_MASK 0xFu #define RDC_SEMAPHORE_GATE_GTFSM_SHIFT 0 #define RDC_SEMAPHORE_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x))<ROMPATCHD[index]) #define ROMC_ROMPATCHCNTL_REG(base) ((base)->ROMPATCHCNTL) #define ROMC_ROMPATCHENH_REG(base) ((base)->ROMPATCHENH) #define ROMC_ROMPATCHENL_REG(base) ((base)->ROMPATCHENL) #define ROMC_ROMPATCHA_REG(base,index) ((base)->ROMPATCHA[index]) #define ROMC_ROMPATCHSR_REG(base) ((base)->ROMPATCHSR) /*! * @} */ /* end of group ROMC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ROMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ROMC_Register_Masks ROMC Register Masks * @{ */ /* ROMPATCHD Bit Fields */ #define ROMC_ROMPATCHD_DATAX_MASK 0xFFFFFFFFu #define ROMC_ROMPATCHD_DATAX_SHIFT 0 #define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x))<MC0PTR) #define SDMAARM_INTR_REG(base) ((base)->INTR) #define SDMAARM_STOP_STAT_REG(base) ((base)->STOP_STAT) #define SDMAARM_HSTART_REG(base) ((base)->HSTART) #define SDMAARM_EVTOVR_REG(base) ((base)->EVTOVR) #define SDMAARM_DSPOVR_REG(base) ((base)->DSPOVR) #define SDMAARM_HOSTOVR_REG(base) ((base)->HOSTOVR) #define SDMAARM_EVTPEND_REG(base) ((base)->EVTPEND) #define SDMAARM_RESET_REG(base) ((base)->RESET) #define SDMAARM_EVTERR_REG(base) ((base)->EVTERR) #define SDMAARM_INTRMASK_REG(base) ((base)->INTRMASK) #define SDMAARM_PSW_REG(base) ((base)->PSW) #define SDMAARM_EVTERRDBG_REG(base) ((base)->EVTERRDBG) #define SDMAARM_CONFIG_REG(base) ((base)->CONFIG) #define SDMAARM_SDMA_LOCK_REG(base) ((base)->SDMA_LOCK) #define SDMAARM_ONCE_ENB_REG(base) ((base)->ONCE_ENB) #define SDMAARM_ONCE_DATA_REG(base) ((base)->ONCE_DATA) #define SDMAARM_ONCE_INSTR_REG(base) ((base)->ONCE_INSTR) #define SDMAARM_ONCE_STAT_REG(base) ((base)->ONCE_STAT) #define SDMAARM_ONCE_CMD_REG(base) ((base)->ONCE_CMD) #define SDMAARM_ILLINSTADDR_REG(base) ((base)->ILLINSTADDR) #define SDMAARM_CHN0ADDR_REG(base) ((base)->CHN0ADDR) #define SDMAARM_EVT_MIRROR_REG(base) ((base)->EVT_MIRROR) #define SDMAARM_EVT_MIRROR2_REG(base) ((base)->EVT_MIRROR2) #define SDMAARM_XTRIG_CONF1_REG(base) ((base)->XTRIG_CONF1) #define SDMAARM_XTRIG_CONF2_REG(base) ((base)->XTRIG_CONF2) #define SDMAARM_SDMA_CHNPRI_REG(base,index) ((base)->SDMA_CHNPRI[index]) #define SDMAARM_CHNENBL_REG(base,index) ((base)->CHNENBL[index]) /*! * @} */ /* end of group SDMAARM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SDMAARM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks * @{ */ /* MC0PTR Bit Fields */ #define SDMAARM_MC0PTR_MC0PTR_MASK 0xFFFFFFFFu #define SDMAARM_MC0PTR_MC0PTR_SHIFT 0 #define SDMAARM_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x))<DC0PTR) #define SDMABP_INTR_REG(base) ((base)->INTR) #define SDMABP_STOP_STAT_REG(base) ((base)->STOP_STAT) #define SDMABP_DSTART_REG(base) ((base)->DSTART) #define SDMABP_EVTERR_REG(base) ((base)->EVTERR) #define SDMABP_INTRMASK_REG(base) ((base)->INTRMASK) #define SDMABP_EVTERRDBG_REG(base) ((base)->EVTERRDBG) /*! * @} */ /* end of group SDMABP_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SDMABP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SDMABP_Register_Masks SDMABP Register Masks * @{ */ /* DC0PTR Bit Fields */ #define SDMABP_DC0PTR_DC0PTR_MASK 0xFFFFFFFFu #define SDMABP_DC0PTR_DC0PTR_SHIFT 0 #define SDMABP_DC0PTR_DC0PTR(x) (((uint32_t)(((uint32_t)(x))<CCPRI.CCPRI) #define SDMACORE_CCPTR_REG(base) ((base)->CCPTR.CCPTR) #define SDMACORE_CCR_REG(base) ((base)->CCR.CCR) #define SDMACORE_EAA_REG(base) ((base)->EAA.EAA) #define SDMACORE_EAB_REG(base) ((base)->EAB.EAB) #define SDMACORE_EAM_REG(base) ((base)->EAM.EAM) #define SDMACORE_ECOUNT_REG(base) ((base)->ECOUNT.ECOUNT) #define SDMACORE_ECTL_REG(base) ((base)->ECTL.ECTL) #define SDMACORE_ED_REG(base) ((base)->ED.ED) #define SDMACORE_EDM_REG(base) ((base)->EDM.EDM) #define SDMACORE_EVENTS_REG(base) ((base)->EVENTS.EVENTS) #define SDMACORE_MC0PTR_REG(base) ((base)->MC0PTR) #define SDMACORE_NCPRI_REG(base) ((base)->NCPRI.NCPRI) #define SDMACORE_NCR_REG(base) ((base)->NCR.NCR) #define SDMACORE_ENDIANNESS_REG(base) ((base)->ENDIANNESS.ENDIANNESS) #define SDMACORE_EVENTS2_REG(base) ((base)->EVENTS2.EVENTS2) #define SDMACORE_MCHN0ADDR_REG(base) ((base)->MCHN0ADDR.MCHN0ADDR) #define SDMACORE_OSTAT_REG(base) ((base)->OSTAT.OSTAT) #define SDMACORE_RTB_REG(base) ((base)->RTB) #define SDMACORE_SDMA_LOCK_REG(base) ((base)->SDMA_LOCK.SDMA_LOCK) #define SDMACORE_TB_REG(base) ((base)->TB.TB) /*! * @} */ /* end of group SDMACORE_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SDMACORE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SDMACORE_Register_Masks SDMACORE Register Masks * @{ */ /* CCPRI Bit Fields */ #define SDMACORE_CCPRI_CCPRI_MASK 0x7u #define SDMACORE_CCPRI_CCPRI_SHIFT 0 #define SDMACORE_CCPRI_CCPRI(x) (((uint32_t)(((uint32_t)(x))<Gate03) #define SEMA4_GATE02_REG(base) ((base)->Gate02) #define SEMA4_GATE01_REG(base) ((base)->Gate01) #define SEMA4_GATE00_REG(base) ((base)->Gate00) #define SEMA4_GATE07_REG(base) ((base)->Gate07) #define SEMA4_GATE06_REG(base) ((base)->Gate06) #define SEMA4_GATE05_REG(base) ((base)->Gate05) #define SEMA4_GATE04_REG(base) ((base)->Gate04) #define SEMA4_GATE11_REG(base) ((base)->Gate11) #define SEMA4_GATE10_REG(base) ((base)->Gate10) #define SEMA4_GATE09_REG(base) ((base)->Gate09) #define SEMA4_GATE08_REG(base) ((base)->Gate08) #define SEMA4_GATE15_REG(base) ((base)->Gate15) #define SEMA4_GATE14_REG(base) ((base)->Gate14) #define SEMA4_GATE13_REG(base) ((base)->Gate13) #define SEMA4_GATE12_REG(base) ((base)->Gate12) #define SEMA4_CPINE_REG(base,index) ((base)->CPINE[index].CPINE) #define SEMA4_CPNTF_REG(base,index) ((base)->CPNTF[index].CPNTF) #define SEMA4_RSTGT_REG(base) ((base)->RSTGT) #define SEMA4_RSTNTF_REG(base) ((base)->RSTNTF) /*! * @} */ /* end of group SEMA4_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SEMA4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks * @{ */ /* Gate03 Bit Fields */ #define SEMA4_GATE03_GTFSM_MASK 0x3u #define SEMA4_GATE03_GTFSM_SHIFT 0 #define SEMA4_GATE03_GTFSM(x) (((uint8_t)(((uint8_t)(x))<DCR.DCR) #define SJC_GPCCR_REG(base) ((base)->GPCCR.GPCCR) #define SJC_GPSSR_REG(base) ((base)->GPSSR.GPSSR) #define SJC_GPUSR1_REG(base) ((base)->GPUSR1) #define SJC_GPUSR2_REG(base) ((base)->GPUSR2.GPUSR2) #define SJC_GPUSR3_REG(base) ((base)->GPUSR3.GPUSR3) #define SJC_SSR_REG(base) ((base)->SSR.SSR) /*! * @} */ /* end of group SJC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SJC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SJC_Register_Masks SJC Register Masks * @{ */ /* DCR Bit Fields */ #define SJC_DCR_DE_TO_ARM_MASK 0x1u #define SJC_DCR_DE_TO_ARM_SHIFT 0 #define SJC_DCR_DE_TO_SDMA_MASK 0x2u #define SJC_DCR_DE_TO_SDMA_SHIFT 1 #define SJC_DCR_DEBUG_OBS_MASK 0x8u #define SJC_DCR_DEBUG_OBS_SHIFT 3 #define SJC_DCR_DIRECT_SDMA_REQ_EN_MASK 0x20u #define SJC_DCR_DIRECT_SDMA_REQ_EN_SHIFT 5 #define SJC_DCR_DIRECT_ARM_REQ_EN_MASK 0x40u #define SJC_DCR_DIRECT_ARM_REQ_EN_SHIFT 6 /* GPCCR Bit Fields */ #define SJC_GPCCR_SCLKR_MASK 0x1u #define SJC_GPCCR_SCLKR_SHIFT 0 #define SJC_GPCCR_ACLKOFFDIS_MASK 0x2u #define SJC_GPCCR_ACLKOFFDIS_SHIFT 1 /* GPSSR Bit Fields */ #define SJC_GPSSR_GPSSR_MASK 0xFFFFFFFFu #define SJC_GPSSR_GPSSR_SHIFT 0 #define SJC_GPSSR_GPSSR(x) (((uint32_t)(((uint32_t)(x))<HPLR) #define SNVS_HPCOMR_REG(base) ((base)->HPCOMR) #define SNVS_HPCR_REG(base) ((base)->HPCR) #define SNVS_HPSR_REG(base) ((base)->HPSR) #define SNVS_HPRTCMR_REG(base) ((base)->HPRTCMR) #define SNVS_HPRTCLR_REG(base) ((base)->HPRTCLR) #define SNVS_HPTAMR_REG(base) ((base)->HPTAMR) #define SNVS_HPTALR_REG(base) ((base)->HPTALR) #define SNVS_LPLR_REG(base) ((base)->LPLR) #define SNVS_LPCR_REG(base) ((base)->LPCR) #define SNVS_LPSR_REG(base) ((base)->LPSR) #define SNVS_LPSMCMR_REG(base) ((base)->LPSMCMR) #define SNVS_LPSMCLR_REG(base) ((base)->LPSMCLR) #define SNVS_LPGPR_REG(base) ((base)->LPGPR) #define SNVS_HPVIDR1_REG(base) ((base)->HPVIDR1) #define SNVS_HPVIDR2_REG(base) ((base)->HPVIDR2) /*! * @} */ /* end of group SNVS_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SNVS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SNVS_Register_Masks SNVS Register Masks * @{ */ /* HPLR Bit Fields */ #define SNVS_HPLR_MC_SL_MASK 0x10u #define SNVS_HPLR_MC_SL_SHIFT 4 #define SNVS_HPLR_GPR_SL_MASK 0x20u #define SNVS_HPLR_GPR_SL_SHIFT 5 /* HPCOMR Bit Fields */ #define SNVS_HPCOMR_LP_SWR_MASK 0x10u #define SNVS_HPCOMR_LP_SWR_SHIFT 4 #define SNVS_HPCOMR_LP_SWR_DIS_MASK 0x20u #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT 5 #define SNVS_HPCOMR_NPSWA_EN_MASK 0x80000000u #define SNVS_HPCOMR_NPSWA_EN_SHIFT 31 /* HPCR Bit Fields */ #define SNVS_HPCR_RTC_EN_MASK 0x1u #define SNVS_HPCR_RTC_EN_SHIFT 0 #define SNVS_HPCR_HPTA_EN_MASK 0x2u #define SNVS_HPCR_HPTA_EN_SHIFT 1 #define SNVS_HPCR_PI_EN_MASK 0x8u #define SNVS_HPCR_PI_EN_SHIFT 3 #define SNVS_HPCR_PI_FREQ_MASK 0xF0u #define SNVS_HPCR_PI_FREQ_SHIFT 4 #define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x))<PRR[index]) /*! * @} */ /* end of group SPBA_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SPBA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SPBA_Register_Masks SPBA Register Masks * @{ */ /* PRR Bit Fields */ #define SPBA_PRR_RARA_MASK 0x1u #define SPBA_PRR_RARA_SHIFT 0 #define SPBA_PRR_RARB_MASK 0x2u #define SPBA_PRR_RARB_SHIFT 1 #define SPBA_PRR_RARC_MASK 0x4u #define SPBA_PRR_RARC_SHIFT 2 #define SPBA_PRR_ROI_MASK 0x30000u #define SPBA_PRR_ROI_SHIFT 16 #define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x))<SCR) #define SRC_A7RCR0_REG(base) ((base)->A7RCR0) #define SRC_A7RCR1_REG(base) ((base)->A7RCR1) #define SRC_M4RCR_REG(base) ((base)->M4RCR) #define SRC_ERCR_REG(base) ((base)->ERCR) #define SRC_HSICPHY_RCR_REG(base) ((base)->HSICPHY_RCR) #define SRC_USBOPHY1_RCR_REG(base) ((base)->USBOPHY1_RCR) #define SRC_USBOPHY2_RCR_REG(base) ((base)->USBOPHY2_RCR) #define SRC_MIPIPHY_RCR_REG(base) ((base)->MIPIPHY_RCR) #define SRC_PCIEPHY_RCR_REG(base) ((base)->PCIEPHY_RCR) #define SRC_SBMR1_REG(base) ((base)->SBMR1) #define SRC_SRSR_REG(base) ((base)->SRSR) #define SRC_SISR_REG(base) ((base)->SISR) #define SRC_SIMR_REG(base) ((base)->SIMR) #define SRC_SBMR2_REG(base) ((base)->SBMR2) #define SRC_GPR1_REG(base) ((base)->GPR1) #define SRC_GPR2_REG(base) ((base)->GPR2) #define SRC_GPR3_REG(base) ((base)->GPR3) #define SRC_GPR4_REG(base) ((base)->GPR4) #define SRC_GPR5_REG(base) ((base)->GPR5) #define SRC_GPR6_REG(base) ((base)->GPR6) #define SRC_GPR7_REG(base) ((base)->GPR7) #define SRC_GPR8_REG(base) ((base)->GPR8) #define SRC_GPR9_REG(base) ((base)->GPR9) #define SRC_GPR10_REG(base) ((base)->GPR10) #define SRC_DDRC_RCR_REG(base) ((base)->DDRC_RCR) /*! * @} */ /* end of group SRC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SRC_Register_Masks SRC Register Masks * @{ */ /* SCR Bit Fields */ #define SRC_SCR_MASK_TEMPSENSE_RESET_MASK 0xF0u #define SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT 4 #define SRC_SCR_MASK_TEMPSENSE_RESET(x) (((uint32_t)(((uint32_t)(x))<HW_ANADIG_TEMPSENSE0) #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_REG(base) ((base)->HW_ANADIG_TEMPSENSE0_SET) #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_REG(base) ((base)->HW_ANADIG_TEMPSENSE0_CLR) #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_REG(base) ((base)->HW_ANADIG_TEMPSENSE0_TOG) #define TEMPMON_HW_ANADIG_TEMPSENSE1_REG(base) ((base)->HW_ANADIG_TEMPSENSE1) #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_REG(base) ((base)->HW_ANADIG_TEMPSENSE1_SET) #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_REG(base) ((base)->HW_ANADIG_TEMPSENSE1_CLR) #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_REG(base) ((base)->HW_ANADIG_TEMPSENSE1_TOG) #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM) #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM_SET) #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM_CLR) #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM_TOG) /*! * @} */ /* end of group TEMPMON_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- TEMPMON Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks * @{ */ /* HW_ANADIG_TEMPSENSE0 Bit Fields */ #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0 #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<URXD) #define UART_UTXD_REG(base) ((base)->UTXD) #define UART_UCR1_REG(base) ((base)->UCR1) #define UART_UCR2_REG(base) ((base)->UCR2) #define UART_UCR3_REG(base) ((base)->UCR3) #define UART_UCR4_REG(base) ((base)->UCR4) #define UART_UFCR_REG(base) ((base)->UFCR) #define UART_USR1_REG(base) ((base)->USR1) #define UART_USR2_REG(base) ((base)->USR2) #define UART_UESC_REG(base) ((base)->UESC) #define UART_UTIM_REG(base) ((base)->UTIM) #define UART_UBIR_REG(base) ((base)->UBIR) #define UART_UBMR_REG(base) ((base)->UBMR) #define UART_UBRC_REG(base) ((base)->UBRC) #define UART_ONEMS_REG(base) ((base)->ONEMS) #define UART_UTS_REG(base) ((base)->UTS) #define UART_UMCR_REG(base) ((base)->UMCR) /*! * @} */ /* end of group UART_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- UART Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup UART_Register_Masks UART Register Masks * @{ */ /* URXD Bit Fields */ #define UART_URXD_RX_DATA_MASK 0xFFu #define UART_URXD_RX_DATA_SHIFT 0 #define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x))<ID) #define USB_HWGENERAL_REG(base) ((base)->HWGENERAL) #define USB_HWHOST_REG(base) ((base)->HWHOST) #define USB_HWDEVICE_REG(base) ((base)->HWDEVICE) #define USB_HWTXBUF_REG(base) ((base)->HWTXBUF) #define USB_HWRXBUF_REG(base) ((base)->HWRXBUF) #define USB_GPTIMER0LD_REG(base) ((base)->GPTIMER0LD) #define USB_GPTIMER0CTRL_REG(base) ((base)->GPTIMER0CTRL) #define USB_GPTIMER1LD_REG(base) ((base)->GPTIMER1LD) #define USB_GPTIMER1CTRL_REG(base) ((base)->GPTIMER1CTRL) #define USB_SBUSCFG_REG(base) ((base)->SBUSCFG) #define USB_CAPLENGTH_REG(base) ((base)->CAPLENGTH) #define USB_HCIVERSION_REG(base) ((base)->HCIVERSION) #define USB_HCSPARAMS_REG(base) ((base)->HCSPARAMS) #define USB_HCCPARAMS_REG(base) ((base)->HCCPARAMS) #define USB_DCIVERSION_REG(base) ((base)->DCIVERSION) #define USB_DCCPARAMS_REG(base) ((base)->DCCPARAMS) #define USB_USBCMD_REG(base) ((base)->USBCMD) #define USB_USBSTS_REG(base) ((base)->USBSTS) #define USB_USBINTR_REG(base) ((base)->USBINTR) #define USB_FRINDEX_REG(base) ((base)->FRINDEX) #define USB_DEVICEADDR_REG(base) ((base)->DEVICEADDR) #define USB_PERIODICLISTBASE_REG(base) ((base)->PERIODICLISTBASE) #define USB_ASYNCLISTADDR_REG(base) ((base)->ASYNCLISTADDR) #define USB_ENDPTLISTADDR_REG(base) ((base)->ENDPTLISTADDR) #define USB_BURSTSIZE_REG(base) ((base)->BURSTSIZE) #define USB_TXFILLTUNING_REG(base) ((base)->TXFILLTUNING) #define USB_ENDPTNAK_REG(base) ((base)->ENDPTNAK) #define USB_ENDPTNAKEN_REG(base) ((base)->ENDPTNAKEN) #define USB_CONFIGFLAG_REG(base) ((base)->CONFIGFLAG) #define USB_PORTSC1_REG(base) ((base)->PORTSC1) #define USB_OTGSC_REG(base) ((base)->OTGSC) #define USB_USBMODE_REG(base) ((base)->USBMODE) #define USB_ENDPTSETUPSTAT_REG(base) ((base)->ENDPTSETUPSTAT) #define USB_ENDPTPRIME_REG(base) ((base)->ENDPTPRIME) #define USB_ENDPTFLUSH_REG(base) ((base)->ENDPTFLUSH) #define USB_ENDPTSTAT_REG(base) ((base)->ENDPTSTAT) #define USB_ENDPTCOMPLETE_REG(base) ((base)->ENDPTCOMPLETE) #define USB_ENDPTCTRL0_REG(base) ((base)->ENDPTCTRL0) #define USB_ENDPTCTRL1_REG(base) ((base)->ENDPTCTRL1) #define USB_ENDPTCTRL2_REG(base) ((base)->ENDPTCTRL2) #define USB_ENDPTCTRL3_REG(base) ((base)->ENDPTCTRL3) #define USB_ENDPTCTRL4_REG(base) ((base)->ENDPTCTRL4) #define USB_ENDPTCTRL5_REG(base) ((base)->ENDPTCTRL5) #define USB_ENDPTCTRL6_REG(base) ((base)->ENDPTCTRL6) #define USB_ENDPTCTRL7_REG(base) ((base)->ENDPTCTRL7) /*! * @} */ /* end of group USB_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- USB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Register_Masks USB Register Masks * @{ */ /* ID Bit Fields */ #define USB_ID_ID_MASK 0x3Fu #define USB_ID_ID_SHIFT 0 #define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x))<USB_x_CTRL1) #define USBNC_USB_x_CTRL2_REG(base) ((base)->USB_x_CTRL2) #define USBNC_USB_x_PHY_CTL2_REG(base) ((base)->USB_x_PHY_CTL2) #define USBNC_USB_x_PHY_STS_REG(base) ((base)->USB_x_PHY_STS) #define USBNC_ADP_CFG1_REG(base) ((base)->ADP_CFG1) #define USBNC_ADP_CFG2_REG(base) ((base)->ADP_CFG2) #define USBNC_ADP_STATUS_REG(base) ((base)->ADP_STATUS) /*! * @} */ /* end of group USBNC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- USBNC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBNC_Register_Masks USBNC Register Masks * @{ */ /* USB_x_CTRL1 Bit Fields */ #define USBNC_USB_x_CTRL1_OVER_CUR_DIS_MASK 0x80u #define USBNC_USB_x_CTRL1_OVER_CUR_DIS_SHIFT 7 #define USBNC_USB_x_CTRL1_OVER_CUR_POL_MASK 0x100u #define USBNC_USB_x_CTRL1_OVER_CUR_POL_SHIFT 8 #define USBNC_USB_x_CTRL1_PWR_POL_MASK 0x200u #define USBNC_USB_x_CTRL1_PWR_POL_SHIFT 9 #define USBNC_USB_x_CTRL1_WIE_MASK 0x400u #define USBNC_USB_x_CTRL1_WIE_SHIFT 10 #define USBNC_USB_x_CTRL1_WKUP_SW_EN_MASK 0x4000u #define USBNC_USB_x_CTRL1_WKUP_SW_EN_SHIFT 14 #define USBNC_USB_x_CTRL1_WKUP_SW_MASK 0x8000u #define USBNC_USB_x_CTRL1_WKUP_SW_SHIFT 15 #define USBNC_USB_x_CTRL1_WKUP_ID_EN_MASK 0x10000u #define USBNC_USB_x_CTRL1_WKUP_ID_EN_SHIFT 16 #define USBNC_USB_x_CTRL1_WKUP_VBUS_EN_MASK 0x20000u #define USBNC_USB_x_CTRL1_WKUP_VBUS_EN_SHIFT 17 #define USBNC_USB_x_CTRL1_WKUP_DPDM_EN_MASK 0x20000000u #define USBNC_USB_x_CTRL1_WKUP_DPDM_EN_SHIFT 29 #define USBNC_USB_x_CTRL1_WIR_MASK 0x80000000u #define USBNC_USB_x_CTRL1_WIR_SHIFT 31 /* USB_x_CTRL2 Bit Fields */ #define USBNC_USB_x_CTRL2_VBUS_SOURCE_SEL_MASK 0x3u #define USBNC_USB_x_CTRL2_VBUS_SOURCE_SEL_SHIFT 0 #define USBNC_USB_x_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x))<PWD) #define USBPHY_PWD_SET_REG(base) ((base)->PWD_SET) #define USBPHY_PWD_CLR_REG(base) ((base)->PWD_CLR) #define USBPHY_PWD_TOG_REG(base) ((base)->PWD_TOG) #define USBPHY_TX_REG(base) ((base)->TX) #define USBPHY_TX_SET_REG(base) ((base)->TX_SET) #define USBPHY_TX_CLR_REG(base) ((base)->TX_CLR) #define USBPHY_TX_TOG_REG(base) ((base)->TX_TOG) #define USBPHY_RX_REG(base) ((base)->RX) #define USBPHY_RX_SET_REG(base) ((base)->RX_SET) #define USBPHY_RX_CLR_REG(base) ((base)->RX_CLR) #define USBPHY_RX_TOG_REG(base) ((base)->RX_TOG) #define USBPHY_CTRL_REG(base) ((base)->CTRL) #define USBPHY_CTRL_SET_REG(base) ((base)->CTRL_SET) #define USBPHY_CTRL_CLR_REG(base) ((base)->CTRL_CLR) #define USBPHY_CTRL_TOG_REG(base) ((base)->CTRL_TOG) #define USBPHY_STATUS_REG(base) ((base)->STATUS) #define USBPHY_DEBUG_REG(base) ((base)->DEBUG) #define USBPHY_DEBUG_SET_REG(base) ((base)->DEBUG_SET) #define USBPHY_DEBUG_CLR_REG(base) ((base)->DEBUG_CLR) #define USBPHY_DEBUG_TOG_REG(base) ((base)->DEBUG_TOG) #define USBPHY_DEBUG0_STATUS_REG(base) ((base)->DEBUG0_STATUS) #define USBPHY_DEBUG1_REG(base) ((base)->DEBUG1) #define USBPHY_DEBUG1_SET_REG(base) ((base)->DEBUG1_SET) #define USBPHY_DEBUG1_CLR_REG(base) ((base)->DEBUG1_CLR) #define USBPHY_DEBUG1_TOG_REG(base) ((base)->DEBUG1_TOG) #define USBPHY_VERSION_REG(base) ((base)->VERSION) /*! * @} */ /* end of group USBPHY_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- USBPHY Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBPHY_Register_Masks USBPHY Register Masks * @{ */ /* PWD Bit Fields */ #define USBPHY_PWD_RSVD0_MASK 0x3FFu #define USBPHY_PWD_RSVD0_SHIFT 0 #define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x))<USB1_VBUS_DETECT) #define USB_ANALOG_USB1_VBUS_DETECT_SET_REG(base) ((base)->USB1_VBUS_DETECT_SET) #define USB_ANALOG_USB1_VBUS_DETECT_CLR_REG(base) ((base)->USB1_VBUS_DETECT_CLR) #define USB_ANALOG_USB1_VBUS_DETECT_TOG_REG(base) ((base)->USB1_VBUS_DETECT_TOG) #define USB_ANALOG_USB1_CHRG_DETECT_REG(base) ((base)->USB1_CHRG_DETECT) #define USB_ANALOG_USB1_CHRG_DETECT_SET_REG(base) ((base)->USB1_CHRG_DETECT_SET) #define USB_ANALOG_USB1_CHRG_DETECT_CLR_REG(base) ((base)->USB1_CHRG_DETECT_CLR) #define USB_ANALOG_USB1_CHRG_DETECT_TOG_REG(base) ((base)->USB1_CHRG_DETECT_TOG) #define USB_ANALOG_USB1_VBUS_DETECT_STAT_REG(base) ((base)->USB1_VBUS_DETECT_STAT) #define USB_ANALOG_USB1_CHRG_DETECT_STAT_REG(base) ((base)->USB1_CHRG_DETECT_STAT) #define USB_ANALOG_USB1_MISC_REG(base) ((base)->USB1_MISC) #define USB_ANALOG_USB1_MISC_SET_REG(base) ((base)->USB1_MISC_SET) #define USB_ANALOG_USB1_MISC_CLR_REG(base) ((base)->USB1_MISC_CLR) #define USB_ANALOG_USB1_MISC_TOG_REG(base) ((base)->USB1_MISC_TOG) #define USB_ANALOG_USB2_VBUS_DETECT_REG(base) ((base)->USB2_VBUS_DETECT) #define USB_ANALOG_USB2_VBUS_DETECT_SET_REG(base) ((base)->USB2_VBUS_DETECT_SET) #define USB_ANALOG_USB2_VBUS_DETECT_CLR_REG(base) ((base)->USB2_VBUS_DETECT_CLR) #define USB_ANALOG_USB2_VBUS_DETECT_TOG_REG(base) ((base)->USB2_VBUS_DETECT_TOG) #define USB_ANALOG_USB2_CHRG_DETECT_REG(base) ((base)->USB2_CHRG_DETECT) #define USB_ANALOG_USB2_CHRG_DETECT_SET_REG(base) ((base)->USB2_CHRG_DETECT_SET) #define USB_ANALOG_USB2_CHRG_DETECT_CLR_REG(base) ((base)->USB2_CHRG_DETECT_CLR) #define USB_ANALOG_USB2_CHRG_DETECT_TOG_REG(base) ((base)->USB2_CHRG_DETECT_TOG) #define USB_ANALOG_USB2_VBUS_DETECT_STAT_REG(base) ((base)->USB2_VBUS_DETECT_STAT) #define USB_ANALOG_USB2_CHRG_DETECT_STAT_REG(base) ((base)->USB2_CHRG_DETECT_STAT) #define USB_ANALOG_USB2_MISC_REG(base) ((base)->USB2_MISC) #define USB_ANALOG_USB2_MISC_SET_REG(base) ((base)->USB2_MISC_SET) #define USB_ANALOG_USB2_MISC_CLR_REG(base) ((base)->USB2_MISC_CLR) #define USB_ANALOG_USB2_MISC_TOG_REG(base) ((base)->USB2_MISC_TOG) #define USB_ANALOG_DIGPROG_REG(base) ((base)->DIGPROG) /*! * @} */ /* end of group USB_ANALOG_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- USB_ANALOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks * @{ */ /* USB1_VBUS_DETECT Bit Fields */ #define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK 0x7u #define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT 0 #define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<WCR) #define WDOG_WSR_REG(base) ((base)->WSR) #define WDOG_WRSR_REG(base) ((base)->WRSR) #define WDOG_WICR_REG(base) ((base)->WICR) #define WDOG_WMCR_REG(base) ((base)->WMCR) /*! * @} */ /* end of group WDOG_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- WDOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Register_Masks WDOG Register Masks * @{ */ /* WCR Bit Fields */ #define WDOG_WCR_WDZST_MASK 0x1u #define WDOG_WCR_WDZST_SHIFT 0 #define WDOG_WCR_WDBG_MASK 0x2u #define WDOG_WCR_WDBG_SHIFT 1 #define WDOG_WCR_WDE_MASK 0x4u #define WDOG_WCR_WDE_SHIFT 2 #define WDOG_WCR_WDT_MASK 0x8u #define WDOG_WCR_WDT_SHIFT 3 #define WDOG_WCR_SRS_MASK 0x10u #define WDOG_WCR_SRS_SHIFT 4 #define WDOG_WCR_WDA_MASK 0x20u #define WDOG_WCR_WDA_SHIFT 5 #define WDOG_WCR_SRE_MASK 0x40u #define WDOG_WCR_SRE_SHIFT 6 #define WDOG_WCR_WDW_MASK 0x80u #define WDOG_WCR_WDW_SHIFT 7 #define WDOG_WCR_WT_MASK 0xFF00u #define WDOG_WCR_WT_SHIFT 8 #define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x))<CTRL_24M) #define XTALOSC_CTRL_24M_SET_REG(base) ((base)->CTRL_24M_SET) #define XTALOSC_CTRL_24M_CLR_REG(base) ((base)->CTRL_24M_CLR) #define XTALOSC_CTRL_24M_TOG_REG(base) ((base)->CTRL_24M_TOG) #define XTALOSC_RCOSC_CONFIG0_REG(base) ((base)->RCOSC_CONFIG0) #define XTALOSC_RCOSC_CONFIG0_SET_REG(base) ((base)->RCOSC_CONFIG0_SET) #define XTALOSC_RCOSC_CONFIG0_CLR_REG(base) ((base)->RCOSC_CONFIG0_CLR) #define XTALOSC_RCOSC_CONFIG0_TOG_REG(base) ((base)->RCOSC_CONFIG0_TOG) #define XTALOSC_RCOSC_CONFIG1_REG(base) ((base)->RCOSC_CONFIG1) #define XTALOSC_RCOSC_CONFIG1_SET_REG(base) ((base)->RCOSC_CONFIG1_SET) #define XTALOSC_RCOSC_CONFIG1_CLR_REG(base) ((base)->RCOSC_CONFIG1_CLR) #define XTALOSC_RCOSC_CONFIG1_TOG_REG(base) ((base)->RCOSC_CONFIG1_TOG) #define XTALOSC_RCOSC_CONFIG2_REG(base) ((base)->RCOSC_CONFIG2) #define XTALOSC_RCOSC_CONFIG2_SET_REG(base) ((base)->RCOSC_CONFIG2_SET) #define XTALOSC_RCOSC_CONFIG2_CLR_REG(base) ((base)->RCOSC_CONFIG2_CLR) #define XTALOSC_RCOSC_CONFIG2_TOG_REG(base) ((base)->RCOSC_CONFIG2_TOG) #define XTALOSC_OSC_32K_REG(base) ((base)->OSC_32K) #define XTALOSC_OSC_32K_SET_REG(base) ((base)->OSC_32K_SET) #define XTALOSC_OSC_32K_CLR_REG(base) ((base)->OSC_32K_CLR) #define XTALOSC_OSC_32K_TOG_REG(base) ((base)->OSC_32K_TOG) /*! * @} */ /* end of group XTALOSC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- XTALOSC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup XTALOSC_Register_Masks XTALOSC Register Masks * @{ */ /* CTRL_24M Bit Fields */ #define XTALOSC_CTRL_24M_XTAL_24M_PWD_MASK 0x1u #define XTALOSC_CTRL_24M_XTAL_24M_PWD_SHIFT 0 #define XTALOSC_CTRL_24M_XTAL_24M_EN_MASK 0x2u #define XTALOSC_CTRL_24M_XTAL_24M_EN_SHIFT 1 #define XTALOSC_CTRL_24M_OSC_XTALOK_MASK 0x4u #define XTALOSC_CTRL_24M_OSC_XTALOK_SHIFT 2 #define XTALOSC_CTRL_24M_OSC_XTALOK_EN_MASK 0x8u #define XTALOSC_CTRL_24M_OSC_XTALOK_EN_SHIFT 3 #define XTALOSC_CTRL_24M_CLKGATE_CTRL_MASK 0x10u #define XTALOSC_CTRL_24M_CLKGATE_CTRL_SHIFT 4 #define XTALOSC_CTRL_24M_CLKGATE_DELAY_MASK 0xE0u #define XTALOSC_CTRL_24M_CLKGATE_DELAY_SHIFT 5 #define XTALOSC_CTRL_24M_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x))<DS_ADDR) #define uSDHC_BLK_ATT_REG(base) ((base)->BLK_ATT) #define uSDHC_CMD_ARG_REG(base) ((base)->CMD_ARG) #define uSDHC_CMD_XFR_TYP_REG(base) ((base)->CMD_XFR_TYP) #define uSDHC_CMD_RSP0_REG(base) ((base)->CMD_RSP0) #define uSDHC_CMD_RSP1_REG(base) ((base)->CMD_RSP1) #define uSDHC_CMD_RSP2_REG(base) ((base)->CMD_RSP2) #define uSDHC_CMD_RSP3_REG(base) ((base)->CMD_RSP3) #define uSDHC_DATA_BUFF_ACC_PORT_REG(base) ((base)->DATA_BUFF_ACC_PORT) #define uSDHC_PRES_STATE_REG(base) ((base)->PRES_STATE) #define uSDHC_PROT_CTRL_REG(base) ((base)->PROT_CTRL) #define uSDHC_SYS_CTRL_REG(base) ((base)->SYS_CTRL) #define uSDHC_INT_STATUS_REG(base) ((base)->INT_STATUS) #define uSDHC_INT_STATUS_EN_REG(base) ((base)->INT_STATUS_EN) #define uSDHC_INT_SIGNAL_EN_REG(base) ((base)->INT_SIGNAL_EN) #define uSDHC_AUTOCMD12_ERR_STATUS_REG(base) ((base)->AUTOCMD12_ERR_STATUS) #define uSDHC_HOST_CTRL_CAP_REG(base) ((base)->HOST_CTRL_CAP) #define uSDHC_WTMK_LVL_REG(base) ((base)->WTMK_LVL) #define uSDHC_MIX_CTRL_REG(base) ((base)->MIX_CTRL) #define uSDHC_FORCE_EVENT_REG(base) ((base)->FORCE_EVENT) #define uSDHC_ADMA_ERR_STATUS_REG(base) ((base)->ADMA_ERR_STATUS) #define uSDHC_ADMA_SYS_ADDR_REG(base) ((base)->ADMA_SYS_ADDR) #define uSDHC_DLL_CTRL_REG(base) ((base)->DLL_CTRL) #define uSDHC_DLL_STATUS_REG(base) ((base)->DLL_STATUS) #define uSDHC_CLK_TUNE_CTRL_STATUS_REG(base) ((base)->CLK_TUNE_CTRL_STATUS) #define uSDHC_STROBE_DLL_CTRL_REG(base) ((base)->STROBE_DLL_CTRL) #define uSDHC_STROBE_DLL_STATUS_REG(base) ((base)->STROBE_DLL_STATUS) #define uSDHC_VEND_SPEC_REG(base) ((base)->VEND_SPEC) #define uSDHC_MMC_BOOT_REG(base) ((base)->MMC_BOOT) #define uSDHC_VEND_SPEC2_REG(base) ((base)->VEND_SPEC2) #define uSDHC_TUNING_CTRL_REG(base) ((base)->TUNING_CTRL) /*! * @} */ /* end of group uSDHC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- uSDHC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup uSDHC_Register_Masks uSDHC Register Masks * @{ */ /* DS_ADDR Bit Fields */ #define uSDHC_DS_ADDR_DS_ADDR_MASK 0xFFFFFFFCu #define uSDHC_DS_ADDR_DS_ADDR_SHIFT 2 #define uSDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x))<